UC3852NG4 - Texas Instruments - Datasheet.Directory

TYPICAL APPLICATION

10/94

FEATURES

•Low-Cost Power Factor

Correction

•Power Factor Great er Than 0.99

•Few External Parts Required

•Contro lled On-Tim e Boost PWM

•Zero-Curr ent Switching

•Limited Peak Current

•Min and Max Frequenc y Limits

•Starting Current Less Than 1mA

•High-Current FET Drive Output

•Under-Voltage Loc kout

DESCRIPTION

The UC1852 prov ides a low-cos t solution to active power-f actor correction ( PF C)

for systems that woul d otherwise draw high peak current pul ses from AC power

lines. This circuit implements zero-current switched boost conversion, producing

sinusoidal input currents with a mi nimum of external components, while keeping

peak current substant ia lly below that of fully-discont inuous convert ers.

The UC1852 provides controlled switch on-time to regulate the output bulk DC

voltage, an off-time defined by the boost inductor, and a zero-current sensing

circuit to react ivate the swit ch cycle. Even though sw itching frequency var ies with

both load and instantaneous line voltage, it can be maintained within a reasonable

range to minimize noise generation.

While allowing higher peak switch currents than continuous PFCs such as the

UC1854, th is devic e offer s less extern al circuitry and sma ller inductors, yet better

performanc e and easier line-noise filtering than discontinuous current PF Cs with

no sacrifice in c omplexity or c ost. The ability to obta in a power factor in excess of

0.99 makes the UC1852 an optimum choice f or low-cost applications in the 50 t o

500 watt power range. Protection features of these devices include under-voltage

lockout, output clamping, peak-current limiting, and maximum-frequency

clamping.

The UC1852 family is available in 8-pin plastic and ceramic dual in-line packages,

and in the 8-pin small outline IC package (SOIC). The UC1852 is specified for

operation from -55°C to +125°C, the UC2852 is specified for operation from -40 °C

to +8 5°C, and the UC3852 is specified for operation from 0°C to +70 °C.

UC1852

UC2852

UC3852

High Power-Fac tor Preregu lato r

UDG-92001

SOIC–8 (T OP VIEW )

D Package

Unless ot her w ise stated, VCC=24V, ISET =50kΩ to GND, RAMP=1nF to GND, ISNS=

–0.1V, VFB conne cted to CO MP, no load on OU T, –55°C<Ta<+125°C for the UC18 52,

–40°C<Ta<+85°C f or the UC2852, and 0°C<Ta<+70°C f or the UC3852, and Ta=Tj.

UC1852

UC2852

UC3852

ELECTRI CAL CHARACTERI ST ICS

ABSOLUTE MAXIMUM RATINGS

Supply Voltag e (Lo w-im peda nce Sou rce )..........................30.0V

Supply Current (High-impedance Source)......................30.0mA

OUT Cur ren t, Peak..... .... .... .... .... .... . .... .... .... .... .... ... .... .... ....±1.0A

OUT Ener gy, Capa citive Load..... .... .... .... ....... .... .... .... .... ....5.0µJ

Input Voltage, ISNS............................................................±5.0V

Input Voltage, V F B.............................................–0.3V to +10.0V

COMP Current...............................................................±10.0mA

ISET Curr ent... .... . .... .... ... .... . .... .... ... .... . .... .... ... .... . .... .... ..–1 0.0m A

Power Dissipation at T a≤25°C (Note 3) ..............................1.0W

Storage Temperature .......................................–65°C to +150 °C

Lead Tem per at ur e (Soldering, 10 Sec onds )...................+300°C

Note 1: All voltage s with respe ct to GND (Pin 1).

Note 2: All curre nt s are posit ive in to the specified t erminal.

Note 3: Refers to DI L-8 Packa ge. Consu lt Packaging Sec tion of

Unitrod e In te gra ted C ircuit s datab ook f or the rmal lim ita tion s and

consider at io ns of pack age.

DIL–8 (TOP VIEW)

J or N Package

CONNECTI ON DIAGRA M

PARAMETER TEST CONDI TIO NS MIN. TYP. MAX. UNIT S

Time r Sect io n

ISET Voltage 4.5 5.0 5.5 V

RAMP Charge Current RAMP=2. 5V 88 98 108 µA

RAMP Discharg e Curr ent ISNS= –1. 0V, RAMP= 1 .0V 12 28 50 mA

RAMP Satur at ion Volt age ISNS= –1.0V, IRAMP=100µA0.006 0.200 V

RAMP Thres hold - Maximum Fre quen cy VFB=10V, CO MP open 0.92 1.02 1.12 V

RAMP Th res hold - PWM Comparato r 3 .9 4 .3 4 .8 V

Current Sense Co mparator

ISNS Resta rt Thresho ld –18 –10 –4 mV

ISNS Fa ult Th res hold –550 –450 –350 mV

ISNS Inpu t Current –100 –30 100 µA

Err or Am pli fier Sectio n

VFB Input Volta ge 4.6 5.0 5.3 V

VFB Input B ias Current –5.0 0 –0 .03 5.00 µA

COMP Sink Cur rent COMP= 7. 5V 10 mA

COMP Source Current COMP=2.5V –300 –175 –100 µA

COMP Clam p Voltage VFB=0.0V, CO MP open 9.2 10.0 10.6 V

OUT O utp ut

OUT Sat ura tion Voltag e High VCC=13V, IOUT= –200mA, RAMP=2V 0.5 1.7 2.5 V

OUT Sat ura tion Voltag e Low IOUT=200mA, ISNS= –1.0V 0.5 1.6 2.2 V

OUT Sat ura tion Voltag e Low @ 10m A I OUT=10mA, ISNS= –1.0V 0.05 0.40 V

OUT C lamp Voltag e IOUT= –200mA, RAMP=2V 10.0 12.0 14.5 V

OUT Volta ge dur ing UVLO I OUT=100mA, VCC=0V 0.5 1.0 2.2 V

Over al l Secti on

Inactive Supp ly Current VCC=10V 0.2 0.4 1.0 mA

Activ e Supply Cur rent 3 .0 6 .0 10.0 mA

VCC Clamp Voltage ICC=25mA 30 33 36 V

VCC Turn -On Threshold 14.5 16.3 17.5 V

VCC Turn -Off Threshold 10.5 11.5 13.0 V

VCC Threshold Hysteresis 3 5 7 V

UDG-92002

DETAILED BLOCK DIAGRAM

COMP: COMP is the output of the error ampli fier and the

input of the PWM comparator. To limit PWM on-ti me, this

pin is clamped to approximately 10V. To implement soft

start, the CO M P pin can be pulled low and ramped up with

a PNP transistor, a capacitor, and a resistor.

GND: Ground for all funct ions is through this pin.

ISET: The dominant function is of this pin is to program

RAMP charging current. RAMP charging current is

approximately 5V divided by the external resistor placed

from ISET to ground. Resistors in the range of 10kΩ to

50kΩ are recommended, producing currents in the range

of 10 0µA to 50 0µA.

A second function of ISET is as reference output. The ISET

pin is normally regulated to 5V ±10%. It is critical that this

pin only see the loading of the RAMP programming resistor,

but a high input-impedance comparator or amplifier may be

connected to this pin or to a tap on the RAMP programming

resistor if required.

The third funct ion of the IS ET pin is as a FAULT output . In

the event of an over-c urrent fault, the ISET pin is forced to

approximately 9V by the fault comparator. This can be used

to trip an external protection circuit which can disable the

load or start a fault rest art cyc le.

ISNS: Th is input to the zero and over curr ent com parator s

is specially built to allow operation over a ±5V dynamic

range. In noisy systems or systems with very high Q

inductors, it is desirable to filter the signal entering the ISNS

input to prevent premature restart or fault cycles. For best

accuracy, ISNS should be connected to a current sense

resistor through no more than 200 ohm s.

OUT: The out put of a high-c urrent power driver capable of

driving the gate of a power MOSFET with peak currents

exceeding ±500mA. To prevent damage to the power

MOSFET, the OUT pin is internally driven by a 12V supply.

However, lead inductance between the OUT pin and the

load can cause overshoot and ringing. External current

boost t ransistors will increase t his overshoot and ringing. If

there is any significant distance between the IC and the

MOSFET, external clamp diodes and/or series damping

resistors may be required. OUT is actively held low when

the VCC is below the UVLO thr eshold.

RAMP: A controlled on-time PW M requires a timer whose

time can be modulated by an external voltage. The timer

current is programmed by a resistor from ISET to GND. A

capacitor from RAMP to GND sets the on time in

conjunction with the voltage on COMP. Recommended

values for the timer capacitors are between 100pF and 1nF.

VCC: VCC is the logic and control power connection for this

device. VCC current is the sum of active device supply

current and the average OUT current. Knowing the

maximum operating frequency and the MOSFET gate

charge (Qg), average OUT current can be estimated by:

IOUT = Q g × F

To prevent noise problems, bypass VCC to GND with bot h

a ceramic and an electrolytic capacitor .

VFB: VFB is the error amplifier inverting input. This input

serves as both the voltage sense input to the error amplifier

UC1852

UC2852

UC3852

PIN DESCRIPTIONS

UDG-92003

Max Frequency vs. Rset and Ct

Rset, k

Maximum

Frequency,

kHz

100

1000

1 10 100

100pF

500pF

1nF

3nF

Ω

OUT Rise and Fall Time

Load Capacitance, nF

100

150

200

0510

Rise Time

Fall Time

Error Amplifier Gain and Phase

Frequency, kHz

Gain

(dB)

Phase

(deg)

-20

100

10 100 1000 10000

Phase

Gain

Max On-Time vs. Rset and Ct

Rset, k

Ω

Maximum

On-Time

100

1000

1 10 100

100pF

300pF

1nF

3nF

10nF

UC1852

UC2852

UC3852

UDG-92006

UDG-92008

UDG-92005

TYPICAL CHARACTERISTICS

UDG-92007

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRI MACK , NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

APPLI CATION INFO RMATIO N: A 100 Watt Power Factor Prere gul ator

This circuit demonstrates a complete power factor preregulator based on the UC3852. This preregulator will supply

up to 100 watts at 400VDC and exhibit power factor greater than 0.995 with less than 10% total harmonic distortion.

Operating input range is 90V to 160V RMS at 50Hz to 60Hz.

This design is intentionally simple, yet fully functional. The UC3852 can also be used in designs featuring soft start,

over-voltage protection, wide power-line voltage operation, and fault latching. For more information on applying

the UC3852, refer to Unitrode A pplication Note U–132.

PARTS LIST

UC1852

UC2852

UC3852

UDG-92004

C1 0.47µF/25 0VAC X2 C lass Polyester

C2 1n F/16V Cer am ic

C3 68µF/35V Aluminum Electrolytic

C4 180pF/16V Ceramic

C5 0.1µF/16V Polye ster or Cera mic

C6 82µF/45 0V A luminu m Electr olyt ic

D1 2A/50 0V Bridge Rectifier (Collmer

KBPC106 or Powertex MB11A02V60)

D2 100m A/5 0V Sw itchin g Diode (1N4148 )

D3 2A/50 0V 250n s Recov ery -Tim e Rect if ier

(Mo torola M R856 )

IC1 UC3852N Power Fact or Controller IC

Q1 IRF83 0 4.5A/ 500V 1.5Ω Power FET

L1 680µH ( Renco RL3792 with

10 Turn 24 AWG Secondary )

R1 150kΩ, 1⁄4W

R2 0.2Ω, 1⁄2W Carbon Composition

R3 10Ω, 1⁄4W

R4 13.3kΩ, 1⁄4W

R5 1MΩ, 1⁄4W

R6 20kΩ, 1⁄4W

R7 200kΩ, 1⁄2W

R8 200kΩ, 1⁄2W

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

UC1852J OBSOLETE CDIP J 8 TBD Call TI Call TI

UC1852J883B OBSOLETE CDIP J 8 TBD Call TI Call TI

UC2852D ACTIVE SOIC D 8 75 Green (RoHS &