1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3022/5
©
FEBRUARY 2009
CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT723622
IDT723632
IDT723642
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
••
••
•Memory storage capacity:
IDT723622 – 256 x 36 x 2
IDT723632 – 512 x 36 x 2
IDT723642 – 1,024 x 36 x 2
••
••
•Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
••
••
•Two independent clocked FIFOs buffering data in opposite
directions
••
••
•Mailbox bypass register for each FIFO
••
••
•Programmable Almost-Full and Almost-Empty flags
••
••
•Microprocessor Interface Control Logic
••
••
•IRA, ORA, AEA, and AFA flags synchronized by CLKA
••
••
•IRB, ORB, AEB, and AFB flags synchronized by CLKB
••
••
•Supports clock frequencies up to 83MHz
••
••
•Fast access times of 8ns
••
••
•Available in 132-pin Plastic Quad Flatpack (PQFP) or space-
saving 120-pin Thin Quad Flatpack (TQFP)
••
••
•Low-power 0.8-Micron Advanced CMOS technology
••
••
•Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
••
••
•Green parts available, see ordering information
DESCRIPTION:
The IDT723622/723632/723642 are a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-
quencies up to 83MHz and have read access times as fast as 8ns. Two
independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip
buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
10
ORB
AEB
36
36
IRB
AFB
B
0
- B
35
IRA
AFA
FS
0
FS
1
A
0
- A
35
ORA
AEA
3022 drw 01
36
36
FUNCTIONAL BLOCK DIAGRAM
2
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
PIN CONFIGURATION
PQFP (PQ132-1, order code: PQF)
TOP VIEW
NC
NC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
NC
NC
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3022 drw 02
NC
NC
NC
V
CC
CLKB
ENB
W/RB
CSB
GND
IRB
ORB
AFB
AEB
V
CC
MBF1
MBB
RST2
FS1
GND
FS0
RST1
MBA
MBF2
AEA
AFA
V
CC
ORA
IRA
CSA
W/RA
ENA
CLKA
GND
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
NC
B
11
B
10
B
9
B
7
B
8
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
74
76
77
78
79
80
81
82
83
75
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a
progammable Almost-Full flag (AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory. AFA and AFB indicate
when the FIFO contains more than a selected number of words.
The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO
are two-stage synchronized to the port clock that writes data into its array. The
Output Ready (ORA, ORB) and Almost-Empty (AEA, AEB) flags of a FIFO are
two-stage synchronized to the port clock that reads data from its array. Offset
values for the Almost-Full and Almost-Empty flags of both FIFOs can be
programmed from Port A.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs will immediately take the device out of the power down state.
The 723622/723632/723642 are characterized for operation from 0°C to
70°C. Industrial temperature range (-40°C to +85°C) is available by special
order. They are fabricated using IDT's high speed, submicron CMOS technology.
3
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (CONTINUED)
TQFP (PN120-1, order code: PF)
TOP VIEW
3022 drw 03
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
VCC
GND
CLKA
ENA
W/RA
CSA
IRA
ORA
VCC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
VCC
AEB
AFB
ORB
IRB
GND
CSB
W/RB
ENB
CLKB
GND
A11
A10
A9
A8
A7
A6
GND
A5
A4
A3
VCC
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
VCC
B7
B8
B9
B10
B11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
4
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol Name I/O Description
A0-A35 Port A Data I/0 36-bit bidirectional data port for side A.
AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words
Empty Flag (Port A) in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
Empty Flag (Port B) in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Full Flag (Port A) locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB Port B Almost- O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
Full Flag (Port B) locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0 - B35 Port B Data I/O 36-bit bidirectional data port for side B.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-
to-HIGH transition of CLKB.
CSA Port A Chip I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A.
Select The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on
Select port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FS1, FS0 Flag Offset I The LOW-to-HIGH transition of a FlFO’s Reset input latches the values of FS0 and FS1.
Selects If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as
the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously
and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1
load the Almost-Empty and Almost-Full offsets for both FlFOs.
IRA Input Ready O IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full
Flag (Port A) and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKA after reset.
IRB Input Ready O IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full
Flag (Port B) and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKB after reset.
M BA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a port A read or write operation.
Select When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for
output and a LOW level selects FIFO2 output register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and
a LOW level selects FIFO1 output register data for output.
MBF1 Mail1 Register O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
Flag register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by
a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is
set HIGH when FIFO1 is reset.
MBF2 Mail2 Register O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Flag Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-
to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also
set HIGH when FIFO2 is reset.
5
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Symbol Name I/O Description
ORA Output Ready O ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is
Flag (Port A) empty and reads from its memory are disabled. Ready data is present on the output register
of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the
third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory.
ORB Output Ready O ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is
Flag (Port B) empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1
when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-
HIGH transition of CLKB after a word is loaded to empty memory.
RST1 FIFO1 Reset I To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0
and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is
written to its RAM.
RST2 FIFO2 Reset I To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0
and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is
written to its RAM.
W/RA Port A Write/ I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Read Select transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
W/RB Port B Write/ I A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
Read Select transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
6
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. Industrial temperature range product is available by special order.
2. All typical values are at VCC = 5V, TA = 25°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT723622
IDT723632
IDT723642
Commercial
tCLK = 12, 15 ns
Symbol Parameter Test Conditions Min. Typ.(2) Max. Unit
VOH Output Logic "1" Voltage VCC = 4.5V, IOH = –4 mA 2.4 — — V
VOL Output Logic "0" Voltage VCC = 4.5V, IOL = 8 mA — — 0.5 V
ILI Input Leakage Current (Any Input) VCC = 5.5V, VI = VCC or 0 — — ±10 µA
ILO Output Leakage Current VCC = 5.5V, VO = VCC or 0 — — ±10 µA
ICC2(3) Standby Current (with CLKA & CLKB running) VCC = 5.5V, VI = VCC –0.2V or 0V — — 8 mA
ICC3(3) Standby Current (no clocks running) VCC = 5.5V, VI = VCC –0.2V or 0V — — 1 mA
CIN(4) Input Capacitance VI = 0, f = 1 MHz — 4 — pF
COUT(4) Output Capacitance VO = 0, f = 1 MHZ — 8 — pF
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage (Commercial) 4.5 5.0 5.5 V
VIH High-Level Input Voltage (Commercial) 2 — — V
VIL Low-Level Input Voltage (Commercial) — — 0.8 V
IOH High-Level Output Current (Commercial) — — –4 mA
IOL Low-Level Output Current (Commercial) — — 8 mA
TAOperating Temperature (Commercial) 0 — 70 °C
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to 7 V
VI(2) Input Voltage Range –0.5 to VCC+0.5 V
VO(2) Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range –65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
7
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA
and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC2 X fo)
where:
N = number of outputs = 36
∆ICC = increase in power supply current for each input at a TTL HIGH level
d c = duty cycle of inputs at a TTL HIGH level of 3.4 V
CL= output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
010 20 30 40 50 6070
0
50
100
250
300
VCC = 5.0V
fS ⎯ Clock Frequency ⎯ MHz
fdata = 1/2 fS
TA = 25°C
CL
= 0pF
VCC = 5.5V
3022 drw 03a
200
150 VCC = 4.5V
80 90
ICC(f) Supply Current mA
8
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Commercial
IDT723622L12 IDT723622L15
IDT723632L12 IDT723632L15
IDT723642L12 IDT723642L15
Symbol Parameter Min. Max. Min. Max. Unit
fSClock Frequency, CLKA or CLKB — 83 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 12 — 15 — ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 5 — 6 — ns
tCLKL Pulse Duration, CLKA and CLKB LOW 5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑3—4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑4 — 4.5 — ns
tENS2 Setup Time, ENA and MBA, before CLKA↑; ENB and MBB before CLKB↑3 — 4.5 — ns
tRSTS Setup Time, RST1 or RST2 LOW before CLKA or CLKB (2) 5—5—ns
tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — n s
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, 0.5 — 1 — ns
and MBB after CLKB↑
tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑(2) 4—4—ns
tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — n s
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB 7.5 — 7.5 — ns
tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 12 — 12 — ns
NOTES:
1. Industrial temperature range product is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
9
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. Industrial temperature range product is available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723622L12 IDT723622L15
IDT723632L12 IDT723632L15
IDT723642L12 IDT723642L15
Symbol Parameter Min. Max. Min. Max. Unit
tAAccess Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 8 2 10 ns
tPIR Propagation Delay Time, CLKA↑ to IRA and CLKB↑ to IRB 2828ns
tPOR Propagation Delay Time, CLKA↑ to ORA and CLKB↑ to ORB 1818ns
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1818ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 1818ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and 0808ns
CLKB↑ to MBF2 LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 28210ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 8 2 10 ns
tRSF Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and 1 10 1 15 ns
MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW 2 6 2 10 ns
and W/RB HIGH to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and 1618ns
CSB HIGH or W/RB LOW to B0-B35 at high-impedance
10
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transition of the Reset inputs. After this reset is complete, the first four writes to
FIFO1 do not store data in the FIFO memory but load the offset registers in the
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to
1,020 for the IDT723642. After all the offset registers are programmed from port
A, the port B Input Ready flag (IRB) is set HIGH, and both FIFOs begin normal
operation. See Figure 3 for relevant offset register parallel programming timing
diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by port A Chip
Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are
in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes
on port A are independent of any concurrent port B operation. Write and Read
cycle timing diagrams for port A can be found in Figure 4 and 7.
The port B control signals are identical to those of port A with the exception
that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read
select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the
port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB is
LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW,
and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port
B are independent of any concurrent port A operation. Write and Read cycle
timing diagrams for port B can be found in Figure 5 and 6.
SIGNAL DESCRIPTION
RESET
After power up, a Master Reset operation must be performed by
providing a LOW pulse to RSTI and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT723622/723632/723642 are reset separately by taking
their Reset (RST1, RST2) inputs LOW for at least four port A Clock (CLKA) and
four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A FIFO reset initializes the internal read and write
pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready
flag (ORA, ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-
Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its
Input Ready flag is set HIGH after two clock cycles to begin normal operation.
A LOW-to-HIGH transition on a FlFO Reset (RST1, RST2) input latches
the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method (for details see Table 1, Flag
Programming and the Almost-Empty Flag and Almost-Full Flag Offset
Programming section that follows). The relevant FIFO Reset timing diagram can
be found in Figure 2.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PRO-
GRAMMING
Four registers in these devices are used to hold the offset values for
the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB)
Offset register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register
is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and
the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each
register name corresponds to its FIFO number. The offset registers can be
loaded with preset values during the reset of a FIFO or they can be programmed
from port A (see Table 1).
— PRESET VALUES
To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, at least one of the flag select
inputs must be HIGH during the LOW-to-HIGH transition of its Reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated
with FIFO2 are loaded with one of the preset values in the same way with FIFO2
Reset (RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset
value loading timing diagram, see Figure 2.
FS1 FS0 RST1 RST2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2)
HH ↑X64 X
HH X↑X64
HL ↑X16 X
HL X↑X16
LH↑X8 X
LHX↑X8
LL↑↑ Programmed from port A Programmed from port A
NOTES:
1 . X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2 . X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
TABLE 1 — FLAG PROGRAMMING
11
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
The setup and hold time constraints to the port Clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read
operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select
and Write/Read select may change states during the setup and hold time
window of the cycle.
When a FIFO Output Ready flag is LOW, the next word written is
automatically sent to the FIFO output register automatically by the LOW-to-HIGH
transition of the port clock that sets the Output Ready flag HIGH. When the Output
Ready flag is HIGH, subsequent data is clocked to the output registers only when
a FIFO read is selected using the port’s Chip Select, Write/Read select, Enable,
and Mailbox select.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag-signal reliability by reducing the
probability of metastable events when CLKA and CLKB operate asynchro-
nously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA.
ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
the relationship of each port flag to FIFO1 and FIFO2.
OUTPUT READY FLAGS (ORA, ORB)
The Output Ready flag of a FIFO is synchronized to the port clock that
reads data from its array. When the Output Ready flag is HIGH, new data
is present in the FIFO output register. When the Output Ready flag is LOW,
the previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to
its output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2. From the time a word is written
to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles
of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag
is LOW if a word in memory is the next data to be sent to the FlFO output register
and three cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Output Ready flag of the FIFO remains
LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and shifting the word to the
FIFO output register.
A LOW-to-HIGH transition on an Output Ready flag synchronizing clock
begins the first synchronization cycle of a write if the clock transition occurs at
time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing
diagrams).
INPUT READY FLAGS (IRA, IRB)
The Input Ready flag of a FlFO is synchronized to the port clock that writes
data to its array. When the Input Ready flag is HIGH, a memory location is free
in the FIFO to receive new data. No memory locations are free when the Input
Ready flag is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. The
state machine that controls an Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FlFO memory status is full, full-1, or
CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O PORT FUNCTION
H X X X X High-Impedance None
L L L X X Input None
LLHL↑Input FIFO2 write
LLHH↑Input Mail2 write
L H L L X Output None
LHHL↑Output FIFO1 read
L H L H X Output None
LHHH↑Output Mail1 read (set MBF1 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O PORT FUNCTION
H X X X X High-Impedance None
L H L X X Input None
LHHL↑Input FIFO1 write
LHHH↑Input Mail1 write
L L L L X Output None
LLHL↑Output FIFO2 read
L L L H X Output None
LLHH↑Output Mail2 read (set MBF2 HIGH)
12
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
almost-empty state is defined by the contents of register X1 for AEB and register
X2 for AEA. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Empty flag is LOW when its FIFO contains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for its Almost-Empty flag to reflect the new
level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of
an Almost-Empty flag synchronizing clock begins the first synchronization cycle
if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figures 12 and 13).
Synchronized Synchronized
Number of Words in FIFO(1,2) to CLKB to CLKA
IDT723622(3) IDT723632(3) IDT723642(3) ORB AEB AFA IRA
000LLHH
1 to X1 1 to X1 1 to X1 H L H H
(X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to [1,024-(Y1+1)] H H H H
(256-Y1) to 255 (512-Y1) to 511 (1,024-Y1) to 1,023 H H L H
256 512 1,024 H H L L
full-2. From the time a word is read from a FIFO, its previous memory location
is ready to be written in a minimum of two cycles of the Input Ready flag
synchronizing clock. Therefore, an Input Ready flag is LOW if less than two
cycles of the Input Ready flag synchronizing clock have elapsed since the next
memory write location has been read. The second LOW-to-HIGH transition on
the Input Ready flag synchronizing Clock after the read sets the Input Ready
flag HIGH.
A LOW-to-HIGH transition on an Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 10 and 11 for timing diagrams).
ALMOST-EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or
programmed from port A.
Synchronized Synchronized
Number of Words in FIFO(1,2) to CLKA to CLKB
IDT723622(3) IDT723632(3) IDT723642(3) ORA AEA AFB IRB
000LLHH
1 to X2 1 to X2 1 to X2 H L H H
(X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1,024-(Y2+1)] H H H H
(256-Y2) to 255 (512-Y2) to 511 (1,024-Y2) to 1,023 H H L H
256 512 1,024 H H L L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or
programmed from port A.
TABLE 4 — FIFO1 FLAG OPERA TION
TABLE 5 — FIFO2 FLAG OPERA TION
13
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchroniz-
ing clock cycle may be the first synchronization cycle (see Figures 14 and 15).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA
writes A0-A35 data to the mail1 register when a port A Write is selected by CSA,
W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes
B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/
RB, and ENB and with MBB HIGH. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register
are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from
the FIFO output register when the port Mailbox select input is LOW and from
the mail register when the port-mailbox select input is HIGH. The Mail1
Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when
a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The
Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA
when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH.
The data in a mail register remains intact after it is read and changes only when
new data is written to the register. For mail register and Mail Register flag timing
diagrams, see Figure 16 and 17.
ALMOST-FULL FLAGS (AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
write pointer and read pointer comparator that indicates when the FIFO memory
status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined
by the contents of register Y1 for AFA and register Y2 for AFB. These registers
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
An Almost-Full flag is LOW when the number of words in its FIFO is greater than
or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or
IDT723642 respectively. An Almost-Full flag is HIGH when the number of words
in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)]
for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data
word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for its Almost-Full flag to reflect the new level of
fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [256/
512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO read that reduces the number
of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an
Almost-Full flag synchronizing clock begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the read that reduces the number of words
14
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and
rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
3022 drw 05
CLKA
RST1,
RST2
IRA
CLKB
IRB
A0 - A35
FS1,FS0
ENA
tFSS
tFSH
tPIR
tENHtENS2 tSKEW1
tDS tDH
tPIR
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
12
(1)
12
CLKA
RST1
IRA
AEB
AFA
MBF1
CLKB
ORB
FS1,FS0
3022 drw 04
t
RSTS
t
RSTH
t
FSH
t
FSS
t
PIR
t
PIR
t
POR
t
RSF
0,1
t
RSF
t
RSF
15
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Figure 5. Port B Write Cycle Timing for FIFO2
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1
NOTE:
1. Written to FIFO2.
3022 drw 07
CLKB
IRB
ENB
B0 - B35
MBB
CSB
W/RB
tCLK
tCLKH tCLKL
tENH
tENH
tENH
tENH
tDH
W1(1) W2(1)
tDS
tENS1
tENH
tENH
No Operation
tENS1
tENS2
tENS2 tENS2 tENS2
HIGH
3022 drw 06
CLKA
IRA
ENA
A0 - A35
MBA
CSA
W/RA
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1(1) W2(1)
t
ENH
t
ENH
No Operation
HIGH
t
ENS1
t
ENS2
t
ENS2
t
ENS2
t
ENS2
16
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1
Figure 7. Port A Read Cycle Timing for FIFO2
NOTE:
1. Read From FIFO2.
3022 drw 09
CLKA
ORA
ENA
A0 - A35
MBA
CSA
W/RA
tCLK
tCLKH tCLKL
tDMV
tEN tAtA
tENH tENH
tENS2
tENH
W1 W2 W3
(1) (1) (1)
tDIS
No Operation
tENS2
tENS2
3022 drw 08
CLKB
ORB
ENB
B0 - B35
MBB
CSB
W/RB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
W1 W2 W3
(1) (1) (1)
t
ENH
t
DIS
No Operation
t
ENS2
t
ENS2
HIGH
17
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
CSA
WRA
MBA
IRA
A0 - A35
CLKB
ORB
ENA
CLKA
123
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
POR
FIFO1 Empty
LOW
HIGH
t
CLKH
W1
HIGH
(1)
t
POR
t
A
t
ENS2
t
ENH
W1
4660 drw 10
Old Data in FIFO1 Output Register
LOW
CSB
HIGH
LOW
MBB
W/RB
ENB
B0 - B35
18
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
CSB
W/RB
MBB
IRB
B0 - B35
CLKA
ORA
CSA
W/RA
MBA
ENB
ENA
A0-A35
CLKB
3022 drw 11
123
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKH
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output Register W1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
(1)
19
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full
CSB
ORB
W/RB
MBB
ENB
B0 -B35
CLKB
IRA
CLKA
CSA
3022 drw 12
W/RA
MBA
12
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
PIR
t
PIR
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register Next Word From FIFO1
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
ENA
A0-A35
Write
20
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Figure 12. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost-Empty
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2 . FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full
AEB
CLKA
ENB
3022 drw 14
ENA
CLKB 2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
X1 Words in FIFO1 (X1+1) Words in FIFO1
(1)
CSA
ORA
W/RA
MBA
ENA
A0 -A35
CLKA
IRB
CLKB
CSB
W/RB
MBB
12
tCLK
tCLKH tCLKL
tENS2 tENH
tA
tSKEW1 tCLK
tCLKH tCLKL
tPIR
tENS2
tENS2
Previous Word in FIFO2 Output Register Next Word From FIFO2
FIFO2 FULL
LOW
LOW
LOW
HIGH
LOW
LOW
(1)
tPIR
tDS
tENH
tENH
tDH
ENB
B0 - B35
To FIFO2
Wriite
3022 drw 13
21
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2 . FIFO2 Write ( CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 13. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2 . FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 14. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full
AFA
CLKA
ENB
3022 drw 16
ENA
CLKB
12
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1 (D-Y1) Words in FIFO1
(1)
AEA
CLKB
ENA
3022 drw 15
ENB
CLKA 2
1
t
EN2S
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
(X2+1) Words in FIFO2X2 Words in FIFO2
(1)
22
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2 . FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 15. Timing for
AFBAFB
AFBAFB
AFB
when FIFO2 is Almost-Full
Figure 16. Timing for Mail1 Register and
MBF1MBF1
MBF1MBF1
MBF1
Flag
3022 drw 18
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
tENS1 tENH
tDS tDH
tPMF tPMF
tEN tMDV tPMR
tENS2 tENH
tDIS
W1 (Remains valid in Mail1 Register after read)FIFO1 Output Register
tENS1
tENS2
tENS2
tENH
tENH
tENH
AFB
CLKB
ENA
3022 drw 17
ENB
CLKA
12
tSKEW2
tENS2 tENH
tPAF
tENS2 tENH
tPAF
[D-(Y2+1)] Words in FIFO2 (D-Y2) Words in FIFO2
(1)
23
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Figure 17. Timing for Mail2 Register and
MBF2MBF2
MBF2MBF2
MBF2
Flag
3022 drw19
CLKB
ENB
B0-B35
MBB
CSB
W/RB
CLKA
MBF2
CSA
MBA
ENA
A0-A35
W/RA
W1
tENH
tDH
tPMF tPMF
tENS2 tENH
tDIS
tEN tMDV
tPMR
FIFO2 Output Register
W1 (Remains valid in Mail 2 Register after read)
tENH
tENH
tENH
tDS
tENS1
tENS1
tENS2
tENS2
24
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Figure 18. Load Circuit and Voltage Waveforms
NOTE:
1. Includes probe and jig capacitance.
3022 drw 20
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
1.1 k Ω
5 V
680 Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3 V
1.5 V 1.5 V
1.5 V
1.5 V
≈
OH
OV
≈
GND
OH
OL
1.5 V 1.5 V
1.5 V 1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
25
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages please contact your sales office.
XXXXXX
Device Type
X XX X X
Power Speed Package Process/
Temperature
Range
X
BLANK
3022 drw 21
Commercial (0°C to +70°C)
Commercial Only Clock Cycle Time (tCLK)
Speed in Nanoseconds
PF
PQF
12
15
L
723622
723632
723642
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Low Power
256 x 36 x 2 ⎯ SyncBiFIFO
™
512 x 36 x 2 ⎯ SyncBiFIFO
™
1,024 x 36 x 2 ⎯ SyncBiFIFO
™
GGreen
DATASHEET DOCUMENT HISTORY
10/04/2000 pgs. 1 through 25, except pages 35.
03/21/2001 pgs. 6 and 7.
08/01/2001 pgs. 1, 6, 8, 9 and 25.
12/18/2001 pg. 23.
02/05/2009 pgs. 1 and 25.
