_______________General Description
The MAX196/MAX198 multirange, 12-bit data-acquisi-
tion systems (DAS) require only a single +5V supply for
operation, yet convert analog signals at their inputs up
to ±10V (MAX196) and ±4V (MAX198). These systems
provide six analog input channels that are indepen-
dently software programmable for a variety of ranges:
±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196;
±VREF, ±VREF/2, 0V to +VREF, and 0V to +VREF/2 for
the MAX198. This range switching increases the effec-
tive dynamic range to 14 bits and provides the flexibility
to interface ±12V, ±15V, and 4mA to 20mA powered
sensors to a single +5V system. In addition, these con-
verters are fault protected to ±16.5V; a fault condition
on any channel will not affect the conversion result of
the selected channel. Other features include a 5MHz
bandwidth track/hold, 100ksps throughput rate, soft-
ware-selectable internal/external clock, internal/external
acquisition control, 12-bit parallel interface, and internal
4.096V or external reference.
Two programmable power-down modes (STBYPD,
FULLPD) provide low-current shutdown between con-
versions. In STBYPD mode, the reference buffer
remains active, eliminating start-up delays.
The MAX196/MAX198 employ a standard microproces-
sor (µP) interface. A three-state data I/O port is config-
ured to operate with 16-bit data buses, and data-
access and bus-release timing specifications are com-
patible with most popular µPs. All logic inputs and out-
puts are TTL/CMOS compatible.
These devices are available in 28-pin DIP, wide SO,
SSOP (55% smaller in area than wide SO), and ceramic
SB packages. For 8+4 bus interface, see the MAX197
and the MAX199 data sheets. An evaluation kit will be
available after December 1995 (MAX196EVKIT-DIP).
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features
♦12-Bit Resolution, 1/2LSB Linearity
♦Single +5V Supply Operation
♦Software-Selectable Input Ranges:
±10V, ±5V, 0V to +10V, 0V to +5V (MAX196)
±VREF, ±VREF/2, 0V to +VREF, 0V to +VREF/2
(MAX198)
♦Internal 4.096V or External Reference
♦Fault-Protected Input Multiplexer
♦6 Analog Input Channels
♦6µs Conversion Time, 100ksps Sampling Rate
♦Internal or External Acquisition Control
♦Two Power-Down Modes
♦Internal or External Clock
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
________________________________________________________________
Maxim Integrated Products
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
VDD
WR
RD
INT
REF
AGND
REFADJ
CH5
CH4
CH3
CH2
CH1
CH0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
CS
CLK
DIP/SO/SSOP/Ceramic SB
TOP VIEW
MAX196
MAX198
__________________Pin Configuration
Call toll free 1-800-722-8266 for free samples or literature.
19-0435; Rev 0; 9/95
PART
MAX196ACNI
MAX196BCNI
MAX196ACWI 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
EVALUATION KIT
AVAILABLE
______________Ordering Information
MAX196BCWI 0°C to +70°C 28 Wide SO
Functional Diagram appears at end of data sheet.
Ordering Information continued at end of data sheet.
MAX196ACAI 0°C to +70°C 28 SSOP
MAX196BCAI 0°C to +70°C 28 SSOP
Aperture Jitter
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (VDD + 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD + 0.3V)
CH0–CH5 to AGND ..........................................................±16.5V
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX196_C_ I/MAX198_C_ I .................................0°C to +70°C
MAX196_E_ I/MAX198_E_ I...............................-40°C to +85°C
MAX196_MYI/MAX198_MYI.............................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX196A/MAX198A
Internal CLK mode/internal acquisition
control (Note 4)
External CLK mode/external acquisition control
External CLK mode/external acquisition control
50kHz, VIN = ±5V (MAX196) or ±4V (MAX198)
(Note 3)
Up to the 5th harmonic
Bipolar
MAX196B/MAX198B
Unipolar
MAX196A/MAX198A
CONDITIONS
10
ps<50 ns15Aperture Delay
dB-86Channel-to-Channel Crosstalk
dB80SFDRSpurious-Free Dynamic Range
dB-85 -78THDTotal Harmonic Distortion
dB
70
LSB
±1/2
INLIntegral Nonlinearity
Bits12Resolution
±0.5 LSB
±0.1
Channel-to-Channel Offset
Error Matching
±10
±5
±1 LSB±1DNLDifferential Nonlinearity
LSB
±3
Offset Error ±5
UNITSMIN TYP MAXSYMBOLPARAMETER
Bipolar
Unipolar
5ppm/°C
3
Gain Temperature Coefficient
(Note 2)
±10
±7 LSB
±7
Gain Error
(Note 2) ±10
MAX196B/MAX198B 69
SINADSignal-to-Noise + Distortion Ratio
ns
Bipolar
Unipolar
Bipolar
MAX196B/MAX198B
MAX196B/MAX198B
Unipolar MAX196B/MAX198B
MAX196B/MAX198B
MAX196A/MAX198A
MAX196A/MAX198A
MAX196A/MAX198A
MAX196A/MAX198A
ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX196) or ±4.096Vp-p (MAX198), fSAMPLE = 100ksps)
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
MAX198
MAX196
MAX198
MAX196
-600 360
IIN -1200 720 µA
±VREF/2 range
±VREF range
±5V range -1200 10
±10V range
-600 10
Bipolar
Input Voltage Range
(see Table 3) VIN -10 10
-5 5
MAX196
-VREF VREF
-VREF/2 VREF/2
MAX198
Bipolar
MAX196
MAX198
0V to 5V or 0V to VREF/2 range
0V to 10V or 0V to VREF range
±5V or ±VREF/2 range
±10V or ±VREF range
Buffer Voltage Gain 1.6384 V/V
REFADJ Adjustment Range ±1.5 %With recommended circuit (Figure 1)
Capacitive Bypass at REF 4.7 µF
REFADJ Output Voltage 2.465 2.500 2.535 V
Load Regulation 10 mV0mA to 0.5mA output current (Note 6)
0V
REF
0V
REF/2
Unipolar
Input Resistance ∆VIN
∆IIN 21 kΩ
16
360
Unipolar
Input Current
720
Bipolar
0V to 5V range 0.1 10
0V to 10V range
Unipolar
2.5
Small-Signal Bandwidth
5
MHz
PARAMETER SYMBOL MIN TYP MAX UNITS
2.5
-3dB
rolloff
1.25
010
V
05
Track/Hold Acquisition Time 3 µs
Input Capacitance 40 pF
REF Output Voltage VREF 4.076 4.096 4.116 V
REF Output Tempco
(Contact Maxim Applications for
guaranteed temperature drift
specifications)
15 ppm/°C
Output Short-Circuit Current 30 mA
CONDITIONS
(Note 5)
TA= +25°C
MAX196_C/MAX198_C
fCLK = 2.0MHz
TC VREF 40MAX196_M/MAX198_M 30MAX196_E/MAX198_E
ANALOG INPUT
INTERNAL REFERENCE
Input Capacitance
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
V2.4 4.18Input Voltage Range
µA
400
Input Current VREF =
4.18V 1
VVDD - 50mV
REFADJ Threshold for
Buffer Disable
Normal, or STANDBY power-down mode kΩ10
Input Resistance FULL power-down mode 5 MΩ
Normal, or STANDBY
power-down mode
FULL power-down mode
Internal acquisition 3.0 5.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONS
FULL power-down mode (Note 7)
5
µs
3.0
tACQI
Acquisition Time
LSB
±0.1 ±1/2
PSRR
Power-Supply Rejection Ratio
(Note 8)
3.0
tACQE
External CLK µs
V4.75 5.25VDD
Supply Voltage
6.0
tCONV
Conversion Time Internal CLK, CCLK = 100pF 6.0 7.7 10.0
To 0.1mV REF bypass
capacitor fully discharged ms
8
Reference Buffer Settling
60 120
60
Normal mode, bipolar ranges
700 850
Normal mode, unipolar ranges
UNITSMIN TYP MAXSYMBOLPARAMETER
STANDBY power-down mode
mA
18
IDD
Supply Current 610
µA
Internal reference ±1/2
CCLK = 100pF MHz1.25 1.56 2.00fCLK
Internal Clock Frequency 0.1 2.0fCLK
External Clock Frequency Range MHz
External CLK
Internal CLK
Power-up (Note 10) µs200
Bandgap Reference
Start-Up Time
External CLK ksps
100
Throughput Rate Internal CLK, CCLK = 100pF 62
CREF = 4.7µF
CREF = 33µF
CIN 15 pF(Note 5)
Input Leakage Current IIN ±10 µAVIN = 0V or VDD
Input Low Voltage VINL 0.8 V
Input High Voltage VINH 2.4 V
POWER REQUIREMENTS
TIMING
REFERENCE INPUT (buffer disabled, reference input applied to REF pin)
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS) (Note 11)
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 5
Note 1: Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR= tF= 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX; unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
Three-State Output Capacitance COUT 15 pF(Note 5)
Output High Voltage VOH VDD - 1 VVDD = 4.75V, ISOURCE = 1mA
Output Low Voltage VOL 0.4 VVDD = 4.75V, ISINK = 1.6mA
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
DIGITAL OUTPUTS (D11–D0, INT)
RD Low to Output Data Valid tDO 120 nsFigure 2, CL= 100pF (Note 12)
Data Valid to WR Setup
Data Valid to WR Hold tDH 0 ns
tDS 60 ns
CLK to WR Setup Time
CLK to WR Hold Time tCWH 50 ns
tCWS 100 ns
CS to RD Setup Time
CS to RD Hold Time tCSRH 0 ns
tCSRS 0 ns
CS to WR Setup Time
CS to WR Hold Time tCSWH 0 ns
tCSWS 0 ns
WR Pulse Width tWR 80 ns
PARAMETER SYMBOL MIN TYP MAX UNITS
CS Pulse Width tCS 80 ns
RD Low to INT High Delay tINT1 120 ns
RD High to Output Disable tTR
CONDITIONS
70 ns(Note 13)
10.0 1 10 100
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
10.5
MAX196/8-3
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.0
11.5
12.0 fSAMPLE = 100kHz
-0.150 0 1000 3000
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
-0.050
0.250
MAX196/8-1
DIGITAL CODE
INTEGRAL NONLINEARITY (LSB)
2000 4000
0.150
0.050
0
-0.100
0.200
0.100
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
4.100
4.080-55 -35 45 105 125
TEMPERATURE (°C)
VREF (V)
-15 525 65
85
4.095
4.090
4.085
REFERENCE OUTPUT VOLTAGE (VREF)
vs. TEMPERATURE
MAX196/8-4
REFADJ
AV = 1.6384
REF
+2.5V
INTERNAL
REFERENCE
MAX196/8-6
0.10-70 -50 50 110 130
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING (LSB)
-30 -10 10 30 70 90
0.20
0.16
0.14
0.12
0.18
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX196/8-5
-70 -50 50 110 130
TEMPERATURE (°C)
PSRR (LSB)
-30 -10 10 30 70 90
0.2
0.4
-0.2
-0.4
-0.6
0
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
100Hz
120Hz
V
DD
= 5V ±0.25V
0.33
0.27-70 -50 50 110 130
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING (LSB)
-30 -10 10 30 70 90
0.32
0.30
0.29
0.28
0.31
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE
MAX196/8-7
0
-120 05025
FFT PLOT
-100
-60
-40
-20
FREQUENCY (kHz)
AMPLITUDE (dB)
-80
fTONE = 10kHz
fSAMPLE = 100kHz
MAX196/8-2
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Digital GroundDGND28 +5V Supply. Bypass with 0.1µF capacitor to AGND.VDD
27
In the internal acquisition mode, when CSis low, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR
starts an acquisition, and a second rising edge on WRends acquisition and starts a conversion cycle.
WR26
PIN
Chip Select, active lowCS2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,
place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical
with CCLK = 100pF.
CLK1
FUNCTIONNAME
100k 510k
24k
REFADJ
+5V
0.01µF
MAX196
MAX198
Figure 1. Reference-Adjust Circuit
3k
3k
DOUT
DOUT
+5V
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
CLOAD CLOAD
Figure 2. Load Circuits for Enable Time
_______________Detailed Description
Converter Operation
The MAX196/MAX198 multirange, fault-tolerant ADCs
use successive approximation and internal input
track/hold (T/H) circuitry to convert an analog signal to
a 12-bit digital output. The 12-bit parallel-output format
provides easy interface to microprocessors (µPs).
Figure 3 shows the MAX196/MAX198 in the simplest
operational configuration.
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode and unipolar mode (MAX196 only), a low-
impedance input source, which settles in less than
1.5µs, is required to maintain conversion accuracy at
the maximum conversion rate.
When the MAX198 is configured for unipolar mode, the
input does not need to be driven from a low-impedance
source. The acquisition time (tAZ) is a function of the
source output resistance (RS), the channel input resis-
tance (RIN), and the T/H capacitance.
Three-State Digital I/O, D11 = MSBD11–D03–14 Analog GroundAGND15 Analog Input ChannelsCH0–CH516–21
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to VDD when using an external reference at the REF pin.
REFADJ22
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF23
INT goes low when conversion is complete and output data is ready.INT24 If CS is low, a falling edge on RD will enable a read operation on the data bus.RD25
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
8 _______________________________________________________________________________________
Acquisition time is calculated as follows:
For 0V to VREF: tAZ = 9 x (RS+ RIN) x 16pF
For 0V to VREF/2: tAZ = 9 x (RS+ RIN) x 32pF
where RIN = 7kΩand tAZ is never less than 2µs (0V to
VREF range) or 3µs (0V to VREF/2 range).
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second
WR rising edge with D5 = 0 (see
External Acquisition
section).
Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
Figure 4 shows the equivalent input circuit. The full-
scale input voltage depends on the voltage at the refer-
ence (VREF). The MAX196 uses a scaling factor, which
allows input voltage ranges of ±10V, ±5V, 0V to +10V,
or 0V to +5V with a 4.096V voltage reference (Table 1).
Program the desired range by setting the appropriate
control bits (D3, D4) in the control byte (Tables 2 and
3). The MAX198 does not use a scaling factor, so its
input voltage range directly corresponds with the refer-
ence voltage. It can be programmed for input voltages
of ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2 (Table
3). When an external reference is applied at REFADJ,
the voltage at REF is given by VREF = 1.6384 x VREFADJ
(2.4V < VREF < 4.18V).
The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with VDD = 0V, the input resistive network provides
current-limiting that adequately protects the device.
Digital Interface
Input data (control byte) and output data are multi-
plexed on a three-state parallel interface. This parallel
I/O can easily be interfaced with a µP. CS, WR, and RD
control the write and read operations. CS is the stan-
dard chip-select signal, which enables a µP to address
the MAX196/MAX198 as an I/O port. When high, it dis-
ables the WR and RD inputs and forces the interface
into a high-Z state.
DGND
VDD
REF
REFADJ
INT
CH5
CH4
CH3
CH2
CH1
CH0
AGND
28
27
23 4.7µF4.7µF
0.01µF 0.01µF
+5V
OUTPUT STATUS
22
24
21
20
19
18
17
16
1
25
µP
CONTROL
INPUTS 26
2
3
4
CLK
RD
WR
CS
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
100pF
µP DATA BUS
15
5
6
7
8
9
10
11
12
13
14
ANALOG
INPUTS
MAX196
MAX198
Figure 3. Operational Diagram
5.12k
R2
R1
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
ON
CHOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX196) OR 5.12kΩ (MAX198)
R2 = 8.67kΩ (MAX196) OR ∞ (MAX198)
Figure 4. Equivalent Input Circuit
RANGE (V)
ZERO SCALE
(V) -FULL SCALE +FULL SCALE
0 to +5 0 — VREF x 1.2207
0 to +10 0 — VREF x 2.4414
±5 — -VREF x 1.2207 VREF x 1.2207
±10 — -VREF x 2.4414 VREF x 2.4414
Table 1. Full Scale and Zero Scale
(MAX196 only)
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 9
Table 2. Control-Byte Format
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)
PD1 PD0 ACQMOD RNG BIP A2 A1 A0
Table 4. Clock and Power-Down Selection
PD1 PD0 DEVICE MODE
0 0 Normal Operation / External Clock Mode
0 1 Normal Operation / Internal Clock Mode
1 0 Standby Power-Down (STBYPD); clock mode
is unaffected
1 1 Full Power-Down (FULLPD); clock mode is
unaffected
Table 3. Range and Polarity Selection
BIP RNG INPUT RANGE (V)
(MAX196)
0 0 0 to 5
0 1 0 to 10
1 0 ±5
1 1 ±10
Table 5. Channel Selection
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5
0 0 0 ∗
0 0 1 ∗
0 1 0 ∗
0 1 1 ∗
1 0 0 ∗
1 0 1 ∗
BIT NAME DESCRIPTION
7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 4).
5 ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
4 RNG Selects the full-scale voltage magnitude at the input (Table 3).
3 BIP Selects unipolar or bipolar conversion mode (Table 3).
2, 1, 0 A2, A1, A0 These are address bits for the input mux to select the “on” channel (Table 5).
INPUT RANGE (V)
(MAX198)
0 to VREF/2
0 to VREF
±VREF/2
±VREF
MAX196/MAX198
Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 2 shows the control-
byte format.
Output Data Format
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When reading
the output data, CS and RD must be low.
How to Start a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX196/
MAX198 for either a unipolar or bipolar input range. A
write pulse (WR + CS) can either start an acquisition inter-
val or initiate a combined acquisition plus conversion. The
sampling interval occurs at the end of the acquisition
interval. The ACQMOD bit in the input control byte offers
two options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Writing a new control byte during a conversion cycle will
abort the conversion and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte with
the ACQMOD bit cleared (ACQMOD = 0). This causes
the write pulse to initiate an acquisition interval whose
duration is internally timed. Conversion starts when this
six-clock-cycle acquisition interval (3µs with fCLK =
2MHz) ends (see Figure 5).
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-down
mode bits (PD0, PD1) can assume new values on the
second write pulse (see
Power-Down Mode
section).
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the
device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when con-
version is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
10 ______________________________________________________________________________________
tCS
tCSWS tWR
tACQI tCONV
tDH
tDS
tINT1
tD0 tTR
HIGH-ZHIGH-Z
tCSRS tCSRH
CS
WR
D7–D0
INT
RD
DOUT
ACQMOD ="0"
DATA VALID
CONTROL
BYTE
tCSWH
Figure 5. Conversion Timing Using Internal Acquisition Mode
Clock Modes
The MAX196/MAX198 operate with either an internal or
an external clock. Control bits (D6, D7) select either
internal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, external clock mode is selected.
Internal Clock Mode
Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 =
1. A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required for
proper operation. Operating at clock frequencies lower
than 100kHz will cause a voltage droop across the hold
capacitor, and subsequently degrade performance.
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
______________________________________________________________________________________ 11
tCS
tCSWS tWR tACQI tCONV
tDH
tDS
tINT1
tD0 tTR
tCSHW
tCSRS tCSRH
ACQMOD = "1"
CS
WR
D7–D0
INT
RD
DOUT
ACQMOD = "0"
DATA VALID
CONTROL
BYTE
CONTROL
BYTE
Figure 6. Conversion Timing Using External Acquisition Mode
2000
00 50 250 350
500
CLOCK PIN CAPACITANCE (pF)
INTERNAL CLOCK PERIOD (ns)
100 150 200 300
1500
1000
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
12 ______________________________________________________________________________________
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
tCWS
tCWH
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "0"
ACQMOD = "0"
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
tDH
tDH tCWH
tCWS
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "1"
ACQMOD = "1" ACQMOD = "0"
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
__________Applications Information
Power-On Reset
At power-up, the internal power-on reset circuitry sets
INT high and puts the device in normal operation/exter-
nal clock mode. This state is selected to keep the inter-
nal clock from loading the external clock driver when
the part is used in external clock mode.
Internal or External Reference
The MAX196/MAX198 can operate with either an inter-
nal or external reference. An external reference can be
connected to either the REF pin or the REFADJ pin
(Figure 9).
To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD. Using the REFADJ input elimi-
nates the need to buffer the reference externally. When
the reference is applied at REFADJ, bypass REFADJ with
a 0.01µF capacitor to AGND.
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.
Internal Reference
The internally trimmed 2.50V reference is gained
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
At REF and REFADJ, the input impedance is a mini-
mum of 10kΩfor DC currents. During conversions, an
external reference at REF must be able to deliver
400µA DC load currents, and must have an output
impedance of 10Ωor less. If the reference has higher
output impedance or is noisy, bypass it close to the
REF pin with a 4.7µF capacitor to AGND.
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).
Power-Down Mode
To save power, you can put the converter into low-
current shutdown mode between conversions. Two
programmable power-down modes are available:
STBYPD and FULLPD. Select STBYPD or FULLPD by
programming PD0 and PD1 in the input control byte.
When power-down is asserted, it becomes effective
only after the end of conversion. In all power-down
modes, the interface remains active and conversion
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
______________________________________________________________________________________ 13
REF
10k
2.5V
26 4.096V
4.7µF
CREF
0.01µF
25REFADJ
AV = 1.638
MAX196
MAX198
Figure 9a. Internal Reference
REF
10k
2.5V
26
4.7µF
CREF
2.5V
25REFADJ
AV = 1.638
0.01µF
MAX196
MAX198
4.096V
Figure 9c. The external reference overdrives the internal refer-
ence.
REF
VDD
10k
2.5V
26 4.096V
4.7µF
CREF
25REFADJ
AV = 1.638
MAX196
MAX198
Figure 9b. External Reference, Reference at REF
MAX196/MAX198
results may be read. Input overvoltage protection is
active in all power-down modes. The device returns to
normal operation on the first WR falling edge during
write operation.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.
However, in FULLPD mode, only the bandgap refer-
ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversions and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows
conversion to begin immediately after power-down
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci-
tor at an 80mV/ms slew rate, and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
currents of 470µA, using the recommended 33µF
capacitor value.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX196/MAX198 down after each conversion
without requiring any start-up time on the next conversion.
Transfer Function
Output data coding for the MAX196/MAX198 is binary
in unipolar mode with 1LSB = (FS / 4096) and twos-
complement binary in bipolar mode with 1LSB = [(2 x
|FS|) / 4096]. Code transitions occur halfway between
successive-integer LSB values. Figures 10 and 11
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
(FS) values, refer to Table 1.
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
14 ______________________________________________________________________________________
OUTPUT CODE
INPUT VOLTAGE (LSB)
0FS
FS - 3/2 LSB
1 LSB =
FULL-SCALE
TRANSITION
123
11... 111
11... 110
11... 101
00... 011
00... 010
00... 001
00... 000
FS
4096
Figure 10. Unipolar Transfer Function
OUTPUT CODE
INPUT VOLTAGE (LSB)
0V +FS - 1 LSB
1 LSB =
-FS
011... 111
011... 110
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
2FS
4096
Figure 11. Bipolar Transfer Function
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best
system performance. For best performance, use a
ground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Digital
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi-
ble. Connect the logic grounds directly to the supply
ground. Bypass VDD with 0.1µF and 4.7µF capacitors
to AGND to minimize high- and low-frequency fluctua-
tions. If the supply is excessively noisy, connect a 5Ω
resistor between the supply and VDD, as shown in
Figure 12.
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
______________________________________________________________________________________ 15
VDD
GND
DGND
DGNDAGND
+5V
+5V
SUPPLY
R* = 5Ω
DIGITAL
CIRCUITRY
4.7µF
0.1µF
MAX196
MAX198
**
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
_________________________________________________________Functional Diagram
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
12
10k
12
8
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
SIGNAL
CONDITIONING
BLOCK
&
OVERVOLTAGE
TOLERANT
MUX
CONTROL LOGIC
&
LATCHES
REF REFADJ
+2.5V
REFERENCE
D0–D11
12-BIT DATA BUS
CH5
CH4
CH3
CH2
CH1
CH0
CLK
CS
WR
RD
INT VDD
AGND
DGND
MAX196
MAX198
AV =
1.638
COMP
SUCCESSIVE-
APPROXIMATION
REGISTER
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND
___________________Chip Topography
CH5
REFADJ
INT
RD
0.231"
(5.870mm)
0.144"
(3.659mm)
D2 CH0CH1D0
D1 AGND
CH4
CH3
CH2
VCC
VDD WRDGND
CLKD11
CS
D10
D9
D8
D7
D6
D5
D4
D3
REF
_Ordering Information (continued)
28 Narrow Ceramic SB**-55°C to +125°CMAX196BMYI 28 Narrow Ceramic SB**-55°C to +125°CMAX196AMYI 28 SSOP-40°C to +85°CMAX196BEAI 28 SSOP-40°C to +85°CMAX196AEAI 28 Wide SO-40°C to +85°CMAX196BEWI
Dice*0°C to +70°CMAX196BC/D PIN-PACKAGETEMP. RANGEPART
* Dice are specified at T
A
= +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
28 Wide SO
28 Narrow Plastic DIP
28 Narrow Plastic DIP-40°C to +85°C
-40°C to +85°C
-40°C to +85°CMAX196AEWI
MAX196BENI
MAX196AENI
28 Narrow Ceramic SB**-55°C to +125°CMAX198BMYI 28 Narrow Ceramic SB**-55°C to +125°CMAX198AMYI 28 SSOP-40°C to +85°CMAX198BEAI 28 SSOP-40°C to +85°CMAX198AEAI 28 Wide SO-40°C to +85°CMAX198BEWI
28 Wide SO
28 Wide SO
28 Narrow Plastic DIP0°C to +70°C
0°C to +70°C
0°C to +70°CMAX198BCWI
MAX198ACWI
MAX198ACNI
28 Wide SO
28 Narrow Plastic DIP
28 Narrow Plastic DIP-40°C to +85°C
-40°C to +85°C
-40°C to +85°CMAX198AEWI
MAX198BENI
MAX198AENI Dice*
28 SSOP
28 SSOP0°C to +70°C
0°C to +70°C
0°C to +70°CMAX198BC/D
MAX198BCAI
MAX198ACAI
28 Narrow Plastic DIP0°C to +70°CMAX198BCNI
