CS4360-DZZR - Cirrus Logic, Inc. - Datasheet.Directory

Cirrus Logic, Inc. 2004

http://www.cirrus.com

CS4360

24-Bit, 192 kHz 6-channel D/A Converter

Features



24-bit Conversion



102 dB Dynamic Range



-91 dB THD+N



Low Clock Jitter Sensitivity



Digital Volume Control with Soft Ramp

– 119 dB Attenuation

– 1-dB Step Size

– Zero Crossing Click-Free Transitions



ATAPI Mixing



Logic Levels Between 5.0 V and 1.8 V



+3.3 V or +5 V Analog Power Supply



116 mW with 3.3 V Supply



Popguard Technology® for Control of Clicks

and Pops

Description

The CS4360 is a complete 6-channel digital-to-analog

system including digital interpolation, fourth-order delta-

sigma digital-to-analog conversion, digital de-emphasis,

volume control, channel mixing and analog filtering. The

advantages of this architecture include: ideal differential

linearity, no distortion mechanisms due to resistor

matching errors, no linearity drift over time and tempera-

ture, and a high tolerance to clock jitter.

The CS4360 accepts data at audio sample rates from

4 kHz to 200 kHz, consumes very little power, and oper-

ates over a wide power supply range. These features are

ideal for cost-sensitive, multi-channel audio systems in-

cluding DVD players, A/V receivers, set-top boxes,

digital TVs and VCRs, mini-component systems, and

mixing consoles.

ORDERING INFORMATION

CS4360-KZ -10 to 70 °C 28-pin TSSOP

CS4360-KZZ -10 to 70 °C Lead Free 28-pin TSSOP

CS4360-DZZ -40 to 85 °C Lead Free 28-pin TSSOP

CDB4360 Evaluation Board

Control Port External

Mute Control

RST

Volume ControlInterpolation Filter Analog Filter AOUT A1

∆Σ

DAC

Mixer

Volume Control

∆Σ

DAC Analog Filter AO UTB1

Interpolation Filter

Volume ControlInterpolation Filter Analog Filter AOUT A2

∆Σ

DAC

Mixer

Volume Control

∆Σ

DAC Analog Filter AO UTB2

Interpolation Filter

Volume ControlInterpolation Filter Analog Filter AOUT A3

∆Σ

DAC

Mixer

Volume Control

∆Σ

DAC Analog Filter AO UT B3

Interpolation Filter

MCLK

Serial Port

LRCK

SCLK

SD I N1

SD I N2

SD I N3

DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS VLC

2VQ

FILT+

GND

VLS

MUTEC1 MUTEC2 MUTEC3

GND

JUL ‘04

DS517F2

CS4360
2DS517F2
TABLE OF CONTENTS
1.  PIN DESCRIPTION ................................................................................................................... 5
2.  TYPICAL CONNECTION DIAGRAM   ...................................................................................... 7
3.  CHARACTERISTICS AND SPECIFICATIONS  ........................................................................ 8
SPECIFIED OPERATING CONDITIONS ................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8
ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) .................................................................. 9
ANALOG CHARACTERISTICS (CS4360-DZZ) ..................................................................... 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE......................... 13
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................... 16
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 17
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE ....................................... 18
DC ELECTRICAL CHARACTERISTICS................................................................................. 19
DIGITAL INPUT CHARACTERISTICS ................................................................................... 19
DIGITAL INTERFACE SPECIFICATIONS.............................................................................. 20
THERMAL CHARACTERISTICS AND SPECIFICATIONS .................................................... 20
4.  APPLICATIONS ...................................................................................................................... 21
4.1 Sample Rate Range/Operational Mode Select  ................................................................ 21
4.1.1 Stand-alone Mode ............................................................................................... 21
4.1.2 Control Port Mode  ............................................................................................... 21
4.2 System Clocking  .............................................................................................................. 21
4.3 Digital Interface Format .................................................................................................... 22
4.3.1 Stand-alone Mode ............................................................................................... 22
4.3.2  Control Port Mode  .............................................................................................. 23
4.4 De-emphasis Control  ....................................................................................................... 23
4.4.1 Stand-alone Mode ............................................................................................... 24
4.4.2 Control Port Mode  ............................................................................................... 24
4.5 Recommended Power-up Sequence  ............................................................................... 24
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. 
To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub-
ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con-
ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi-
bility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement
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under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS").  CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT-
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OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
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MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER.  IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc.  All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor. Purchase of I²C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies con-
veys a license under the Philips I²C Patent Rights to use those components in a standard I²C system.

CS4360
DS517F2 3
5.1 Stand-alone Mode ............................................................................................... 24
5.2 Control Port Mode ............................................................................................... 24
6 Popguard® Transient Control  .......................................................................................... 24
6.1 Power-up ............................................................................................................. 24
6.2 Power-down  ........................................................................................................ 24
6.3 Discharge Time ................................................................................................... 25
7 Mute Control  .................................................................................................................... 25
8 Grounding and Power Supply Arrangements  .................................................................. 25
8.1 Capacitor Placement ........................................................................................... 25
8.2 Power Supply Sections ....................................................................................... 25
9 Control Port Interface  ...................................................................................................... 25
9.1 Memory Address Pointer (MAP)  ......................................................................... 26
9.1a INCR (Auto Map Increment)  ................................................................ 26
9.1b MAP0-3 (Memory Address Pointer) ..................................................... 26
9.2 I²C Mode  ............................................................................................................. 26
9.2a I²C Write ............................................................................................... 26
9.2b I²C Read ............................................................................................... 27
9.3 SPI Mode  ............................................................................................................ 27
9.3a SPI Write .............................................................................................. 28
 REGISTER QUICK REFERENCE  ......................................................................................... 29
 REGISTER DESCRIPTIONS .................................................................................................. 30
1 Mode Control 1 (address 01h) ......................................................................................... 30
1.1 Auto-mute (AMUTE) Bit 7 ....................................................................................... 30
1.2 Digital Interface Format (DIF) Bit 4-6 ...................................................................... 30
1.3 De-emphasis Control (DEM) Bit 2-3........................................................................ 31
1.4 Functional Mode (FM) Bit 0-1.................................................................................. 31
2  Invert Signal (address 02h) ............................................................................................. 31
2.1 Invert Signal Polarity (INV_xx) Bit 0-5..................................................................... 31
3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
Mixing Control Pair 3 (Channels A3 & B3) (address 05h)............................................. 31
3.1 ATAPI Channel Mixing and Muting (atapi) Bit 0-3................................................... 32
4 Volume Control (addresses 06h - 0Bh)  ........................................................................... 33
4.1 MUTE (MUTE) Bit 7 ................................................................................................ 33
4.2 VOLUME CONTROL (xx_VOL) Bit 0-6................................................................... 33
5 Mode Control 2 (address 0Dh) ......................................................................................... 33
5.1 Soft Ramp and Zero Cross CONTROL (SZC) Bit 6-7............................................. 33
5.2 Control Port Enable (CPEN) Bit 5 ........................................................................... 34
5.3 Power Down (PDN) Bit 4......................................................................................... 34
5.4 Popguard® Transient Control (POPG) Bit 3 ........................................................... 34
5.5 Freeze Controls (FREEZE) Bit 2............................................................................. 35
5.6 Master Clock DIVIDE ENABLE (MCLKDIV) Bit 1 ................................................... 35
5.7 Single Volume Control (SNGLVOL) Bit 0................................................................ 35
6 Revision Register (Read Only) (address 0Dh)  ................................................................ 35
6.1 Revision Indicator (REV) [Read Only] Bit 0-3 ......................................................... 35
 PARAMETER DEFINITIONS .................................................................................................. 36
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 36
Dynamic Range ...................................................................................................................... 36
Interchannel Isolation ............................................................................................................. 36
Interchannel Gain Mismatch................................................................................................... 36
Gain Error ............................................................................................................................... 36
Gain Drift ................................................................................................................................ 36

CS4360
4DS517F2
8.  REFERENCES ........................................................................................................................ 36
9.  PACKAGE DIMENSIONS ....................................................................................................... 37
LIST OF FIGURES
Figure 1. Typical Connection Diagram  .......................................................................................... 7
Figure 2. Output Test Load  ......................................................................................................... 10
Figure 3. Maximum Loading ........................................................................................................ 10
Figure 4. Single-speed Stopband Rejection ................................................................................ 14
Figure 5. Single-speed Transition Band  ...................................................................................... 14
Figure 6. Single-speed Transition Band (Detail)  ......................................................................... 14
Figure 7. Single-speed Passband Ripple  .................................................................................... 14
Figure 8. Double-speed Stopband Rejection  .............................................................................. 14
Figure 9. Double-speed Transition Band ..................................................................................... 14
Figure 10. Double-speed Transition Band (Detail)  ........................................................................ 15
Figure 11. Double-speed Passband Ripple ................................................................................... 15
Figure 12. Serial Mode Input Timing  .............................................................................................16
Figure 13. Control Port Timing - I²C Mode  .................................................................................... 17
Figure 14. Control Port Timing - SPI Mode  ................................................................................... 18
Figure 15. Left Justified up to 24-Bit Data  .....................................................................................23
Figure 16. I2S, up to 24-Bit Data  ................................................................................................... 23
Figure 17. Right Justified Data  ...................................................................................................... 23
Figure 18. De-emphasis Curve  ..................................................................................................... 23
Figure 19. I²C Write  ....................................................................................................................... 27
Figure 20. I²C Read ....................................................................................................................... 27
Figure 21. SPI Write ...................................................................................................................... 28
Figure 22. ATAPI Block Diagram  ..................................................................................................32
LIST OF TABLES
Table 1. CS4360 Stand-alone Operational Mode............................................................................. 21
Table 2. CS4360 Control Port Operational Mode............................................................................. 21
Table 3. Single-speed Mode Standard Frequencies ........................................................................ 21
Table 4. Double-speed Mode Standard Frequencies....................................................................... 21
Table 5. Quad-speed Mode Standard Frequencies ......................................................................... 22
Table 6. Digital Interface Format - Stand-alone Mode...................................................................... 22
Table 7. Power Supply Control Sections ..........................................................................................25
Table 8. Digital Interface Formats - Control Port Mode .................................................................... 30
Table 9. ATAPI Decode.................................................................................................................... 32
Table 10. Example Digital Volume Settings ..................................................................................... 33

CS4360

DS517F2 5

1. PIN DESCRIPTION

VLS MUTEC1

SDIN1 AOUTA1

SDIN2 AOUTB1

SDIN3 MUTEC2

SCLK AOUTA2

LRCK AOUTB2

MCLK VA

VD GND

GND AOUTA3

RST AOUTB3

DIF1/SCL/CCLK MUTEC3

DIF0/SDA/CDIN VQ

M1/AD0/CS FILT+

VLC M2

821

12 17

14 15

CS4360

6DS517F2

Pin Name #Pin Description

VLS 1Serial Audio Interface Power (Input) - Positive power for the serial audio interface.

SDIN1

SDIN2

SDIN3

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

SCLK 5Serial Clock (Input) - Serial clock for the serial audio interface.

LRCK 6Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio

data line.

MCLK 7Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VD 8Digital Power (Input) - Positive power supply for the digital section.

GND 9

Ground (Input)

RST 10 Reset (Input) - Powers down device and resets all internal resisters to their default settings.

VLC 14 Control Port Interface Power (Input) - Positive power for the control port interface.

FILT+ 16 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.

VA 22 Analog Power (Input) - Positive power supply for the analog section.

AOUTB3

AOUTA3

AOUTB2

AOUTA2

AOUTB1

AOUTA1

Analog Outputs (Output) - The full scale analog line output level is specified in the An alo g Ch ara cteri s -

tics and Specifications table.

MUTEC3

MUTEC2

MUTEC1

Mute Control (Output) - Control signal for optional mute circuit.

Control Port

Definitions

SCL/CCLK 11 Serial Control Port Clock (Input) - Serial clock for the control port interface.

SDA/CDIN 12 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Input for SPI data.

AD0/CS 13 Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip

in SPI mode.

Stand-Alone

Definitions

DIF1

DIF0

Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial

Clock and Serial Audio Data.

Mode Selection (Input) - Determines the operational mode of the device.

CS4360

DS517F2 7

2. TYPICAL CONNECTION DIAGRAM

Digital

Audio

Source

VLS

GND

CS4360

MCLK

AOUTA1

0.1 µF +1 µF

+3.3 V to +5 V *

µ C/

Mode

Configuration 13

SDIN1

DIF1/SCL/CCLK

DIF0/SDA/CDIN

M1/AD0/CS

RST

MUTEC1

OPTIONAL

MUTE

CIRCUIT

3.3 µF 0.1 µF

AOUTA1

C = 4πFs(R 560)

FILT+

15 M2

LRCK

SCLK

SDIN3

SDIN2

3.3 µF 10 k ΩC

560 Ω

3.3 µF 10 kΩC

560 Ω

26 AOUTB1

OPTIONAL

MUTE

CIRCUIT

AOUTA2

3.3 µF 10 kΩC

560 Ω

3.3 µF 10 k ΩC

560 Ω

23 AOUTB2

OPTIONAL

MUTE

CIRCUIT

AOUTA3

3.3 µF 10 k ΩC

560 Ω

3.3 µF 10 kΩC

560 Ω

19 AOUTB3

AOUTB1

0.1 µ F3.3 µF

AOUTA2

MUTEC2

AOUTB2

AOUTA3

MUTEC3

AOUTB3

0.1 µF

1 µF

GND

0.1 µF

+1.8 V to +5 V *

VLC

0.1 µF

+1.8 V to +5 V *

RL+560

+3.3 V to VA *

* All supplies can be tied together

Figure 1. Typical Connection Diagram

CS4360

8DS517F2

3. CHARACTERISTICS AND SPECIFICATIONS

Typical performance characteristics are derived from measurements taken at TA = 25°C. Min/Max performance

characteristics and specifications are guaranteed over the operating temperature and voltages.

SPECIFIED OPERATING CONDITIONS GND = 0 V; all voltages with respect to GND.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to GND. Operation beyond these limits may result in permanent damage to

the device. Normal operation is not guaranteed at these extremes.

Notes: 1. Nominal VD supply must be less than or equal to the nominal VA supply.

2. Any pin except supplies.

Parameters Symbol Min Typ Max Units

DC Power Supply

Analog 3.3 V Nominal

(Note 1) 5.0 V Nominal

VA 3.0

4.5

3.3

3.6

5.5

Digital 2.5 V Nominal

(Note 1) 3.3 V Nominal

5.0 V Nominal

VD 2.25

3.0

4.5

2.5

3.3

2.75

3.6

5.5

Serial Audio Interface 1.8 V Nominal

2.5 V Nominal

3.3 V Nominal

5.0 V Nominal

VLS 1.7

2.25

3.0

4.5

1.8

2.5

3.3

1.9

2.75

3.6

5.5

Control Port Interface 1.8 V Nominal

2.5 V Nominal

3.3 V Nominal

5.0 V Nominal

VLC 1.7

2.25

3.0

4.5

1.8

2.5

3.3

1.9

2.75

3.6

5.5

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial Audio Interface

Control Port Interface

VLS

VLC

-0.3

6.0

Input Current (Note 2) Iin -±10mA

Digital Input Voltage Serial Audio Interface

Control Port Interface

VIND_S

VIND_C

-0.3

VLS+0.4

VLC+0.4

Ambient Operating Temperature (power applied) TA-55 125 °C

Storage Temperature Tstg -65 150 °C

CS4360

DS517F2 9

ANALOG CHARACTERISTICS (CS4360-KZ/KZZ)

Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement

bandwidth is 10 Hz to 20 kHz; test load RL=10kΩ, CL = 10 pF (see Figure 2). All supplies = VA = 5.0 V or 3.3 V.

Notes: 3. One-half LSB of triangular PDF dither is added to data.

Parameter

5.0 V 3.3 V

Min Typ Max Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-86

-91

-74

-34

-86

Double-Speed Mode Fs = 96 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-86

-91

-74

-34

-86

Quad-Speed Mode Fs = 192 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-86

-91

-74

-34

-86

CS4360

10 DS517F2

ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) (Continued)

4. Refer to Figure 3.

Parameters Symbol Min Typ Max Units

Dynamic Performance for All Modes

Interchannel Isolation (1 kHz) - 102 - dB

DC Accuracy

Interchannel Gain Mismatch ICGM - 0.1 - dB

Gain Drift - ±100 - ppm/°C

Analog Output Characteristics and Specifications

Full Scale Output Voltage 0.60•VA 0.66•VA 0.72•VA Vpp

Output Impedance Zout - 100 - Ω

Minimum AC-Load Resistance (Note 4) RL-3-kΩ

Maximum Load Capacitance (Note 4) CL- 100 - pF

AOUTx

AGND

3.3 µF

out

RLCL

Figure 2. Output Test Load

100

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k

Ω

)

125

Figure 3. Maximum Loading

CS4360

DS517F2 11

ANALOG CHARACTERISTICS (CS4360-DZZ)

Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement

bandwidth is 10 Hz to 20 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 2). All supplies = VA = 5.0 V and 3.3 V.

Parameter

VA = 5.0 V VA = 3.3 V

Min Typ Max Min Typ Max Unit

Single-speed Mode Fs = 48 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-84

-91

-74

-34

-84

Double-speed Mode Fs = 96 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-84

-91

-74

-34

-84

Quad-speed Mode Fs = 192 kHz

Dynamic Range (Note 3)

unweighted

A-Weighted

40 kHz Bandwidth A-Weighted

102

100

Total Harmonic Distortion + Noise (Note 3)

0 dB

-20 dB

-60 dB

-91

-79

-39

-84

-91

-74

-34

-84

CS4360

12 DS517F2

ANALOG CHARACTERISTICS (CS4360-DZZ) (Continued)

Parameters Symbol Min Typ Max Units

Dynamic Performance for All Modes

Interchannel Isolation (1 kHz) - 102 - dB

DC Accuracy

Interchannel Gain Mismatch ICGM - 0.1 - dB

Gain Drift - ±100 - ppm/°C

Analog Output Characteristics and Specifications

Full Scale Output Voltage 0.60•VA 0.66•VA 0.72•VA Vpp

Output Impedance Zout - 100 - Ω

AC-load Resistance (Note 4) RL3- -kΩ

Load Capacitance (Note 4) CL--100pF

CS4360

DS517F2 13

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can

be referenced to the desired sample rate by multiplying the given characteristic by Fs.

Notes: 5. For Single-speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.

For Double-speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

6. De-emphasis is only available in Single-speed Mode.

Parameter Min Typ Max Unit

Single-Speed Mode (4 kHz to 50 kHz sample rates)

Passband

to -0.05 dB corner

to -3 dB corner

0.4535

0.4998

Frequency Response 10 Hz to 20 kHz -0.02 - +0.035 dB

StopBand 0.5465 - - Fs

StopBand Attenuation (Note 5) 50 - - dB

Group Delay - 9/Fs - s

De-emphasis Error (Relative to 1 kHz) (Note 6)

Control Port Mode Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

St and-al one Mode Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+0.2/-0.1

+0.05/-0.14

+0/-0.22

+1.5/-0

+0.05/-0.14

+0.2/-0.4

Double-Speed Mode (50 kHz to 100 kHz sample rates)

Passband

to -0.1 dB corner

to -3 dB corner

0.4621

0.4982

Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB

StopBand 0.577 - - Fs

StopBand Attenuation (Note 5) 55 - - dB

Group Delay - 4/Fs - s

Quad-Speed Mode - (100 kHz to 200 kHz sample rates)

Passband

to -3 dB corner 0 - 0.25 Fs

Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB

Group Delay - 1.5/Fs - s

CS4360

14 DS517F2

Figure 4. Single-speed Stopband Rejection Figure 5. Single-speed Transition Band

Figure 6. Single-speed Transition Band (Detail) Figure 7. Single-speed Passband Ripple

Figure 8. Double-speed Stopband Rejection Figure 9. Double-speed Transition Band

CS4360

DS517F2 15

Figure 10. Double-speed Transition Band (Detail) Figure 11. Double-speed Passband Ripple

CS4360

16 DS517F2

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Inputs: Logic 0 = GND, Logic 1 = VLS.

Parameters Symbol Min Max Units

MCLK Frequency 1.024 51.2 MHz

MCLK Duty Cycle 40 60 %

Input Sample Rate Single-speed Mode

Double-speed Mode

Quad-speed Mode

100

200

kHz

LRCK Duty Cycle 45 55 %

SCLK Pulse Width Low tsclkl 20 - ns

SCLK Pulse Width High tsclkh 20 - ns

SCLK Frequency Single-speed Mode

Double-speed Mode

128xFs

64xFs

Quad-speed Mode (MCLKDIV = 0) -Hz

Quad-speed Mode (MCLKDIV = 1) -Hz

SCLK rising to LRCK edge delay tslrd 20 - ns

SCLK rising to LRCK edge setup time tslrs 20 - ns

SDINx valid to SCLK rising setup time tsdlrs 20 - ns

SCLK rising to SDINx hold time tsdh 20 - ns

Figure 12. Serial Mode Input Timing

sclkh

slrs

slrd

sdlrs

tsdh

sclkl

SDINx

SCLK

LRCK

MCLK

-----------------

MCLK

-----------------

CS4360

DS517F2 17

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE

Inputs: Logic 0 = GND, Logic 1 = VLC

Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

9. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.

Parameter Symbol Min Max Unit

I²C Mode

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 7) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL and SDA trc, trc -1µs

Fall Time SCL and SDA tfc, tfc - 300 ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling (Note 8) tack - (Note 9) ns

56 F

-----------------

---

28 F

------------------

---------------

tbuf thdst

tlow thdd

thigh

tsud

Stop Start

SDA

SCL

tirs

RST

thdst

trc

tfc

tsust

tsusp

Start Stop

Repeated

trd tfd

tack

Figure 13. Control Port Timing - I²C Mode

CS4360

18 DS517F2

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)

Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

11. Data must be held for sufficient time to bridge the transition time of CCLK.

12. For fsclk < 1 MHz.

Parameter Symbol Min Max Unit

SPI Mode

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 10) tspi 500 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl -ns

CCLK High Time tsch -ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 11) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 12) tr2 - 100 ns

Fall Time of CCLK and CDIN (Note 12) tf2 - 100 ns

MCLK

-----------------

MCLK

-----------------

tr2 tf2

tdsu t

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 14. Control Port Timing - SPI Mode

CS4360

DS517F2 19

DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND.

Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each

speed mode, and open outputs, unless otherwise specified.

14. ILC measured with no external loading on pin 12 (SDA).

15. Power Down Mode is defined as RST = LO with all clocks and data lines held static.

16. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the

capacitance will also increase the PSRR.

DIGITAL INPUT CHARACTERISTICS GND = 0 V; all voltages with respect to GND.

Parameters Symbol Min Typ Max Units

Normal Operation (Note 13)

Power Supply Current VA = 5.0 V

VD = 5.0 V

VA = 3.3 V

VD = 3.3 V

VLS = 5.0 V

VLC = 5.0 V

VLS = 3.3 V

VLC = 3.3 V

(Note 14)

ILS

ILC

ILS

ILC

µA

Power Dissipation All Supplies = 5.0 V

All Supplies = 3.3 V

235

116

265

128

Power-down Mo de (Note 15)

Power Supply Current All Supplies = 5.0 V

All Supplies = 3.3 V

µA

Power Dissipation All Supplies = 5.0 V

All Supplies = 3.3 V

µW

All Modes of Operation

Power Supply Rejection Ratio (Note 16) 1 kHz

60 Hz

PSRR -

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

0.5•VA

250

0.01

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

250

0.01

kΩ

MUTEC Low-level Output Voltage - 0 - V

MUTEC High-level Output Voltage - VA - V

Maximum MUTEC Drive Current - 3 - mA

Parameters Symbol Min Typ Max Units

Input Leakage Current Iin --±10µA

Input Capacitance - 8 - pF

CS4360

20 DS517F2

DIGITAL INTERFACE SPECIFICATIONS GND = 0 V; all voltages with respect to GND.

THERMAL CHARACTERISTICS AND SPECIFICATIONS

Parameters Symbol Min Max Units

1.8 V Logic

High-level Input Voltage Serial Audio

Control Port

VIH

80%

VLS

VLC

Low-level Input Voltage Serial Audio

Control Port

VIL

-13%

13%

VLS

VLC

2.5 V Logic

High-level Input Voltage Serial Audio

Control Port

VIH

70%

VLS

VLC

Low-level Input Voltage Serial Audio

Control Port

VIL

-13%

13%

VLS

VLC

3.3 V Logic

High-level Input Voltage Serial Audio

Control Port

VIH

70%

VLS

VLC

Low-level Input Voltage Serial Audio

Control Port

VIL

-13%

13%

VLS

VLC

5.0 V Logic

High-level Input Voltage Serial Audio

Control Port

VIH

70%

VLS

VLC

Low-level Input Voltage Serial Audio

Control Port

VIL

-13%

13%

VLS

VLC

Parameters Symbol Min Typ Max Units

Package Thermal Resistance TSSOP (-KZ/KZZ & -DZZ) θJA -40-°C/Watt

Ambient Operating Temperature (Power Applied) -KZ/KZZ

-DZZ

TA-10

-40

+70

+85

°C

CS4360

DS517F2 21

4. APPLICATIONS

4.1 Sample Rate Range/Operational Mode Select

4.1.1 Stand-Alone Mode

The device operates in one of four operational modes determined by the Mode pins in Stand-alone mode.

Sample rates outside the specified range for each mode are not supported.

4.1.2 Control Port Mode

The device operates in one of three operational modes determined by the FM bits (see section 6.1.4) in

Control Port mode. Sample rates outside the specified range for each mode are not supported.

4.2 System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.

The LRCK, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK

according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio

sample rates and the required MCLK frequency, are illustrated in Tables 3-5.

Sample Rate

(kHz)

MCLK (MHz)

256x 384x 512x 768x 1024x*

32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

Table 3. Single-speed Mode Standard Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x 192x 256x 384x 512x*

64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

Table 4. Double-speed Mode Standard Frequencies

M2 M1 Input Sample Rate (FS)MODE

0 0 4 kHz - 50 kHz Single-Speed (without De-emphasis)

0 1 32 kHz - 48 kHz Single-Speed (with De-emphasis)

1 0 50 kHz - 100 kHz Double-Speed

1 1 100 kHz - 200 kHz Quad-Speed

Table 1. CS4360 Stand-Alone Operational Mode

FM1 FM0 Input Sample Rate (FS)MODE

0 0 4 kHz - 50 kHz Single-speed

0 1 50 kHz - 100 kHz Double-speed

1 0 100 kHz - 200 kHz Quad-speed

1 1 Reserved Reserved

Table 2. CS4360 Control Port Operational Mode

CS4360

22 DS517F2

*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Ch)

4.3 Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats in Stand-alone mode, as illustrated

in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.

4.3.1 Stand-Alone Mode

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship

between the LRCK, SCLK and SDIN, see Figures 15-17.

Sample Rate

(kHz)

MCLK (MHz)

64x 96x 128x 192x 256x*

176.4 11.2896 16.9344 22.5792 33.8688 45.1584

192 12.2880 18.4320 24.5760 36.8640 49.1520

Table 5. Quad-speed Mode Standard Frequencies

DIF1 DIF0 DESCRIPTION FORMAT FIGURE

Left Justified, up to 24-bit Data 016

I2S, up to 24-bit Data 115

Right Justified, 16-bit Data 217

Right Justified, 24-bit Data 317

Table 6. Digital Interface Format - Stand-alone Mode

CS4360

DS517F2 23

4.3.2 Control Port Mode

The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section

6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.

4.4 De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in

sample rate, Fs.

Notes: De-emphasis is only available in Single-speed Mode.

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LS B

Figure 15. Left Justified up to 24-Bit Data

LRCK

SCLK

Left Channel Right Channel

SDIN +3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB

LSB LSB

Figure 16. I2S, up to 24-Bit Data

LRCK

SCLK

Left Channel

SDIN +6 +5 +4 +3 +2+1+7-1 -2 -3 -4 -5LSB

Right Channel

MSB LSB +6 +5 +4 +3 +2+1+7-1 -2 -3 -4 -5

MSB LSB

Figure 17. Right Justified Data

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 18. De-emphasis Curve

CS4360

24 DS517F2

4.4.1 Stand-Alone Mode

The operational mode pins, M2 and M1, selects the 44.1 kHz de-emphasis filter. Please see section 4.1

for the desired de-emphasis control.

4.4.2 Control Port Mode

The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3

for the desired de-emphasis control.

4.5 Recommended Power-up Sequence

4.5.1 Stand-Alone Mode

1) Hold RST low until the power supply and configuration pins are stable, and the master and left/right

clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control

port is reset to its default settings and VQ will remain low.

2) Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-

alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK

cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.5.2 Control Port Mode

1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the

appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default

settings and VQ will remain low.

2) Bring RST high. The device will remain in a low power state with VQ low.

3) Load the desired register settings while keeping the PDN bit set to 1.

4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when

the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of pow-

er-up timing.

4.6 Popguard® Transient Control

The CS4360 uses a novel technique to minimize the effects of output transients during power-up and pow-

er-down. This technology, when used with external DC-blocking capacitors in series with the audio out-

puts, minimizes the audio transients commonly produced by single-ended single-supply converters. It is

activated inside the DAC when the RST pin or PDN bit is enabled/disabled and requires no other external

control, aside from choosing the appropriate DC-blocking capacitors.

4.6.1 Power-up

When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND.

Following a delay of approximately 1000 LRCK cycles, each output begins to ramp toward the quiescent

voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins. This

gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent

voltage, minimizing the power-up transient.

4.6.2 Power-down

To prevent transients at power-down, the device must first enter its power-down state. When this occurs,

audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their

place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge.

Once this charge is dissipated, the power to the device may be turned off and the system is ready for the

next power-on.

CS4360

DS517F2 25

4.6.3 Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-

fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will

occur when the audio outputs are initially clamped to GND. The time that the device must remain in the

power-down state is related to the value of the DC-blocking capacitance and the output load. For example,

with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

4.7 Mute Control

The Mute Control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1),

or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute

circuits to prevent the clicks and pops that can occur in any single-ended single supply system.

Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute

minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system

designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute

circuit. Please see the CDB4360 data sheet for a suggested mute circuit.

4.8 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4360 requires careful attention to power supply and ground-

ing arrangements if its potential performance is to be realized. Figure 1 shows the recommended power

arrangements, with VA, VD, VLS and VLC connected to clean supplies. If the ground planes are split be-

tween digital ground and analog ground, the GND pins of the CS4360 should be connected to the analog

ground plane.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted

coupling into the modulators. The CDB4360 evaluation board demonstrates the optimum layout and pow-

er supply arrangements.

4.8.1 Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be placed on each supply pin and referenced to analog ground.

4.8.2 Power Supply Sections

Each power supply pin provides power to specific sections of the CS4360. The logic voltage level for each

section must adhere to the corresponding power supply voltage setting. For example: If VLC = 1.8 V; VLS

= 3.3 V; VD = VA = 5 V; then the logic level for all mode configuration inputs must equal 1.8 V.

4.9 Control Port Interface

The control port is used to load all the internal register settings (see section 6). The operation of the control

port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer-

ence problems, the control port pins should remain static if no operation is required.

The control port operates in one of two modes: I²C or SPI.

Notes: MCLK must be applied during all I²C communication.

Pin #s Description Power Supply Reference

2, 3, 4, 5, 6, 7 Serial Audio Interface Inputs VLS

10, 11, 12, 13, 15 Mode Configuration Inputs VLC

Table 7. Power Supply Control Sections

CS4360

26 DS517F2

4.9.1 Memory Address Pointer (MAP)

The MAP byte precedes the control port register byte during a write operation and is not available again

until after a start condition is initiated. During a read operation the byte transmitted after the ACK will con-

tain the data of the register pointed to by the MAP (see sections 4.9.1a and 4.9.3 for write/read details).

4.9.1a INCR (Auto Map Increment)

The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is

set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP

will auto increment after each byte is written, allowing block reads or writes of successive registers.

Default = ‘0’

0 - Disabled

1 - Enabled

4.9.1b MAP0-3 (Memory Address Pointer)

Default = ‘0000’

4.9.2 I²C Mode

In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial

control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address

(001000[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the

device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI mode will be selected.

4.9.2a I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in section 3.

1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth

bit of the address byte is the R/W bit.

2) Wait for an acknowledge (ACK) from the device, then write to the memory address pointer, MAP. This

byte points to the register to be written.

3) Wait for an acknowledge (ACK) from the device, then write the desired data to the register pointed to

by the MAP.

4) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers

are written, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to repeat

the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP

condition to the bus.

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

CS4360

DS517F2 27

4.9.2b I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifi-

cations. During this operation it is first necessary to write to the device, specifying the appropriate register

through the MAP.

1) After writing to the MAP (see section 4.9.1), initiate a repeated START condition to the I²C bus fol-

lowed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting

of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.

2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the

contents of the register pointed to by the MAP. The MAP will contain the address of the last register

written to the MAP.

3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-

tinue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the

desired registers are read, initiate a STOP condition to the bus.

4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to repeat

the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP

condition to the bus.

4.9.3 SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 21 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the control port. When the device detects a high-to-low transition on the

AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

SDA

SCL

001000 AD0 W

Start

ACK MAP

1-8 ACK DATA

1-8 ACK

Stop

Figure 19. I²C Write

SDA

SCL

001000 AD0 W

Start

ACK MAP

1-8 ACK 001000 AD0 R

Repeated START

Aborted W RITE

ACK Data 1-8

(pointed to by MAP)

Data 1-8

(pointed to by MAP)

ACK

Stop

Figure 20. I²C Read

CS4360

28 DS517F2

4.9.3a SPI Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in section 3.

1) Bring CS low.

2) The address byte on the CDIN pin must then be 00100000.

3) Write to the memory address pointer, MAP. This byte points to the register to be written.

4) Write the desired data to the register pointed to by the MAP.

5) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers

are written, then bring CS high.

6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring

CS high, and repeat the procedure detailed from step 1. If no further writes to other registers are de-

sired, bring CS high.

MAP

MSB

LSB

DATA

byte 1 byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

0010000

Figure 21. SPI Write

CS4360

DS517F2 29

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

1h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

default 10000000

2h Invert Signal Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

default 00000000

3h Mixing Control P1 Reserved Reserved Reserved Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

default 00001001

4h Mixing Control P2 Reserved Reserved Reserved Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

default 00001001

5h Mixing Control P3 Reserved Reserved Reserved Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

default 00001001

6h Volume Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

default 00000000

7h Volume Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

default 00000000

8h Volume Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

default 00000000

9h Volume Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

default 00000000

0Ah Volume Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

default 00000000

0Bh Volume Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

default 00000000

0Ch Mode Control 2 SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL

default 10011000

0Dh Revision Indicator Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

default 0000XXXX

CS4360

30 DS517F2

6. REGISTER DESCRIPTIONS

Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise stated.

6.1 MODE CONTROL 1 (ADDRESS 01H)

6.1.1 AUTO-MUTE (AMUTE) BIT 7

Defaul t = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or 1. A single sample of non-static data will release the mute. Detection and muting

is done independently for each channel. The quiescent voltage on the output will be retained and the

Mute Control pin will become active during the mute period. The muting function is affected, similar

to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.

6.1.2 DIGITAL INTERFACE FORMAT (DIF) BIT 4-6

Default = 000 - Format 0 (Left Justified, up to 24-bit data)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the

Digital Interface Format and the options are detailed in Figures 15-17.

76543210

AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

10000000

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

000

Left Justified, up to 24-bit data 015

001

I2S, up to 24-bit data 116

010

Right Justified, 16-bit data 217

011

Right Justified, 24-bit data 317

100

Right Justified, 20-bit data 417

101

Right Justified, 18-bit data 517

110

Reserved --

111

Reserved --

Table 8. Digital Interface Formats - Control Port Mode

CS4360

DS517F2 31

6.1.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3

Defaul t = 00

00 - Disabled

01 - 44.1 kHz

10 - 48 kHz

11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-

sponse at 32-, 44.1- or 48-kHz sample rates. (See Figure 18.)

Note: De-emphasis is only available in Single-speed Mode.

6.1.4 FUNCTIONAL MODE (FM) BIT 0-1

Defaul t = 00

00 - Single-speed Mode (4- to 50-kHz sample rates)

01 - Double-speed Mode (50- to 100-kHz sample rates)

10 - Quad-speed Mode (100- to 200-kHz sample rates)

11 - Reserved

Function:

Selects the required range of input sample rates.

6.2 INVERT SIGNAL (ADDRESS 02H)

6.2.1 INVERT SIGNAL POLARITY (INV_XX) BIT 0-5

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits invert the signal polarity for each of their respective channels.

6.3 MIXING CONTROL PAIR 1 (CHANNELS A1 & B1) (ADDRESS 03H)

MIXING CONTROL PAIR 2 (CHANNELS A2 & B2) (ADDRESS 04H)

MIXING CONTROL PAIR 3 (CHANNELS A3 & B3) (ADDRESS 05H)

76543210

Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

00000000

76543210

Reserved Reserved Reserved Reserved PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0

00001001

CS4360

32 DS517F2

6.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-3

Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo)

Function:

The CS4360 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to

Table 9 and Figure 22 for additional information.

Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

0000 MUTE MUTE

0001 MUTE R

0010 MUTE L

0011 MUTE [(L+R)/2]

0100 R MUTE

0101 R R

0110 R L

0111 R [(L+R)/2]

1000 L MUTE

1001 L R

1010 L L

1011 L [(L+R)/2]

1100[(L+R)/2] MUTE

1101[(L+R)/2] R

1110[(L+R)/2] L

1111[(L+R)/2] [(L+R)/2]

Table 9. ATAPI Decode

A Channel

Volume

Control Aout

Aout

Left Channel

Audio Data

Right Channel

Audio Data

B Channel

Volume

Control

& Mute

Figure 22. ATAPI Block Diagram

CS4360

DS517F2 33

6.4 VOLUME CONTROL (ADDRESSES 06H - 0BH)

6.4.1 MUTE (MUTE) BIT 7

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output

will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero

Cross bits. The MUTEC pin will become active during the mute period if the Mute function is enabled

for both channels in the pair.

6.4.2 VOLUME CONTROL (XX_VOL) BIT 0-6

Default = 0

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1-dB increments

from 0 to -119 dB. Volume settings are decoded as shown in Table 10. The volume changes are im-

plemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB

are equivalent to enabling the MUTE bit.

6.5 MODE CONTROL 2 (ADDRESS 0DH)

6.5.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 6-7

Defaul t = 10

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp and Zero Cross

Function:

Immediate Change

When Immediate Change is selected all level changes will be implemented immediately in one step.

76543210

xx_MUTE xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

00000000

Binary Code Decimal Value Volume Setting

0001010 10 -10 dB

0010100 20 -20 dB

0101000 40 -40 dB

0111100 60 -60 dB

1011010 90 -90 dB

Table 10. Example Digital Volume Settings

76543210

SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL

10011000

CS4360

34 DS517F2

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will

occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur

after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally

ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock

periods.

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The

1/8 dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms

to 21.3 ms at 48 kHz sample rate) if the signal does not encounter zero crossings. The zero cross

function is independently monitored and implemented for each channel.

6.5.2 CONTROL PORT ENABLE (CPEN) BIT 5

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

The Control Port will become active and reset to the default settings when this function is enabled.

6.5.3 POWER DOWN (PDN) BIT 4

Defaul t = 1

0 - Disabled

1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, but the contents of the

control registers will be retained in this mode. The power-down bit defaults to ‘enabled’ on power-up

and must be disabled before normal operation in Control Port mode can occur.

6.5.4 POPGUARD® TRANSIENT CONTROL (POPG) BIT 3

Defaul t = 1

0 - Disabled

1 - Enabled

Function:

The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to

the quiescent voltage during power-on or power-off when this function is enabled. Please see section

4.6 for implementation details.

CS4360

DS517F2 35

6.5.5 FREEZE CONTROLS (FREEZE) BIT 2

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until

the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta-

neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

6.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) BIT 1

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all

other internal circuitry.

6.5.7 SINGLE VOLUME CONTROL (SNGLVOL) BIT 0

Defaul t = 0

0 - Disabled

1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. When enabled, the volume on all channels is determined by the

A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.

6.6 REVISION REGISTER (READ ONLY) (ADDRESS 0DH)

6.6.1 REVISION INDICATOR (REV) [READ ONLY] BIT 0-3

Defaul t = none

0001 - Revision A

0010 - Revision B

0011 - Revision C

etc.

Function:

This read-only register indicates the revision level of the device.

76543210

Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

0000XXXX

CS4360

36 DS517F2

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the spec-

ified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over

the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth

made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement

to full scale. This technique ensures that the distortion components are below the noise level and do not

affect the measurement. This measurement technique has been accepted by the Audio Engineering So-

ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8. REFERENCES

1) CDB4360 Evaluation Board Datasheet

2) “The I²C Bus Specification: Version 2.1” Philips Semiconductors, January 2000.

http://www.semiconductors.philips.com

CS4360

DS517F2 37

9. PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A-- --0.47-- --1.20

A1 0.002 0.004 0.006 0.05 0.10 0.15

A2 0.03150 0.035 0.04 0.80 0.90 1.00

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.378 BSC 0.382 BSC 0.386 BSC 9.60 BSC 9.70 BSC 9.80 BSC 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.029 0.50 0.60 0.75

∝0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

28L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

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