ATF-50189
2.4 GHz high-linearity second stage LNA/ driver using ATF-50189
Application Note 5106
Introduction
Avago Technologies’ ATF-50189 is a high linearity, medium
power, low noise E-pHEMT FET in a low cost surface mount
SOT89 package. It is suitable for high output IP3 LNA Q2
& Q3 stages or driver amplier in receiver or transmitter
designs, respectively. This short note highlights a 2.4 GHz
amplier that is suitable for adaptation into WLAN & ISM-
band products.
The ATF-50189 is packaged in an industry standard 4-lead
SOT-89. The package has two source leads with large sur-
face areas for ecient heat dissipation and low inductance
RF grounding.
This application note describes the use of the ATF-50189
in an extremely high dynamic range low noise amplier
(LNA) or buer amplier. The demo-board’s nominal per-
formance at 2.4 GHz are: - G = 12.8 dB and output P1dB =
25dBm. With some optimization of the DC & RF operating
conditions, an output intercept point of 45dBm can be
easily achieved. The input and output return losses are
better than 12 dB.
EPHEMT biasing
The enhancement mode technology provides superior per-
formance while allowing a dc grounded source amplier
with a single polarity power supply to be easily designed
and built. As opposed to a typical depletion mode PHEMT
where the gate must be made negative with respect to
the source for proper operation, an enhancement mode
PHEMT requires that the gate be made more positive than
the source for normal operation. Biasing an enhancement
mode PHEMT is as simple as biasing a bipolar transistor.
Instead of a 0.7V base to emitter voltage, the enhancement
mode PHEMT requires about a 0.6V potential between the
gate and source, Vgs, for the target drain current, Ids.
2
Figure 1. ATF-50189 2.4 GHz amplier
J1
J2
C1
C5
C3
C6
C2
C7
Q1
L1
L2
R1
R2 R3 R4 R5 R6 R7
C4
R8 R9
R10
C8
C9
L3
1
2
3
4
J3
Circuit Description
Biasing is accomplished by the use of a voltage divider
network consisting of R2 till R9. The voltage for the divider
is derived from the drain voltage which provides a form of
voltage feedback to help keep drain current constant.
At the input side, the combination of R1 and C7 enhance
Q1’s stability by terminating the gate resistively at low
frequency. L1 and C5 form the bias-decoupling network.
To reduce circuit loss, L1 should have the following char-
acteristics: - high unloaded Q, (QUL) and, operated below
its Self Resonant Frequency (SRF). C5 is dimensioned for
low reactance at the operating frequency (fopr). C1 & C2
form a capacitive tap matching for Q1’s input.
At the output, the ferrite bead chip, L3, works in conjunc-
tion with C8 to provide a resistive termination down to
the tens of MHz range. Although a resistor can provide
the same function, the power dissipation will be high. L2
and C6 form the bias-decoupling network. L2 and C6 are
chosen with the same criteria as L1 and C5. C3 & C4 form
a capacitive tap matching for Q1’s output.
3
R10
C9
J3
C7
C5
C3 C4
Q1
C8
L2
L3
L1
C1
R7 R6 R5 R4 R3 R2
J1 J2
R1
R8 R9
C6
C2
Demoboard
A generic demonstration board is available for quick proto-
typing and evaluation of the ATF-50189 in the VHF till 3 GHz
range. To replicate the material cost and space constraints
imposed on consumer products, the demoboard was de-
signed around low cost 0.031inch FR4 dielectric and small
surface mount components. Unfortunately, the signicant
high frequency losses in FR4 and low Q inductors detract
from the ATF-50189’s true performance potential. RF con-
nections to the demoboard are made via edge-mounted
microstrip to SMA coax transitions, J1 and J2.
Figure 2. Fully assembled demoboard with connectors and screws for heatsink
Figure 3. Component layout legend
The demoboard requires a single 4.8 V power supply. The
relatively high current (> 300 mA) drawn by the demoboard
can result in appreciable voltage drop over long supply
wires. The 4-pin connector, J3, permits 4-wire “Kelvin
contact” to be used for compensating for voltage drop in
conjunction with power supplies that support such func-
tion. If a conventional 2-wire supply is used, J3’s two outer
leads are left unconnected.
4
Figure 4. Positions of PCB trace cuts and distance between heatsink screws
11 mm
Cut trace for R10
Cut trace/s for Ids fine tune
Just like bipolar transistors, which exhibit a wide variation
in HFE within a particular part number, the ATF-50189’s
forward transconductance, gm, can vary from unit to unit.
The resistor network, R3~R7, on the demoboard allows
ne-tuning the gate bias, Vg, to cover the range of gm
variation. The individual PCB traces connecting to R3~R7
is cut one at a time until the demoboard draws the target
current range of 315 ± 15 mA. This results in Vds = 4.5 volt
and Ids = 280mA at the device-under-test, Q1.
The PCB trace leading to the positive supply needs to
be cut to t the resistor, R10. By connecting a voltmeter
across R10, the current drawn by the demoboard can be
monitored.
Table 1. Cut on R3~R7 traces versus initial demoboard current
Initial Idd (ma) Cut the trace/s connected to the resistor/s
Min Max R3 R4 R5 R6 R7
250 259 X X X X X
260 269 X X X X
270 279 X X X
280 289 X X
290 299 X
300 309
Two 3mm holes are provided for mounting a heat sink to
the ground plane on the opposite side of the demoboard.
Multiple via-holes around Q1, conduct heat to the ground
plane and heat sink interface. To reduce the interface’s ther-
mal resistance, apply a thin layer of silicon grease thermal
compound and tighten mounting screws with the correct
torque recommended by the heat sink manufacturer (usu-
ally slightly beyond nger tight).
5
Figure 5. Input matching & biasing networks
1
2
3
Figure 6. Measured trajectories of input impedance during the
various phases of matching
Linear Simulation
An RF simulator like ADS allows the input and output tuning
networks to be dimensioned with fewer “cut & try” itera-
tions. In addition, critical parameters such as stability and
gain can be predicted during the preliminary design stage.
For example, if simulation forecasts a strong tendency to
self-oscillation, the designer can pre-empt the problem
by incorporating additional stabilization components into
the preliminary circuit.
There is no need for preliminary characterization of the ATF-
50189 as the Touchstone formatted “s2p” les at various DC
biasing conditions and the ADS model can be downloaded
from the Avago Technologies website.
The correlation between simulation and measurement data
hinges on how detailed the equivalent circuit is. To strike a
reasonable compromise between circuit complexity and
simulation accuracy, only the components’ and PCB’s most
signicant rst-order parasitic are included. For example,
when a ground return path consists of many via-holes in
parallel, the resultant parasitic approximates ideal ground.
So, the via-holes can be excluded from the simulated circuit
without adversely aecting the accuracy.
The trajectories of the input match can be veried in a ‘step-
by-step’ manner as shown in the gure 6. The curve marked
as “1” represents the initial impedance at the position of the
rst matching component, C1. Subsequently, the addition
of C1 moves the input-side impedance along the constant
resistance circle to “2”. The shunt capacitor, C2, shifts point
“2” to the nal position “3” near to the Smith chart centre
whilst traveling along the constant admittance circle.
SLC
C2
C=1.8 pF
L=Ls
SLC
C5
C=15 pF
L=1.0 nH
VAR
VAR1
Ls =0.7 nH
W=1.44 mm
Eqn
Var
MS UB
MS ub1
TanD=0.02
Er=4.6
H=0.8 m m
MS ub
S_P aram
SP1
Step=0.05 GHz
Stop=2.9 GHz
Start=1.9 GHz
S-P ARAMETERS
COAX
TL9
L=7 mm
SLC
C1
C=1.5 pF
L=Ls
MLIN
TL3
L=2.5 mm
W=W
MLIN
TL1
L=1.1 mm
W=W
MLIN
TL7
L=8 mm
W=W
Term
Term 1
Z=50 O hm
Num =1
MLIN
TL2
L=1.5 mm
W=W
PLCQ
L1
C=0.3 pF
Ql=58.0
L=15 nH S2P
SNP 1
2
1
R e f
6
Figure 7. Output biasing and matching circuit
Figure 8. Measured trajectories of output impedance
1
2
3
The trajectories of the output match are shown in gure 8.
The curve marked as “1” represents the initial impedance at
the position of the rst output matching component, C3.
Subsequently, the addition of C3 moves the trace along the
constant resistance circle to “2”. The last matching compo-
nent, C4 nudges the curve along the constant admittance
circle to position “3” in the vicinity of the chart centre.
Output:
C2~TL4 17 + j22
SLC
C3
C=3.3 pF
L=Ls
SLC
C4
C=1 pF
L=Ls
PLCQ
L2
C=0.3 pF
Ql=58.0
L=15 nH
MLIN
TL8
L=7.5 mm
W=W
COAX
TL10
L=7 mm
MLIN
TL4
L=1.5 mm
W=W
MLIN
TL5
L=1.5 mm
W=W
MLIN
TL6
L=2.5 mm
W=W
Term
Term2
Z=50 Ohm
Num=2
SLC
C6
C=15 pF
L=1.0 nH
S2P
SNP1
2
1
Ref
7
Figure 9. Measured NF
dm1
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
2100 2200 2300 2400 2500 2600 2700
Freq (MHz)
NF (dB)
Measured performance
The demoboard performance was measured under the
following test conditions: - Vds = 4.5 V, Ids = 280 mA and
fc = 2.4 GHz.
The ATF-50189 is intended for either the driver amplier, or
the second-stage LNA slots, in transmit and receive chains,
respectively. So, matching for minimum noise gure (NF)
does not carry the same over-riding consideration as would
have been in a rst-stage LNA. However, good return loss
over a broad bandwidth is required in these two slots. In
line with this design goal, no attempt was made to tweak
the input match for the lowest NF.
While satisfying the requirement for good input match,
the NF can be improved, especially at higher microwave
frequencies, by reducing the inevitable circuit losses. The
low cost bias inductor at the input can be replaced with a
higher Q component, e.g. air-cored spring wound inductor.
The degradation in NF due to losses in the inductor can
be estimated from: -
u
lu
Q
QQ
loss −
=log20
Additionally, some reduction in input-side loss may be
obtained by changing the PCB material from FR4 to a lower
loss substrate, such as Rogers RO4350.
The ATF-50189 demoboard amplier exhibits good input
and output return losses. This minimizes detuning eects
when the amplier is cascaded with other stages in the
RF chain. For example, lters and aerials are especially
susceptible to the adverse eects of reective terminations.
Designing the amplier’s input and output for a close match
to 50Ω over the operating bandwidth, prevents unpredict-
able shift in the cascaded frequency response.
8
The 1 dB gain compression point, P1dB, indicates the upper limit of either the input or the output power level at which
saturation has started to occur. Non-linear eects become increasingly prominent as the amplier is driven to this
limit. Linear modulation schemes require the power to be backed o several dBs from this limit. The P1dB is measured
by progressively increasing the input power while noting the point when the gain became compressed by 1 dB. P1dB
is customarily referred to the output. The demoboard nominal output P1dB is approximately 25dBm.
Figure 11. Measured forward gain and reverse isolation
Figure 10. Measured input and output return loss
dB
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
dm2
S11 S22
Start: 1.900000 GHz Stop: 2.900000 GHz
06/12/2004 11:45:25 8753ES
The gain was approximately 12.8 dB in the middle of the pass-band. Slightly more gain can be obtained at the expense
of higher cost by using high Q inductors and/or a PCB substrate with lower loss.
Figure 12. Measured gain vs. output power
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
dm2
G
Start: 10.000000 dBm Stop: 30.000000 dBmPout
P1dB_dm2_2ele.SP~.spt
The intercept point is another measure of amplier linearity. The theoretical point when the fundamental signal and
the third order intermodulation distortion are of equal amplitude is the third order intercept point, IP3. The distortion
level at other power levels can be conveniently calculated from the amplier’s IP3 specication.
Two test signals spaced 5 MHz apart were used for evaluating the ATF-50189 demoboard. The large dynamic range
between the fundamental tones and the intermodulation products meant that the latter is barely above the spectrum
analyzer’s noise oor. To measure the 3rd order product amplitude accurately, a very narrow sweep span can be used to
improve the signal to noise ratio. As a tradeo from the narrow sweep span, only one fundamental and one 3rd order
intermodulation output signals can be practically displayed on the graph. Both the fundamental and intermodulation
tones are overlaid over the same frequency axis for amplitude comparison purpose. The IP3, referenced to the output,
can be calculated from: -
2
3
IM
PIP fund
∆
+=
where
fund
P
is the amplitude of either one of the fundamental outputs, and
IM∆
is the amplitude dierence between
the fundamental tones and the intermodulation products.
The output intercept point, OIP3, is approximately 45dBm.
10
Inadvertent coupling between the amplier’s input and output and component parasitic can lead to instability in
the upper microwave region. If there are pronounced gain peaks above its operating frequency, the amplier may
oscillate under certain operating conditions. In a wideband sweep test of the ATF-50189 demoboard up to 18 GHz,
no abnormal peak was recorded in the frequency response.
Figure 14. Stability (k) calculated from measured s-parameters
10
9
8
7
6
5
4
3
2
1
0
cl008-1#2 2-ele match
k
Start: 10.000000 MHz Stop: 6.000000 GHz
06/12/2004 11:45:25 8753ES
Like all microwave transistors, the ATF-50189 demonstrates increasing gain corresponding with decreasing frequency.
If this phenomenon is not tamed with the appropriate countermeasures, the amplier can break into self-oscillation
below its operating frequency - in the tens of MHz range. To assess the eectiveness of the low frequency circuit sta-
bilization described previously, the Rollett stability criterion was calculated from the measurement of the demoboard’s
s-parameters. The ATF-50189 demoboard exhibits unconditional stability (k >1) over the range of frequencies that an
8753 network analyzer is capable of operating. This reduces the design eort required to adapt the ATF-50189 into
the nal product.
Figure 13. Overlay of fundamental tone and intermodulation product
dBm
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
SoftPlot Measurement Presentation
imd2 f1
Start: 2.399754 GHz Stop: 2.400250 GHz
Res BW: 3 kHz Vid BW: 3 kHz Sweep: 140 ms
15/12/2004 17:26:44 HP8563Edm2_imd.spt
Figure 15. Wideband gain sweep
dB
60
50
40
30
20
10
0
-10
-20
-30
-40
dm1
G (dB)
Start: 1.000000 GHz Stop: 18.000000 GHz
widebandGSweep@dm1.spt
The nominal performance of the ATF-50189 demoboard
is summarized below: -
Table 1. Demoboard nominal performance values
Vsupply (V) 4.8
Isupply (mA) 320
Fc (MHz) 2400
G (dB) 12.8
RL in (dB) < -12
RL in (dB) < -12
k > 1
P1dB (dBm) 25
OIP3 (dBm) 45
12
Demoboard part list
The demoboard’s table of components is listed here. L3 is
a ferrite bead inductor in surface mount package.
Table 2. List of components
Pos. Value Size Description Manfacturer
C1 1.5 pF 0603 Murata
C2 1.8 pF 0603 Murata
C3 3.3 pF 0603 Murata
C4 1.0 pF 0603 Murata
C5 15 pF 0603 Murata
C6 15 pF 0603 Murata
C7 10 nF 0603 Murata
C8 10 nF 0603 Murata
C9 2.2 uF 0603 Murata
J1 SMA conn. 0.8mm Pcb edge mount
J2 SMA conn. 0.8mm Pcb edge mount
J3 4 pin header 2.54mm spacing
L1 15 nH 0603 Toko
L2 15 nH 0603 Toko
L3 60 R 0805 BLM21PG600SN1D Murata
Q1 ATF-50189 Agilent
R1 10 R 0603
R2 15 R 0603
R3 330 R 0603
R4 330 R 0603
R5 330 R 0603
R6 330 R 0603
R7 330 R 0603
R8 100 R 0603
R9 1 R 0603
R10 1 R 0603
Active bias
Passive biasing was used in this application note for
circuit simplicity and low component count. However,
active biasing is imperative for the ATF-50189 amplier in
volume production. Active biasing confers the ability to
hold the drain to source current constant over variations
in both gm and temperature. A very inexpensive method
of accomplishing this is to use two PNP bipolar transistors
arranged in a pseudo-current mirror conguration.
Due to resistors R1 and R3, this circuit is not acting as a true
current mirror, but if the voltage drop across R1 and R3 is
kept identical then it still displays some of the more useful
characteristics of a current mirror. For example, transistor
Q1 is congured with its base and collector tied together.
This acts as a simple PN junction, which helps temperature
compensate the Emitter-Base junction of Q2.
To calculate the values of R1, R2, R3, and R4 the following
parameters must be know or chosen rst:
Ids is the device drain-to-source current;
IR is the Reference current for active bias;
Vdd is the power supply voltage available;
Vds is the device drain-to-source voltage;
Vg is the typical gate bias;
Vbe1 is the typical Base-Emitter turn on voltage for Q1 &
Q2;
Therefore, resistor R3, which sets the desired device drain
current, is calculated as follows:
2
3
cds
dsdd
II
VV
R+
−
=
where, IC2 is chosen for stability to be 10 times the typical
gate current and also equal to the reference current IR.
The next three equations are used to calculate the rest of
the biasing resistors.
Note that the voltage drop across R1 must be set equal to
the voltage drop across R3, but with a current of IR.
R
dsdd
I
VV
R−
=1
(5)
R2 sets the bias current through Q1.
R
beds
I
VV
R1
2−
=
(6)
R4 sets the gate voltage for the FET.
2
4
C
g
I
V
R=
(7)
Thus, by forcing the emitter voltage (VE) of transistor Q1
equal to Vds, this circuit regulates the drain current similar
to a current mirror. As long as Q2 operates in the forward
active mode, this hold true. In other words, the Collector-
Base junction of Q2 must be kept reversed biased.
Vdd
L3
L2
C8
C3
C4
R5
C5
C6
Q1
R2
Q2
R3
R4
R1
R6
Vds
Vg
VE
14
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Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2799EN
AV01-0677EN - November 29, 2006