REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8131
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Low-Cost, High-Speed
Differential Driver
FUNCTIONAL BLOCK DIAGRAM
18
+DIN
–DIN
27NC
VOCM
36
V+ V–
45–OUT
+OUT
AD8131
NC = NO CONNECT
1.5kV
1.5kV
750V750V
FEATURES
High Speed
400 MHz –3 dB Full Power Bandwidth
2000 V/s Slew Rate
Fixed Gain of 2 with No External Components
Internal Common-Mode Feedback to Improve Gain
and Phase Balance
–60 dB @10 MHz
Separate Input to Set the Common-Mode Output
Voltage
Low Distortion
68 dB SFDR @ 5 MHz 200 ⍀ Load
Low Power 7.5 mA @ 3 V
Power Supply Range +2.7 V to ⴞ5 V
APPLICATIONS
Video Line Driver
Digital Line Driver
Low Power Differential ADC Driver
Differential In/Out Level Shifting
Single-Ended Input to Differential Output Driver
GENERAL DESCRIPTION
The AD8131 is a differential or single-ended input to differen-
tial output driver requiring no external components for a fixed
gain of 2. The AD8131 is a major advancement over op amps
for driving signals over long lines or for driving differential input
ADCs. The AD8131 has a unique internal feedback feature that
provides output gain and phase matching that are balanced to
–60 dB at 10 MHz, reducing radiated EMI and suppressing
harmonics. Manufactured on ADI’s next generation XFCB
bipolar process, the AD8131 has a –3 dB bandwidth of 400 MHz
and delivers a differential signal with very low harmonic distortion.
The AD8131 is a differential driver for the transmission of
high-speed signals over low-cost twisted pair or coax cables.
The AD8131 can be used for either analog or digital video
signals or for other high-speed data transmission. The AD8131
driver is capable of driving either Cat3 or Cat5 twisted pair or coax
with minimal line attenuation. The AD8131 has considerable
cost and performance improvements over discrete line driver
solutions.
The AD8131 can replace transformers in a variety of applica-
tions preserving low frequency and dc information. The AD8131
does not have the susceptibility to magnetic interference and
hysteresis of transformers, while being smaller in size, easier
to work with, and has the high reliability associated with ICs.
The AD8131’s differential output also helps balance the input
for differential ADCs, optimizing the distortion performance of
the ADCs. The common-mode level of the differential output
is adjustable by a voltage on the V
OCM
pin, easily level-shifting
the input signals for driving single supply ADCs with dual supply
signals. Fast overload recovery preserves sampling accuracy.
The AD8131 will be available in both SOIC and µSOIC packages
for operation over –40ⴗC to +85ⴗC.
FREQUENCY – MHz
BALANCE ERROR – dB
–8011000
–40
10 100
–20
–30
–50
–60
–70
DVOUT,dm = 2V p-p
DVOUT,cm/DVOUT, dm
VS = +5V
VS = 65V
Figure 1. Output Balance Error vs. Frequency
REV. 0
–2–
AD8131–SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
ⴞD
IN
to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
OUT
= 2 V p-p 400 MHz
–3 dB Small Signal Bandwidth V
OUT
= 0.2 V p-p 320 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 0.2 V p-p 85 MHz
Slew Rate V
OUT
= 2 V p-p, 10% to 90% 2000 V/µs
Settling Time 0.1%, V
OUT
= 2 V p-p 14 ns
Overdrive Recovery Time V
IN
= 5 V to 0 V Step 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 200 Ω–68 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 200 Ω–63 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–95 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–79 dBc
Third Harmonic V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 200 Ω–94 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 200 Ω–70 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–101 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–77 dBc
IMD 20 MHz, R
L,dm
= 800 Ω–54 dBc
IP3 20 MHz, R
L,dm
= 800 Ω30 dBm
Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz
Differential Gain Error NTSC, R
L,dm
= 150 Ω0.01 %
Differential Phase Error NTSC, R
L,dm
= 150 Ω0.06 Degrees
INPUT CHARACTERISTICS
Offset Voltage V
OS,dm
= V
OUT,dm
; V
DIN+
= V
DIN–
= V
OCM
= 0 V ±2±7mV
T
MIN
to T
MAX
Variation ±8µV/°C
V
OCM
= Float ±4mV
T
MIN
to T
MAX
Variation ±10 µV/°C
Input Resistance Single-Ended Input 1.125 kΩ
Differential Input 1.5 kΩ
Input Capacitance 1pF
Input Common-Mode Voltage –7.0 to +5.0 V
CMRR ∆V
OUT,dm
/∆V
IN,cm
; ∆V
IN,cm
= ±0.5 V –70 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆V
OUT
; Single-Ended Output –3.6 to +3.6 V
Linear Output Current 60 mA
Gain ∆V
OUT,dm
/∆V
IN,dm
; ∆V
IN,dm
= ±0.5 V 1.97 2 2.03 V/V
Output Balance Error ∆V
OUT,cm
/∆V
OUT,dm
; ∆V
OUT,dm
= 1 V –70 dB
V
OCM
to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth ∆V
OCM
= 600 mV 210 MHz
Slew Rate V
OCM
= –1 V to +1 V 500 V/µs
DC PERFORMANCE
Input Voltage Range ±3.6 V
Input Resistance 120 kΩ
Input Offset Voltage V
OS,cm
= V
OUT,cm
; V
DIN+
= V
DIN–
= V
OCM
= 0 V ±1.5 ±7mV
V
OCM
= Float ±2.5 mV
Input Bias Current 0.5 µA
V
OCM
CMRR [∆V
OUT,dm
/∆V
OCM
]; ∆V
OCM
= ±0.5 V –60 dB
Gain ∆V
OUT,cm
/∆V
OCM
; ∆V
OCM
= ±1 V 0.988 1 1.012 V/V
POWER SUPPLY
Operating Range ±1.4 ±5.5 V
Quiescent Current V
DIN+
= V
DIN–
= V
OCM
= 0 V 10.5 11.5 12.5 mA
T
MIN
to T
MAX
Variation 25 µA/°C
Power Supply Rejection Ratio ∆V
OUT,dm
/∆V
S
; ∆V
S
= ±1 V –70 –56 dB
OPERATING TEMPERATURE RANGE –40 +85 °C
Specifications subject to change without notice.
(@ 25ⴗC, VS = ⴞ5 V, VOCM = 0, G = 2, RL,dm = 200 ⍀, unless otherwise noted. Refer to
Figures 2 and 37 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
REV. 0 –3–
AD8131
SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
ⴞD
IN
to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
OUT
= 2 V p-p 385 MHz
–3 dB Small Signal Bandwidth V
OUT
= 0.2 V p-p 285 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 0.2 V p-p 65 MHz
Slew Rate V
OUT
= 2 V p-p, 10% to 90% 1600 V/µs
Settling Time 0.1%, V
OUT
= 2 V p-p 18 ns
Overdrive Recovery Time V
IN
= 5 V to 0 V Step 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 200 Ω–67 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 200 Ω–56 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–94 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–77 dBc
Third Harmonic V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 200 Ω–74 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 200 Ω–67 dBc
V
OUT
= 2 V p-p, 5 MHz, R
L,dm
= 800 Ω–95 dBc
V
OUT
= 2 V p-p, 20 MHz, R
L,dm
= 800 Ω–74 dBc
IMD 20 MHz, R
L,dm
= 800 Ω–51 dBc
IP3 20 MHz, R
L,dm
= 800 Ω29 dBm
Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz
Differential Gain Error NTSC, R
L,dm
= 150 Ω0.02 %
Differential Phase Error NTSC, R
L,dm
= 150 Ω0.08 Degrees
INPUT CHARACTERISTICS
Offset Voltage V
OS,dm
= V
OUT,dm
; V
DIN+
= V
DIN–
= V
OCM
= 2.5 V ±3±7mV
T
MIN
to T
MAX
Variation ±8µV/°C
V
OCM
= Float ±4mV
T
MIN
to T
MAX
Variation ±10 µV/°C
Input Resistance Single-Ended Input 1.125 kΩ
Differential Input 1.5 kΩ
Input Capacitance 1pF
Input Common-Mode Voltage –1.0 to +4.0 V
CMRR ∆V
OUT,dm
/∆V
IN,cm
; ∆V
IN,cm
= ±0.5 V –70 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆V
OUT
; Single-Ended Output 1.0 to 3.7 V
Linear Output Current 45 mA
Gain ∆V
OUT,dm
/∆V
IN,dm
; ∆V
IN,dm
= ±0.5 V 1.96 2 2.04 V/V
Output Balance Error ∆V
OUT,cm
/∆V
OUT,dm
; ∆V
OUT,dm
= 1 V –62 dB
V
OCM
to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth ∆V
OCM
= 600 mV 200 MHz
Slew Rate V
OCM
= 1.5 V to 3.5 V 450 V/µs
DC PERFORMANCE
Input Voltage Range 1.0 to 3.7 V
Input Resistance 30 kΩ
Input Offset Voltage V
OS,cm
= V
OUT,cm
; V
DIN+
= V
DIN–
= V
OCM
= 2.5 V ±5±12 mV
V
OCM
= Float ±10 mV
Input Bias Current 0.5 µA
V
OCM
CMRR [∆V
OUT,dm
/∆V
OCM
]; ∆V
OCM
= 2.5 V ± 0.5 V –60 dB
Gain ∆V
OUT,cm
/∆V
OCM
; ∆V
OCM
= 2.5 V ± 1 V 0.985 1 1.015 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current V
DIN+
= V
DIN
= V
OCM
= 2.5 V 9.25 10.25 11.25 mA
T
MIN
to T
MAX
Variation 20 µA/°C
Power Supply Rejection Ratio ∆V
OUT,dm
/∆V
S
; ∆V
S
= ±0.5 V –70 –56 dB
OPERATING TEMPERATURE RANGE –40 +85 °C
Specifications subject to change without notice.
(@ 25ⴗC, VS = 5 V, VOCM = 2.5 V, G = 2, RL,dm = 200 ⍀, unless otherwise noted. Refer to Figures 2 and 37
for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
REV. 0
AD8131
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8131 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5 V
V
OCM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 250 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above listed in the operational section of this
specification is not implied. Exposure to Absolute Maximum Ratings for any
extended periods may affect device reliability.
2
Thermal resistance measured on SEMI standard 4-layer board.
8-Lead SOIC θ
JA
= 121°C/W
8-Lead µSOIC θ
JA
= 142°C/W
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8131AR –40°C to +85°C 8-Lead SOIC SO-8
AD8131AR-REEL
AD8131AR-REEL7
AD8131ARM –40°C to +85°C 8-Lead µSOIC RM-8
AD8131ARM-REEL
AD8131ARM-REEL7
AD8131-EVAL Evaluation Board
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1–D
IN
Negative Input.
2V
OCM
Voltage applied to this pin sets the common-
mode output voltage with a ratio of 1:1. For
example, 1 V dc on V
OCM
will set the dc bias
level on +OUT and –OUT to 1 V.
3 V+ Positive Supply Voltage.
4 +OUT Positive Output. Note: the voltage at –D
IN
is
inverted at +OUT.
5 –OUT Negative Output. Note: the voltage at +D
IN
is inverted at –OUT.
6 V– Negative Supply Voltage.
7 NC No Connect.
8+D
IN
Positive Input
PIN CONFIGURATION
18
+D
IN
–D
IN
27NC
V
OCM
36
V+ V–
45–OUT
+OUT
AD8131
NC = NO CONNECT
1.5kV
1.5kV
750V750V
REV. 0
AD8131
–5–
AD8131
1500V
1500V
750V
750V
24.9V
49.9VRL,dm = 200V
Figure 2. Basic Test Circuit
FREQUENCY – MHz
GAIN – dB
12
–31 100010 100
9
6
3
0
VOUT = 2V p-p
VS = 65V
mSO
SOIC
Figure 5. Large Signal Frequency
Response
FREQUENCY – MHz
DISTORTION – dBc
–50
–100
07010 50
–60
–70
–80
–90
–110 20 30 40 60
RL,dm = 800V
VOUT,dm = 1V p-p
HD3 (VS = 3V)
HD2 (VS = 3V)
HD3 (VS = 5V)
HD2 (VS = 5V)
Figure 8. Harmonic Distortion vs.
Frequency
FREQUENCY – MHz
GAIN – dB
12
–31 100010 100
9
6
3
0
VOUT = 200mV p-p
VS = 65V
SOIC
mSO
Figure 3. Small Signal Frequency
Response
FREQUENCY – MHz
GAIN – dB
12
–31 100010 100
9
6
3
0
VOUT = 2V p-p
VS = 65V
VS = 5V
Figure 6. Large Signal Frequency
Response
FREQUENCY – MHz
DISTORTION – dBc
–50
–100
07010 50
–60
–70
–80
–90
–110 20 30 40 60
HD2 (VS = 65V)
HD3 (VS = 5V)
HD2 (VS = 5V)
HD3 (VS = 65V)
RL,dm = 800V
VOUT,dm = 2V p-p
–40
Figure 9. Harmonic Distortion vs.
Frequency
FREQUENCY – MHz
GAIN – dB
12
–31 100010 100
9
6
3
0
VOUT = 200mV p-p
VS = 5V
VS = 65V
Figure 4. Small Signal Frequency
Response
AD8131
1500V
1500V
750V
750V
24.9V
49.9V
LPF 300V
300V
HPF
ZIN = 50V
2:1 TRANSFORMER
Figure 7. Harmonic Distortion Test
Circuit (R
L,dm
= 800
Ω
)
DIFFERENTIAL OUTPUT VOLTAGE – V
p
-
p
DISTORTION – dBc
–65
–115 015
–75
–85
–95
–105
234 6
HD3 (F = 20MHz)
–55 VS = 65V
RL,dm = 800V
HD2 (F = 20MHz)
HD2 (F = 5MHz) HD3 (F = 5MHz)
Figure 10. Harmonic Distortion vs.
Differential Output Voltage
REV. 0
AD8131
–6–
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DISTORTION – dBc
–50
–100
0 3.5
0.5 2.5
–60
–70
–80
–90
–110 1.0 1.5 2.0 3.0
HD3 (F = 20MHz)
VS = 5V
RL,dm = 800V
HD3 (F = 5MHz)
HD2 (F = 20MHz)
HD2 (F = 5MHz)
4.0
Figure 11. Harmonic Distortion vs.
Differential Output Voltage
RLOAD – V
DISTORTION – dBc
–50
–100
700
500
–60
–70
–80
–90
–110
200 300 400 600
HD3 (F = 20MHz)
VS = 5V
VOUT,dm = 2V p-p
HD2 (F = 20MHz)
800
HD3 (F = 5MHz)
HD2 (F = 5MHz)
900 1000
Figure 14. Harmonic Distortion vs.
R
LOAD
FREQUENCY – MHz
INTERCEPT – dBm
45
20
50
30
40
35
30
25
1501020 40 607080
VS = 5V
VS = 65V
RL,dm = 800V
Figure 17. Third Order Intercept vs.
Frequency
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DISTORTION – dBc
–50
–100
1.5
1.0
–60
–70
–80
–90
–110
0.25 0.50 0.75 1.25
HD3 (F = 20MHz)
VS = 3V
RL,dm = 800V
HD2 (F = 20MHz)
1.75
HD3 (F = 5MHz)
HD2 (F = 5MHz)
Figure 12. Harmonic Distortion vs.
Differential Output Voltage
RLOAD – V
DISTORTION – dBc
–50
–100
700
500
–60
–70
–80
–90
–110
200 300 400 600
HD3 (F = 20MHz)
HD2 (F = 20MHz)
800
HD3 (F = 5MHz)
HD2 (F = 5MHz)
900 1000
VS = 3V
VOUT,dm = 1V p-p
Figure 15. Harmonic Distortion vs.
R
LOAD
1V 5ns
VS = 65V
VOUT,dm
VOUT–
V+DIN
VOUT+
Figure 18. Large Signal Transient
Response
RLOAD – V
DISTORTION – dBc
–50
–100
700
500
–60
–70
–80
–90
–110
200 300 400 600
HD3 (F = 20MHz)
VS = 65V
VOUT,dm = 2V p-p
HD2 (F = 20MHz)
800
HD3 (F = 5MHz)
HD2 (F = 5MHz)
900 1000
Figure 13. Harmonic Distortion vs.
R
LOAD
FREQUENCY – MHz
POUT – dBm
–50
–100
50
–60
–70
–80
–90
–110
49.5 50.5
fC = 50MHz
VS = 65V
RL,dm = 800V
0
–10
–20
–30
–40
10
Figure 16. Intermodulation Distortion
5ns
VS = 65V
40mV
VS = 5V
Figure 19. Small Signal Transient
Response
REV. 0
AD8131
–7–
5ns
VS = 65V
400mV
VS = 5V VOUT = 2V p-p
Figure 20. Large Signal Transient
Response
150V
AD8131
1500V
1500V
750V
750V
24.9V
49.9VCL
24.9V
24.9V
Figure 23. Capacitor Load Drive Test
Circuit
AD8131
1500V
1500V
750V
750V
24.9V
VOUT,dm VOUT,cm
100V
100V
Figure 26. CMRR Test Circuit
5ns
300mV
V
S
= 3V
V
OUT
= 1.5V p-p
Figure 21. Large Signal Transient
Response
1.25ns
400mV
C
L
= 0pF C
L
= 5pF C
L
= 20pF
V
S
= 65V
Figure 24. Large Signal Transient
Response for Various Capacitor
Loads
FREQUENCY – MHz
CMRR – dB
–8011000
–40
10 100
–20
–30
–50
–60
–70
DV
OUT
,dm/
DV
IN
,cm
DV
OUT
,cm/DV
IN
,cm
V
S
= 65V
V
IN
,cm = 1V p-p
Figure 27. CMRR vs. Frequency
4ns
VS = 65V
VOUT,dm
V+DIN
1V/DIV
2mV/DIV
Figure 22. 0.1% Settling Time
FREQUENCY – MHz
PSRR – dB
0
–8011000
–40
10 100
–10
–20
–30
–50
–60
–70
–PSRR
(VS = 65V)
+PSRR
(VS = 65V, +5V)
DVOUT,dm
DVS
Figure 25. PSRR vs. Frequency
FREQUENCY – MHz
IMPEDANCE – V
0.1110 100
100
10
1
SINGLE-ENDED OUTPUT
VS = 5V
VS = 65V
Figure 28. Single-Ended Z
OUT
vs.
Frequency
REV. 0
AD8131
–8–
AD8131
1500V
1500V
750V
750V
24.9V
49.9V
100V
100V
Figure 29. Output Balance Error Test
Circuit
TEMPERATURE – 8C
SUPPLY CURRENT – mA
15
7
–50 90
–30 50
13
11
9
5 –10 10 30 70
VS = 5V
VS = 65V
VS = 3V
Figure 32. Quiescent Current vs.
Temperature
FREQUENCY – MHz
GAIN – dB
11000
–40
10 100
–20
–30
–50
–70
VS = 65V
–60
DVOUT,dm
DVOCM
DVOCM = 2V p-p
DVOCM = 600mV p-p
–80
–90
Figure 35. V
OCM
CMRR vs. Frequency
FREQUENCY – MHz
BALANCE ERROR – dB
–8011000
–40
10 100
–20
–30
–50
–60
–70
DVOUT,dm = 2V p-p
DVOUT,cm/DVOUT,dm
VS = 65V
VS = 5V
Figure 30. Output Balance Error vs.
Frequency
FREQUENCY – Hz
NOISE – nV/ Hz
0.1k 100k
70
1k 10k
110
90
50
10
30
1M 10M 100M
VS = 65V
Figure 33. Voltage Noise vs.
Frequency
400mV 5ns
VS = 65V
VOCM = –1V TO +1V
VOUT,cm
Figure 36. V
OCM
Transient Response
TEMPERATURE – 8C
DIFFERENTIAL OFFSET VOLTAGE – mV
4
0
–50 90
–30 50
3
2
1
–1 –10 10 30 70
VS = 65V
VS = 5V
VS = +3V(VOCM = 0V)
Figure 31. Output Offset Voltage vs.
Temperature
FREQUENCY – MHz
GAIN – dB
100
0
110
6
3
–3
–9
VS = 65V
–6
DVOUT,cm
DVOCM
DVOCM = 2V p-p
DVOCM = 600mV p-p
1000
Figure 34. V
OCM
Gain Response
REV. 0
AD8131
–9–
OPERATIONAL DESCRIPTION
Definition of Terms
AD8131
+IN
–IN
RF
RF
RG
RG
+DIN
VOCM
–DIN
RL,dm
+OUT
VOUT,dm
–OUT
+OUT
–OUT
Figure 37. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
V
OUT,dm
= (V
+OUT
– V
–OUT
)
V
+OUT
and V
–OUT
refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node volt-
ages. The output common-mode voltage is defined as:
V
OUT,cm
= (V
+OUT
+ V
–OUT
)/2
Balance is a measure of how well differential signals are matched
in amplitude and exactly 180 degrees apart in phase. Balance
is most easily determined by placing a well-matched resistor
divider between the differential voltage nodes and comparing
the magnitude of the signal at the divider’s midpoint with the
magnitude of the differential signal. By this definition, output
balance is the magnitude of the output common-mode voltage
divided by the magnitude of the output differential-mode
voltage:
Output Balance Error V
V
OUT cm
OUT dm
=,
,
THEORY OF OPERATION
The AD8131 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on high open-loop gain and negative feed-
back to force these outputs to the desired voltages. The AD8131
behaves much like a standard voltage feedback op amp and
makes it easy to perform single-ended-to-differential conversion,
common-mode level-shifting, and amplification of differential
signals.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers,
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
The AD8131 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set by internal resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy
to arbitrarily set the output common-mode level. It is forced, by
internal common-mode feedback, to be equal to the voltage
applied to the V
OCM
input, without affecting the differential
output voltage.
The AD8131 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring external
components or adjustments. The common-mode feedback loop
forces the signal component of the output common-mode voltage
to be zeroed. The result is nearly perfectly balanced differential
outputs, of identical amplitude and exactly 180 degrees apart
in phase.
Analyzing an Application Circuit
The AD8131 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure
37. For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to V
OCM
can also be
assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Closed-Loop Gain
The differential mode gain of the circuit in Figure 37 can be
determined to be described by the following equation:
V
V
R
R
OUT dm
IN dm
F
G
,
,
==2
where R
F
= 1.5 kΩ and R
G
= 750 Ω nominally.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
GR
R
N
F
G
=+
=13
The total output referred noise for the AD8131, including the
contributions of R
F
, R
G
, and op amp, is nominally 25 nV/√Hz
at 20 MHz.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Figure
37, at +D
IN
and –D
IN
, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (R
IN
,
dm
)
between the inputs (+D
IN
and –D
IN
) is simply:
R
IN,dm
= 2 × R
G
= 1.5 k
Ω
In the case of a single-ended input signal (for example if –D
IN
is
grounded and the input signal is applied to +D
IN
), the input
impedance becomes:
REV. 0
AD8131
–10–
RR
R
RR
k
IN dm
G
F
GF
,.=−×+
(
)
=
1
2
1 125 Ω
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R
G
.
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8131 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –D
IN
in Figure 37 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
Setting the Output Common-Mode Voltage
The AD8131’s V
OCM
pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V–). Relying on this internal bias will
result in an output common-mode voltage that is within about
25 mV of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8131 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small resistor in series with the amplifier’s outputs as shown in
Figure 23.
APPLICATIONS
Twisted-Pair Line Driver
The AD8131 has on-chip resistors that provide for a gain-of-
two without any external parts. Several on-chip resistors are
trimmed to ensure that the gain is accurate, the common-mode
rejection is good, and the output is well balanced. This makes
the AD8131 very suitable as a single-ended-to-differential
twisted-pair line driver.
Figure 38 shows a circuit of an AD8131 driving a twisted-pair
line, like a Category 3 or Category 5 (Cat3 or Cat5), that are
already installed in many buildings for telephony and data com-
munications. The characteristic impedance of such transmission
lines is usually about 100 Ω. The outstanding balance of the
AD8131 output will minimize the common-mode signal and there-
fore the amount of EMI generated by driving the twisted pair.
The two resistors in series with each output terminate the line at
the transmit end. Since the impedances of the outputs of the
AD8131 are very low, they can be thought of as a short circuit,
and the two terminating resistors form a 100 Ω termination at
the transmit end of the transmission line. The receive end is
directly terminated by a 100 Ω resistor across the line.
This back-termination of the transmission line divides the out-
put signal by two. The fixed gain of two of the AD8131 will
create a net unity gain for the system from end to end.
In this case, the input signal is provided by a signal generator
with an output impedance of 50 Ω. This is terminated with a
49.9 Ω resistor near +D
IN
of the AD8131. The effective parallel
resistance of the source and termination is 25 Ω. The 24.9 Ω
resistor from –D
IN
to ground matches the +D
IN
source impedance
and minimizes any dc and gain errors.
If +D
IN
is driven by a low-impedance source over a short dis-
tance, such as the output of an op amp, then no termination
resistor is required at +D
IN
. In this case, the –D
IN
can be
directly tied to ground.
+3 V Supply Differential A-to-D Driver
Many newer A-to-D converters can run from a single +3 V
supply, which can save significant system power. In order to
increase the dynamic range at the analog input, they have differ-
ential inputs, which doubles the dynamic range with respect to a
single-ended input. An added benefit of using a differential
input is that the distortion can be improved.
The low distortion and ability to run from a single +3 V supply
make the AD8131 suited as an A-to-D driver for some 10-bit,
single supply applications. Figure 39 shows a schematic for a
circuit for an AD8131 driving an AD9203, a 10-bit, 40 MSPS
A-to-D converter.
The common mode of the AD8131 output is set at midsupply
by the voltage divider connected to V
OCM
, and ac bypassed with
a 0.1 µF capacitor. This provides for maximum dynamic range
between the supplies at the output of the AD8131. The 110 Ω
resistors at the AD8131 output, along with the shunt capacitors
form a one pole, low-pass filter for lowering noise and antialiasing.
Figure 40 shows an FFT plot that was taken from the combined
devices at an analog input frequency of 2.5 MHz and a 40 MSPS
sampling rate. The performance of the AD8131 compares very
favorably with a center-tapped transformer drive, which has
typically been the best way to drive this A-to-D converter. The
AD8131 has the advantage of maintaining dc performance,
which a transformer solution cannot provide.
Unity-Gain, Single-Ended-to-Differential Driver
If it is not necessary to offset the output common-mode volt-
age (via the V
OCM
pin), then the AD8131 can make a simple
unity-gain single-ended-to-differential amplifier that does not
require any external components. Figure 41 shows the schematic
for this circuit.
Referring to Figure 2, when –D
IN
is left floating, there is 100
percent feedback of +OUT to –IN via the internal feedback
resistor. This contrasts with the typical gain-of-two operation
where –D
IN
is grounded and one third of the +OUT is fed back
to –IN. The result is a closed-loop differential gain of one.
Upon careful observation, it can be seen that only +D
IN
and
V
OCM
are referenced to ground. It is the case that the ground
voltage at V
OCM
is the reference for this circuit. In this unity
gain configuration, if a dc voltage is applied to V
OCM
to shift the
common-mode voltage, a differential dc voltage will be created
at the output, along with the common-mode voltage change.
Thus, this configuration cannot be used when it is desired to
offset the common-mode voltage of the output with respect to
the input at +D
IN
.
REV. 0
AD8131
–11–
AD8131
24.9V
49.9V
49.9V
49.9V
8
2
3
6
5
4
10mF
0.1mF+
+5V
–5V
10mF
0.1mF+
100V
RECEIVER
1
Figure 38. Single-Ended-to-Differential 100
Ω
Line Driver
AD8131
24.9V
49.9V
110V
110V
8
2
3
6
0.1mF10mF
+
3V
LPF
0.1mF
10kV
+3V 1
VOCM
20pF
20pF
AD9203
26
25
28
AVDD DRVDD
AINP
AINN
AVSS DRVSS
3V
27
0.1mF
DIGITAL
OUTPUTS
1
2
10kV
Figure 39. Test Circuit for AD8131 Driving an AD9203,
10 Bit, 40 Msps A-to-D Converter
FREQUENCY – MHz
POUT – dBm
10
–40
2.5
2.3
0
–10
–20
–30
–50
2.0 2.1 2.2 2.4 2.6
–60
–110
–70
–80
–90
–100
–120 2.92.7 2.8 3.0
Figure 40. FFT Plot for AD8131/AD9203
49.9V
8
2
3
6
5
4
10mF
0.1mF+
+5V
–5V
10mF
0.1mF+
VOCM
1
INPUT
–OUT
+OUT
Figure 41. Unity Gain, Single-Ended-to-Differential
Amplifier
REV. 0
AD8131
–12–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3724–2.5–10/99
PRINTED IN U.S.A.
8-Lead SOIC
(SO-8)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
88
08
0.0196 (0.50)
0.0099 (0.25) 3 458
85
41
0. 1968 (5.00)
0. 1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC 0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
8-Lead SOIC
(RM-8)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
338
278
0.120 (3.05)
0.112 (2.84)
85
41
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05) 0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
