VIPer53DIP VIPer53SP (R) OFF LINE PRIMARY SWITCH TYPICAL OUTPUT POWER CAPABILITY European (195 - 265 Vac) US / Wide range (85 - 265 Vac) DIP-8 50W 30W PowerSO-10TM 65W 40W TYPE Note: 10 1 Above power capabilities are given under adequate thermal conditions FEATURES n SWITCHING FREQUENCY UP TO 300 kHz n CURRENT LIMITATION n CURRENT MODE CONTROL WITH ADJUSTABLE LIMITATION n SOFT START AND SHUT DOWN CONTROL n AUTOMATIC BURST MODE IN STAND-BY CONDITION ("BLUE ANGEL" COMPLIANT) n UNDERVOLTAGE LOCKOUT WITH HYSTERESIS n HIGH VOLTAGE STARTUP CURRENT SOURCE n OVERTEMPERATURE PROTECTION n OVERLOAD AND SHORT-CIRCUIT CONTROL ) s ( ct BLOCK DIAGRAM u d o r P e t e l o s b O PowerSO-10TM DIP-8 DESCRIPTION The VIPer53 combines in the same package an enhanced current mode PWM controller with a high voltage MDMesh Power Mosfet. Typical applications cover off line power supplies with a secondary power capability ranging up to 30W in wide range input voltage or 50W in single European voltage range and DIP-8 package, with the following benefits: - Overload and short circuit controlled by feedback monitoring and delayed device reset. - Efficient standby mode by enhanced pulse skipping. - Primary regulation or secondary loop failure protection through high gain error amplifier. c u d e t le ) s t( o r P o s b O OSC DRAIN ON/OFF OSCILLATOR PWM LATCH OVERTEMP. DETECTOR R1 S FF R2 R3 R4 BLANKING TIME SELECTION Q 1V R5 H COMP 0.5V UVLO COMPARATOR 150/400ns BLANKING VDD 8.4/ 11.5V PWM COMPARATOR STANDBY COMPARATOR 0.5V 4V CURRENT AMPLIFIER 8V 125k 15V ERROR AMPLIFIER 4.35V OVERLOAD COMPARATOR OVERVOLTAGE COMPARATOR 18V 4.5V TOVL June 2004 COMP SOURCE 1/24 VIPer53DIP / VIPer53SP PIN FUNCTION Name Function Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up. The functions of this pin are managed by four threshold voltages: - VDDon: Voltage value at which the device starts switching (Typically 11.5 V). - VDDoff: Voltage value at which the device stops switching (Typically 8.4 V). - VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V). - VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V). VDD SOURCE Power Mosfet source and circuit ground reference. DRAIN Power Mosfet drain. Also used by the internal high voltage current source during the start-up phase, for charging the external VDD capacitor. COMP Input of the current mode structure, and output of the internal error amplifier. Allows the setting of the dynamic characteristic of the converter through an external passive network. Useful voltage range extends from 0.5 V to 4.5 V. The Power Mosfet is always off below 0.5 V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the TOVL pin. TOVL Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.35V. OSC Allows the setting of the switching frequency through an external Rt-Ct network. c u d CURRENT AND VOLTAGE CONVENTIONS IDD ID VDD DRAIN e t le I OSC OSC so 15V I TOVL VOSC ) s ( ct VTOVL r P e 1 8 TOVL OSC 2 7 VDD t e l o bs O SOURCE SOURCE COMP o r P VDS SOURCE ICOMP VCOMP u d o CONNECTION DIAGRAM COMP b O - TOVL VDD ) s t( 3 6 4 5 DRAIN NC NC 1 10 NC 2 9 NC NC 3 8 NC VDD 4 7 OSC TOVL 5 6 COMP SOURCE DRAIN PowerSO-10TM DIP-8 ORDER CODES PACKAGE DIP-8 PowerSO-10TM 2/24 TUBE TAPE and REEL VIPer53DIP - VIPer53SP VIPer53SP13TR VIPer53DIP / VIPer53SP ABSOLUTE MAXIMUM RATINGS Symbol Parameter Continuous Drain Source Voltage (Tj=25 ... 125C) VDS ID Unit -0.3 ... 620 V Internally limited A 0 ... 19 V 0 ... VDD V -2 ... 2 mA 200 1.5 V kV Internally limited C (See note 1) Continuous Drain Current VDD Value Supply Voltage VOSC OSC Input Voltage Range ICOMP ITOVL COMP and TOVL Input Current Range VESD Electrostatic Discharge: Machine Model (R=0; C=200pF) Charged Device Model (See note 1) Tj Junction Operating Temperature Tc Case Operating Temperature -40 to 150 C Storage Temperature -55 to 150 C Tstg ) s t( Note: 1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 k should be inserted in series with the TOVL pin. c u d THERMAL DATA Symbol Parameter Rthj-case DIP-8 Rthj-amb DIP-8 Rthj-case PowerSO-10TM Rthj-amb PowerSO-10TM Max Value P e let ro (See note 2) (See note 3) o s b O - Unit 20 C/W 80 C/W 2 C/W 60 C/W Note: 2. When mounted on a standard single-sided FR4 board with 50mm of Cu (at least 35 m thick) connected to the DRAIN pin. 3. When mounted on a standard single-sided FR4 board with 50mm of Cu (at least 35 m thick) connected to the device tab. ) s ( ct u d o r P e t e l o s b O 3/24 VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj=25C, VDD=13V, unless otherwise specified) POWER SECTION Symbol Parameter Test Conditions Min. Typ. Max. Unit Drain-Source Voltage ID=1mA; VCOMP=0V Off State Drain Current VDS=500V; VCOMP=0V; Tj=125C Static Drain-Source On State Resistance ID=1A; VCOMP=4.5V; VTOVL=0V Tj=25C Tj=100C 0.9 tfv Fall Time ID=0.2A; VIN=300V (See figure 1 and note 4) 100 ns trv Rise Time ID=1A; VIN=300V (See figure 1 and note 4) 50 ns Coss Drain Capacitance VDS=25V 170 pF CEon Effective Output Capacitance 200V < VDSon < 400V 60 pF BVDSS IDSS RDS(on) 620 (See note 5) V 150 A 1 1.7 ) s t( Note 4. On clamped inductive load 5. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon 1.5 1 2 V DSon and the following formula: E ton = --- C Eon 300 ---------------- 300 2 c u d OSCILLATOR SECTION Symbol Parameter Test Conditions e t le FOSC1 Oscillator Frequency Initial Accuracy RT=8k; CT=2.2nF FOSC2 Oscillator Frequency Total Variation (See figure 12) RT=8k; CT=2.2nF VDD=VDDon ... VDDovp; Tj=0 ... 100C VOSChi Oscillator Peak Voltage VOSClo Oscillator Valley Voltage u d o ) s ( ct r P e t e l o s b O 4/24 (See figure 9) o s b O - o r P Min. Typ. Max. Unit 95 100 105 kHz 93 100 107 kHz 9 V 4 V VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj=25C, VDD=13V, unless otherwise specified) SUPPLY SECTION Symbol Parameter Test Conditions Min. Typ. Max. Unit 50 V Drain Voltage Starting Threshold VDD=5V; IDD=0mA 34 IDDch1 Startup Charging Current VDD=0 ... 5V; VDS=100V (See figure 2) -12 mA IDDch2 Startup Charging Current VDD=10V; VDS=100V (See figure 2) -2 mA IDDchoff Startup Charging Current in Thermal Shutdown VDD=5V; VDS=100V Tj > TSD - THYST (See figure 5) VDSstart 0 mA IDD0 Operating Supply Current Fsw=0kHz; VCOMP=0V Not Switching 8 IDD1 Operating Supply Current F =100kHz sw Switching 9 11 mA mA VDDoff VDD Undervoltage Shutdown Threshold (See figure 2) 7.5 8.4 9.3 VDDon VDD Startup Threshold (See figure 2) 10.2 11.5 12.8 VDDhyst VDD Threshold Hysteresis (See figure 2) 2.6 3.1 VDDovp VDD Overvoltage Shutdown Threshold (See figure 7) 17 18 19 V Min. Typ. Max. Unit 14.5 15 15.5 V ERROR AMPLIFIER SECTION Symbol Parameter e t le Test Conditions so VDDreg VDD Regulation Point ICOMP=0mA VDDreg VDD Regulation Point Total Variation ICOMP=0mA; Tj=0 ... 100C GBW Unity Gain Bandwidth From Input =VDD to Output = VCOMP ICOMP=0mA (See figure 10) AVOL Voltage Gain Gm ) s ( ct ICOMP=0mA DC Transconductance u d o (See figure 3) VCOMPhi Output High Level ICOMP=0.4mA; VDD=14V ICOMPlo Output Sinking Current t e l o ICOMPhi Output Sourcing Current V V % 700 kHz dB 40 45 (See figure 3) 1 1.4 ICOMP=-0.4mA; VDD=16V ) s t( 2 (See figure 10) VCOMP=2.5V Output Low Level r P e o r P b O - VCOMPlo c u d V 1.8 mS 0.2 V (See note 6) 4.5 V VCOMP=2.5V; VDD=16V (See figure 3) -0.6 mA VCOMP=2.5V; VDD=14V (See figure 3) 0.6 mA Note 6. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on the COMP pin. s b O 5/24 VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj = 25 C, VDD = 13 V, unless otherwise specified) PWM COMPARATOR SECTION Symbol Parameter HCOMP VCOMP / IDPEAK VCOMP=1 ... 4 V dID/dt=0 (See figure 8) VCOMP Offset dID/dt=0 (See figure 8) IDlim Peak Drain Current Limitation ICOMP=0mA; VTOVL=0V dID/dt=0 (See figure 8) IDmax Drain Current Capability VCOMP=VCOMPovl; VTOVL=0V dID/dt=0 (See figure 8) td Current Sense Delay to Turn-Off ID=1A VCOMP Blanking Time Change Threshold (See figure 11) tb1 Blanking Time VCOMP < VCOMPBL (See figure 11) 300 400 500 ns tb2 Blanking Time VCOMP > VCOMPBL (See figure 11) 100 150 200 ns tONmin1 Minimum On Time VCOMP < VCOMPBL 450 600 750 ns tONmin2 Minimum On Time VCOMP > VCOMPBL 250 350 450 ns VCOMPoff VCOMP Shutdown Threshold (See figure 6) VCOMPos VCOMPbl Test Conditions Parameter Test Conditions e t le o s b O - VCOMP Overload Threshold ITOVL=0mA VDIFFovl VCOMPhi to VCOMPovl Voltage Difference VDD=VDDoff ... VDDreg; ITOVL=0mA (See figure 4 and note 7) VOVLth VTOVL Overload Threshold tOVL Overload Delay VCOMPovl Typ. Max. Unit 1.7 2 2.3 V/A 0.5 1.7 2 2.3 A 1.6 1.9 2.3 A Min. ns 1 V c u d ) s t( COVL=100nF Typ. Max. 4.35 50 (See figure 4) u d o 250 o r P (See figure 4 and note 7) ) s ( ct V 0.5 OVERLOAD PROTECTION SECTION Symbol Min. (See figure 4) 150 V Unit V 250 mV 4 V 8 ms Note 7. VCOMPovl is always lower than VCOMPhi. r P e OVERTEMPERATURE PROTECTION SECTION t e l o Symbol TSD bs O THYST 6/24 Parameter Test Conditions Thermal Shutdown Temperature (See fig. 5) Thermal Shutdown Hysteresis (See fig. 5) Min. Typ. Max. Unit 140 160 C 40 C VIPer53DIP / VIPer53SP Figure 1: Rise and Fall Time ID C<<COSS C L D t VDD DRAIN VDS 300V OSC 15V 90% trv tfv TOVL COMP t 10% Figure 2: Start-up VDD Current Figure 4: Overload event Normal operation IDD0 VDDon VDDhyst e t le VDDoff VDDoff VDD VDDon IDDch2 o s b O VCOMP ) s ( ct IDDch1 u d o Figure 3: Output Characteristics r P e ICOMP t e l o s b O ) s t( o r P Abnormal operation t VDIFFovl VCOMPhi VCOMPovl VDS = 100 V FSW = 0 kHz ICOMPhi c u d VDD IDD 0 SOURCE t VTOVL VOVLth tOVL Slope = Gm VDDreg t VDD VDS Not switching Switching ICOMPlo t 7/24 VIPer53DIP / VIPer53SP Figure 5: Thermal Shutdown Figure 7: Overvoltage Event Tj VDD TSD VDDovp TSD-T HYST t VDD t VCOMP VDDon Abnormal operation Automatic startup Normal operation t VCOMP t VDS c u d Switching ro t P e let Figure 6: Shut Down Action t Figure 8: Comp Pin Gain and Offset o s b O - VOSC IDpeak VOSChi ) s ( ct VOSClo VCOMP s b O IDlim IDmax t u d o r P e t e l o VCOMPoff Slope = 1 / HCOMP VCOMP t ID t 8/24 ) s t( Not switching VCOMPos VCOMPovl VCOMPhi VIPer53DIP / VIPer53SP Figure 9: Oscillator Schematic and Settings Vcc The switching frequency settings shown on the graphic here below is valid within the following boundaries: VDD Rt OSC R t > 2k PWM section F SW < 300 kHz 320 Ct SOURCE c u d Frequency (kHz) 300 2.2nF e t le 1nF 4.7nF 100 10nF ) s ( ct 22nF u d o ) s t( o r P o s b O - 10 r P e 1 10 100 RT (K) t e l o s b O 9/24 VIPer53DIP / VIPer53SP Figure 10: Error Amplifier Transfer Function Vin VDD DRAIN OSC 15V TOVL COMP This configuration is for test purpose only. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should be always connected between COMP pin and ground. See figures 14, 15 and 18. SOURCE Vout R 2.5 V Gain (dB) 60 Open c u d 40 R = 10 k 20 R = 2.2 k e t le R = 470 0 -20 -40 ) s ( ct -60 1 10 o s b O - 100 u d o r P e Figure 11: Blanking Time t e l o tb tb1 s b O tb2 VCOMP VCOMPbl 10/24 VCOMPhi o r P 1k 10k 100k Frequency (Hz) 1M 10M ) s t( VIPer53DIP / VIPer53SP Figure 12: Typical Frequency Variation vs. Junction Temperature Normalised Frequency 1.04 1.02 1 0.98 0.96 -20 0 20 40 60 80 100 Temperature (C) Figure 13: Typical Current Limitation vs. Junction Temperature Normalised IDlim ) s ( ct 1.04 1.02 e t le c u d 120 ) s t( o r P o s b O - u d o r P e s b O t e l o 1 0.98 0.96 -20 0 20 40 60 80 100 120 Temperature (C) 11/24 VIPer53DIP / VIPer53SP Figure 14: Off Line Power Supply With Auxiliary Supply Feedback F1 C1 AC IN D1 T1 C2 R1 R2 C3 T2 D2 L1 D4 D3 R4 C8 C9 DC OUT U1 VIPer73 R3 VDD DRAIN C10 OSC 15V TOVL C4 COMP R6 1k R5 C5 C11 10nF C6 (s) t c u d o r P e s b O 12/24 e t le C7 o s b O - PRIMARY REGULATION CONFIGURATION EXAMPLE The schematic on figure 14 delivers a fixed output voltage by using the internal error amplifier of the device in a primary feedback configuration. The primary auxiliary winding provides a voltage to the VDD pin, and is automatically regulated at 15 V thanks to the internal error amplifier connected on this pin. The secondary voltage has to be adjusted through the turn ratio of the transformer between auxiliary and secondary. The error amplifier of the VIPer53 is a transconductance one: its output is a current proportional to the difference of voltage between the VDD pin and the internal trimmed 15 V reference, i.e. the error voltage. As the transconductance value is set at a relatively low value to control the overall loop gain and insure stability, this current has to be integrated by a capacitor (C7 in the above schematic). When the steady state operation is reached, this capacitor blocks any DC current from the COMP pin and imposes a nil error voltage. Therefore, the VDD voltage is accurately regulated to 15 V. t e l o c u d SOURCE ) s t( o r P This results in a good load regulation, which depends only on transformer coupling and output diodes impedance. The current mode structure takes care of all incoming voltage changes, thus providing at the same time an excellent line regulation. The switching frequency can be set to any value through the choice of R3 and C5. This allows to optimize the efficiency of the converter by adopting the best compromise between switching losses, EMI (Lower with low switching frequencies) and transformer size (Smaller with high switching frequencies). For an output power of a few watts, typical switching frequencies are comprised between 20 kHz and 40 kHz because of the small size of the transformer. For higher power, 70 kHz to 130 kHz are generally chosen. The value of the compensation resistor R5 sets the dynamic behavior of the converter. It can be adjusted to provide the best compromise between stability and recovering time with fast load changes. VIPer53DIP / VIPer53SP Figure 15: Off Line Power Supply With Optocoupler Feedback F1 C1 AC IN D1 T1 R2 C2 R1 C3 T2 D2 L1 D4 D3 R4 C8 C9 DC OUT U1 VIPer73 R3 VDD DRAIN C10 OSC 15V R8 TOVL C4 COMP c u d SOURCE U2 C5 R9 1k C6 C11 10nF R5 ) s t( o r P C12 C7 e t le R7 U3 (t s) o s b O - SECONDARY FEEDBACK CONFIGURATION EXAMPLE When a more accurate output voltage is needed, the definitive way is to monitor it directly on secondary side, and to drive the PWM controller through an optocoupler as shown on figure 15. The optocoupler is connected in parallel with the compensation network on the COMP pin. The design of the auxiliary winding will be made in such a way that the V DD voltage is always lower than the internal 15 V reference. The internal error amplifier will therefore be saturated in the high state, and because of its transconductance nature, will deliver a constant biasing current of 0.6 mA to the optotransistor. This current doesn't depend on the compensation voltage, and so it doesn't depend on the output load either. The gain of the optocoupler ensures consequently a constant biasing of the TL431 device (U3) which is in charge of secondary regulation. If the optocoupler gain is sufficiently low, no additional components are required to ensure a minimum current biasing of U3. Also, the o r P e s b O t e l o c u d R6 low biasing current value avoid any ageing of the optocoupler. The constant current biasing can be used to simplify the secondary circuit: Instead of a TL431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. As the current flowing in this branch remains constant for the same reason as above, typical load regulation of 1% can be achieved from zero to full output current with this simple configuration. Since the dynamic characteristics of the converter are set on the secondary side through components associated to U3, the compensation network has only a role of gain stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed value of 1 k, offering the possibility of using C7 as a soft start capacitor: When starting up the converter, the VIPer53 device delivers a constant current of 0.6 mA on the COMP pin, creating a constant voltage of 0.6 V in R5 and a rising slope across C7. This voltage shape together with the operating range of 0.5 V to 4.5 V 13/24 VIPer53DIP / VIPer53SP provides a soft start-up of the converter. The rising speed of the output voltage can be set through the value of C7. C4 and C6 values must be adjusted accordingly in order to ensure a correct start-up. CURRENT MODE TOPOLOGY The VIPer53 implements the conventional current mode control method for regulating the output voltage. This kind of feedback includes two nested regulation loops: The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS. When VS reaches VCOMP, the power switch is turned off. This structure is completely integrated as shown on the Block Diagram of page 1, with the current amplifier, the PWM comparator, the blanking time function and the PWM latch. The following formula gives the peak current in the Power MOSFET according to the compensation voltage: V C OMP - V COMPos I Dpeak = ---------------------------------------------H COM P The outer loop defines the level at which the inner loop regulates peak current in the power switch. For this purpose, VCOMP is driven by the output of the error amplifier (Either the internal one in primary feedback configuration or a TL431 through an optocoupler in secondary feedback configuration, see figures 14 and 15) and is set accordingly the peak drain current for each switching cycle. As the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also provides a good converter start-up control. As the compensation voltage can be controlled to increase slowly during the start-up phase, the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. The simpler voltage mode structure which only controls the duty cycle, leads generally to high currents at start-up with the risk of transformer saturation. The compensation pin can also be used to limit the current capability of the device (See Current Limitation section). An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of ) s ( ct u d o r P e t e l o s b O 14/24 current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode. STANDBY MODE The device implements a special feature to address the low load condition. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits: - It reduces the switching losses, thus providing low consumption on the mains lines. The device is compliant with "Blue Angel" and other similar standards, requiring less than 0.5 W of input power when in standby. - It allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on. For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM latch and the Power MOSFET in the off state as long as VCOMP remains below 0.5 V (See Block Diagram on page 1). If the output load requires a duty cycle below the one defined by the minimum turn on of the device, the error amplifier decreases its output voltage until it reaches this 0.5 V threshold (VCOMPoff). The Power MOSFET can be completely off for some cycles, and resumes normal operation as soon as VCOMP is higher than 0.5 V. The output voltage is regulated in burst mode. The corresponding ripple is not higher than the nominal one at full load. In addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to VCOMP value. Below 1 V (VCOMPbl), the blanking time increases to 400 ns, whereas it is 150 ns for higher voltages (See figure 11). The minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. This brutal change induces an hysteresis between normal operation and burst mode as shown on figure 16. When the output power decreases, the system reaches point 2 where VCOMP equals VCOMPbl. The minimum turn on time passes immediately from 350 ns to 600 ns, exceeding the effective turn on time that should be needed at such output power level. Therefore the regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst mode and to control the output voltage. The corresponding hysteresis can be seen on the switching frequency which passes from FSWnom which is the normal switching frequency set by the components connected to the OSC pin, to FSWstby. Note that this frequency is c u d o s b O - e t le o r P ) s t( VIPer53DIP / VIPer53SP Figure 16: Standby Mode Implementation ton 3 600ns Minimum turn on 1 2 350ns VCOMP VCOMPsd VCOMPoff VCOMPbl PIN 1 PRST 3 2 PSTBY FSW FSWstby FSWnom actually an equivalent number of switching pulses per second, rather than a fixed switching frequency, as the device is working in burst mode. As long as the power remains below P RST the output of the regulation loop remains stuck at VCOMPsd and the converter works in burst mode. Its "density" increases (i.e. the number of missing cycles decreases) as the power approaches PRST and resumes finally normal operation at point 1. The hysteresis cannot be seen on the switching frequency, but the COMP pin voltage which passes brutally at that power level from point 3 to point 1. The power points value PRST and PSTBY are defined by the following formulas: 1 2 1 2 P RST = --- F SWnom ( tb 1 + td ) V IN -----2 Lp 1 2 P STBY = --- F SW nom Ip ( V COMPbl ) Lp 2 uc (t s) HIGH VOLTAGE START-UP CURRENT SOURCE An integrated high voltage current source provides a bias current from the DRAIN pin during the startup phase. This current is partially absorbed by internal control circuits in standby mode with reduced consumption and also supplies the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 14 or 15. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start-up, when the device starts switching. This time tss depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin and possible secondary feedback circuit. The following formula can be used for defining the minimum capacitor needed: I DD1 tss C VDD > ----------------------V DDhyst c u d e t le ) s t( o r P Figure 17 shows a typical start-up event. VDD starts from 0 V with a charging current I DDch1 at about 9 mA. When about VDDoff is reached, the o s b O - d o r P e Where Ip(VCOMPbl) is the peak Power MOSFET current corresponding to a compensation voltage of VCOMPbl (1V), that is to say about 250 mA. Note that the power point P STBY where the converter is going into burst mode doesn't depend on the input voltage. The standby frequency FSWstb y is given by: P STBY F SWstby = -------------- F SWnom P RST t e l o s b O The ratio between the nominal switching frequency and the standby one can be as high as 4, depending on the Lp value and input voltage. Figure 17: Startup Waveforms IDD IDD1 t IDDch2 IDDch1 VDD tss VDDreg VDDst VDDsd tsu t 15/24 VIPer53DIP / VIPer53SP charging current is reduced down to IDDch2 which is about 0.6 mA. This lower current leads to a slope change on the VDD rise. The device starts switching for a VDD equal to VDDon, and the auxiliary winding delivers some energy to the VDD capacitor after the start-up time tss. The charging current change at VDDoff allows a fast complete start-up time tsu, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section. SHORT-CIRCUIT AND OVERLOAD PROTECTION A VCOMPovl threshold of about 4.35 V has been implemented on the COMP pin. When VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically 4 V (VOVLth), the internal mosfet driver is disabled and the device stops switching. This state is latched thanks to the regulation loop which maintains the COMP pin voltage above the VCOMPovl threshold. Since the VDD pin doesn't receive any more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the device is reset, recharging the VDD capacitor for a new restart cycle. Note that if VCOMP drops down below the V COMPovl threshold for any reason during the VDD drop, the device resumes switching immediately. The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, D RST must be kept as low as possible, without compromising the real start up of the converter. A typical value of about 10 % is generally sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the following conditions: -6 C OVL > 12.5 10 tss C OVL I DDc h2 1 4 C VDD > 8 10 ------------ - 1 --------------------------------- D RST V DDhyst ) s ( ct r P e bs Refer to the previous start-up section for the definition of tss, and CVDD must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted. All this behavior can be observed on figure 4. In Figure 8 the value of the drain current Id for VCOMP=VCOMPovl is shown. The corresponding parameter I Dmax is the drain current to take into account for design purpose. Since IDmax represents the maximum value for which the O 16/24 TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer53 includes a transconductance error amplifier. Transconductance Gm is the change in output current ICOMP versus change in input voltage VDD. Thus: Gm = I COMP V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Z C OMP = V COMP 1 VCOM P = --------- Gm VDD I COMP This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: A VOL = Gm Z COM P ) s t( where Gm value for VIPer53 is typically 1.4 mA/V. Gm is well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z must be connected between the COMP pin and ground in order to define accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(s) = Gm Z(s) The error amplifier frequency response is shown in figure 10 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 140 K. More complex impedances can be connected on the COMP pin to achieve different compensation methods. A capacitor provides an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, c u d e t le o r P o s b O - u d o t e l o overload protection is not triggered, it defines the power capability of the power supply. Figure 18: Typical Compensation Network VDD DRAIN OSC 15V TOVL COMP SOURCE Rcomp 10nF Ccomp VIPer53DIP / VIPer53SP introducing a zero and ensuring a correct phase margin. This configuration is illustrated in figure 18 Figure 19: Typical Transfer Functions for the schematic and figure 19 for the error Gain (dB) 60 Rcomp=4.7k Ccomp=470nF 50 40 30 20 10 0 -10 1 10 100 1k 10k 100k 1M c u d Frequency (Hz) Phase () 0 e t le -20 -30 -40 -50 -60 ) s ( ct -70 -80 -90 u d o -100 r P e t e l o 1 10 o s b O - 100 1k 10k 100k 1M Frequency (Hz) amplifier transfer function for a typical set of values for CCOMP and RCOMP. Note that a capacitor of 10 nF (minimum value: 8 nF) should always be connected to the COMP pin to insure a correct stability of the internal error amplifier. The complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. A theoretical example can be seen in figure 20 for a discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no optocoupler, the internal error amplifier is fully used for regulation). A typical schematic corresponding to this situation can be seen on figure 14. s b O o r P Rcomp=4.7k Ccomp=470nF -10 ) s t( The transfer function of the power cell is represented as G(s) in figure 20. It exhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, RL1 and RL2. A zero at higher frequency values then appears, due to the output capacitor ESR. Note that the overall transfer function doesn't depend on the input voltage, thanks to the current mode control. The error amplifier has a fixed behavior, similar to the one shown in figure 19. Its bandwidth is limited, in order to avoid injection of high frequency noise 17/24 VIPer53DIP / VIPer53SP Figure 20: Complete Converter Transfer Function G(S) P M AX 3.2 -------------------P O U T1 P MAX 3.2 -------------------P OU T 2 1 ---------------------------------------R C L1 O UT 1 ---------------------------------------R C L2 O UT F 1 1 -----------------------------------------------2 ES R C O UT F(S) Gm R 1 ---------------------------------------------------------------2 R C C O M P CO M P FC COMP F 1 c u d e t le F(S).G(S) ) s ( ct o r P e 1 t e l o du FBW 2 o s b O R COMP = With: FBW 1 in the current mode section. A zero due to the RCOMP-C COMP network is set at the same value as the maximum load RL2 pole. The total transfer function is shown as F(s).G(s) at the bottom of figure 20. For maximum load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and the result is a ) s t( o r P POUT2 F BW 2 RL2 C OUT ----------------- -----------------------------------------------Gm PM AX 2 VOUT P OUT2 = -------------RL2 1 F s b O 18/24 perfect first order decreasing slope until it reaches the zero of the output capacitor ESR. The error amplifier cut off then prevents definitely any further spurious noise or resonance from disturbing the regulation loop. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has a double interest: - The higher it is the faster will be the reaction to an eventual load change, and the smaller will be the output voltage change. - The phase shift in the complete system at this point has to be less than 135 to ensure a good stability. Generally, a first order gives 90 of phase shift, and 180 for a second order. In figure 20, the unity gain is reached in a first order slope, so the stability is ensured. The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: As the transfer function above the zero due the capacitor ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero. As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in figure 20), the above criteria will be checked for this condition and allows to define the value of RCOMP, as the error amplifier gain depends only on this value for this frequency range. The following formula can be derived: 2 And: P M AX = --- LP ILIM F SW : 2 The lowest load gives another condition for stability: The frequency FBW1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier. This condition can be met by adjusting the CCOMP value: R L1 COUT C COMP > --------------------------------------------- 2 6.3 Gm R COMP 2 V OUT POUT1 = -------------R L1 POUT1 ----------------PM AX With: The above formula gives a minimum value for CCOMP. It can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity ICOMPhi at start-up. VIPer53DIP / VIPer53SP SPECIAL RECOMMENDATIONS As stated in the error amplifier section, a capacitor of 10 nF (minimum value: 8 nF) should always be connected to the COMP pin to insure a correct stability of the internal error amplifier. This is represented on figures 14, 15 and 18. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 k should be inserted in series with the TOVL pin, as shown on figures 14 and 15. Note that this resistance doesn't impact the overload delay, as its value is negligible in front of the internal pull up resistance (about 125 k). SOFTWARE IMPLEMENTATION All the above considerations and some others are included in a design software which provides all the needed components around the VIPer device for a specified output configuration. This software is available in download on the ST internet site. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 19/24 VIPer53DIP / VIPer53SP Plastic DIP-8 MECHANICAL DATA mm. DIM. MIN. TYP MAX. A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.26 E1 6.10 6.35 7.11 e 2.54 eA 7.62 eB L 2.92 Package Weight ) s ( ct c u d 3.30 Gr. 470 e t le 3.81 o r P o s b O - u d o r P e t e l o s b O P001 20/24 ) s t( 10.92 VIPer53DIP / VIPer53SP PowerSO-10TM MECHANICAL DATA mm. DIM. MIN. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) (*) inch TYP 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 MAX. MIN. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 1.80 1.10 8 8 0.047 0.031 0 2 TYP. c u d 1.27 0.050 1.25 1.20 13.80 13.85 e t le 0.50 1.20 0.80 0 2 (*) Muar only POA P013P (s) t c u 10 d o r P e H E t e l o o s b O - s b O ) s t( 0.053 0.055 0.567 0.565 0.002 0.070 0.043 8 8 0.10 A B E2 E4 SEATING PLANE B DETAIL "A" A C 0.25 h 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 B 1 e o r P MAX. D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" P095A 21/24 VIPer53DIP / VIPer53SP PowerSO-10TM SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 14.6 - 14.9 CASABLANCA B 10.8 - 11 MUAR C 6.30 C A A 0.67 - 0.73 1 9.5 10 9 8 7 2 3 4 5 B 0.54 - 0.6 All dimensions are in mm. 1.27 Base Q.ty Bulk Q.ty Tube length ( 0.5) 6 Casablanca Muar 50 50 1000 1000 532 532 A B C ( 0.1) 10.4 16.4 4.9 17.2 0.8 0.8 TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) e t le TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) r P e u d o t e l o s b O ) s ( ct o s b O - 600 600 330 1.5 13 20.2 24.4 60 30.4 c u d o r P ) s t( All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 22/24 1 VIPer53DIP / VIPer53SP DIP-8 TUBE SHIPMENT (no suffix) A C B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) 20 1000 532 8.4 11.2 0.8 c u d All dimensions are in mm. e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 23/24 1 VIPer53DIP / VIPer53SP c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com 24/24