June 2004 1/24
VIPer53DIP
VIPer53SP
OFF LINE PRIMARY SWITCH
®
TYPICAL OUTPUT POWER CAPABILITY
Note: Above power capabilities are given under adequate
thermal conditions
FEATURES
n
SWITCHING FREQ UENCY UP TO 300 kHz
n
CURRENT LIMITATION
n
CURRENT MODE CONTROL WITH
ADJUSTABLE LIMITATION
n
SOFT START AN D SHUT DOWN CONTROL
n
AUTOMATIC BURST MO DE IN STAND-BY
CONDITION (“BLUE ANGEL” COMPLIA NT)
n
UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
n
HIGH VO LTAG E STARTUP CURRENT
SOURCE
n
OVERTEMPER ATURE PR O TECTION
n
OVERLOAD AND SHORT-CIRCUI T CONTROL
DESCRIPTION
The VIPer53 combines in the same package an
enhanced current mode PWM controller with a
high voltage MDMesh Power Mosfet. Typical
applications cover off line power supplies with a
secondary power capability ranging up to 30W in
wide range input voltage or 50W in single
European voltage range and DIP-8 package, with
the following benefit s:
– Overload and short circuit controlled by
feedback monitoring and delayed device r eset.
– Efficient standby mode by enhanced pulse
skipping.
– Primary regulation or secondary loop failure
protection through high gain error amplifier.
TYPE European
(195 - 265 Vac) US / Wide range
(85 - 265 Vac)
DIP-8 50W 30W
PowerSO-10™65W 40W 1
10
DIP-8 PowerSO-10™
BLOCK DIAGRAM
FF
OSCILLATOR
150/400ns
BLANKING
1V
4V
OVERTEMP.
DETECTOR
8.4/
11.5V
15V
0.5V
VDD
OSC DRAIN
TOVL COMP SOURCE
PWM
LATCH
ON/OFF
BLANKING TIME
SELECTION
PWM
COMPARATOR
CURRENT
AMPLIFIER
S
R1
R2
R3 R4 R5
Q
8V
4.35V
OVERLOAD
COMPARATOR
18V 4.5V
125k
0.5V
STANDBY
COMPARATOR
OVERVOLTAGE
COMPARATOR
ERROR
AMPLIFIER
UVLO
COMPARATOR HCOMP
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PIN FUNCTION
CURRENT AND VOLTAGE C ONVENTIONS
CONNECTION DIAGRAM
ORDER CODES
Name Function
VDD
Power supply of the control circuits. Also provides the charging current of the external capacitor during
start-up. The functions of this pin are managed by four threshold voltages:
- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).
- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).
- VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V).
- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).
SOURCE Power Mosfet source and circuit ground reference.
DRAIN Power Mosfet drain. Also used by the internal high voltage current source during the start-up phase, for
charging the external VDD capacitor.
COMP
Input of the current mode structure, and output of the internal error amplifier. Allows the setting of the
dynamic characteristic of the converter through an external passive network. Useful voltage range
extends from 0.5 V to 4.5 V. The Power Mosfet is always off below 0.5 V, and the overload protection is
triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the
TOVL pin.
TOVL Allows the connection of an external capacitor for delaying the overload protection, which is triggered by
a voltage on the COMP pin higher than 4.35V.
OSC Allows the setting of the switching frequency through an external Rt-Ct network.
PACKAGE TUBE TAPE and R EEL
DIP-8 VIPer53DIP -
PowerSO-10™ VIPer53SP VIPer53SP13TR
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
IDD
VDD
IOSC
VOSC
ITOVL
VTOVL
ICOMP
VCOMP
ID
VDS
1
2
3
4
5
10
9
8
7
6
VDD
TOVL
NC
NC
NC
OSC
COMP
NC
NC
SOURCE
DRAIN
SOURCE
TOVLCOMP
VDD
NC
DRAIN
SOURCE
1
54
8
7
6
2
3
OSC
DIP-8 PowerSO-10™
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ABSOLUTE MAXIMUM RATINGS
Note : 1. In or der to im prov e the r ugged nes s of the de vice v ersu s ev entua l dr ain ov ervolt ag es, a res istan ce of 1 kΩ s hou ld b e in sert ed i n
seri es with the TOVL pi n.
THE RMAL D ATA
Note: 2. Whe n m ounted on a standard single-sided F R4 board with 50m m ² of Cu (at l east 35 µm thick) connected to the DRAIN pin.
3. When mount ed on a standard single-sided F R4 boa rd with 50m m ² of Cu (at l east 35 µm thick) connected to the device tab.
Symbol Parameter Value Unit
VDS Continuous Drain Source Voltage (Tj=25 ... 125°C) (See note 1) -0.3 ... 620 V
IDContinuous Drain Current Internally limited A
VDD Supply Voltage 0 ... 19 V
VOSC OSC Input Voltage Range 0 ... VDD V
ICOMP
ITOVL COMP and TOVL Input Current Range (See note 1) -2 ... 2 mA
VESD Electrostatic Discharge:
Machine Model (R=0Ω; C=200pF)
Charged Device Model 200
1.5 V
kV
TjJunction Operating Temperature Internally limited °C
TcCase Operating Temperature -40 to 150 °C
Tstg Storage Temperature -55 to 150 °C
Symbol Parameter Max Value Unit
Rthj-case DIP-8 20 °C/W
Rthj-amb DIP-8 (See note 2) 80 °C/W
Rthj-case PowerSO-10™2°C/W
Rthj-amb PowerSO-10™(See note 3) 60 °C/W
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ELECTRICAL CHARACTE RISTICS (Tj=25°C , VDD=13V, unless otherwise specified)
PO W ER SECTION
Note 4. On cla m ped inductive lo ad
5. This pa ramet er can be used t o compu te the ener gy dissipated at t urn on Eton ac cording to the init i al drain to source vo ltage VDSon
and the following formula:
OSCILLATOR S E C TI ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVDSS Drain-Source Voltage ID=1mA; VCOMP=0V 620 V
IDSS Off State Drain Current VDS=500V; VCOMP=0V; Tj=125°C 150 µA
RDS(on) Static Drain-Source
On State Resistance
ID=1A; VCOMP=4.5V; VTOVL=0V
Tj=25°C
Tj=100°C 0.9 1
1.7 Ω
Ω
tfv Fall Time ID=0.2A; VIN=300V
(See figure 1 and note 4) 100 ns
trv Rise Time ID=1A; VIN=300V
(See figure 1 and note 4) 50 ns
Coss Drain Capacitance VDS=25V 170 pF
CEon Effective Output
Capacitance 200V < VDSon < 400V (See note 5) 60 pF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
FOSC1 Oscillator Frequency
Initial Accuracy RT=8kΩ; CT=2.2nF (See figure 9) 95 100 105 kHz
FOSC2 Oscillator Frequency
Total Variation RT=8kΩ; CT=2.2nF (See figure 12)
VDD=VDDon ... VDDovp; Tj=0 ... 100°C 93 100 107 kHz
VOSChi Oscillator Peak Voltage 9 V
VOSClo Oscillator Valley Voltage 4 V
Eton 1
2
---CEon 3002VDSon
300
----------------
1.5
⋅⋅⋅
=
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ELECTRICAL CHARACTE RISTICS (Tj=25°C , VDD=13V, unless otherwise specified)
SUPPLY SECTION
ERR OR AMPLIFIER SECTION
Note 6. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on
the COM P pi n.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDSstart Drain Voltage Starting
Threshold VDD=5V; IDD=0mA 34 50 V
IDDch1 Startup Charging Current VDD=0 ... 5V; VDS=100V (See figure 2) -12 mA
IDDch2 Startup Charging Current VDD=10V; VDS=100V (See figure 2) -2 mA
IDDchoff Startup Charging Current
in Thermal Shutdown VDD=5V; VDS=100V (See figure 5)
Tj > TSD - THYST 0mA
IDD0 Operating Supply Current
Not Switching Fsw=0kHz; VCOMP=0V 811mA
IDD1 Operating Supply Current
Switching Fsw=100kHz 9mA
VDDoff VDD Undervoltage
Shutdown Threshold (See figure 2) 7.5 8.4 9.3 V
VDDon VDD Startup Threshold (See figure 2) 10.2 11.5 12.8 V
VDDhyst VDD Threshold
Hysteresis (See figure 2) 2.6 3.1 V
VDDovp VDD Overvoltage
Shutdown Threshold (See figure 7) 17 18 19 V
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDDreg VDD Regulation Point ICOMP=0mA (See figure 3) 14.5 15 15.5 V
∆VDDreg VDD Regulation Point
Total Variation ICOMP=0mA; Tj=0 ... 100°C 2%
GBW Unity Gain Bandwidth From Input =VDD to Output = VCOMP
ICOMP=0mA (See figure 10) 700 kHz
AVOL Voltage Gain ICOMP=0mA (See figure 10) 40 45 dB
GmDC Transconductance VCOMP=2.5V (See figure 3) 1 1.4 1.8 mS
VCOMPlo Output Low Level ICOMP=-0.4mA; VDD=16V 0.2 V
VCOMPhi Output High Level ICOMP=0.4mA; VDD= 14V (See note 6) 4.5 V
ICOMPlo Output Sinking Current VCOMP=2.5V; VDD=16V (See figure 3) -0.6 mA
ICOMPhi Output Sourcing Current VCOMP=2.5V; VDD=14V (See figure 3) 0.6 mA
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ELECTRICAL CHARACTE RISTICS (Tj = 25 °C, VDD = 13 V, unless otherwise specified)
PWM COMPARATOR SECTION
OVERLOAD PROTECTION SECTION
Note 7. VCOMPovl is always lower than VCOMPhi.
OVERTEMPERATURE PROTECTION SECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
HCOMP ∆VCOMP / ∆IDPEAK VCOMP=1 ... 4 V (See figure 8)
dID/dt=0 1.7 2 2.3 V/A
VCOMPos VCOMP Offset dID/dt=0 (See figure 8) 0.5 V
IDlim Peak Drain Current
Limitation ICOMP=0mA; VTOVL=0V (See figure 8)
dID/dt=0 1.7 2 2.3 A
IDmax Drain Current Capability VCOMP=VCOMPovl; VTOVL=0V
dID/dt=0 (See figure 8) 1.6 1.9 2.3 A
tdCurrent Sense Delay to
Turn-Off ID=1A 250 ns
VCOMPbl VCOMP Blanking Time
Change Thres hold (See figure 11) 1 V
tb1 Blanking Time VCOMP < VCOMPBL (See figure 11) 300 400 500 ns
tb2 Blanking Time VCOMP > VCOMPBL (See figure 11) 100 150 200 ns
tONmin1 Minimum On Time VCOMP < VCOMPBL 450 600 750 ns
tONmin2 Minimum On Time VCOMP > VCOMPBL 250 350 450 ns
VCOMPoff VCOMP Shutdown
Threshold (See figure 6) 0.5 V
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCOMPovl VCOMP Overload
Threshold ITOVL=0mA (See figure 4 and note 7) 4.35 V
VDIFFovl VCOMPhi to VCOMPovl
Voltage Difference VDD=VDDoff ... VDDreg; ITOVL=0mA
(See figure 4 and note 7) 50 150 250 mV
VOVLth VTOVL Overload
Threshold (See figure 4) 4 V
tOVL Overload Delay COVL=100nF (See figure 4) 8ms
Symbol Parameter Test Conditions Min. Typ. Max. Unit
TSD Thermal Shutdow n
Temperature (See fig. 5) 140 160 °C
THYST The rmal Shutdow n
Hysteresis (See fig. 5) 40 °C
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Figure 1: Rise and Fa ll Time
Figure 2: S tart-up VDD Cu rrent
Figure 3: Output Characteristics
Fi gure 4: Overload event
ID
VDS
90%
10%
tfv trv
t
t
300V
CLD
C<<COSS
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
IDD
VDD
VDDhyst
VDDoff VDDon
IDD0
IDDch1
IDDch2
VDS = 100 V
FSW = 0 kHz
ICOMP
VDD
VDDreg
ICOMPhi
ICOMPlo
0
Slope = Gm
Normal
operation
t
t
VTOVL
VCOMP
t
VDD
VCOMPhi
VDDon
VDDoff
VDS
t
Switching
Not
switching
Abnormal
operation
VCOMPovl
VOVLth tOVL
VDIFFovl
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Figure 5: Thermal Shutdown
Figure 6: Shut Down Action
Fi gure 7: Overvoltage Event
Fi gure 8: Comp Pin Gain and Offset
t
t
VDD
VCOMP
t
Tj
VDDon
TSD
TSD-THYST
Automatic
startup
t
t
ID
VCOMP
t
VOSC
VCOMPoff
VOSChi
VOSClo
Abnormal
operation
t
t
VDS
VCOMP
t
VDD
VDDovp
Switching
Not
switching
Normal
operation
VCOMP
IDpeak
VCOMPos VCOMPhi
Slope = 1 / HCOMP
IDlim
VCOMPovl
IDmax
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Figure 9: Oscillator Schematic and Settings
The switching freq uency settings shown
on the graphic here below is valid within
the following boundaries:
Rt2kΩ>
F
SW 300kHz<
320 Ω
SOURCE
OSC
VDD
PWM
section
Ct
Rt
Vcc
1 10 100
10
300
100
Frequency (kHz)
RT(KΩ)
1nF
2.2nF
4.7nF
10nF
22nF
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Figure 10: E rror Amplifier Transfer Function
Figure 11: Blanking Time
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
R
2.5 V
Vin
Vout
-60
-40
-20
0
20
40
60
Gain (dB)
Frequency (Hz)
Open
R = 10 kΩ
R = 2.2 kΩ
R = 470 Ω
1 10 100 1k 10k 100k 1M 10M
This configuration is for test purpose only. In
order to insure a correct stability of the error
amplifier, a capacitor of 10nF (minimum
value: 8nF) should be always connected
between COMP pin and ground. See figures 14,
15 and 18 .
VCOMP
tb
tb1
tb2
VCOMPbl VCOMPhi
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Figure 12: Typical Frequenc y Variation vs. Junction Tem perature
Figure 13: Typical Current Limitation vs. Junction Tem perat ure
-20 0 20 40 60 80 100 120
0.96
0.98
1
1.02
1.04
Normalised Frequency
Temperature (°C)
-20 0 20 40 60 80 100 120
0.96
0.98
1
1.02
1.04
Normalise d IDlim
Temperature (°C)
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Figure 14: Off Line Power Supply With Auxiliary Supply Feedback
PRIMARY REGULATION CONFIGURATION
EXAMPLE
The schemat ic on f igure 14 deli vers a fixed out put
voltage by using the internal error amplifier of the
device in a primary feedback configuration. The
primary auxiliary winding provides a voltage t o the
VDD pin, and is automatically regulated at 15 V
thanks to t he i nterna l error am plifier con necte d on
this pin. The secondary voltage has to be adjusted
through the turn ratio of the transformer between
auxiliary and secondary.
The error amplifier of the VIPer53 is a
transconductance one: its output is a current
proportional to the difference of voltage between
the VDD pin and the internal trimmed 15 V
reference, i.e. the error voltage. As the
transconductance value is set at a relatively low
value to control the overall loop gain and insure
stability, this current has to be integrated by a
capacitor (C7 in the abo ve schematic). Whe n the
steady state operation is reached, this capacitor
blocks any DC current from the COMP pin and
imposes a nil error voltage. Therefore, the VDD
voltage is accurately regulated to 15 V.
This results in a good load regulation, which
depends only on transformer coupling and ou tput
diodes impedance. The current mode structure
takes care of all incoming voltage changes, thus
providing at the same time an excellent line
regulation.
The switching frequency can be set to any value
through the choice of R3 and C5. This allows to
optimize the efficiency of the converter by adopting
the best compromise between switching losses,
EMI (Lower with low switching frequencies) and
transformer size (Smaller with high switching
frequencies). F or an output power of a few watts,
typical switching frequencies are comprised
betwee n 2 0 kHz and 40 k Hz because of the sma ll
size of the transformer. For higher power, 70 kHz
to 130 kHz are generally chosen.
The value of the compensation resistor R5 sets the
dynamic behavior of the converter. It can be
adjuste d to provide the best compro mise between
stability and recovering time with fast load
changes.
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
U1
VIPer73
R3
R4 D3
D1
C1
T1
C2
F1
R1
D2
C7
C5
C4
C6
T2
D4 C8
C10
L1
C9
R2
C3
AC IN
DC OUT
C11
10nF
R5
R6
1k
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Figure 15: Off Line Power Supply With Optocoupler Feedback
SECONDARY FEE DBACK CONFIGURATION
EXAMPLE
When a more accurate output voltage is needed,
the definitive way is to monitor it directly on
secondary side, and to drive the PWM controller
through an optocoupler as shown on figure 15.
The optocoupler is connected in parallel with the
compensation network on the COMP pin. The
design of the auxiliary winding will be made in such
a way that the VDD voltage is always lower than the
internal 15 V refe renc e. The internal error amplifi er
will therefore be saturated in the high state, and
because of its transconductance nature, will
deliver a cons t ant biasi ng c urrent of 0. 6 mA to the
optotransistor. Thi s cu rrent d oesn’t depe nd on the
compensation voltage, and so it doesn’t depend on
the output load either. The gain of the optocouple r
ensures consequently a constant biasing of the
TL431 device (U3) which is in charge of secondary
regulation. If the optocoupler gain is sufficiently
low, no additional components are required to
ensure a minimum current biasing of U3. Als o, the
low biasing current value avoi d any ageing of the
optocoupler.
The constant current biasing can be used to
simpli fy th e se condary circuit: Instead of a TL431,
a simple zener and resistance network in series
with the optocoupler diode can insure a good
secondary regulation. As t he current flowing in this
branch remains constant for the same reason as
above, typical load regulation of 1% can be
achieved from zero to full output current with this
simple configuration.
Since the dynam ic c haract eristics o f the converter
are set on the secondary side through components
associated to U3, the compensation network has
only a role of gain stabilization for the optocoupler,
and its valu e can be freely chose n. R5 can be set
to a fixed value of 1 kΩ, offering the po ssibility of
using C7 as a soft start capacitor: When starting up
the converter, the VIPer53 device delivers a
constant current of 0.6 mA on the COMP pin,
creating a constant voltage of 0.6 V in R5 and a
rising slope across C7. This voltage shape
together with the operating ra nge of 0.5 V to 4.5 V
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
U1
VIPer73
R5
R3
R4 D3
D1
C1
T1
C2
F1
R1
D2
C7
C5
C4
C6
T2
D4 C8
C10
L1
C9
R2
C3
AC IN
DC OUT
U2
U3
C12
R6
R7
R8
C11
10nF
R9
1k
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provides a soft start-up of the converter. The rising
speed of the out put voltage can be set through the
value of C7. C4 and C6 values must be adjusted
accordingly in order to ensure a correct start-up.
CURRENT MODE TOPOLOG Y
The VIPer53 implements the conventional current
mode control method for regulating the output
voltage. This kind of feedback i ncludes two nest ed
regulation loops:
The inner loop controls the peak primary current
cycle by cycle. When the Power MOSFET output
transistor is on, the inductor current (primary side
of the transformer) is monitored with a SenseFET
technique and converted into a voltage VS. When
VS reaches VCOMP, the power switch is turned off.
This structure is completely integrated as shown
on the Block Diagram of page 1, with the current
amplifier, the P WM com parator, t he blanking ti me
function and the PWM latch. The following formula
gives the peak current in the Power MOSFET
according to the compensation voltage:
The outer loop def ines the le ve l at which t he inne r
loop regulates peak current in the power switch.
For this purpos e, V COMP is driven b y the output of
the error amplifier (Either the internal one in
primary feedback configuration or a TL431 through
an optocoupler in secondary feedback
configuration, see figures 14 and 15) and is set
accordingly the peak drain current for each
switching cycle .
As the inner loop regulates the peak primary
current in the primary side of the transformer, all
input voltage changes are compens ated for before
impacting the output voltage. This results in an
improved line regulation, instantaneous correction
to line changes and better stability for the voltage
regulation loop.
Current mode topology also provides a good
converter start-up control. As the compensation
voltage can be cont rolled to i ncrease slowly during
the start-up phase, the peak primary current will
follow this soft voltage slope to provide a smooth
output voltage rise, without any overshoot. The
simpler voltage mode st ructure which only controls
the duty cycle, leads generally to high currents at
start-up with the risk of tr ansf ormer saturat ion. The
compensation pin can also be used to limit the
current capability of the device (See Current
Limitation section).
An integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spik es caused by primary side transformer
capacitance or secondary side rectifier reverse
recovery time when working in continuous mode.
STANDBY MODE
The device implements a special feature to
address the low load c ondition. The corresponding
function described hereafter consists of reducing
the switch ing frequency by going into burst mode,
with the following benefits:
– It reduces the switching losses, thus providing
low consumption on the mains lines. The device
is compliant with “Blue Angel” and other similar
standards, requiring less than 0.5 W of input
power when in standby.
– It allows the regulation of the output voltage,
even if the load corresponds to a duty c ycle that
the device is not able to generate because of the
internal blanking time , and associated m ini mum
turn on.
For this purpose, a comparator monitores the
COMP pin voltage, and maintains the PWM latch
and the P ower MOSFET in the off state as long as
VCOMP remains below 0.5 V (See Block Diagram
on page 1). If the output load requires a duty cycle
below the one defined by the minimum turn on of
the device, the er ror amplifier decreases its output
voltage until it reaches this 0.5 V threshold
(VCOMPoff). The Power MOSFET can be
completely off for some cycles, and resumes
normal operation as s oon as VCOMP is higher than
0.5 V. The output voltage is regulated in burst
mode. T he corres pondi ng ripple is not hi gher t han
the nominal one at full load.
In addition, the minimum turn on time which
defin es the frontie r between normal operat ion and
burst mode changes according to VCOMP value.
Below 1 V (VCOMPbl), the blanking time increases
to 40 0 ns, whereas it is 150 ns for high er v oltages
(See figure 11). The minimum turn on times
resulting from these values are respectively 600 ns
and 350 ns, when taking into account internal
propagation time. This brutal change induces an
hysteresis between normal operation and burst
mode as s hown on figure 16.
When the output power decreases, the system
reaches point 2 where VCOMP equals VCOMPbl.
The minimum turn on time passes immediately
from 350 ns to 600 ns, exceeding the effective turn
on time that should be needed at such output
power level. Therefore the regulation loop will
quickly drive VCOMP to VCOMPoff (Point 3) in order
to pass into burst mode and to control the output
voltage. The corresponding hysteresis can be
seen on the switching frequency which passes
from FSWnom which is the normal switching
frequency set by the components connected to the
OSC pin, to FSWstby. Note that this frequency is
I
Dpeak VCOMP VCOMPos
–
HCOMP
----------------------------------------------=
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actually an equ ivalent number of s witching pulses
per second, rather than a fixed switching
frequency, as the d evice is working in burst mode.
As long as the power remains below PRST the
output of the regulation loop remains stuck at
VCOMPsd and the converter works in burst mode.
Its “density” increases (i.e. the number of missing
cycles decreas es) as t he power approac hes P RST
and resumes finally normal operation at point 1.
The hysteresis cannot be seen on the switching
frequency, but the COMP pin voltage which
passes brut ally at that power le ve l from poi nt 3 to
point 1.
The power points value PRST and PSTBY are
defined by the following form ulas:
Where Ip(VCOMPbl) is the peak Power MOSFET
current corresponding to a compensation voltage
of VCOMPbl (1V), that is to say about 250 mA. Note
that th e power point P STBY where t he converter i s
going into burst mode does n’t depend on the input
voltage.
The standby frequen cy FSWstb y is given by:
The ratio between the nominal switching frequency
and the standby one can be as high as 4,
depending on the Lp value and input voltage.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An int egrat ed high voltage current source provides
a bias current from t he DRAIN pin during the start-
up phase. This current is partially absorbed by
internal control circuits in standby mode with
reduced consumption and also supplies the
external capacitor connected to the VDD pin. As
soon as the voltage on this pin reaches the high
voltage threshold VDDon of the UVLO logic, the
device turns into act ive mode and starts switching.
The start-up c urrent generato r is switched of f, and
the convert er should normally provide the nee ded
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure 14
or 15.
The ext ernal capac itor CVDD on the VDD pin m ust
be sized according to the time needed by the
converter to start-up, when the device starts
switching. This time tss depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the COMP
pin and possible secondary feedback circuit. The
following formula can be used for defining the
mini mum capac itor needed:
Figure 17 shows a typical start-up event. VDD
starts from 0 V with a charging current IDDch1 at
about 9 mA. When about VDDoff is reached, the
Fi
gure
16
:
S
tan
db
y
M
o
d
e
I
mp
l
ementat
i
on
VCOMP
VCOMPsd VCOMPbl
VCOMPoff
600ns
350ns
FSW
PIN
FSWnom
FSWstby
PSTBY
PRST
Minimum 1
3
2
1
2
3
ton
turn on
PRST 1
2
---FSWnom tb1td+()
2VIN
21
Lp
------⋅⋅ ⋅⋅=
PSTBY 1
2
---FSWnom Ip2VCOMPbl
()Lp⋅⋅ ⋅=
FSWstby PSTBY
PRST
-------------- FSWnom
⋅=
CVDD IDD1tss⋅
VDDhyst
----------------------->
Figu re 17: Startup Waveforms
IDD
IDD1
tss
IDDch2
IDDch1
t
t
VDDsd
VDDst
VDDreg
VDD
tsu
Obsolete Product(s) - Obsolete Product(s)
VIPer53DIP / VIPer53SP
16/24
charging current is reduced down to I DDch2 which
is about 0.6 mA. This lower current leads to a slope
change on the VDD rise. The device starts
switching for a VDD equal to VDDon, and the
auxiliary winding delivers so me energy to the VDD
capacitor after the start-up time tss.
The charging current change at VDDoff allows a fast
complete start-up time tsu, and maintains a low
restart duty cycle. This is especially useful f or short
circuits and overloads conditions, as described in
the following section.
SHORT-CIRCUIT AND OVERLOAD
PROTECTION
A VCOMPovl threshold of about 4.35 V has been
implemented on the COMP pin. When VCOMP goes
above this level, the capacitor connected on the
TOVL pin begins to charge. When reaching
typically 4 V (VOVLth), the internal mosfet driver is
disabled and the device stops switching. This state
is latched thanks to the regulation loop which
maintains the COMP pin voltage above the
VCOMPovl threshold. Since the VDD pin doesn’t
receive any more energy from the auxiliary
winding, its voltage drops down until it reaches
VDDoff and the device is reset, recharging the
VDD capacitor for a n ew restart cycle. Note that if
VCOMP drops down below t he VCOMPovl threshold
for any reason during the VDD drop, the device
resumes switch ing immed iately.
The device enters an endless restart sequence if
the overload or short circuit condition is
maintained. The restart duty cycle DRST is defined
as the time ratio for which the device tries to
restart, thus delivering its full power capability to
the output. In order to keep th e whole con ve rter in
a safe state during this event, D RST m ust be kept
as low as p ossible, without com prom ising the real
start up of the converter. A typical value of about
10 % i s generally sufficient. For this purpose, both
VDD and TOVL capacitors can be used to satisfy
the following conditions:
Refer to the previous start-up section for the
definition of tss, and CVDD must also be checked
against the limit given in this section. The
maximum value of the two calculus will be
adopted.
All this behavior can be observed on figure 4. In
Figure 8 the value of the drain current Id for
VCOMP=VCOMPovl is shown. The corresponding
parameter IDmax is the drain current to take into
account for design purpose. Since IDmax
represents the maximum value for which the
overload protection is not triggered, it defines the
power capability of the power supply.
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer53 includes a transconductance error
amplifier. Transconductance Gm is the change in
output current ICOMP versus change in input
voltage VDD. Thus:
The output impe dance ZCOMP at t he output of this
amplif ier (COMP pin) can be defined as:
This last equation shows that the open loop gain
AVOL can be related to Gm and Z COMP:
where Gm value for VIPer53 is typically 1.4 mA/V.
Gm is well defined by specification, but ZCOMP and
therefore A VOL a re subject to large tolerances. A n
impedance Z must be connected between the
COMP pin and ground in order to define accurately
the transfer function F of the error amplifier,
accordin g to the following equation, v ery similar to
the one above:
The error ampli fier frequency response is shown in
figure 10 for dif ferent values of a simple resistance
connected on the COMP pin. The unloaded
transconductance error amplifier shows an internal
ZCOMP of about 140 KΩ. More complex
impedances can be connected on the COMP pin to
achieve different compensation methods. A
capacitor provides an integrator function, thus
eliminating the DC static error, and a resistanc e in
series leads to a flat gain at higher frequency,
COVL 12.5 10 6–tss⋅⋅>
CVDD 810
41
DRST
------------ 1–
COVL IDDch2
⋅
VDDhyst
----------------------------------⋅⋅ ⋅>
Gm VDD
∂
∂ICOMP
=
ZCOMP ICOMP
∂
∂VCOMP 1
Gm
---------VDD
∂
∂VCOMP
⋅
==
AVOL Gm ZCOMP
⋅
=
Fs() Gm Z s()⋅=
Figu re 18: T ypical Com pensat ion Network
15V
VDD
OSC
DRAIN
SOURCECOMPTOVL
Rcomp
Ccomp
10nF
Obsolete Product(s) - Obsolete Product(s)
VIPe r53DIP / VIPer53SP
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introducing a zero and ensuring a correct phase
margin. This configuration i s illustrated in figure 18 for the schematic and figure 19 for the error
amplifier transfer function for a typical set of values
for CCOMP and RCOMP. Note that a capacitor of
10 nF (minimum value: 8 nF) should always be
connected to the COMP pin to insure a correct
stability of the internal error amplifier.
The complete converter open loop transfer
function can be built from bot h power cell and error
amplifier transfer functions. A theoretical example
can be seen in figure 20 for a discontinuo us mode
flyback loaded by a simple resistor, regulated from
primary side (no optocoupler, the internal error
amplifier is fully used for regulation). A typical
schematic corresponding to this situation can be
seen on figure 14.
The transfer function of the power cell is
represen ted as G(s) in figure 20. It e xhibits a pole
which depends on the output load and on the
output capacitor value. As the load of a converter
may change, two curves are shown for two
different values of output resistance value, R L1 and
RL2. A zero at higher frequency values then
appears, due to the output capacitor ESR. Note
that the overall transfer function doesn’t depend on
the input voltage, thanks to the current mode
control.
The error amplifier has a fixed behavior, simil ar to
the one shown in figure 19. Its bandwidth is limited,
in o rder to avoid i njection of high frequency noise
Fi
gure
19
:
T
yp
i
ca
l
T
rans
f
er
F
unct
i
ons
Frequenc y (H z)
1 10 100 1k 10k 100k 1M
Gain (dB)
-10
0
10
20
30
40
50
60 Rcomp=4.7k
Ccomp=470nF
Fr eq ue nc y (H z)
Phase (°)
1 10 100 1k 10k 100k 1M
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0Rcomp=4.7k
Ccomp=470nF
Obsolete Product(s) - Obsolete Product(s)
VIPer53DIP / VIPer53SP
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in the current mode section. A zero due to the
RCOMP-CCOMP net work i s set at the same valu e as
t he maximum load RL2 pole.
The total t ransfer function is shown as F(s).G(s) at
the bottom of figure 20. For maximum load (plain
line), the load pol e is exactly c ompensat ed by the
zero of the error amplifier, and the result is a
perfect first order decreasing s lope until it reaches
the zero of the output capacitor ESR. The error
amplif ier cut of f then prevents definitely any further
spurious noise or resonance from disturbing the
regulat ion loop.
The point where the complet e transfer function has
a unity gain is known as t he regula tio n bandwidth
and has a double interest:
– The highe r it is the fas ter will be the reaction to
an eventual load change, and the smaller will be
the output voltage change.
– The phase shift in the complete system at this
point has to be less t han 135 ° to ensure a good
stability. Generally, a first order gives 90 ° of
phase s hift, and 180 ° for a second order.
In figure 20, the unity gain is reached in a first order
slope, so the s tability is en su r ed.
The dynamic load regulation is improved by
increasing the regulation bandwidth, but some
limitations have to be respected: As the transfer
function above the zero due the capacitor ESR is
not reliable (The ESR itself is not well specified,
and other parasitic effects may take place), the
bandwidth should always be lower than the
minimum of FC and ESR zero.
As the highest bandwidth is obtained with the
highest output power (Plain line with RL2 load in
figure 20), the above criteria will be checked for
this condition and allows to define the value of
RCOMP, as the error amplifier gain depends only
on this value for this frequency range. The
following formula can be derived:
With:
And: :
The lowest load gives another condition for
stability: T he frequency FBW1 must not encounter
the second order slope generated by the load pole
and the integrator part of the error amplifier. This
condition can be met by adjusting the CCOMP
value:
With:
The above formula gives a minimum value for
CCOMP. It can be then increased to provide a
natural soft start function as this capacitor is
charged by the error amplifier current capacity
ICOMPhi at start-up.
Fi
gure
20
:
C
omp
l
ete
C
onverter
T
rans
f
er
F
unct
i
on
G(S)
F
FC
F
F
F(S)
F(S).G(S)
1
πRL1COUT
⋅⋅
----------------------------------------
1
πRL2COUT
⋅⋅
----------------------------------------
1
2πESR COUT
⋅⋅ ⋅
------------------------------------------------
1
2πRCOMP CCOMP
⋅⋅ ⋅
----------------------------------------------------------------
FBW2
FBW1
1
1
1
3.2 PMAX
POUT2
--------------------
⋅
3.2 PMAX
POUT1
--------------------
⋅
Gm RCOMP
⋅
RCOMP
POUT2
PMAX
----------------- FBW2RL2COUT
⋅⋅
Gm
------------------------------------------------
⋅
=
POUT2
VOUT
2
RL2
--------------=
PMAX 1
2
---LPILIM
2FSW
⋅⋅ ⋅
=
CCOMP
RL1COUT
⋅
6.3 Gm RCOMP
2
⋅⋅
---------------------------------------------POUT1
PMAX
-----------------
⋅>
POUT1
VOUT
2
RL1
--------------=
Obsolete Product(s) - Obsolete Product(s)
VIPe r53DIP / VIPer53SP
19/24
SPECIAL RECOMMENDATIONS
As stated in t he error amplifier section, a capacitor
of 10 nF (minim um value: 8 nF) s hould always be
connected to the COMP pin to insure a correct
stability of the internal error amplifier. This is
represented on figures 14, 15 and 18.
In order to improve the ruggedness of the device
versus eventual drain overvoltages, a resistance of
1kΩ should be inserted in series with the TOVL
pin, as shown on figures 1 4 an d 15. No te that this
resistance doesn’t impact the overload delay, as its
value is negligible in front of the internal pull up
resistance (about 125 kΩ).
SOFTWARE IMPLE MEN T A TION
All the above cons iderations and some o thers are
included in a design software which provides all
the needed com ponents around the VIPer device
for a specified output configuration. This software
is available in download on the ST internet site.
Obsolete Product(s) - Obsolete Product(s)
VIPer53DIP / VIPer53SP
20/24
DIM. mm.
MIN. TYP MAX.
A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56
b2 1.14 1.52 1.78
c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.26
E1 6.10 6.35 7.11
e 2.54
eA 7.62
eB 10.92
L 2.92 3.30 3.81
Package Weig ht Gr. 470
P001
Plastic DIP-8 MECHANICAL DATA
Obsolete Product(s) - Obsolete Product(s)
VIPe r53DIP / VIPer53SP
21/24
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A (*) 3.4 3.6 0.134 0.142
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
B (*) 0.37 0.53 0.014 0.021
C 0.35 0.55 0.013 0.022
C (*) 0.23 0.32 0.009 0.0126
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
E 9.30 9.50 0.366 0.374
E2 7.20 7.60 0.283 300
E2 (*) 7.30 7.50 0.287 0.295
E4 5.90 6.10 0.232 0.240
E4 (*) 5.90 6.30 0.232 0.248
e 1.27 0.050
F 1.25 1.35 0.049 0.053
F (*) 1.20 1.40 0.047 0.055
H 13.80 14.40 0.543 0.567
H (*) 13.85 14.35 0.545 0.565
h 0.50 0.002
L 1.20 1.80 0.047 0.070
L (*) 0.80 1.10 0.031 0.043
α0º 8º 0º 8º
α (*) 2º 8º 2º 8º
PowerSO-10™ MECHANICAL DATA
(*) Muar only POA P013P
DETAIL "A"
PLANE
SEATING
α
L
A1
F
A1
h
A
D
D1
= =
= =
E4
0.10 A
C
A
B
B
DETAIL "A"
SEATING
PLANE
E2
10
1
eB
HE
0.25
P095A
Obsolete Product(s) - Obsolete Product(s)
VIPer53DIP / VIPer53SP
22/24
PowerSO-10™ SUG G EST ED PAD LAYO U T
1
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
All dimensions are in mm.
Base Q.ty 600
Bulk Q.ty 600
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spac ing P0 (± 0.1) 4
Component Spacing P 24
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No co m ponentsNo com ponents Co m ponents
500m m min
500m m min
Em pty components pockets
sa led with co ver tape.
User direction of feed
6.30
10.8 - 11
14.6 - 14.9
9.5
1
2
3
4
51.27
0.67 - 0.73
0.54 - 0.6
10
9
8
7
6
B
A
C
All dime nsions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1)
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8
TUBE SHIPMENT (no suffix)
C
A
B
MUARCASABLANCA
Obsolete Product(s) - Obsolete Product(s)
VIPe r53DIP / VIPer53SP
23/24
1
DIP-8 TUB E SHIPMENT (no suffix)
All dimensions are in mm.
Base Q.ty 20
Bulk Q.ty 1000
Tube length (± 0.5) 532
A8.4
B11.2
C (± 0.1) 0.8
A
B
C
Obsolete Product(s) - Obsolete Product(s)
VIPer53DIP / VIPer53SP
24/24
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of use o f such inf ormation nor for any inf ringement of patents or other rig hts of th ird parties which may results from its u se . No license is
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are n ot authori zed for use as critical components in lif e support devices or s ys tems wi thout ex press written approval of STM i croelectronics.
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