1/16
¡ Semiconductor MSM514800C/CSL
DESCRIPTION Please ignore data of MSM518400C (not available)
The MSM514800CSL is a 524,288-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514800CSL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM514800CSL is available in a 28-pin plastic SOJ or 28-
pin plastic TSOP. The self-refresh version) is specially designed for lower-
power applications.
FEATURES
• 524,288-word ¥ 8-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
•Refresh: 1024 cycles/128 ms
• Fast page mode, read modify write capability
•CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•CAS before RAS self-refresh capability
• Package options:
28-pin 400 mil plastic SOJ(SOJ28-P-400-1.27)(Product : MSM514800CSL-xxJS)
28-pin 400 mil plastic TSOP
(TSOPII28-P-400-1.27-K)
(Product : MSM514800CSL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
¡ Semiconductor
MSM514800CSL
524,288-Word ¥ 8-Bit DYNAMIC RAM: FAST PAGE MODE TYPE
Family
t
RAC
60 ns
70 ns
80 ns
Operating (Max.)
660 mW
605 mW
550 mW
Power Dissipation
Cycle Time
(Min.)
110 ns
130 ns
150 ns
MSM514800CSL-60
MSM514800CSL-70
MSM514800CSL-80
t
AA
30 ns
35 ns
40 ns
t
CAC
20 ns
20 ns
20 ns
Standby (Max.)
Access Time (Max.)
1.1 mW
t
OEA
20 ns
20 ns
20 ns
E2G0024-17-42
This version: Jan. 1998
Previous version: May 1997
2/16
¡ Semiconductor MSM514800C/CSL
PIN CONFIGURATION (TOP VIEW)
28-Pin Plastic SOJ 28-Pin Plastic TSOP
(K Type)
3
4
5
9
10
11
12
13
DQ2
DQ3
DQ4
A9R
A0
A1
A2
A3
26
25
24
20
19
18
17
16
DQ7
DQ6
DQ5
A8
A7
A6
A5
A4
2
DQ1 27 DQ8
1
V
CC
28 V
SS
3
4
5
9
10
11
12
13
26
25
24
20
19
18
17
16
227
128
6NC 23 23
821NC 21
6
8
722 227
14V
CC
15 V
SS
14 15
DQ2
DQ3
DQ4
A9R
A0
A1
A2
A3
DQ1
V
CC
NC
V
CC
DQ7
DQ6
DQ5
A8
A7
A6
A5
A4
DQ8
V
SS
NC
CAS
RAS
WE OE
RAS
WE
CAS
OE
V
SS
Pin Name Function
A0 - A8, A9R Address Input
RAS Row Address Strobe
CAS Column Address Strobe
DQ1 - DQ8 Data Input / Data Output
OE Output Enable
Write Enable
Power Supply (5 V)
Ground (0 V)
NC No Connection
V
CC
V
SS
WE
Note: The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
3/16
¡ Semiconductor MSM514800C/CSL
BLOCK DIAGRAM
Timing
Generator
Timing
Generator
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
A0 - A8
VCC
VSS
On Chip
VBB Generator
Row
De-
coders
Word
Drivers
Memory
Cells
Refresh
Control Clock
Sense
Amplifiers
Column
Decoders
Write
Clock
Generator
I/O
Selector
Output
Buffers
RAS
CAS
WE
OE
8DQ1 - DQ8
8
88
8
8Input
Buffers
8
9
10
9
9
1
A9R
4/16
¡ Semiconductor MSM514800C/CSL
*: Ta = 25°C
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
–1.0 to 7.0
50
1
0 to 70
–55 to 150
V
mA
W
°C
°C
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
VT
IOS
PD*
Topr
Tstg
Parameter UnitSymbol
Recommended Operating Conditions
Input High Voltage
Power Supply Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
Max.
5.5
0
6.5
0.8
V
V
V
V
Typ.
5.0
0
—
—
Min.
4.5
0
2.4
–1.0
(Ta = 0°C to 70°C)
Parameter UnitSymbol
Capacitance
Input Capacitance (A0 - A8, A9R) C
IN1
C
IN2
C
I/O
pF
pF
pF
Input Capacitance
(RAS, CAS, WE, OE)
Output Capacitance (DQ1 - DQ8)
Max.
7
7
8
Typ.
—
—
—
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
Parameter UnitSymbol
5/16
¡ Semiconductor MSM514800C/CSL
DC Characteristics
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
4. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
5. SL version.
Parameter
Symbol
Condition
MSM514800
C/CSL-70
MSM514800
C/CSL-80
MSM514800
C/CSL-60
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C)
I
OH
= –5.0 mAOutput High Voltage
I
OL
= 4.2 mAOutput Low Voltage
0 V £ V
I
£ 6.5 V;
All other pins notInput Leakage Current
under test = 0 V
DQ disable
Output Leakage Current 0 V £ V
O
£ 5.5 V
RAS, CAS cycling,
Average Power
t
RC
= Min.
Supply Current
(Operating)
RAS, CAS = V
IH
Power Supply RAS, CAS
Current (Standby)
RAS cycling,Average Power
CAS = V
IH
,Supply Current
t
RC
= Min.(RAS-only Refresh)
RAS = V
IH
,
Power Supply CAS = V
IL
,
Current (Standby) DQ = enable
Average Power
CAS before RAS
Supply Current
(CAS before RAS Refresh)
RAS = V
IL
,Average Power
CAS cycling,Supply Current
t
PC
= Min.(Fast Page Mode)
t
RC
= 125 ms,
Average Power
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC5
I
CC6
I
CC7
I
CC10
CAS before RAS,
Supply Current
t
RAS
£ 1 ms
(Battery Backup)
≥ V
CC
–0.2 V
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
110
2
1
110
5
110
100
300
200
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
100
2
1
100
5
100
90
300
200
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
120
2
1
120
5
120
110
300
200
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
1, 2
1
1, 2
1
1, 2
1, 3
1, 4,
5
1, 5
RAS cycling,
Average Power
I
CCS
RAS £ 0.2 V,
Supply Current
CAS £ 0.2 V
(CAS before RAS — 300 — 300— 300 mA1, 5
Self-Refresh)
6/16
¡ Semiconductor MSM514800C/CSL
AC Characteristics (1/2)
Parameter
MSM514800
C/CSL-70
MSM514800
C/CSL-80
MSM514800
C/CSL-60
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
CAS to Data Output Buffer Turn-off Delay Time
Transition Time
RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
CAS Pulse Width
CAS Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
Access Time from OE
OE to Data Output Buffer Turn-off Delay Time
Refresh Period
Refresh Period (SL version)
RAS Hold Time referenced to OE
Min. Max. Min. Max.
RAS Hold Time from CAS Precharge
Symbol
tRC
tRWC
tPC
tPRWC
tRAC
tCAC
tAA
tCPA
tOFF
tT
tRP
tRAS
tRASP
tRSH
tCAS
tCSH
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tOEA
tOEZ
tREF
tREF
tROH
tRHCP
Min. Max.
Output Low Impedance Time from CAS tCLZ
CAS Precharge Time (Fast Page Mode) tCP
tAR
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
110
155
40
85
—
—
—
—
0
0
3
40
60
60
15
10
20
60
20
15
10
0
10
0
10
30
0
0
0
—
0
—
—
15
—
—
—
—
60
20
30
35
—
15
50
—
10,000
100,000
—
—
10,000
—
40
30
—
—
—
—
—
—
—
—
—
20
15
16
128
—
150
205
50
105
—
—
—
—
0
0
3
60
80
80
20
10
20
80
20
15
10
0
10
0
15
40
0
0
0
—
0
—
—
20
—
—
—
—
80
20
40
45
—
20
50
—
10,000
100,000
—
—
10,000
—
60
40
—
—
—
—
—
—
—
—
—
20
20
16
128
—
4, 5, 6
4, 5
4, 6
4
7
5
6
8
8
4
7
4
3
11
130
185
45
100
—
—
—
—
0
0
3
50
70
70
20
10
20
70
20
15
10
0
10
0
15
35
0
0
0
—
0
—
—
20
—
—
—
—
70
20
35
40
—
20
50
—
10,000
100,000
—
—
10,000
—
50
35
—
—
—
—
—
ns50 — 60 —55 —
—
—
—
—
20
20
16
128
—
ns35 — 45 —40 —
7/16
¡ Semiconductor MSM514800C/CSL
AC Characteristics (2/2)
MSM514800
C/CSL-70
MSM514800
C/CSL-80
MSM514800
C/CSL-60
Write Command Pulse Width
Write Command to CAS Lead Time
Write Command to RAS Lead Time
Data-in Set-up Time
Data-in Hold Time from RAS
CAS to WE Delay Time
RAS to WE Delay Time
Column Address to WE Delay Time
RAS to CAS Hold Time (CAS before RAS)
CAS Active Delay Time from RAS Precharge
Data-in Hold Time
Write Command Hold Time
Write Command Hold Time from RAS
OE Command Hold Time
OE to Data-in Delay Time
RAS Pulse Width
(CAS before RAS Self-Refresh)
RAS Precharge Time
(CAS before RAS Self-Refresh)
CAS Hold Time
(CAS before RAS Self-Refresh)
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Write Command Set-up Time
t
WP
t
CWL
t
RWL
t
DS
t
DHR
t
CWD
t
RWD
t
AWD
t
CHR
t
RPC
t
DH
t
WCH
t
WCR
t
OEH
t
OED
t
RASS
t
RPS
t
CHS
t
WCS
Min. Max.
Parameter
Symbol
Min. Max. Min. Max.
RAS to CAS Set-up Time (CAS before RAS)t
CSR
CAS Precharge WE Delay Time t
CPWD
NoteUnit
15
20
20
0
55
50
100
65
10
15
10
15
15
55
20
20
100
130
–50
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
10
9
9
9
10
11
11
11
9
15
15
15
0
50
40
90
60
10
15
10
15
15
50
15
15
100
110
–40
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
20
0
60
50
110
70
10
15
10
15
15
60
20
20
100
150
–60
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
70 — ns65 — 75 —
8/16
¡ Semiconductor MSM514800C/CSL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. Only SL version.
9/16
¡ Semiconductor MSM514800C/CSL
TIMING WAVEFORM
Read Cycle
,
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
OH
V
OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,
,
t
RC
t
RAS
t
RP
t
AR
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
Row Column
t
RCS
t
RRH
t
RCH
t
AA
t
ROH
t
OEA
t
CAC
t
RAC
t
OEZ
t
OFF
Open
t
CLZ
Valid Data-out
Write Cycle (Early Write)
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,,,
t
RC
t
RAS
t
RP
t
AR
t
CRP
t
RCD
t
CSH
t
RSH
t
CRP
t
CAS
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
Row Column
t
WCS
t
WCH
t
WCR
t
DHR
t
DS
t
DH
Valid Data-in
t
WP
t
RAL
Open
t
CWL
t
RWL
E2G0096-17-41I
10/16
¡ Semiconductor MSM514800C/CSL
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
I/OH
V
I/OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,
,,
t
RWC
t
RAS
t
RP
t
AR
t
CRP
t
CSH
t
RCD
t
CRP
t
RSH
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
Row Column
t
CWD
t
CWL
t
RWD
t
RWL
t
WP
t
AA
t
AWD
t
OEA
t
OED
t
CAC
t
RAC
t
OEZ
t
DS
t
DH
t
CLZ
Valid
Data-out
Valid
Data-in
t
RAD
t
RCS
t
OEH
Read Modify Write Cycle
11/16
¡ Semiconductor MSM514800C/CSL
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle (Early Write)
"H" or "L"
RAS
CAS
VIH
VIL
–
–
VIH
VIL
–
–
DQ VIH
VIL
–
–
Address VIL
–
–
WE VIH
VIL
–
–
,
,
,
tRASP tRP
tAR
tCRP tRCD
tCAS
tCP tCAS
tRSH
tCRP
tCAS
tASR tRAH tCAH
tCSH tASC tCAH tASC tCAH
tRAL
Row Column Column Column
tRAD
tWCS tWCH
tWP
tWCS tWCH
tWP
tWCS tWCH
tWP
tDS tDH tDS tDH tDS tDH
Valid Data-in Valid
Data-in
Valid
Data-in
tDHR
Note: OE = "H" or "L"
VIH
tASC
tPC tRHCP
tCP
tCWL tCWL tRWL
tCWL
tWCR
,
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
OH
V
OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,
,
,
t
RASP
t
RP
t
AR
t
CRP
t
RCD
t
PC
t
RSH
t
CRP
t
CAS
t
CAS
t
CP
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
Row Column Column Column
t
RCS
t
RCH
t
RCS
t
RCS
t
RCH
t
AA
t
OEA
t
AA
t
AA
t
RRH
t
OEA
t
OEA
t
CAC
t
RAC
t
OFF
t
OEZ
t
CAC
t
CLZ
t
OFF
t
OEZ
t
CAC
t
CLZ
t
OEZ
t
OFF
t
CLZ
Valid
Data-out
Valid
Data-out
Valid
Data-out
t
RHCP
t
CP
t
RCH
t
CPA
t
CPA
12/16
¡ Semiconductor MSM514800C/CSL
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
,
t
RC
t
RAS
t
RP
t
CRP
t
RPC
t
ASR
t
RAH
Row
"H" or "L"
DQ V
OH
V
OL
–
–
Note: WE, OE = "H" or "L"
Open
t
OFF
Fast Page Mode Read Modify Write Cycle
t
WP
RAS
CAS
Address
OE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
DQ V
I/OH
V
I/OL
–
–
,
,
,
,
,
,
,
t
RASP
t
AR
t
RP
t
CSH
t
PRWC
t
RSH
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
Row Column Column Column
t
RWD
t
RCS
t
CWD
t
CWL
t
CWD
t
CWL
t
CWD
t
RWL
t
CWL
t
AWD
t
AWD
t
AWD
t
OEA
t
WP
t
OEA
t
WP
t
OEA
t
AA
t
OED
t
CAC
t
DS
t
DH
t
CAC
t
AA
t
RAC
t
DS
t
DH
t
CPA
t
OED
t
CAC
t
AA
t
DS
t
DH
t
CLZ
t
CLZ
t
CLZ
Out In Out OutIn In
t
ROH
t
OEZ
t
OEZ
t
CPA
t
OED
t
RCS
t
RCS
t
CPWD
t
CPWD
"H" or "L"
t
OEZ
RAS-Only Refresh Cycle
13/16
¡ Semiconductor MSM514800C/CSL
RAS
CAS
VIH
VIL
–
–
VIH
VIL
–
–
Column
Row
DQ VOH
VOL
–
–
WE VIH
VIL
–
–
OE VIH
VIL
–
–
Address VIH
VIL
–
–
,,
,
tRC tRC
tRAS tRP tRAS tRP
tAR
tCRP tRCD tRSH tCHR
tRAD
tASR
tASC
tRAH tCAH
tRCS tRAL tRRH
tAA
tROH
tOEA
tCAC
tCLZ
tRAC
tOFF
tOEZ
Valid Data-out
,
"H" or "L"
CAS before RAS Refresh Cycle
Hidden Refresh Read Cycle
RAS
CAS
VIH
VIL
–
–
VIH
VIL
–
–
tCHR
Note: WE, OE, Address = "H" or "L"
DQ VOH
VOL
–
–
tRC
tRP tRAS tRP
tRPC
tCP tCSR
tRPC
tOFF
Open
,,
"H" or "L"
14/16
¡ Semiconductor MSM514800C/CSL
Hidden Refresh Write Cycle
RAS
CAS
Address
OE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
"H" or "L"
WE V
IH
V
IL
–
–
DQ V
IH
V
IL
–
–
,
,,
,
,,
t
RC
t
RC
t
RAS
t
RAS
t
RP
t
RP
t
AR
t
CRP
t
RCD
t
RSH
t
CHR
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
Row Column
t
RWL
t
WCS
t
WCH
t
WP
t
WCR
t
DS
t
DH
Valid Data-in
t
DHR
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
"H" or "L"
,
DQ V
OH
V
OL
–
–
t
RP
t
RASS
t
RPS
t
RPC
t
CSR
t
CP
t
RPC
t
CHS
Open
Note: WE, OE, Address = "H" or "L"
Only SL version
t
OFF
"H" or "L"
CAS before RAS Self-Refresh Cycle
15/16
¡ Semiconductor MSM514800C/CSL
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
SOJ28-P-400-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.30 TYP.
Mirror finish
16/16
¡ Semiconductor MSM514800C/CSL
(Unit : mm)
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
TSOPII28-P-400-1.27-K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.51 TYP.
Mirror finish
