FAST PRODUCTS 74F373 Octal transparent latch (3-State) 74F374 Octal D flip-flop (3-State) Product specification IC15 Data Handbook Philips Semiconductors 1994 Dec 05 Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 74F373 Octal transparent latch (3-State) 74F374 Octal D-type flip-flop (3-State) The 74F374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. FEATURES * 8-bit transparent latch -- 74F373 * 8-bit positive edge triggered register -- 74F374 * 3-State outputs glitch free during power-up and power-down * Common 3-State output register * Independent register and 3-State buffer operation * SSOP Type II Package The register is fully edge triggered. The state of the D input, one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is low, the data in the register appears at the outputs. When OE is high, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. TYPE The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. 74F373 The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. TYPE The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. 74F374 TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 4.5ns 35mA TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 165MHz 55mA When OE is high, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE PKG DWG # VCC = 5V 10%, Tamb = 0C to +70C 20-pin plastic DIP N74F373N, N74F374N SOT146-1 20-pin plastic SOL N74F373D, N74F374D SOT163-1 20-pin plastic SSOP type II N74F373DB, N74374DB SOT399-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20A/0.6mA Enable input (active high) 1.0/1.0 20A/0.6mA Output enable inputs (active low) 1.0/1.0 20A/0.6mA Clock pulse input (active rising edge) 1.0/1.0 20A/0.6mA 3-State outputs 150/40 3.0mA/24mA PINS D0 - D7 E (74F373) OE CP (74F374) Q0 - Q7 DESCRIPTION NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. December 5, 1994 2 853-0369 14383 Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 PIN CONFIGURATION - 74F373 PIN CONFIGURATION - 74F374 OE OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 Q0 D0 D1 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 Q1 Q2 D2 D2 7 14 D5 D3 D3 8 13 D4 Q3 9 12 Q4 Q3 GND GND 10 11 E 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 SF00250 4 7 8 13 14 17 18 3 E 11 CP 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 D6 Q6 Q5 D5 D4 Q4 CP 9 12 VCC = Pin 20 GND = Pin 10 15 16 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 OE 1 D7 IEC/IEE SYMBOL - 74F374 D0 D1 D2 D3 D4 D5 D6 D7 11 Q7 SF00253 LOGIC SYMBOL - 74F373 3 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 2 5 6 9 12 15 16 19 VCC = Pin 20 GND = Pin 10 SF00251 SF00254 IEC/IEEE SYMBOL - 74F374 IEC/IEEE SYMBOL - 74F373 1 1 11 3 11 EN1 EN2 2D 3 1 2 EN1 C2 2D 1 2 4 5 7 6 9 4 5 7 6 8 9 13 12 13 12 14 15 14 15 17 16 18 19 8 17 16 18 19 SF00255 SF00252 December 5, 1994 3 Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 LOGIC DIAGRAM FOR 74F373 D1 4 D0 3 D E D2 7 D E Q D3 8 D E Q D4 13 D E Q D5 14 D E Q D6 17 D E Q D7 18 D E Q D E Q Q 11 E OE 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 15 Q4 16 Q5 19 Q6 Q7 SF00256 LOGIC DIAGRAM FOR 74F374 D0 3 D1 4 D CP Q CP OE D2 7 D CP Q D3 8 D CP Q D4 13 D CP Q D5 14 D CP Q D6 17 D CP Q D7 18 D CP Q D CP Q 11 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 Q4 15 Q5 16 Q6 19 Q7 SF00257 FUNCTION TABLE FOR 74F373 E Dn INTERNAL REGISTER OUTPUTS OE INPUTS L H L L L L H H H H L l L L L h H H L L X NC NC H L X NC Z H H Dn Dn Z NOTES: H = High-voltage level h = High state must be present one setup time before the high-to-low enable transition L = Low-voltage level l = Low state must be present one setup time before the high-to-low enable transition NC= No change X = Don't care Z = High impedance "off" state = High-to-low enable transition December 5, 1994 OPERATING MODE Q0 - Q7 4 Enable and read register Latch and read register Hold Disable outputs Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 FUNCTION TABLE FOR 74F374 INTERNAL OUTPUTS OE INPUTS CP Dn REGISTER Q0 - Q7 L l L L L h H H L X NC NC H X NC Z H Dn Dn Z NOTES: H = High-voltage level h = High state must be present one setup time before the low-to-high clock transition L = Low-voltage level l = Low state must be present one setup time before the low-to-high clock transition NC= No change X = Don't care Z = High impedance "off" state = Low-to-high clock transition Not low-to-high clock transition = OPERATING MODE Load and read register Hold Disable outputs ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) RATING UNIT VCC Supply voltage PARAMETER -0.5 to +7.0 V VIN Input voltage -0.5 to +7.0 V IIN Input current -30 to +5 mA VOUT Voltage applied to output in high output state -0.5 to VCC V IOUT Current applied to output in low output state 48 mA Tamb Operating free air temperature range 0 to +70 C Tstg Storage temperature range -65 to +150 C SYMBOL RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current -18 mA IOH High-level output current -3 mA IOL Low-level output current 24 mA Tamb Operating free air temperature range +70 C December 5, 1994 0 5 V V Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL 10%VCC 2.4 VIH = MIN, IOH = MAX 5%VCC 2.7 VCC = MIN, VIL = MAX, 10%VCC VIH = MIN, IOL = MAX 5%VCC High level output voltage High-level VOL O Low level output voltage Low-level VIK II IIH IIL Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V IOZH Off-state output current, high-level voltage applied IOZL Off-state output current, low-level voltage applied current3 Short-circuit output ICC Supply current (total) MIN VCC = MIN, VIL = MAX, VOH IOS LIMITS TEST CONDITIONS1 PARAMETER MAX UNIT V 3.4 V 0.35 0.50 V 0.35 0.50 V -0.73 -1.2 100 20 -0.6 V A A mA VCC = MAX, VO = 2.7V 50 A VCC = MAX, VO = 0.5V -50 A -150 mA 60 mA VCC = MAX 74F373 TYP2 -60 35 VCC = MAX 74F374 57 86 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION Tamb = 0C to +70C VCC = +5.0V CL = 50pF, RL = 500 VCC = +5.0V 10% CL = 50pF, RL = 500 UNIT MIN TYP MAX MIN MAX Waveform 3 3.0 2.0 5.3 3.7 7.0 5.0 3.0 2.0 8.0 6.0 ns Waveform 2 5.0 3.0 9.0 4.0 11.5 7.0 5.0 3.0 12.0 8.0 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL Propagation delay E to Qn tPZH tPZL Output enable time to high or low level Waveform 6 Waveform 7 2.0 2.0 5.0 5.6 11.0 7.5 2.0 2.0 11.5 8.5 ns tPHZ tPLZ Output disable time from high or low level Waveform 6 Waveform 7 2.0 2.0 4.5 3.8 6.5 5.0 2.0 2.0 7.0 6.0 ns fmax Maximum clock frequency Waveform 1 150 165 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.5 3.5 5.0 5.0 7.5 7.5 3.0 3.0 8.5 8.5 ns tPZH tPZL Output enable time to high or low level Waveform 6 Waveform 7 2.0 2.0 9.0 5.3 11.0 7.5 2.0 2.0 12.0 8.5 ns tPHZ tPLZ Output disable time from high or low level Waveform 6 Waveform 7 2.0 2.0 5.3 4.3 6.0 5.5 2.0 2.0 7.0 6.5 ns December 5, 1994 74F373 74F374 6 140 ns Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 AC SETUP REQUIREMENTS LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu (L) Setup time, high or low level Dn to E th (H) th (L) Hold time, high or low level Dn to E tw (H) E Pulse width, high tsu (H) tsu (L) Setup time, high or low level Dn to CP th (H) th (L) Hold time, high or low level Dn to CP tw (H) tw (L) CP Pulse width, high or low 74F373 74F374 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL= 50pF, RL = 500 MAX MIN UNIT MAX Waveform 4 0 1.0 0 1.0 ns Waveform 4 3.0 3.0 3.0 3.0 ns Waveform 1 3.5 4.0 ns Waveform 5 2.0 2.0 2.0 2.0 ns Waveform 5 0 0 0 0 ns Waveform 5 3.5 4.0 3.5 4.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn 1/fmax CP V M VM VM VM VM tPLH tw(L) VM Qn tPHL tPLH tw(H) tPHL Qn VM VM VM SF00260 SF00258 Waveform 3. Propagation delay for data to output Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency Dn tsu(H) tw(H) E VM VM tPHL Qn VM E VM VM th(H) VM tsu(L) VM th(L) VM tPLH VM SF00261 VM Waveform 4. Data setup time and hold times SF00259 Waveform 2. Propagation delay for enable to output and enable pulse width December 5, 1994 VM 7 Philips Semiconductors Product specification Latch/flip-flop 74F373/74F374 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn VM VM tsu(H) VM tsu(L) th(H) VM OEn VM VM th(L) tPZL CP VM tPLZ VM VM Qn, Qn VOL +0.3V SF00262 Waveform 5. Data setup time and hold times SF00264 Waveform 7. 3-State output enable time to low level and output disable time from low level OEn VM VM tPZH tPHZ Qn, Qn VOH -0.3V VM 0V SF00263 Waveform 6. 3-State output enable time to high level and output disable time from high level TEST CIRCUIT AND WAVEFORMS SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open PULSE GENERATOR 7.0V VCC tw 90% NEGATIVE PULSE 90% VM VM 10% VIN RL VOUT AMP (V) 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V D.U.T. RT CL RL Test circuit for 3-state outputs AMP (V) VM VM 10% 10% tw DEFINITIONS: 0V Input pulse definition RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 90% POSITIVE PULSE INPUT PULSE REQUIREMENTS family amplitude 74F 3.0V VM 1.5V rep. rate 1MHz tw tTLH 500ns 2.5ns tTHL 2.5ns SF00265 December 5, 1994 8 Philips Semiconductors Product specification Latch/flip-flop 74F373, 74F374 DIP20: plastic dual in-line package; 20 leads (300 mil) 1994 Dec 05 9 SOT146-1 Philips Semiconductors Product specification Latch/flip-flop 74F373, 74F374 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1994 Dec 05 10 SOT163-1 Philips Semiconductors Product specification Latch/flip-flop 74F373, 74F374 NOTES 1994 Dec 05 11 Philips Semiconductors FAST Products Product specification Latch/flip-flop 74F373, 74F374 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1994 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05119