Features
• Multisourced 2 x 5 package style
• Operates with 62.5/125 µm and 50/125 µm multimode
ber
• Single +3.3 V power supply
• Wave solder and aqueous wash process compatibil-
ity
• Manufactured in an ISO 9001 certied facility
• Full compliance with ATM Forum
• UNI SONET OC-3 multimode ber physical layer speci-
cation
• Full compliance with the optical performance require-
ments of the FDDI PMD standard
• Full compliance with the optical performance require-
ments of 100Base-FX version of IEEE802.3u
• RoHS compliant
• PECL Signal Detect Output
• Temperature range:
HFBR-5961LZ 0 °C to +70 °C
HFBR-5961ALZ -40 °C to +85 °C
HFBR-5961GZ 0 °C to +70°C (No EMI shield)
HFBR-5961AGZ -40 °C to +85°C (No EMI shield)
Applications
• SONET/SDH equipment interconnect, OC-3/SDH
STM-1 rate
• Fast Ethernet
• Multimode ber ATM backbone links
Description
The HFBR-5961xxZ transceiver from Avago provides the
system designer with a product to implement a range of
solutions for multimode ber Fast Ethernet and SONET
OC-3 (SDH STM-1) physical layers for ATM and other
services.
This transceiver is supplied in the industry standard 2 x
5 DIP style with an LC ber connector interface with an
external connector shield.
Transmitter Section
The transmitter section of the HFBR-5961xxZ utilizes
a 1300 nm InGaAsP LED. This LED is packaged in the
optical subassembly portion of the transmitter section.
It is driven by a custom silicon IC which converts dier-
ential PECL logic signals, ECL referenced (shifted) to a
+3.3 V supply, into an analog LED drive current.
Receiver Section
The receiver section of the HFBR-5961xxZ utilizes an
InGaAs PIN photodiode coupled to a custom silicon
transimpedance preamplier IC. It is packaged in the
optical subassembly portion of the receiver.
This PIN/preamplier combination is coupled to a
custom quantizer IC which provides the nal pulse
shaping for the logic output and the Signal Detect
function. The Data output is dierential. The Signal
Detect output is single ended. Both Data and Signal
Detect outputs are PECL compatible, ECL referenced
(shifted) to a +3.3 V power supply. The receiver
outputs, Data Output and Data Out Bar, are squelched
at Signal Detect deassert. That is, when the light input
power decreases to a typical -38 dBm or less, the Signal
Detect deasserts, ie. the Signal Detect output goes to a
PECL low state. This forces the receiver outputs, Data
Out and Data Out Bar to go steady PECL levels high and
low respectively.
HFBR-5961LZ/ALZ/GZ/AGZ
Multimode Small Form Factor (SFF) Transceivers for ATM, FDDI,
Fast Ethernet and SONET OC-3/SDH STM-1 with LC connector
Data Sheet
2
Figure 1. Block Diagram
DATA OUT
SIGNAL
DETECT
DATA IN
QUANTIZER IC
LED DRIVER IC
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
LED
OPTICAL
SUBASSEMBLY
DATA OUT
DATA IN
LC
RECEPTACLE
RX
SUPPLY
TX
SUPPLY
RX
GROUND
TX
GROUND
Package
The overall package concept for the Avago transceiver
consists of three basic elements; the two optical subas-
semblies, an electrical subassembly, and the housing as
illustrated in the block diagram in Figure 1.
The package outline drawing and pin out are shown in
Figures 2 and 5. The details of this package outline and
pin out are compliant with the multisource denition of
the 2 x 5 DIP. The low prole of the Avago transceiver
design complies with the maximum height allowed for
the LC connector over the entire length of the package.
The optical subassemblies utilize a high-volume
assembly process together with low-cost lens elements
which result in a cost eective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the ICs and
various surface mounted passive circuit elements are
attached.
The receiver section includes an internal shield for the
electrical and optical subassemblies to ensure high
immunity to external EMI elds.
The outer housing including the LC ports is molded
of lled nonconductive plastic to provide mechani-
cal strength. The solder posts of the Avago design are
isolated from the internal circuit of the transceiver.
The transceiver is attached to a printed circuit board
with the ten signal pins and the two solder posts which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand
the loads imposed on the transceiver by mating with
the LC connector ber cables.
3
Figure 2. Pin Out Diagram
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
NC
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
RX TX
o
o
o
o
o
1
2
3
4
5
o
o
o
o
o
10
9
8
7
6
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
Top
View
Mounting
Studs/Solder
Posts
Pin 7 Transmitter Signal Ground VEE TX:
Directly connect this pin to the transmitter ground
plane.
Pin 8 NC:
No connection.
Pin 9 Transmitter Data In TD+:
No internal terminations are provided. See recom-
mended circuit schematic.
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are provided. See recom-
mended circuit schematic.
Mounting Studs/Solder Posts
The mounting studs are provided for transceiver me-
chanical attachment to the circuit board. It is rec-
ommended that the holes in the circuit board be
connected to chassis ground.
Application Information
The Applications Engineering group is available to assist
you with the technical understanding and design trade-
os associated with these transceivers. You can contact
them through your Avago sales representative.
The following information is provided to answer some
of the most common questions about the use of these
parts.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical
power for a ber optic link to accommodate ber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging
and unplanned losses due to cable plant recongura-
tion or repair.
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than normally
associated with these technologies in the industry.
The industry convention is 1.5 dB aging for 1300 nm
LEDs. The 1300 nm Avago LEDs are specied to expe-
rience less than 1 dB of aging over normal commercial
equipment mission life periods. Contact your Avago
sales representative for additional details.
Pin Descriptions:
Pin 1 Receiver Signal Ground VEE RX:
Directly connect this pin to the receiver ground plane.
Pin 2 Receiver Power Supply VCC RX:
Provide +3.3 V dc via the recommended receiver power
supply lter circuit. Locate the power supply lter
circuit as close as possible to the VCC RX pin.
Pin 3 Signal Detect SD:
Normal optical input levels to the receiver result in a
logic “1” output.
Low optical input levels to the receiver result in a logic
“0” output.
This Signal Detect output can be used to drive a PECL
input on an upstream circuit, such as Signal Detect
input of Loss of Signal-Bar.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are provided. See recom-
mended circuit schematic.
Pin 5 Receiver Data Out RD+:
No internal terminations are provided. See recom-
mended circuit schematic.
Pin 6 Transmitter Power Supply VCC TX:
Provide +3.3 V dc via the recommended transmitter
power supply lter circuit. Locate the power supply
lter circuit as close as possible to the VCC TX pin.
4
Figure 3. Recommended Decoupling and Termination Circuits
o VEE
RX
o VCC
RX
o SD
o RD-
o RD+
Z = 50 Ω
Z = 50 Ω
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
Z = 50 Ω
10 9 8 7 6
SD
LVPECL
VCC
(+3.3 V)
TERMINATE AT
DEVICE INPUTS
LVPECL
VCC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
VCC
(+3.3 V)
Z = 50 Ω
1 2 3 4 5
TD- o
TD+ o
N/C o
VEE
TX
o
VCC
TX
o
1 µH
C2
1 µH
C1
C3 10 µF
VCC
(+3.3 V)
TX
RX
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
100 Ω
100 Ω
130 Ω
130 Ω
130 Ω
130 Ω
LVTTL
130 Ω
82 Ω
Recommended Handing Precautions
Avago recommends that normal status precautions be
taken in the handling and assembly of these transceiv-
ers to prevent damage which may be induced by elec-
trostatic discharge (ESD). The HFBR-5961xxZ series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD
damage during shipment of storage.
Board Layout - Decoupling Circuit, Ground Planes and Termi-
nation Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 3 provides a good example of a
schematic for a power supply decoupling circuit that
works will with these parts, It is further recommend-
ed that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current.
This recommendation is in keeping with good high
frequency board layout practices. Figures 3 and 4 show
two recommended termination schemes.
5
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern dened in
the original multisource announcement which dened
the 2 x 5 package style. This drawing is reproduced in
Figure 6 with the addition of ANSI Y14.5M compliant
dimensioning to be used as a guide in the mechani-
cal layout of your circuit board. Figure 6 illustrates the
recommended panel opening and the position of the
circuit board with respect to this panel.
Figure 4. Alternative Termination Circuits
o V
EE
R
X
o V
CC
R
X
o SD
o RD-
o RD+
Z = 50 Ω
130 Ω
VCC
(+3.3 V)
10 nF
Z = 50 Ω
130 Ω
82 Ω 82 Ω
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
Z = 50 Ω
10 9 8 7 6
SD
LVPECL
VCC
(+3.3 V)
TERMINATE AT DEVICE INPUTS
LVPECL
VCC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
Z = 50 Ω
1 2 3 4 5
TD- o
TD+ o
N/C o
V
EE
T
X
o
V
CC
T
X
o
1 µH
C2
1 µH
C1
C3 10 µF
VCC
(+3.3 V)
TX
RX
Note:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading R1 is optional.
10 nF
130 Ω
82 Ω
VCC
(+3.3 V)
130 Ω
82 Ω
VCC
(+3.3 V)
10 nF
LVTTL
82 Ω
130 Ω
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certication of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
6
ALL DIMENSIONS IN MILIMETERS(INCHES)
Figure 5. Package Outline Drawing
7
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The rst case is during handling of the transceiver prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded
wrist straps, work benches, and oor mats in ESD con-
trolled areas.
The second case to consider is static discharges to the
exterior the equipment chassis containing the trans-
ceiver parts. To the extent that the LC connector is
exposed to the outside of the equipment chassis it may
be subject to whatever ESD system level test criteria
that the equipment is intended to meet.
Figure 6. Recommended Board Layout Hole Pattern
2.29
(.090)
15.24
(.600)
MIN. PITCH
14.22 ± .10
(.560 ± .004)
A
A
0.81 ± .10
(.032 ± .004)
20 x Ø
1.40 ± .10
(.055 ± .004)
4 x Ø (NOTE 5) SEE DETAIL A
13.34
(.525)
12.16
(.479) 15.24
(.600)
7.59
(.299)
10.16
(.400)
4.57
(.180)
7.11
(.280)
1.78
(.070)
9 X
3.56
(.140)
5 4 3 2 1
6 7 8 9 10
SEE NOTE 3
8.89
(.350)
10.16 ± .10
(.400 ± .004)
TOP OF PCB
SECTION A - A
A
+ 1.50
- 0
(+.059)
(- .000)
1.00
(.039)
+ 0
- 0.75
(+.000)
(- .030)
15.75
(.620)
DETAIL B (4 x)
1
.039
1.8
.071
DETAIL A (3 x)
3
(.118)
2 x Ø MAX. (AREA FOR EYELET'S)
6
(.236)
1.40 ± .10
(.055 ± .004)
2 x Ø (NOTE 4)
3
(.118)
25.75
(1.014)
MIN. PITCH
SEE DETAIL B
Electromagnetic Interference (EMI)
Most equipment designs utilizing this high speed trans-
ceiver from Avago will be required to meet the require-
ments of FCC in the United States, CENELEC EN55022
(CISPR 22) in Europe and VCCI in Japan.
This product is suitable for use in designs ranging from
a desktop computer with a single transceiver to a con-
centrator or switch product with a large number of
transceivers.
NOTES:
1. THIS PAGE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT AND FRONT PANEL OPENINGS FOR SFF TRANSCEIVERS.
2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NO METAL TRACES ALLOWED IN KEEP-OUT AREAS.
3. THIS DRAWING SHOWS EXTRA PIN HOLES FOR 2 x 6 PIN AND 2 x 10 PIN TRANSCEIVERS. THESE EXTRA HOLES ARE NOT REQUIRED FOR HFBR-5961xxZ AND OTHER
2 x 5 PIN SFF MODULES.
4. HOLES FOR MOUNTING STUDS MUST NOT BE TIED TO SIGNAL GROUND BUT MAY BE TIED TO CHASSIS GROUND.
5. HOLES FOR HOUSING LEADS OPTIONAL AND NOT REQUIRED FOR HFBR-5961L/HFBR-5961G. IF NEEDED IN FUTURE, THESE HOLES MUST BE TIED TO SIGNAL
GROUND.
6. ALL DIMENSIONS ARE IN MILLIMETERS (INCHES).
8
Regulatory Compliance Table
Feature Test Method Performance
Electrostatic Discharge
(ESD) to the Electrical
Pins
MIL-STD-883C Meets Class 2 (2000 to 3999 Volts).Withstand up to 2200 V
applied between electrical pins.
Electrostatic Discharge
(ESD) to the LC Recep-
tacle
Variation of IEC 61000-4-2 Typically withstand at least 25 kV without damage when
the LC connector receptacle is contacted by a Human Body
Model probe.
Electromagnetic Inter-
ference (EMI)
FCC Class B
CENELEC CEN55022 VCCI
Class 2
Transceivers typically provide a 10 dB margin to the noted
standard limits when tested at a certied test range with
the transceiver mounted to a circuit card without a chassis
enclosure.
Immunity Variation of IEC 61000-4-3 Typically show no measurable eect from a 10 V/m eld
swept from 80 to 450 MHz applied to the transceiver when
mounted to a circuit card withouta chassis enclosure.
Eye Safety AEL Class 1EN60825-1 (+A11) Compliant per Avago testing under single fault conditions.
TUV Certication - R 02071015
Component Recogni-
tion
Underwriters Laboratories and
Canadian Standards Association Joint
Component Recognition for Informa-
tion Technology Equipment including
Electrical Business Equipment
UL File #: E173874
200
100
l C
– TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES – ns
1280 1300 1320
180
160
140
120
13601340
∆λ
- TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) - nm
1.0
1.5
2.5
3.0
2.0
HFBR-5961xxZ TRANS-
MITTER TEST RESULTS
OF λC,
∆λ AND tr/f ARE
1260
tr/f
– TRANSMITTER
OUTPUT OPTICAL RISE/
FALL TIMES – ns
3.0
CORRELATED AND COMPLY
WITH THE ALLOWED
SPECTRAL WIDTH AS A
FUNCTION OF CENTER
WAVELENGTH FOR
VARIOUS RISE AND
FALL TIMES.
0
1
2
3
4
5
6
-3 -2 -1 0 1 2 3
EYE SAMPLING TIME POSITION (ns)
RELATIVE INPUT OPTICAL POWER (dB)
CONDITIONS:
1. TA = +25 C
2. VCC = 3.3 V dc
3. INPUT OPTICAL RISE/
FALL TIMES = 2.1/1.9 ns.
4. INPUT OPTICAL POWER
IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 15 AND 16 APPLY.
Figure 8. Relative Input Optical Power vs Eye Sampling Time Position
Figure 7. Transmitter Output Optical Spectral Width (FWHM) vs. Transmit-
ter Output Optical Center Wavelength and Rise/Fall Times
Immunity
Equipment utilizing these transceivers will be subject
to radio-frequency electromagnetic elds in some envi-
ronments. These transceivers have a high immunity to
such elds.
For additional information regarding EMI, susceptibil-
ity, ESD and conducted noise testing procedures and
results. Refer to Application Note 1166, Minimizing
Radiated Emissions of High-Speed Data Communica-
tions Systems.
Transceiver Reliability and Performance Qualication Data
The 2 x 5 transceivers have passed Avago reliability and
performance qualication testing and are undergoing
ongoing quality and reliability monitoring. Details are
available from your Avago sales representative.
These transceivers are manufactured at the Avago
Singapore location which is an ISO 9001 certied
facility.
Applications Support Material
Contact your local Avago Component Field Sales Oce
for information on how to obtain PCB layouts and eval-
uation boards for the 2 x 5 transceivers.
9
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to
each parameter in isolation, all other parameters having values within the recommended operating conditions. It
should not be assumed that limiting values of more than one parameter can be applied to the product at the same
time. Exposure to the absolute maximum ratings for extended periods can adversely aect device reliability.
Parameter Symbol Minimum Typical Maximum Units Notes
Storage Temperature TS-40 +100 °C
Lead Soldering Temperature TSOLD +260 °C
Lead Soldering Time tSOLD 10 sec
Supply Voltage VCC -0.5 3.63 V
Data Input Voltage VI-0.5 VCC V
Dierential Input Voltage (p-p) VD2.0 V 1
Output Current IO50 mA
Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Units Notes
Case Operating Temperature
HFBR-5961LZ/GZ
HFBR-5961ALZ/AGZ
TC
TC
0
-40
+70
+85
°C
°C
Supply Voltage VCC 2.97 3.3 3.63 V
Data Input Voltage - Low VIL - VCC -1.810 -1.475 V
Data Input Voltage - High VIH - VCC -1.165 -0.880 V
Data and Signal Detect Output Load RL50 W2
Dierential Input Voltage (p-p) VD0.800 V
Transmitter Electrical Characteristics
HFBR-5961LZ/GZ (TC = 0 °C to +70 °C, VCC=2.97 V to 3.63 V)
HFBR-5961ALZ/AGZ (TC = -40 °C to +85 °C, VCC=2.97 V to 3.63V)
Parameter Symbol Minimum Typical Maximum Units Notes
Supply Current ICC 110 175 mA 3
Power Dissipation PDISS 0.4 0.64 W 5a
Data Input Current - Low IIL -350 -2 µA
Data Input Current - High IIH 18 350 µA
10
Receiver Electrical Characteristics
HFBR-5961LZ/AGZ (TC = 0 °C to +70 °C, VCC = 2.97V to 3.63 V)
HFBR-5961ALZ/AGZ (TC = -40 °C to +85 °C, VCC = 2.97 V to 3.63 V)
Parameter Symbol Minimum Typical Maximum Units Notes
Supply Current ICC 65 120 mA 4
Power Dissipation PDISS 0.225 0.44 W 5b
Data Output Voltage - Low VOL - VCC -1.840 -1.620 V 6
Data Output Voltage - High VOH - VCC -1.045 -0.880 V 6
Data Output Rise Time tr0.35 2.2 ns 7
Data Output Fall Time tf0.35 2.2 ns 7
Signal Detect Output Voltage - Low VOL - VCC -1.840 -1.620 V 6
Signal Detect Output Voltage - High VOH - VCC -1.045 -0.880 V 6
Signal Detect Output Rise Time tr0.35 2.2 ns 7
Signal Detect Output Fall Time tf0.35 2.2 ns 7
Power Supply Noise Rejection PSNR 50 mV
Transmitter Optical Characteristics
HFBR-5961LZ/GZ (TC = 0 °C to +70 °C, VCC = 2.97 V to 3.63 V)
HFBR-5961ALZ/AGZ (TC = -40 °C to +85 °C, VCC = 2.97 V to 3.63 V)
Parameter Symbol Minimum Typical Maximum Units Notes
Output Optical Power
BOL62.5/125 µm, NA = 0.275 Fiber
EOL
PO-19
-20
-15.7 -14 dBm avg 8
Output Optical Power
BOL50/125 µm, NA = 0.20 Fiber
EOL
PO-22.5
-23.5
-14 dBm avg 8
Optical Extinction Ratio 0.02
-47
0.2
-27
%dB 9
Output Optical Power at Logic Low 0 State PO (“0”) -45 dBm avg 10
Center Wavelength lC1270 1308 1380 nm 23, Figure 7
Spectral Width - FWHM
Spectral Width - RMS
Dl 14763 nm 11, 23
Figure 7
Optical Rise Time tr0.6 2.1 3.0 ns 12, 23
Figure 7
Optical Fall Time tf0.6 1.9 3.0 ns 12, 23
Figure 7
Systematic Jitter Contributed
by the Transmitter OC-3
SJ 0.4 1.2 ns p-p 13a
Duty Cycle Distortion Contributed
by the Transmitter FE
DCD 0.36 0.6 ns p-p 13b
Data Dependent Jitter Contributed
by the Transmitter FE
DDJ 0.07 0.6 ns p-p 13c
Random Jitter Contributed by the Transmitter
OC-3
FE
RJ 0.1
0.1
0.52
0.69
ns p-p 14a
14b
11
Receiver Optical and Electrical Characteristics
HFBR-5961LZ/GZ (TC = 0 °C to +70 °C, VCC = 2.97 V to 3.63 V)
HFBR-5961ALZ/AGZ (TC = -40 °C to +85 °C, VCC = 2.97 V to 3.63 V)
Parameter Symbol Minimum Typical Maximum Units Notes
Input Optical Power at minimum
at Window Edge
OC-3
FE
PIN MIN (W)
-30
-31
dBm avg 15a, Figure 8
15b
Input Optical Power at Eye Center
OC-3
FE
PIN MIN (C) -31
-31.8
dBm avg 16a, Figure 8
16b
Input Optical Power Maximum
OC-3
FE
PIN MAX -14
-14
dBm avg 15a
15b
Operating Wavelength l1270 1380 nm
Systematic Jitter Contributed
by the Receiver
OC-3
SJ 0.2 1.2 ns p-p 17a
Duty Cycle Distortion Contributed
by the Receiver
FE
DCD 0.08 0.4 ns p-p 17b
Data Dependent Jitter Contributed
by the Receiver FE DDJ 0.07 1.0 ns p-p 17c
Random Jitter Contributed by the Receiver
OC-3
FE
RJ 0.3
0.3
1.91
2.14
ns p-p 18a
18b
Signal Detect - Asserted
OC-3
FE
PAPD + 1.5 dB -31
-33
dBm avg 19
Signal Detect - Deasserted PD-45 dBm avg 20
Signal Detect - Hysteresis PA - PD1.5 dB
Signal Detect Assert Time (o to on) 0 2 100 µs 21
Signal Detect Deassert Time (on to o) 0 5 100 µs 22
Notes:
1. This is the maximum voltage that can be applied across the Dierential Transmitter Data Inputs to prevent damage to the input ESD protec-
tion circuit.
2. The outputs are terminated with 50 W connected to VCC – 2 V.
3. The power supply current needed to operate the transmitter is provided to dierential ECL circuitry. This circuitry maintains a nearly constant
current ow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and
conducted or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50 W connected to VCC – 2 V and an Input Optical Power level of –14 dBm average.
5a. The power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current.
5b. The power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus the sum of the products
of the output voltages and currents.
6. This value is measured with respect to VCC with the output terminated into 50W connected to VCC - 2 V.
7. The data output rise and fall times are measured between 20% and 80% levels with the output connected to VCC – 2 V through 50 W.
8. These optical power values are measured
with the following conditions:
The Beginning of life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wave-
length LEDs. The actual degradation observed in Avago’s 1300 nm LED products is < 1 dB, as specied in this data sheet. Over the specied
operating voltage and temperature ranges. With 25 MBd (12.5 MHz square-wave), input signal. At the end of one meter of noted optical ber
with cladding modes removed. The average power value can be converted to a peak power value by adding 3 dB. Higher output optical
power transmitters are available on special request. Please consult with your local Avago sales representative for further details.
12
9. The Extinction Ratio is a measure of the modulation depth of the optical signal.. The data “0” output optical power is compared to the data “1”
peak output optical power and expressed as a percentage. With the transmitter driven by a 25 MBd (12.5 MHz square-wave) input signal, the
average optical power is measured. The data “1” peak power is then calculated by adding 3 dB to the measured average optical power. The
data “0” output optical power is found by measuring the optical power when the transmitter is driven by a logic “0” input. The extinction ratio
is the ratio of the optical power at the “0” level compared to the optical power at the “1” level expressed as a percentage or in decibels.
10. The transmitter will provide this low level of Output Optical Power when driven by a Logic “0” input. This can be useful in link troubleshoot-
ing.
11. The relationship between Full Width Half Maximum and RMS values for Spectral Width is derived from the assumption of a Gaussian shaped
spectrum which results in a 2.35 X RMS = FWHM relationship.
12. The optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input signal.
The ANSI T1E1.2 committee has designated the possibility of dening an eye pattern mask for the transmitter optical output as an item for
further study. Avago will incorporate this requirement into the specications for these products if it is dened. The HFBR-59XXL products
typically comply with the template requirements of CCITT (now ITU-T) G.957 Section 3.2.5, Figure 5 for the STM- 1 rate, excluding the optical
receiver lter normally associated with single mode ber measurements which is the likely source for the ANSI T1E1.2 committee to follow in
this matter.
13a. Systematic Jitter contributed by the transmitter is dened as the combination of Duty Cycle Distortion and Data Dependent Jitter. System-
atic Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square-wave), 223-1 pseudorandom data pattern input signal.
13b. Duty Cycle Distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal using an IDLE Line State, 125
MBd (62.5 MHz square-wave), input signal.
13c. Data Dependent Jitter contributed by the transmitter is specied with the FDDI test pattern described in FDDI PMD Annex A.5.
14a. Random Jitter contributed by the transmitter is specied with a 155.52 MBd (77.5 MHz square-wave) input signal.
14b. Random Jitter contributed by the transmitter is specied with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See Applica-
tion Information - Transceiver Jitter Performance Section of this data sheet for further details.
15a. This specication is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal character-
istics are present per the following denitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to
the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal to 1
x 10-10.
At the Beginning of Life (BOL) over the specied operating temperature and voltage ranges 23 input is a 155.52 MBd, 2 - 1 PRBS data pattern
with 72 “1” s and 72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958 Appendix I.
Receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. The actual test data window time-width is
set to simulate the eect of worst case optical input jitter based on the transmitter jitter values from the specication tables. The test window
time-width is HFBR-5961L 3.32 ns.
Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave, input signal to simulate any cross-talk present between the transmitter and
receiver sections of the transceiver.
15b. This specication is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal char-
acteristics are present per the following denitions. The Input Optical Power dynamic range from the minimum level (with a window time-
width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than
or equal to 2.5 x 10-10.
• At the Beginning of Life (BOL)
• Over the specied operating temperature and voltage ranges
• Input symbol pattern is the FDDI test pattern dened in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle base-
line wander eect of 50 kHz. This sequence causes a near worst case condition for inter-symbol interference.
• Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum
allowed eye-opening presented to the FDDI PHY PM_Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum
window time-width of 2.13 ns is based upon the worst case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0
ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ and RJ jitter components
that is dicult to implement with production test equipment. The receiver can be equivalently tested to the worst case FDDI PMD input jitter
conditions and meet the minimum output data window time-width of 2.13 ns. This is accomplished by using a nearly ideal input optical signal
(no DCD, insignicant DDJ and RJ) and measuring for a wider window time-width of 4.6 ns. This is possible due to the cumulative eect of jitter
components through their superposition (DCD and DDJ are directly additive and RJ components are rms additive). Specically, when a nearly
ideal input optical test signal is used and the maximum receiver peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns)
exist, the minimum window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window time-width
of 4.6 ns guarantees the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Avago
receiver.
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present
between the transmitter and receiver sections of the transceiver.
16a. All conditions of Note 15a apply except that the measurement is made at the center of the symbol with no window time- width.
16b. All conditions of Note 15b apply except that the measurement is made at the center of the symbol with no window time-width.
17a. Systematic Jitter contributed by the receiver is dened as the combination of Duty Cycle Distortion and Data Dependent Jitter. System-
atic Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square- wave), 223 - 1 psuedorandom data pattern input signal.
17b. Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal. The input optical power level is -20 dBm average.
17c. Data Dependent Jitter contributed by the receiver is specied with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The
input optical power level is -20 dBm average.
18a. Random Jitter contributed by the receiver is specied with a 155.52 MBd (77.5 MHz square- wave) input signal.
18b. Random Jitter contributed by the receiver is specied with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is at maximum “PIN Min. (W)”. See Application Information - Transceiver Jitter Section for further information.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-0820EN - April 24, 2009
Ordering Information
1300 nm LED (Operating Case Temperature 0 to +70 °C)
HFBR-5961LZ/HFBR-5961GZ
1300 nm LED (Operating Case Temperature -40 to +85 °C)
HFBR-5961ALZ/HFBR-5961AGZ
19. This value is measured during the transition from low to high levels of input optical power.
20. This value is measured during the transition from high to low levels of input optical power. At Signal Detect Deassert, the receiver outputs
Data Out and Data Out Bar go to steady PECL levels High and Low respectively.
21. The Signal Detect output shall be asserted within 100 us after a step increase of the Input Optical Power.
22. Signal detect output shall be de-asserted within 350 µs after a step decrease in the Input Optical Power. At Signal Detect Deassert, the
receiver outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively.
23. The HFBR-5961L transceiver complies with the requirements for the trade-os between center wavelength, spectral width, and rise/fall times
shown in Figure 7. This gure is derived from the FDDI PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the description in
ANSI T1E1.2 Revision 3. The interpretation of this gure is that values of Center Wavelength and Spectral Width must lie along the appropriate
Optical Rise/Fall Time curve.