LF to 2.7 GHz
Dual 60 dB TruPwr™ Detector
Data Sheet AD8364
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005-2012 Analog Devices, Inc. All rights reserved.
FEATURES
RMS measurement of high crest-factor signals
Dual-channel and channel difference outputs ports
Integrated accurately scaled temperature sensor
Wide dynamic range ±1 dB over 60 dB
±0.5 dB temperature-stable linear-in-dB response
Low log conformance ripple
+5 V operation at 70 mA, –40°C to +85°C
Small footprint, 5 mm × 5 mm, LFCSP
APPLICATIONS
Wireless infrastructure power amplifier linearization/control
Antenna VSWR monitor
Gain and power control and measurement
Transmitter signal strength indication (TSSI)
Dual-channel wireless infrastructure radios
FUNCTIONAL BLOCK DIAGRAM
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
05334-001
1 2 3 4 5 6 7 8
CHPB
CLPB
VLVL
VREF
ADJA
ADJB
COMB
DECB
24 23 22 21 20 19 18 17
CHPA
CLPA
ACO
M
TEMP
ACO
M
VPSR
COM
A
DECA
25
26
27
28
29
30
31
32
VPSA
VPSB
INHB
INLB
C
OMR
PWDN
INLA
INHA
16
15
14
13
12
11
10
9
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BIAS
TEMP
OUTA
OUTB
I
SIG2
I
TGT2
VGA
CONTROL
VGA
CONTROL
I
SIG2
I
TGT2
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD8364 is a true rms, responding, dual-channel RF power
measurement subsystem for the precise measurement and control
of signal power. The flexibility of the AD8364 allows communi-
cations systems, such as RF power amplifiers and radio transceiver
AGC circuits, to be monitored and controlled with ease. Operating
on a single 5 V supply, each channel is fully specified for operation
up to 2.7 GHz over a dynamic range of 60 dB. The AD8364
provides accurately scaled, independent, rms outputs of both RF
measurement channels. Difference output ports, which measure
the difference between the two channels, are also available. The
on-chip channel matching makes the rms channel difference
outputs extremely stable with temperature and process variations.
The device also includes a useful temperature sensor with an
accurately scaled voltage proportional to temperature, specified
over the device operating temperature range. The AD8364 can
be used with input signals having rms values from −55 dBm to
+5 dBm referred to 50 Ω and large crest factors with no
accuracy degradation.
Integrated in the AD8364 are two matched AD8362 channels
(see the AD8362 data sheet for more information) with improved
temperature performance and reduced log conformance ripple.
Enhancements include improved temperature performance and
reduced log-conformance ripple compared to the AD8362. On-
chip wide bandwidth output op amps are connected to accom-
modate flexible configurations that support many system
solutions.
The device can easily be configured to provide four rms
measurements simultaneously. Linear-in-dB rms measurements
are supplied at OUTA and OUTB, with conveniently scaled
slopes of 50 mV/dB. The rms difference between OUTA and
OUTB is available as differential or single-ended signals at
OUTP and OUTN. An optional voltage applied to VLVL
provides a common mode reference level to offset OUTP and
OUTN above ground.
The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, for
the operating temperature of –40°C to +85°C.
AD8364 Data Sheet
Rev. B | Page 2 of 44
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
General Description and Theory .................................................. 18
Square Law Detector and Amplitude Target ............................. 19
RF Input Interface ...................................................................... 19
Offset Compensation ................................................................. 19
Temperature Sensor Interface ................................................... 20
VREF Interface ........................................................................... 20
Power-Down Interface ............................................................... 20
VST[A, B] Interface .................................................................... 20
OUT[A, B, P, N] Outputs .......................................................... 21
Measurement Channel Difference Output Using
OUT[P, N] ................................................................................... 22
Controller Mode ......................................................................... 22
RF Measurement Mode Basic Connections ............................ 23
Controller Mode Basic Connections ....................................... 24
Constant Output Power Operation .......................................... 27
Gain-Stable Transmitter/Receiver ............................................ 29
Temperature Compensation Adjustment................................ 31
Device Calibration and Error Calculation .............................. 31
Selecting Calibration Points to Improve Accuracy over a
Reduced Range ........................................................................... 32
Altering the Slope ....................................................................... 34
Channel Isolation ....................................................................... 34
Choosing the Right Value for CHP[A, B] and CLP[A, B] .... 36
RF Burst Response Time ........................................................... 36
Single-Ended Input Operation ................................................. 36
Printed Circuit Board Considerations ..................................... 37
Package Considerations ............................................................. 37
Description of Characterization ............................................... 38
Basis for Error Calculations ...................................................... 38
Evaluation Board ........................................................................ 40
Outline Dimensions ....................................................................... 41
Ordering Guide .......................................................................... 41
REVISION HISTORY
1/12—Rev. A to Rev. B
Change to Figure 84 ....................................................................... 40
11/11—Rev. 0 to Rev. A
Changes to Figure 2 .......................................................................... 8
Changes to Automatic Power Control Section ........................... 24
Replaced Evaluation and Characterization Circuit Board
Layouts Section with Evaluation Board Section ......................... 40
Changes to Figure 84 ...................................................................... 40
Deleted Figure 85 and Figure 86; Renumbered Sequentially ... 41
Updated Outline Dimensions ....................................................... 41
Changes to Ordering Guide .......................................................... 41
Deleted Table 7, AD8364-EVAL-500 Evaluation Board
Configuration Options and AD8364-EVAL-2140 Evaluation
Board Configuration Options; Renumbered Sequentially ....... 42
Deleted Evaluation Boards Section and Figure 87 ..................... 44
Deleted Figure 88 ............................................................................ 45
Deleted Assembly Drawings Section, Figure 89, and
Figure 90 .......................................................................................... 46
4/05—Revision 0: Initial Version
Data Sheet AD8364
Rev. B | Page 3 of 44
SPECIFICATIONS
VS = VPSA = VPSB = VPSR = 5 V, TA = 25°C, Channel A frequency = Channel B frequency, VLVL = VREF, VST[A, B] = OUT[A, B],
O U T [ P, N] = FBK[A, B], differential input via Balun, CW input f ≤ 2.7 GHz, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Channel A and Channel B, CW sine wave input
Signal Input Interface INH[A, B] (Pins 26, 31) INL[A, B] (Pins 27, 30)
Specified Frequency Range LF 2.7 GHz
DC Common-Mode Voltage 2.5 V
Signal Output Interface OUT[A, B] (Pins 15, 10)
Wideband Noise CLP[A, B] = 0.1µF, fSPOT = 100 kHz,
RF input = 2140 MHz, ≥−40 dBm
40 nV/√Hz
MEASUREMENT MODE,
450 MHz OPERATION
ADJA = ADJB = 0 V, error referred to best fit line using
linear regression @ PINH[A, B] = −40 dBm and −20 dBm,
TA = 25°C, balun = M/A-Com ETK4-2T
±1 dB Dynamic Range1 Pins OUT[A, B] 69 dB
−40°C < TA < +85°C 65 dB
±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/59 dB
−40°C < TA < +85°C, (Channel A/Channel B) 50/52 dB
Maximum Input Level ±1 dB error 12 dBm
Minimum Input Level ±1 dB error −58 dBm
Slope 51.6 mV/dB
Intercept −59 dBm
Output Voltage—High Power In Pins OUT[A, B] @ PINH[A, B] = −10 dBm 2.53 V
Output Voltage—Low Power In Pins OUT[A, B] @ PINH[A, B] = −40 dBm 0.99 V
Temperature Sensitivity Deviation from OUT[A, B] @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm −0.1, +0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm −0.2, +0.3 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm −0.3, +0.4 dB
Deviation from OUTP to OUTN @ 25°C
−40°C < T
A
< 85°C; P
INH[A, B]
= −10 dBm, −25 dBm
±0.25
dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm, −25 dBm ±0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm, −25 dBm ±0.2 dB
Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 71 dB
Input A to OUTB Isolation Freq separation = 1 kHz
Input B to OUTA Isolation2 PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB 54 dB
PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB 54 dB
Input Impedance INHA/INLA, INHB/INLB differential drive 210||0.1 Ω||pF
Input Return Loss With recommended balun −12 dB
MEASUREMENT MODE,
880 MHz OPERATION
ADJA = ADJB = 0 V, error referred to best fit line using
linear regression @ PINH[A, B] = −40 dBm and −20 dBm,
TA = 25°C, balun = Mini-Circuits® JTX-4-10T
±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 66/57 dB
−40°C < TA < +85°C 58/40 dB
±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/54 dB
−40°C < TA < +85°C 20/20 dB
Maximum Input Level ±1 dB error, (Channel A/Channel B) 8/0 dBm
Minimum Input Level ±1 dB error, (Channel A/Channel B) −58/−57 dBm
Slope 51.6 mV/dB
Intercept −59.2 dBm
Output Voltage—High Power In Pins OUT[A, B] @ PINH[A, B] = −10 dBm 2.54 V
Output Voltage—Low Power In Pins OUT[A, B] @ PINH[A, B] = −40 dBm 0.99 V
AD8364 Data Sheet
Rev. B | Page 4 of 44
Parameter Conditions Min Typ Max Unit
Temperature Sensitivity Deviation from OUT[A, B] @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm +0.5 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm +0.5 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm +0.5 dB
Deviation from OUTP to OUTN @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm, −25 dBm +0.1, −0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm, −25 dBm +0.1, −0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm, −25 dBm +0.1, −0.2 dB
Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 64 dB
Input A to OUTB Isolation PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB 35 dB
Input B to OUTA Isolation2 PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB 35 dB
Input Impedance INHA/INLA, INHB/INLB differential drive 200||0.3 Ω||pF
Input Return Loss With recommended balun −9 dB
MEASUREMENT MODE,
1880 MHz OPERATION
ADJA = ADJB = 0.75 V, error referred to best fit line using
linear regression @ PINH[A, B] = −40 dBm and −20 dBm,
TA = 25°C, balun = Murata LDB181G8820C-110
±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 69/61 dB
−40°C < T
A
< +85°C
60/50
dB
±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/51 dB
−40°C < TA < +85°C 58/51 dB
Maximum Input Level ±1 dB error, (Channel A/Channel B) 11/3 dBm
Minimum Input Level ±1 dB error −58 dBm
Slope 50 mV/dB
Intercept −62 dBm
Output Voltage—High Power In Pins OUT[A, B] @ PINH[A,B] = −10 dBm 2.49 V
Output Voltage—Low Power In Pins OUT[A, B] @ PINH[A,B] = −40 dBm 0.98 V
Temperature Sensitivity Deviation from OUT[A, B] @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm +0.5, −0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm +0.5, −0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm +0.5, −0.2 dB
Deviation from OUTP to OUTN @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm, −25 dBm ±0.3 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm, −25 dBm ±0.3 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm, −25 dBm ±0.3 dB
Input A to Input B Isolation
Baluns = Macom ETC1.6-4-2-3 (both channels)
61
dB
Input A to OUTB Isolation PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB 33 dB
Input B to OUTA Isolation2 PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB 33 dB
Input Impedance INHA/INLA, INHB/INLB differential drive 167||0.14 Ω||pF
Input Return Loss With recommended balun −8 dB
MEASUREMENT MODE,
2.14 GHz OPERATION
ADJA = ADJB = 1.02 V, error referred to best fit line using
linear regression @ PINH[A, B] = −40 dBm and −20 dBm,
TA = 25°C, balun = Murata LDB212G1020C-001
±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 66/57 dB
−40°C < TA < +85°C 58/40 dB
±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/54 dB
−40°C < TA < +85°C 30/30 dB
Maximum Input Level ±1 dB Error, (Channel A/Channel B) −2/−4 dBm
Minimum Input Level ±1 dB Error, (Channel A/Channel B) −57−51 dBm
Slope Channel A/Channel B 49.5/52.1 mV/dB
Intercept Channel A/Channel B −58.3/−57.1 dBm
Output Voltage—High Power In Pins OUT[A, B] @ PINH[A, B] = −10 dBm 2.42 V
Output Voltage—Low Power In Pins OUT[A, B] @ PINH[A, B] = −40 dBm 0.90 V
Data Sheet AD8364
Rev. B | Page 5 of 44
Parameter Conditions Min Typ Max Unit
Temperature Sensitivity Deviation from OUT[A, B] @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm +0.1, −0.4 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm +0.1, −0.4 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm +0.1, −0.4 dB
Deviation from OUTP to OUTN @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm, −25 dBm +0.1, −0.4 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm, −25 dBm +0.2, −0.2 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm, −25 dBm +0.1, −0.2 dB
Deviation from CW Response 5.5 dB peak-to-rms ratio (WCDMA one channel) 0.2 dB
12 dB peak-to-rms ratio (WCDMA three channels) 0.3 dB
18 dB peak-to-rms ratio (WCDMA four channels) 0.3 dB
Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 58 dB
Input A to OUTB Isolation PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB 33 dB
Input B to OUTA Isolation2 PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB 33 dB
Input Impedance INHA/INLA, INHB/INLB differential drive 150||1.9 Ω||pF
Input Return Loss With recommended balun −10 dB
MEASUREMENT MODE,
2.5 GHz OPERATION
ADJA = ADJB = 1.14 V, error referred to best fit line using
linear regression @ PINH[A, B] = −40 dBm and −20 dBm,
TA = 25°C, balun = Murata LDB182G4520C-110
± 1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 69/63 dB
−40°C < TA < +85°C 58 dB
±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 55/50 dB
−40°C < TA < +85°C 25 dB
Maximum Input Level ±1 dB error, (Channel A/Channel B) 17/11 dBm
Minimum Input Level ±1 dB error −52 dBm
Slope 50 mV/dB
Intercept −52.7 dBm
Output Voltage—High Power In Pins OUT[A, B] @ PINH[A, B] = −10 dBm 2.14 V
Output Voltage—Low Power In Pins OUT[A, B] @ PINH[A, B] = −40 dBm 0.65 V
Temperature Sensitivity Deviation from OUT[A, B] @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm ±0.5 dB
−40°C < TA < 85°C; PINH[A, B] = −25 dBm ±0.5 dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm ±0.5 dB
Deviation from OUTP to OUTN @ 25°C
−40°C < TA < 85°C; PINH[A, B] = −10 dBm, −25 dBm ±0.3 dB
−40°C < T
A
< 85°C; P
INH[A, B]
= −25 dBm, −25 dBm
±0.3
dB
−40°C < TA < 85°C; PINH[A, B] = −40 dBm, −25 dBm ±0.3 dB
Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 54 dB
Input A to OUTB Isolation PINHB = −50 dBm, OUTB = OUTBPINHB ± 1 dB 31 dB
Input B to OUTA Isolation2 PINHA = −50 dBm, OUTA = OUTAPINHA ± 1 dB 31
Input Impedance INHA/INLA, INHB/INLB differential drive 150||1.7 Ω||pF
Input Return Loss With recommended balun −11.5 dB
OUTPUT INTERFACE Pin OUTA and OUTB
Voltage Range Min RL ≥ 200 Ω to ground 0.09 V
Voltage Range Max RL ≥ 200 Ω to ground VS − 0.15 V
Source/Sink Current OUTA and OUTB held at VS/2, to 1% change 70 mA
AD8364 Data Sheet
Rev. B | Page 6 of 44
Parameter Conditions Min Typ Max Unit
SETPOINT INPUT Pin VSTA and VSTB
Voltage Range Law conformance error ≤1 dB 0.5 3.75 V
Input Resistance 68 kΩ
Logarithmic Scale Factor f = 450 MHz, −40°C ≤ TA ≤ +85°C 50 mV/dB
Logarithmic Intercept
f = 450 MHz, −40°C ≤ T
A
≤ +85°C, referred to 50 Ω
−55
dBm
CHANNEL DIFFERENCE OUTPUT Pin OUTP and OUTN
Voltage Range Min RL ≥ 200 Ω to ground 0.1 V
Voltage Range Max RL ≥ 200 Ω to ground VS − 0.15 V
Source/Sink Current OUTP and OUTN held at VS/2, to 1% change 70 mA
DIFFERENCE LEVEL ADJUST Pin VLVL
Voltage Range
3
OUT[P, N] = FBK[A, B]
0
5
V
OUT[P,N] Voltage Range OUT[P, N] = FBK[A, B] 0 VS −
0.15
V
Input Resistance 1 kΩ
TEMPERATURE COMPENSATION Pin ADJA and ADJB
Input Voltage Range 0 2.5 V
Input Resistance >1 MΩ
VOLTAGE REFERENCE Pin VREF
Output Voltage RF in = −55 dBm 2.5 V
Temperature Sensitivity −40°C ≤ TA ≤ +85°C 0.4 mV/°C
Current Limit Source/Sink 1% change 10/3 mA
TEMPERATURE REFERENCE Pin TEMP
Output Voltage TA = 25°C, RL ≥ 10 kΩ 0.62 V
Temperature Coefficient −40°C ≤ TA ≤ +85°C, RL ≥ 10 kΩ 2 mV/°C
Current Source/Sink TA = 25°C to 1% change 1.6/2 mA
POWER-DOWN INTERFACE Pin PWDN
Logic Level to Enable Logic LO enables 1 V
Logic Level to Disable Logic HI disables 3 V
Input Current Logic HI PWDN = 5 V 95 µA
Logic LO PWDN = 0 V <100 µA
Enable Time PWDN LO to OUTA/OUTB at 100% final value,
CLPA/B = Open, CHPA/B = 10 nF, RF in = 0 dBm
2 µs
Disable Time PWDN HI to OUTA/OUTB at 10% final value,
CLPA/B = Open, CHPA/B = 10nF, RF in = 0 dBm
1.6 µs
POWER INTERFACE
Pin VPS[A, B], VPSR
Supply Voltage 4.5 5.5 V
Quiescent Current RF in = −55 dBm, VS = 5 V 70 mA
−40°C ≤ TA ≤ +85°C 90 mA
Supply Current PWDN enabled, VS = 5 V 500 µA
−40°C ≤ TA ≤ +85°C 900 µA
1 Best fit line, linear regression.
2 See Figure 75 for a plot of isolation vs. frequency for a ±1 dB error.
3 VLVL + OUTA/2 should not exceed VPSA − 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB − 1.31 V.
Data Sheet AD8364
Rev. B | Page 7 of 44
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPSA, VPSB, VPSR 5.5 V
PWDN, VSTA, VSTB, ADJA, ADJB,
FBKA, FBKB
0 V, 5.5 V
Input Power (Referred to 50 Ω) 23 dBm
Internal Power Dissipation 600 mW
θ
JA
39.8°C/W
1, 2
θ
JC
3.9°C/W
2
θJB 22.8°C/W2
ΨJT 0.4°C/W1, 2
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1 Still air.
2 All values are modeled using a standard 4-layer JEDEC test board with the
pad soldered to the board and thermal vias in the board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8364 Data Sheet
Rev. B | Page 8 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
25
26
27
24
CHPA
CLPA
ACOM
TEMP
ACOM
VPSR
COMA
DECA
12
11
10
9
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
VSTA
1
2
3
4
5
VREF
VLVL
CLPB
ADJA
ADJB
COMB
DECB
CHPB
6
7
8
28
29
30
31
32
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
VPSA
23
22
21
20
19
18
17
AD8364
TOP VIEW
PIN 1
INDICATOR
05334-002
NOTES
1. THE EX P OSE D P ADDLE O N THE UNDE RS IDE OF
THE P ACKAGE SHOUL D BE S OLDE RE D TO
A GROUND PL ANE WI TH LOW THERM AL AND
EL E CTRICAL CHARACT E RIST ICS.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
Equiv. Circuit
1 CHPB Connect to common via a capacitor to determine 3 dB point of Channel B input signal high-pass
filter.
2, 23 DECB, DECA Decoupling Terminals for INHA/INLA and INHB/INLB. Connect to common via a large capacitance
to complete input circuit. Figure 52
3, 22, 29 COMB, COMA, COMR Input System Common Connection. Connect via low impedance to system common.
4, 5 ADJB, ADJA Temperature Compensation for Channel B and Channel A. An external voltage is connected to
these pins to improve temperature drift. This voltage can be derived from VREF, that is, connect a
resistor from VREF to ADJ[A, B] and another resistor from ADJ[A, B] to ground. The value of these
resistors change as the frequency changes.
Figure 68
6 VREF General-Purpose Reference Voltage Output of 2.5 V. Figure 54
7 VLVL Reference Level Input for OUTP and OUTN. (Usually connected to VREF through a voltage divider
or left open). Figure 58
8, 17 CLPB, CLPA Channel B and Channel A Connection for Loop Filter Integration (Averaging) Capacitor. Connect a
ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor
to improve loop stability and response time.
9
VSTB
The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel
B, which results in zero current flow in the loop integrating capacitor pin, CLPB.
Figure 56
10 OUTB Channel B Output of Error Amplifier. In measurement mode, normally connected directly to VSTB. Figure 57
11 FBKB Feedback Through 1 kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTN.
12
OUTN
Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKB
and follows the equation OUTN = OUTA − OUTB + VLVL.
Figure 58
13 OUTP Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKA
and follows the equation OUTP = OUTA − OUTB + VLVL. Figure 58
14
FBKA
Feedback Through 1kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTP.
15
OUTA
Channel A Output of Error Amplifier. In measurement mode, normally connected directly to VSTA.
Figure 57
16 VSTA The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel
A that results in zero current flow in the loop integrating capacitor pin, CLPA. Figure 56
18, 20 ACOM Analog Common for Channels A and B. Connect via low impedance to common.
21, 25, 32 VPSR, VPSA, VPSB Supply for the Input System of Channels A and B. Supply for the internal references. Connect to
+5 V power supply.
19 TEMP Temperature Sensor Output. Figure 53
24 CHPA Connect to common via a capacitor to determine 3 dB point of Channel A input signal high-pass
filter.
26, 27 INHA, INLA Channel A High and Low RF Signal Input Terminal. Figure 52
28 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8364. Figure 55
30, 31
INLB, INHB
Channel B Low and High RF Signal Input Terminal.
Figure 52
Under
Package
Exposed Paddle The exposed paddle on the underside of the package should be soldered to a ground plane with
low thermal and electrical characteristics.
Data Sheet AD8364
Rev. B | Page 9 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V; TA = +25°C, –40°C, +85°C; CLPA/B = OPEN. Colors: +25°C black, –40°C blue, +85°C red.
5
0
–60 20
05334-060
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
A
B
Figure 3. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at
450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive,
Balun = Macom ETK4-2T
5
0
–60 20
05334-075
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
Figure 4. Distribution of OUT[A, B] Voltage and Error over Temperature After
Ambient Normalization vs. Input Amplitude for at Least 30 Devices from
Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential
Drive, Balun = Macom ETK4-2T
0.20
–0.20
–60 20
05334-070
OUTA–OUTB (V)
0.15
0.10
0
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–0.15
–0.10
–0.05
0.05
Figure 5. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over
Temperature for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz,
ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T
5
0
–60 20
05334-065
OUT [P, N] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
OUTP
OUTN
Figure 6. O UT[P, N] Voltage and Log Conformance vs. Input Amplitude at
450 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,
ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T
(Note that the OUTP and OUTN Error Curves Overlap)
5
0
–60 20
05334-079
OUTP–OUTN (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
–5
–1
–2
–3
–4
Figure 7. Distribution of [OUTP − OUTN] Voltage and Error over Temperature
After Ambient Normalization vs. Input Amplitude for at Least 30 Devices
from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave,
Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept
05334-003
RF INPUT AT INLA (dBm) 10–40 –35 –30 –25 –20 –15 –10 –5 0 5
ERROR (dB)
4
2
0
–2
–4
–6
–8
–10
SERIES NAME INDICATES THE
POLARITY AND MAGNITUDE OF THE
DEVIATION APPLIED TO THE INHA
INPUT, RELATIVE TO THE INLA INPUT,
AS REFERENCED TO THE REF SIGNAL.
+1DB
+2DB
–1DB
–2DB
+10DEG
+15DEG
–10DEG
–15DEG
REF
Figure 8. Log Conformance vs. Input Amplitude at various Amplitude and
Phase Balance points, 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave,
Differential Drive
AD8364 Data Sheet
Rev. B | Page 10 of 44
5
0
–60 20
05334-061
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
B
A
Figure 9. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at
880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive,
Balun = Mini-Circuits JTX-4-10T
5
0
–60 20
05334-076
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
A
B
Figure 10. Distribution of OUT[A, B] Voltage and Error over Temperature After
Ambient Normalization vs. Input Amplitude for at Least 15 Devices from
Multiple Lots, Frequency = 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential
Drive, Balun =JTX-4-10T
0.20
–0.20
–60 20
05334-071
OUTA–OUTB (V)
0.15
0.10
0
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–0.15
–0.10
–0.05
0.05
Figure 11. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over
Temperature for at Least 15 Devices from Multiple Lots, Frequency =
880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun =JTX-4-10T
5
0
–60 20
05334-066
OUT[P, N] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
OUTN OUTP
Figure 12. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at
880 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,
ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun = JTX-4-10T
(Note that the OUTP and OUTN Error Curves Overlap)
5
–5
–60 20
05334-084
OUTP–OUTN (V)
3
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–3
–1
1
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
ERROR (dB)
4
2
–4
–2
0
Figure 13. Distribution of [OUTP − OUTN] Voltage and Error over
Temperature After Ambient Normalization vs. Input Amplitude for at Least
15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] =0.5 V, Sine
Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept
05334-004
RF INPUT AT INLA (dBm) 10–40 –35 –30 –25 –20 –15 –10 –5 0 5
ERROR (dB)
4
2
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
REF
+1dB
+2dB
-1dB
-2dB
+10DEG
+20DEG
-10DEG
-15DEG
+30DEG
SERIES NAME INDICATES THE POLARITY
AND MAGNITUDE OF THE DEVIATION
APPLIED TO THE INHA INPUT, RELATIVE
TO THE INLA INPUT, AS REFERENCED TO
THE REF SIGNAL.
Figure 14. Log Conformance vs. Input Amplitude at Various Amplitude and
Phase Balance points, 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave,
Differential Drive
Data Sheet AD8364
Rev. B | Page 11 of 44
5
0
–60 20
05334-062
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
B
A
Figure 15. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at
1.88 GHz, Typical Device, TADJ[A, B]= 0.65 V, Sine Wave, Differential Drive,
Balun = Murata LDB181G8820C-110
5
0
–60 20
05334-083
OUT[A ,B] (V)
4
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
1
2
3
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
ERROR (dB)
Figure 16. Distribution of OUT[A, B] Voltage and Error over Temperature After
Ambient Normalization vs. Input Amplitude for at Least 20 Devices from
Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave,
Differential Drive, Balun = Murata LDB181G8820C-110
0.20
–0.20
–60 20
05334-072
OUTA–OUTB (V)
0.15
0.10
0
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–0.15
–0.10
–0.05
0.05
Figure 17. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over
Temperature for at Least 20 Devices from Multiple Lots, Frequency =
1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata
LDB181G8820C-110
5
0
–60 20
05334-067
OUT[P, N] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
OUTPOUTN
Figure 18. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at
1.88 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,
ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata
LDB181G8820C-110 (Note that the OUTP and OUTN Error Curves Overlap)
5
0
05334-080
OUTP–OUTN (V)
4
3
2
1
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
–5
–1
–2
–3
–4
–60 20
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
Figure 19. Distribution of [OUTP − OUTN] Voltage and Error over
Temperature After Ambient Normalization vs. Input Amplitude for at Least
20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] =0.65 V,
Sine Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept
05334-005
RF INPUT AT INLA (dBm) 10–40 –30 –25 –20–35 –15 –10 –5 0 5
ERROR (dB)
2
–2
0
–6
–4
–10
–8
–12
–16
–14
–18
REF
+1dB
+2dB
–1dB
–2dB
+10deg
+20DEG
–10deg
–20deg
+30deg
–30deg
SERIES NAME INDICATES THE POLARITY
AND MAGNITUDE OF THE DEVIATION
APPLIED TO THE INHA INPUT, RELATIVE
TO THE INLA INPUT, AS REFERENCED TO
THE REF SIGNAL.
Figure 20. Log Conformance vs. Input Amplitude at Various Amplitude and
Phase Balance Points, 1.880 GHz, Typical Device, ADJ[A, B] = 0.65 V,
Sine Wave, Differential Drive
AD8364 Data Sheet
Rev. B | Page 12 of 44
5
0
–60 20
05334-063
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
B
A
Figure 21. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at
2.14 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive,
Balun = Murata LDB212G1020C-001
5
0
–60 20
05334-077
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
A
B
Figure 22. Distribution of OUT[A, B] Voltage and Error over Temperature After
Ambient Normalization vs. Input Amplitude for at Least 3 Devices from
Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave,
Differential Drive, Balun = Murata LDB212G1020C-001
0.20
–0.20–60 20
05334-073
OUTA–OUTB (V)
0.15
0.10
0
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–0.15
–0.10
–0.05
0.05
Figure 23. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over
Temperature for 3 Devices from Multiple Lots, Frequency = 2.14 GHz,
ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata
LDB212G1020C-001
5
0
–60 20
05334-068
OUT[P, N] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
OUTN OUTP
Figure 24. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at
2.14 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,
ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata
LDB212G1020C-001 (Note that the OUTP and OUTN Error Curves Overlap)
5
0
–60 20
05334-081
OUTP–OUTN (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
–5
–1
–2
–3
–4
Figure 25. Distribution of [OUTP − OUTN] Voltage and Error over
Temperature After Ambient Normalization vs. Input Amplitude for at Least
3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V,
Sine Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept
05334-006
RF INPUT AT INLA (dBm) 10–40 –35 –30 –25 –20 –15 –10 –5 0 5
ERROR (dB)
4
0
–2
2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
–24
REF
+1dB
+2dB
–1dB
–2dB
+10DEG
+20DEG
–10DEG
–20DEG
+30DEG
–30DEG
SERIES NAME INDICATES THE POLARITY
AND MAGNITUDE OF THE DEVIATION
APPLIED TO THE INHA INPUT, RELATIVE
TO THE INLA INPUT, AS REFERENCED TO
THE REF SIGNAL.
Figure 26. Log Conformance vs. Input Amplitude at Various Amplitude and
Phase Balance Points, 2.140 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine
Wave, Differential Drive
Data Sheet AD8364
Rev. B | Page 13 of 44
5
0
–60 20
05334-064
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
A
B
Figure 27. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at
2.5 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun
= Murata LDB182G4520C-110
5
0
–60 20
05334-078
OUT[A, B] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
Figure 28. Distribution of OUT[A, B] Voltage and Error over Temperature After
Ambient Normalization vs. Input Amplitude for at Least 15 Devices from
Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] = 1.1 V, Sine Wave, Differential
Drive, Balun = Murata LDB182G4520C-110
0.20
–0.20
–60 20
05334-074
OUTA–OUTB (V)
0.15
0.10
0
–50 –40 –30 –20 –10 0 10
INPUT AMPLITUDE (dBm)
–0.15
–0.10
–0.05
0.05
Figure 29. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over
Temperature for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz,
ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata
LDB182G4520C-110
5
0
–60 20
05334-069
OUT[P, N] (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
OUTP
OUTN
Figure 30. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at
2.5 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device,
ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata
LDB182G4520C-110 (Note that the OUTP and OUTN Error Curves Overlap)
5
0
–60 20
05334-082
OUTP–OUTN (V)
4
3
2
1
–50 –40 –30 –20 –10 0 10
2.5
–2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR (dB)
INPUT AMPLITUDE (dBm)
–5
–1
–2
–3
–4
Figure 31. Distribution of [OUTP − OUTN] Voltage and Error over
Temperature After Ambient Normalization vs. Input Amplitude for at Least
15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] =1.1 V, Sine
Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept
05334-007
RF INPUT AT INLA (dBm) 10–40 –35 –30 –25 –20 –15 –10 –5 0 5
ERROR (dB)
4
0
2
–6
–4
–2
–12
–10
–8
–22
–20
–18
–16
–14
–24
REF
+1dB
+2dB
–1dB –2dB
+10DEG
+20DEG –10DEG
–20DEG
+30DEG
–30DEG
SERIES NAME INDICATES THE POLARITY AND
MAGNITUDE OF THE DEVIATION APPLIED TO
THE INHA INPUT, RELATIVE TO THE INLA INPUT,
AS REFERENCED TO THE REF SIGNAL.
Figure 32. Log Conformance vs. Input Amplitude at Various Amplitude and
Phase Balance Points, 2.500 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave,
Differential Drive
AD8364 Data Sheet
Rev. B | Page 14 of 44
05334-008
P
IN
MEAS (dBm) 20–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
ERROR (dB)
2.0
1.0
1.5
0.5
0
–0.5
–1.5
–1.0
–2.0
ERROR CW ERROR QPSK 4dB CF
ERROR 256 QAM 8dB CF
ERROR 1C TM1-32 DPCH
13dB CF
ERROR 16C CDMA2K
9CH SR1 14dB CF
Figure 33. Output Error from CW Linear Reference vs. Input Amplitude with
Different Waveforms, CW, QPSK, 256QAM, WCDMA 1-Carrier Test Model 1
with 32 DPCH, CDMA2000, 16-Carrier, 9-Channel SR1 Frequency 2.140 GHz,
CLP[A, B] = 1 µF, Balun = Murata LDB212G1020C-001
05334-009
P
IN
MEAS (dBm) 20–60 –55 –50 –45 –35 –30 –25 –20 –15 –5–10 0 5 10 15–40
ERROR (dB)
2
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR CW
ERROR 3
CARRIER TM1-64
ERROR 4
CARRIER TM1-64
ERROR 1
CARRIER TM1-64
ERROR 2
CARRIER TM1-64
Figure 34. Error from CW Linear Reference vs. Input Amplitude with Different
Waveforms, CW, WCDMA1, 2-, 3-, and 4-Carrier, Test Model 1 with 64 DPCH,
Frequency 2.14 GHz, Balun = Murata LDB212G1020C-001
05334-010
P
IN
MEAS (dBm) 20–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
ERROR (dB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
ERROR CW
ERROR 3 CARRIER
CDMA2K SR1
ERROR 4 CARRIER
WCDMA TM 1-64
Figure 35. Output Voltage and Error from CW Linear Reference vs. Input
Amplitude with Different Waveforms, CW, 3-Carrier CDMA2000 SR1,
4-Carrier WCDMA, Test Model 1 with 64 DPCH, Frequency 2.140 GHz,
Balun = Murata LDB212G1020C-001
05334-011
P
IN
MEAS (dBm) 20–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
ERROR (dB)
2.0
1.0
1.5
–0.5
0
0.5
–1.0
–1.5
–2.0
ERROR CW
ERROR FWD 1 CARRIER
CDMA2K 9CH SR1
ERROR FWD 16
CARRIER CDMA2K
9CH SR1
ERROR FWD 4
CARRIER CDMA2K
9CH SR1
ERROR FWD 1 CARRIER
CDMA2K PILOTSR1
ERROR FWD 4
CARRIER CDMA2K
9CH SR1
ERROR FWD 3
CARRIER CDMA2K
9CH SR1
Figure 36. Error from CW Linear Reference vs. Input Amplitude with Different
Waveforms, CW, 1-Carrier CDMA2000 Pilot CH SR1, 1-Carrier CDMA2000
9CH SR1, 3-Carrier CDMA2000 9CH SR1, 4-Carrier CDMA2000 9CH SR1
Frequency 16-Carrier CDMA2000 9CH SR1, Frequency 2.140 GHz, Balun =
Murata LDB212G1020C-001
Data Sheet AD8364
Rev. B | Page 15 of 44
05334-053
0180
30
330
60
90
270
300
120
240
150
210
Figure 37. Differential Input Impedance (S11) vs. Frequency; ZO = 50 Ω
05334-012
VREF (V) 2.5062.486 2.490 2.494 2.5022.488 2.492 2.4982.496 2.5042.500
COUNT
14
10
6
4
12
8
2
0
TOTAL = 40 DEVICES
RF INPUT = –60dBm
Figure 38. Distribution of VREF for 40 Devices
05334-013
VREF (V)
0.617 0.619 0.6250.6230.621 0.627
COUNT
14
10
6
4
12
8
2
0
TOTAL = 40 DEVICES
RF INPUT = –60dBm
Figure 39. Distribution of TEMP Voltage for 40 Devices
05334-014
TEMPERATURE (°C) 90–40 –20 –10 0 10–30 20 30 40 60 70 8050
CHANGE IN VREF (mV)
20
15
5
10
–5
0
–15
–10
–20
Figure 40. Change in VREF vs. Temperature for 11 Devices
05334-057
10
100
1000
10000
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
OUTPUT NOISE (nV/ Hz)
450MHz
450MHz, 0dB
450MHz, –20dB
450MHz, RF OFF
450MHz, –40dB
2140MHz, 0dB 2140MHz, –20dB 2140MHz, –40dB
Figure 41. Noise Spectral Density of OUT[A, B]; CLP[A, B] = Open
05334-059
10
100
1000
10000
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–20dB
–40dB
0dB
RF OFF
OUTPUT NOISE (nV/ Hz)
Figure 42. Noise Spectral Density of OUT[P, N]; CLP[A, B] = 0.1 µF,
Frequency = 2140 MHz
AD8364 Data Sheet
Rev. B | Page 16 of 44
05334-058
10
100
1000
10000
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
–20dB
–40dB
0dB
RF OFF
OUTPUT NOISE (nV/ Hz)
Figure 43. Noise Spectral Density of OUT[A, B]; CLP[A, B] = 0.1 µF,
Frequency = 2140 MHz
05334-015
REF2 1.0V 2.0µs
CH2 5.0V
CH4 1.0V M2.0µs 1.25GS/s
A CH2 2.1V 800ps/pt
2
B2
RF BURST ENABLE
OUTA
CARRIER FREQUENCY 450MHz,
CLPA = OPEN
0dBm
–20dBm
–40dBm
V
DD
= 5V
V
A
= 5V
V
B
= 0V
Figure 44. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency 450 MHz, CLPA = Open
05334-016
REF2 1.0V 2.0ms
CH2 5.0V
CH4 1.0V M2.0µs 1.25MS/s
A CH2 2.1V 800ns/pt
2
B2
RF BURST ENABLE
OUTA
CARRIER FREQUENCY 450MHz,
CLPA = 0.1µF
0dBm
–20dBm
–40dBm
V
DD
= 5V
V
A
= 5V
V
B
= 0V
Figure 45. Output Response to RF Burst Input for Various RF Input Levels,
Carrier Frequency 450 MHz, CLPA = 0.1 µF
05334-017
REF2 1.0V 4.0µs
CH2 5.0V
CH4 1.0V M4.0µs 625MS/s
A CH2 2.1V 1.6ns/pt
2
B2
OUTA
CARRIER FREQUENCY 450MHz,
CLPA = OPEN
0dBm
–20dBm
–40dBm
PWDN
V
DD
= 5V
V
A
= 5V
V
B
= 0V
Figure 46. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 450 MHz, CLPA = Open
05334-018
REF2 1.0V 2.0µs
CH2 5.0V
CH4 1.0V M2.0ms 1.25MS/s
A CH2 1.7V 800ns/pt
2
B2
OUTA
CARRIER FREQUENCY 450MHz,
CLPA = 0.1µF
0dBm
–20dBm
–40dBm
PWDN
V
DD
= 5V
V
A
= 5V
V
B
= 0V
Figure 47. Output Response Using Power-Down Mode for Various RF Input
Levels, Carrier Frequency 450 MHz, CLPA = 0.1 µF, CHPA = 10 nF
Data Sheet AD8364
Rev. B | Page 17 of 44
05334-019
RF INPUT (dBm) 20–60 –40–50 –20–30 0 10–10
ERROR (dB)
2.0
1.5
0.5
1.0
–0.5
0
–1.5
–1.0
–2.0
Figure 48. Output Voltage Stability vs. VP (Supply Voltage) at 2.14 GHz,
When VP Varies by 10%,ADJ[A, B] =0.85 V, Sine Wave, Differential Drive,
Murata LDB212G1020C-001
05334-020
V
PWDN
(V) 2.41.0 1.2 1.4 1.6 1.8 2.0 2.2
SUPPLY CURRENT (mA)
80
70
60
50
40
30
20
10
0
V
PWDN
DECREASING
V
PWDN
INCREASING
Figure 49. Supply Current vs. VPWDN
AD8364 Data Sheet
Rev. B | Page 18 of 44
GENERAL DESCRIPTION AND THEORY
The AD8364 is a dual-channel, 2.7 GHz, true rms responding
detector with 60 dB measurement range. It incorporates two
AD8362 channels with shared reference circuitry (See the
AD8362 datasheet for more information). Multiple enhancements
have been made to the AD8362 cores to improve measurement
accuracy. Log-conformance peak-to-peak ripple has been reduced
to <±0.2 dB over the entire dynamic range. Temperature stability
of the rms output measurements provides <±0.5 dB error over
the specified temperature range of −40°C to 85°C through
proprietary techniques. The use of well-matched channels offers
extremely temperature-stable difference outputs, OUTP and
OUTN. Given well-matched channels through IC integration,
the rms measurement outputs, OUTA and OUTB, drift in the
same manner. With OUTP shorted to FBKA, the function at
OUTP is
OUTP = OUTA – OUTB + V LV L (1)
When OUTN is shorted to FBKB, the function at OUTN is
OUTN = OUTB – OUTA + V LV L (2)
OUTP and OUTN are insensitive to the common drift due to
the difference cancellation of OUTA and OUTB.
The AD8364 is a fully calibrated rms-to-dc converter capable of
operating on signals of a few hertz to 2.7 GHz or more. Unlike
logarithmic amplifiers, the AD8364 response is waveform
independent. The device accurately measures waveforms that
have a high peak-to-rms ratio (crest factor). Figure 50 shows a
block diagram.
A single channel of the AD8364 consists of a high performance
AGC loop. As shown in Figure 51, the AGC loop comprises
a wide bandwidth variable gain amplifier (VGA), square law
detectors, an amplitude target circuit, and an output driver. For
a more detailed description of the functional blocks, see the
AD8362 data sheet.
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
05334-001
12345678
CHPB
CLPB
VLVL
VREF
ADJA
ADJB
COMB
DECB
24 23 22 21 20 19 18 17
CHPA
CLPA
ACOM
TEMP
ACOM
VPSR
COMA
DECA
25
26
27
28
29
30
31
32
VPSA
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
16
15
14
13
12
11
10
9
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BIAS
TEMP
OUTA
OUTB
ISIG2
ITGT2
VGA
CONTROL
VGA
CONTROL
ISIG2
ITGT2
Figure 50. Block Diagram
V
IN
V
REF
×0.03
V
SIG
C
F
V
ST[A, B]
CLP [A, B]
V
REF
2.5V
OFFSET
NULLING
INH[A, B]
INL[A, B] VGA
SETPOINT
INTERFACE
OUTPUT
BUFFER
CHP[A, B]
VST[A, B]
V
REF
GSET
BAND GAP
REFERENCE
TEMPERATURE
COMPENSATION
x
2
x
2
C
LPF
EXTERNAL
05334-023
ADJ[A, B]
OUT[A, B]
ACOM
Figure 51. Single-Channel Details
Data Sheet AD8364
Rev. B | Page 19 of 44
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
The output of the VGA, called VSIG, is applied to a wideband
square law detector. The detector provides the true rms
response of the RF input signal, independent of waveform, up
to a crest factor of 6. The detector output, called ISQU, is a
fluctuating current with positive mean value. The difference
between ISQU and an internally generated current, ITGT[A, B], is
integrated by CF and a capacitor attached to CLP[A, B]. CF is
the on-chip 25 pF filter capacitor. CLP[A, B] can be used to
arbitrarily increase the averaging time while trading off
response time. When the AGC loop is at equilibrium,
MEAN(ISQU) = ITGT[A, B] (3)
This equilibrium occurs only when
MEAN(VSIG2) = VTGT[A, B]2 (4)
where VTGT is an attenuated version of the VREF voltage.
Because the square law detectors are electrically identical and
well matched, process and temperature dependent variations
are effectively cancelled.
By forcing the above identity through varying the VGA
setpoint, it is apparent that
RMS(VSIG) = √(MEAN(VSIG2)) = √(VTGT2) = VTGT (5)
Substituting the value of VSIG, we have
RMS(G0 × RFIN exp(−VST[A, B]/VGNS)) = VTGT (6)
When connected as a measurement device VST[A, B] =
OUT[A, B]. Solving for OUT[A, B] as a function of RFIN,
OUT[A, B] = VSLOPE × Log10(RMS(RFIN)/VZ) (7)
where VSLOPE is laser trimmed to 1 V/decade (or 50 mV/dB) at
100 MHz. VZ is the intercept voltage, since Log 10(1) = 0 when
RMS(RFIN) = VZ. If desired, the effective value of VSLOPE may be
altered by using a resistor divider from OUT[A, B] to drive
VST[A, B]. The intercept, VZ, is also laser trimmed to 180 µV
(−62 dBm, referred to 50 Ω) with a CW signal at 100 MHz. This
value is extrapolated, because OUT[A, B] do not respond to input
of less than approximately −55 dBm with differential drive.
In most applications, the AGC loop is closed through the
setpoint interface, VST[A, B]. In measurement mode, OUT[A, B]
are tied to VST[A, B], respectively. In controller mode, a control
voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control
input of a system. The RF feedback signal to the input pins is
forced to have an rms value determined by VSTA or VSTB.
RF INPUT INTERFACE
The AD8364’s RF inputs are connected as shown in Figure 52.
There are 100 Ω resistors connected between DEC[A, B] and
INH[A, B] and also between DEC[A, B] and INL[A, B]. The
DEC[A, B] pins have a dc level established as (7 × VPS[A, B] +
55 × VBE)/30. With a 5 V supply, DEC[A, B] is approximately
2.5 V.
Signal-coupling capacitors must be connected from the input
signal to the INH[A, B] and INL[A, B] pins. The high-pass
corner is
fhigh-pass = 1/(2 × π × 100 × C) (8)
A decoupling capacitor should be connected from DEC[A, B] to
ground to attenuate any signal at the midpoint. A 100 pF and
0.1 µF cap from DEC[A, B] to ground are recommended, with a
1 nF coupling capacitor such that signals greater than 1.6 MHz
can be measured. For coupling signals less than 1.6 MHz,
100 × Ccoupling for the DEC[A, B] capacitor generally can be used.
VGA
COM[A, B]
VSP[A, B]
VIN
COM[A, B]
VSP[A, B]
COM[A, B]
VSP[A, B]
DEC[A, B]
INH[A, B]
INL[A, B]
05334-024
100Ω
100Ω
Figure 52. AD8364 RF Inputs
OFFSET COMPENSATION
An offset-nulling loop is used to address small dc offsets in the
VGA. The high-pass corner frequency of this loop is internally
preset to about 1 MHz using an on-chip capacitor of 25 pF
(1/(2 × 5K × 25 pF)), which is sufficiently low for most HF
applications. The high-pass corner can be reduced by a
capacitor from CHP[A, B] to ground. The input offset voltage
varies depending on the actual gain at which the VGA is
operating and, thus, on the input signal amplitude. When an
excessively large value of CHP[A, B] is used, the offset
correction process may lag the more rapid changes in the VGA’s
gain, which may increase the time required for the loop to fully
settle for a given steady input amplitude.
AD8364 Data Sheet
Rev. B | Page 20 of 44
TEMPERATURE SENSOR INTERFACE
The AD8364 provides a temperature sensor output capable of
driving about 1.6 mA. A 330 Ω-equivalent internal resistance is
connected from TEMP to COMR to provide current sink
capability. The temperature scaling factor of the output voltage is
approximately 2 mV/°C. The typical absolute voltage at 25°C is
about 620 m V.
TEMP
VPSR
INTERNAL
VPTAT
4kΩ
1kΩ
COMR
350Ω
05334-025
Figure 53. TEMP Interface Simplified Schematic
VREF INTERFACE
An internal voltage reference is provided to the user at Pin VREF.
The VREF voltage is a temperature stable 2.5 V reference that
can drive about 18 mA. An 830 Ω equivalent internal resistance
is connected from VREF to ACOM for 3 mA sink capability.
V
REF
VPSR
INTERNAL
VOLTAGE
9kΩ
1.465kΩ
COMR
900Ω
05334-026
Figure 54. VREF Interface Simplified Schematic
POWER-DOWN INTERFACE
The operating and stand-by currents for the AD8364 at 25°C are
approximately 70 mA and 500 µA, respectively. The PWDN pin
is connected to an internal resistor divider made with two 42 kΩ
resistors. The divider voltage is applied to the base of an NPN
transistor to force a power-down condition when the device is
active. Typically when PWDN is pulled greater than 2 V, the
device is powered down. Figure 46 and Figure 47 show typical
response times for various RF input levels. The output reaches
to within 0.1 dB of its steady-state value in about 1.6 µs; the
reference voltage is available to full accuracy in a much shorter
time. This wake-up response vary depending on the input
coupling means and the capacitances CDEC[A, B], CHP[A, B],
and CLP[A, B].
PWDN
42kΩ
42kΩ
COMR
POWER DOWN
SIGNAL
05334-027
Figure 55. PWDN Interface Simplified Schematic
VST[A, B] INTERFACE
The VST[A, B] interface has a high input impedance of 72 kΩ.
The voltage at VST[A, B] is converted to an internal current
used to steer the VGA gain. The VGA attenuation control is
set to 20 dB/V.
GAIN ADJUST
1.35µA/dB
VST[A, B]
18.5kΩ
ACOM
36kΩ
36kΩ
05334-028
Figure 56. VST[A, B] Interface Simplified Schematic
Data Sheet AD8364
Rev. B | Page 21 of 44
OUT[A, B, P, N] OUTPUTS
The output drivers used in the AD8364 are different than the
output stage on the AD8362. The AD8364 incorporates rail-to-
rail output drivers with pull-up and pull-down capabilities.
The output noise is approximately 40 nV/√Hz at 100 kHz.
OUT[A, B, P, N] can source and sink up to 70 mA. There is also an
internal load from both OUTA and OUTB to ACOM of 2.5 kΩ.
OUT[A, B]
VPS[A, B]
COM[A, B]
INTERNAL
VOLTAGE
2kΩ
500Ω
ACOM
05334-029
Figure 57. OUT[A, B] Interface Simplified Schematic
OUTP
VPSRVLVL
FBKA COMR
OUTA
OUTB
05334-030
OUTN
VPSRVLVL
FBKB COMR
OUTB
OUTA
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
Figure 58. OUT[P, N] Interface Simplified Schematic
AD8364 Data Sheet
Rev. B | Page 22 of 44
MEASUREMENT CHANNEL DIFFERENCE OUTPUT
USING OUT[P, N]
The AD8364 incorporates two operational amplifiers with rail-
to-rail output capability to provide a channel difference output.
As in the case of the output drivers for OUT[A, B], the output
stages have the capability of driving 70 mA. The output noise is
approximately 40 nV/√Hz at 100 kHz. OUTA and OUTB are
internally connected through 1 kΩ resistors to the inputs of each
op amp. The pin VLVL is connected to the positive terminal of
both op amps through 1 kΩ resistors to provide level shifting. The
negative feedback terminal is also made available through a 1 kΩ
resistor. The input impedance of VLVL is 1 kΩ and FBK[A, B]
is 2 kΩ. See Figure 59 for the connections of these pins.
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
05334-001
1234567
8
CHPB
CLPB
VLVL
VREF
ADJA
ADJB
COMB
DECB
24 23 22 21 20 19 18 17
CHPA
CLPA
ACOM
TEMP
ACOM
VPSR
COMA
DECA
25
26
27
28
29
30
31
32
VPSA
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
16
15
14
13
12
11
10
9
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BIAS
TEMP
OUTA
OUTB
I
SIG2
I
TGT2
VGA
CONTROL
VGA
CONTROL
I
SIG2
I
TGT2
Figure 59. Op Amp Connections (All Resistors are 1 kΩ ± 20%)
If OUTP is connected to FBKA, then OUTP is given as
OUTP = OUTA – OUTB + V LV L (9)
If OUTN is connected to FBKB, then OUTN is given as
OUTN = OUTB – OUTA + V LV L (10)
In this configuration, all four measurements, OUT[A, B, P, N],
are made available simultaneously. A differential output can be
taken from OUTP − OUTN, and VLVL can be used to adjust
the common-mode level for an ADC connection.
CONTROLLER MODE
The channel difference outputs can be used for controlling a
feedback loop to the AD8364’s RF inputs. A capacitor connected
between FBKA and OUTP forms an integrator, keeping in mind
that the on-chip 1 kΩ feedback resistor forms a zero. (The value
of the on-chip resistors can vary as much as ±20% with manufac-
turing process variation.) If Channel A is driven and Channel B
has a feedback loop from OUTP through a PA, then OUTP
integrates to a voltage value such that
OUTB = (OUTA + V LV L )/2 (11)
The output value from OUTN may or may not be useful. It is
given by
OUTN = 0 V (12)
For VLVL < OUTA/3,
Otherwise,
OUTN = (3 × VLVL – OUTA)/2 (13)
If VLVL is connected to OUTA, then OUTB is forced to equal
OUTA through the feedback loop. This flexibility provides the
user with the capability to measure one channel operating at a
given power level and frequency while forcing the other channel
to a desired power level at another frequency. ADJA and ADJB
should be set to different voltage levels to reduce the temperature
drift of the output measurement. The temperature drift will be
statistical sum of the drift from Channel A and Channel B. As
stated before, VLVL can be used to force the slaved channel to
operate at a different power than the other channel. If the two
channels are forced to operate at different power levels, then
some static offset occurs due to voltage drops across metal
wiring in the IC.
If an inversion is necessary in the feedback loop, OUTN can be
used as the integrator by placing a capacitor between OUTN
an d OU TP. This changes the output equation for OUTB and
OUTP to
OUTB = 2 × OUTA − VLVL (14)
For VLVL < OUTA/2,
OUTN = 0 V (15)
Otherwise,
OUTN = 2 × VLVL – OUTA (16)
The previous equations are valid when Channel A is driven and
Channel B is slaved through a feedback loop. When Channel B
is driven and Channel A is slaved, the above equations can be
altered by changing OUTB to OUTA and OUTN to OUTP.
Data Sheet AD8364
Rev. B | Page 23 of 44
RF MEASUREMENT MODE BASIC CONNECTIONS
The AD8364 requires a single supply of nominally 5 V. The
supply is connected to the three supply pins, VPSA, VPSB, and
VPSR. Each pin should be decoupled using the two capacitors
with values equal or similar to those shown in Figure 60. These
capacitors must provide a low impedance over the full
frequency range of the input, and they should be placed as close
as possible to the VPOS pins. Two different capacitors are used
in parallel to provide a broadband ac short to ground.
The input signals are applied to the input differentially. The RF
inputs of the AD8364 have a differential input impedance of
200 Ω. When the AD8364 RF inputs are driven from a 50 Ω
source, a 4:1 balun transformer is recommended to provide the
necessary impedance transformation. The inputs can be driven
single-ended, however, this reduces the measurement range of
the rms detectors (see the Single-Ended Input Operation
section).
Table 4. Baluns Used to Characterize the AD8364
Frequency Balun
450 MHz MIA-COM ETK4-2T
880 MHz Mini-Circuits JTX-4-10T
1880 MHz Murata LDB181G8820C-110
2140 MHz Murata LDB212G1020C-001
2500 MHz Murata LDB182G4520C-110
The device is placed in measurement mode by connecting OUTA
and/or OUTB to VSTA and/or VSTB, respectively. This closes the
AGC loop within the device with OUT[A, B] representing the
VGA control voltage, which is required to present the correct
rms voltage at the input of the internal square law detector.
As the input signal to Channel A and Channel B are swept over
their nominal input dynamic range of +10 dBm to −50 dBm,
the output swings from 0 V to 3.5 V. The voltages OUTA and
OUTB are also internally applied to a difference amplifier with
a gain of two. So as the dB difference between INA and INB
ranges from approximately −30 dB to +30 dB, the difference
voltage on OUTP and OUTN swings from −3.5 V to +3.5 V.
Input differences larger than ±30 dB can be measured as long as
the absolute input level at INA and INB are within their nominal
ranges of +10 dBm to −50 dBm. However, measurement of large
differences between INA and INB are affected by on-chip signal
leakage (see the Channel Isolation section). The common-mode
level of OUTP and OUTN is set by the voltage applied to VLVL.
These output can be easily biased up to a common-mode
voltage of 2.5 V by connecting VREF to VLVL. As the gain range
is swept, OUTP swings from approximately 1 V to 4.5 V and
OUTN swings from 4.5 V to 1 V.
AD8364 Data Sheet
Rev. B | Page 24 of 44
26
27
28
29
30
32
31
15
14
13
12
11
9
10
76 85
43
12
25 16
18
19 17
20
21
22
24 23
VPOS
C20
100pF
C21
0.1µF
C22
0.1µF
C1
0.1µFC24
100pF
C19
0.1µF
R201
R191R171
C16
0.1µF
AD8364ACPZ
C9
0.1µF
C9
0.1µF
C14
0.1µF
C23
100pF
C8
0.1µF
C10
100pF
C11
0.1µF
R5
0Ω
R24
0Ω
C12
100pF
C13
0.1µF
VPOS
VPOS
VPSA
CHPA CLPAACOMTEMPACOMVPSRCOMADECA
CHPB CLPBVLVLVREFADJAADJBCOMBDECB
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
05334-031
OUTA
OUTP
OUTN
OUTB
R181
C5
0.1µF
INPA
1:4
C7
0.1µF
C6
0.1µF
T2
C2
0.1µF
INPB
1:4
C4
0.1µF
C3
0.1µF
T1
EXPOSED PADDLE
1SEE TEXT.
Figure 60. Basic Connections for Operation in Measurement Mode
CONTROLLER MODE BASIC CONNECTIONS
In addition to being a measurement device, the AD8364 can
also be configured to measure and control rms signal levels. The
AD8364 has two controller modes. Each of the two rms log
detectors can be separately configured to set and control the
output power level of a variable gain amplifier (VGA) or
variable voltage attenuator (VVA). Alternatively, the two rms
log detectors can be configured to measure and control the gain
of an amplifier or signal chain.
Automatic Power Control
Figure 61 shows how the device should be reconfigured to
control output power.
The RF input to the device is configured as before. A directional
coupler taps off some of the power being generated by the VGA
(typically a 10 dB to 20 dB coupler is used). A power splitter can
be used instead of a directional coupler if there are no concerns
about reflected energy from the next stage in the signal chain.
Some additional attenuation may be required to set the
maximum input signal at the AD8364 to be equal to the
recommended maximum input level for optimum linearity and
temperature stability at the frequency of operation.
VSTA and OUTA are no longer shorted together. OUTA now
provides a bias or gain control voltage to the VGA. The gain
control sense of the VGA must be negative and monotonic, that
is, increasing voltage tends to decrease gain. However, the gain
control transfer function of the device does not need to be well
controlled or particularly linear. If the gain control sense of the
VGA is positive, an inverting op amp circuit with a dc offset
shift can be used between the AD8364 and the VGA to keep the
gain control voltage in the 0 V to 5 V range.
VSTA becomes the setpoint input to the system. This can be
driven by a DAC, as shown in Figure 61, if the output power is
expected to vary, or it can simply be driven by a stable reference
voltage if constant output power is required. This DAC should
have an output swing that covers the 0 V to 3.5 V range.
Data Sheet AD8364
Rev. B | Page 25 of 44
When VSTA is set to a particular value, the AD8364 compares
this value to the equivalent input power present at the RF input.
If these two values do not match, OUTA increases or decreases
in an effort to balance the system. The dominant pole of the
error amplifier/integrator circuit that drives OUTA is set by the
capacitance on Pin CLPA; some experimentation may be
necessary to choose the right value for this capacitor. In general,
CLPA should be chosen to provide stable loop operation for the
complete output power control range. If the slope (in dB/V) of
the gain control transfer function of the VGA is not constant,
CLPA must be chosen to guarantee a stable loop when the gain
control slope is at its maximum. On the other hand, CLPA must
provide adequate averaging to the internal low range squaring
detector so that the rms computation is valid. Larger values of
CLPA tend to make the loop less responsive.
The relationship between VSTA and the RF input follows from
the measurement mode behavior of the device. For example,
from Figure 9, which shows the measurement mode transfer
function at 880 MHz, it can be seen that an input power of
−10 dBm yields an output voltage of 2.5 V. Therefore, in
controller mode, VSTA should be set to 2.5 V, which results in
an input power of −10 dBm to the AD8364.
AD8364
VGA OR VVA
(OUTPUT POWER
DECREASES AS
V
APC
INCREASES)
INHA
INHA
INLA
C5
0.1µF
1:4
C7
0.1µF
C6
0.1µF
T2
SEE TEXT
VSTA
OUTA
VAPC
DAC 0V TO 3.5V
(0V TO 4.9V AVAILABLE SWING)
PIN POUT
ATTENUATOR
05334-032
Figure 61. Operation in Controller Mode for Automatic Power Control
Automatic Gain Control
Figure 62 shows how the AD8364 can be connected to provide
automatic gain control to an amplifier or signal chain.
Additional pins are omitted for clarity. In this configuration,
both rms detectors are connected in measurement mode with
appropriate filtering being used on CLP[A, B] to effect a valid
rms computation on both channels. OUTA, however, is also
connected to the VLVL pin of the on-board difference amplifier.
Also, the OUTP output of the difference amplifier drives a
variable gain element (either VVA or VGA) and is connected
back to the FBKA input via a capacitor so that it is operating as
an integrator.
Assume that OUTA is much bigger than OUTB. Because OUTA
also drives VLVL, this voltage is also present on the noninverting
input of the op amp driving OUTP. This results in a net current
flow from OUTP through the integrating capacitor into the
FBKA input. This results in the voltage on OUTP increasing. If
the gain control transfer function of the VVA/VGA is positive,
this increases the gain, which in turn increases the input signal
to INHB. The output voltage on the integrator continues to
increase until the power on the two input channels is equal,
resulting in a signal chain gain of unity.
If a gain other than 0 dB is required, an attenuator can be used
in one of the RF paths, as shown in Figure 62. Alternatively,
power splitters or directional couplers of different coupling
factors can be used. Another convenient option is to apply a
voltage on VLVL other than OUTA. Refer to Equation 11 and
the Controller Mode section for more detail.
If the VGA/VVA has a negative gain control sense, the OUTN
output of the difference amplifier can be used with the
integrating capacitor tied back to FBKB.
The choice of the integrating capacitor affects the response time
of the AGC loop. Small values give a faster response time but
can result in instability, whereas larger values reduce the response
time. Note that in this mode, the capacitors on CLPA and CLPB,
which perform the rms averaging function, must still be used
and also affect the loop response time.
AD8364 Data Sheet
Rev. B | Page 26 of 44
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
VGA
CONTROL
CLPF
CLPF
VLVL
INHB
INLB
INLA
INHA
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
OUTA
OUTB
I
TGT2
I
SIG2
I
TGT2
I
SIG2
VGA
CONTROL
AD8364
C
INT
DIFF OUT +
C2
0.1µF
1:4
C4
0.1µF
C3
0.1µF
T2
1:4
C5
0.1µF
1:4
C7
0.1µF
C6
0.1µF
T1
1:4
ATTENUATOR
VGA/VVA
DIRECTIONAL
OR
POWER SPLITTER
DIRECTIONAL
OR
POWER SPLITTER
05334-054
I
ERR
Figure 62. Operation in Controller Mode for Automatic Gain Control
Data Sheet AD8364
Rev. B | Page 27 of 44
CONSTANT OUTPUT POWER OPERATION
In controller mode, the AD8364 can be used to hold the output
power stable over a broad temperature/input power range. This
can be very useful in systems, such as a transmit module driving
a high power amplifier (HPA) in a base station, that connect
multiple power sensitive modules together. In applications
where stable output power is needed, the RF output is
connected to Channel B using a coupler, VLVL is connected to
VREF, VSTB is used to set the power to a particular level and
can be controlled using a DAC or a dc voltage, OUTB is used to
drive the gain control of an amplifier that is capable of negative-
gain law conformance (such as the AD8367), and ADJB (set at
0 V in this example) is used to control the temperature drift.
Using this configuration, the RF input signal is down converted
to 80 MHz using the AD8343 and amplified using the AD8367.
The signal then splits and part of it is fed back to the AD8364
through Channel B, and a setpoint voltage is applied to VSTB.
This voltage corresponds to a particular power level, which is
determined by the slope of the AD8364. The power detected at
the input of the AD8364 is compared with this voltage, and the
voltage present at OUTB is adjusted up or down to match the
setpoint voltage, with the power detected on the input. The
OUTB voltage is connected to the gain control of the AD8367
VGA and increases or decreases the gain of the AD8367,
resulting in the output power being held constant, regardless of
variations in the input power. The AD8364 is able to maintain a
fixed output power from the AD8367 even though its input
power is changing. The input power can vary over a 36 dB
range, while the output power remains constant and the drift
over temperature is less than 0.2 dB
Figure 64 shows a constant output power circuit using the
AD8364 and the AD8367 VGA. The input power was swept
from +3 dBm to −35 dBm, the output power was measured at
multiple temperatures between −40°C and +85°C, and the
power changed less than ±0.07 dB (Figure 63).
05334-033
P
IN
(dBm) 5–40 –35 –30 –20 –15–25 –10 –5 0
P
OUT
(dBm)
–15.0
–15.2
–15.3
–15.1
–15.4
–15.5
–15.7
–15.6
–15.8
–15.9
–16.0
P
OUT
+25°C
–20°C
P
OUT
–40°C
P
OUT
+85°C
Figure 63. AD8364 Constant Power Performance
AD8364 Data Sheet
Rev. B | Page 28 of 44
26
27
28
29
30
32
31
15
14
13
12
11
9
10
76 8
5
4
3
12
25 16
18
19 17
20
21
22
24 23
C5
0.1µF
R3
OPEN
INPA
J3
PWDN
J2
1:4
C7
0.1µF
C6
0.1µF
C5
0.1µF
R1
OPEN
INPB
J1 1:4
C3
0.1µF
T2
LDB181G8820C-110
T1
ETK4-2T
VPOS
VPOS
TP1
COMM
TP2
A
B
SW1
R2
10kΩ
C20
100pF
C21
0.1µF
C22
0.1
µF
C1
0.1µFC24
100pF
R21
0Ω
R16
OPEN
C19
0.1µFC18
OPEN
R20
0Ω
R18
0ΩR15
0Ω
C16
0.1µF
C17
0.1µF
VREF
R13
OPEN R14
OPEN
R12
0Ω
R11
0Ω
R10
0Ω
R9
0Ω
AD8364ACPZ
EXPOSED PADDLE
C9
0.1µF
C9
0.1µFC15
0.1µF
C23
100pF
C8
0.1µF
C10
100pF
C11
0.1µF
C14
0.1µF
R6
0Ω
R5
0Ω
R4
0Ω
R23
0Ω
R24
0Ω
TEMP
SENSOR
J4
C12
100pF
C13
0.1µF
VPOS
VPSA
CHPA CLPAACOMTEMPACOMVPSRCOMADECA
CHPB CLPBVLVLVREFADJAADJBCOMBDECB
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
VSTB
0.4V TO
3.4V
05334-055
MODE SEL
0V TO 1.2V
90MHz
LPF
RFIN
1880MHz 0Ω0Ω
107Ω
IFOUT
80MHz
11dB
COUPLING
C4
0.1µF
AD8367
AD8343
0.705V
Figure 64. Constant Output Power Circuit
Data Sheet AD8364
Rev. B | Page 29 of 44
GAIN-STABLE TRANSMITTER/RECEIVER
There are many applications for a transmitter or receiver with a
highly accurate temperature-stable gain. For example, a
multicarrier base station high power amplifier (HPA) using
digital predistortion has a power detector and an auxiliary
receiver. The power detector and all parts associated with it can
be removed if the auxiliary receiver has a highly accurate
temperature-stable gain. With a set gain receiver, the ADC on
the auxiliary receiver can not only determine the overall power
being transmitted but can also determine the power in each
carrier for a multicarrier HPA.
In controller mode, the AD8364 can be used to hold the
receiver gain constant over a broad input power/temperature
range. In this application, the difference outputs are used to
hold the receiver gain constant.
The RF input is connected to INPA, using a 19.1 dB coupler,
and the down converted output from our signal chain is
connected to INPB, using a 10.78 dB coupler. A 0.1 µF capacitor
is connected between FBKA and OUTP, forming an integrator.
OUTA is connected to VLVL, forcing OUTP to adjust the VGA
so that OUTB is equal to OUTA. The circuit gain is set by the
difference in the coupling values of the input and output
couplers. As noted, OUTP is used to drive the gain control of
the ADL5330 by adjusting the gain up or down as needed to
force the power at the AD8364 inputs to be equal in amplitude.
Since operating at different frequencies, the appropriate voltages
on the ADJ[A, B] pins must be supplied. Because INPA is
operating at 1880 MHz, ADJA is set to 0.75 V. Likewise, because
INPB is operating at 80 MHz, ADJB is set to 0 V.
Because the difference in the coupler values is 8.32 dB, a fixed
gain of −8.32 dB is expected. In practice, there is a gain of
−13 dB. This is caused by the intercept shift of the AD8364 due
to its frequency response, the insertion loss of the output
coupler, and the insertion loss differences of the baluns used on
the input of the AD8364. In this configuration, approximately
33 dB of control range with 0.5 dB drift over temperature is
obtained.
Figure 66 shows a gain-stable receiver amplifier circuit using
the AD8364 to control an ADL5330 VGA and the AD8343
mixer. The input power was swept from +3 dBm to −35 dBm,
the output power was measured, and the gain was calculated at
multiple temperatures between −40°C and +85°C. Note that the
gain changed less than ±0.45 dB over this range (Figure 65).
Most of the gain change was caused by performance differences
at different frequencies.
05334-034
P
IN
(dBm) 5–40 –25 –15 –5–20–35 –30 –10 0
GAIN (dB)
–11.0
–11.5
–12.0
–12.5
–13.0
–13.5
–14.0
–40°C
+25°C
+85°C
Figure 65. Performance of Gain-Stable Receiver
AD8364 Data Sheet
Rev. B | Page 30 of 44
26
27
28
29
30
32
31
15
14
13
12
11
9
10
76 8
5
4
3
12
25 16
18
19 17
20
21
22
24 23
C5
0.1µF
R3
OPEN
INPA
J3
PWDN
J2
1:4
C7
0.1µF
C6
0.1µF
C5
0.1µF
R1
OPEN
INPB
J1 1:4
C3
0.1µF
T2
LDB181G8820C-110
T1
ETK4-2T
VPOS
VPOS
TP1
COMM
TP2
A
B
SW1
R2
10kΩ
C20
100pF
C21
0.1µF
C22
0.1µF
C1
0.1µFC24
100pF
R21
0Ω
R16
OPEN
C19
0.1µFC18
OPEN
R20
0Ω
R18
0ΩR15
0Ω
C16
0.1µF
C17
0.1µF
VREF
R13
OPEN R14
OPEN
R12
0Ω
R11
0Ω
R9
0Ω
0.1µF
AD8364
C9
0.1µF
C9
0.1µFC15
0.1µF
C23
100pF
C8
0.1µF
C10
100pF
C11
0.1µF
C14
0.1µF
R6
0Ω
R5
0Ω
R4
0Ω
R23
0Ω
R24
0Ω
TEMP
SENSOR
J4
C12
100pF
C13
0.1µF
VPOS
VPSA
CHPA CLPAACOMTEMPACOMVPSRCOMADECA
CHPB CLPBVLVLVREFADJAADJBCOMBDECB
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
05334-056
MODE SEL
0V TO 1.2V
90MHz
LPF
RFIN
1880MHz 0Ω0Ω
107Ω
IFOUT
80MHz
11dB
COUPLING
19dB
COUPLING
0Ω0Ω
454Ω
C4
0.1µF
AD8343
DIFF OUT +
ADL5330
0.75V
Figure 66. Gain-Stable Receiver Circuit
Data Sheet AD8364
Rev. B | Page 31 of 44
TEMPERATURE COMPENSATION ADJUSTMENT
The AD8364 has a highly stable measurement output with
respect to temperature. However, when the RF inputs exceed a
frequency of 600 MHz, the output temperature drift must be
compensated for using ADJ[A, B] for optimal performance.
Proprietary techniques are used to compensate for the temper-
ature drift. The absolute value of compensation varies with
frequency, balun choice, and circuit board material. Table 5
shows recommended voltages for ADJ[A, B] to maintain a
temperature drift error of typically ±0.5 dB or better over the
entire rated temperature range with the recommended baluns.
Table 5. Recommended Voltages for ADJ[A, B]
Frequency (MHz) 450 880 1880 2140 2500
ADJ[A, B] (V) 0 0.5 0.65 0.85 1.10
Compensating the device for temperature drift using ADJ[A, B]
allows for great flexibility. If the user requires minimum temper-
ature drift at a given input power or subset of the dynamic range,
the ADJ[A, B] voltage can be swept while monitoring OUT[A, B]
over temperature. Figure 67 shows the result of such an exercise
with a broadband balun, one that is not the recommended balun
at 1880 MHz. The value of ADJ[A, B] where the output has
minimum movement (approximately 0.77 V for the example in
Figure 67) is the recommended voltage for ADJ[A, B] to achieve
minimum temperature drift at a given power and frequency.
05334-035
ADJA (V) 2.500 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25
OUTA (V)
1.70
1.65
1.60
1.55
1.50
1.45
1.40
+85°C
+65°C
+45°C
+25°C
+10°C
–40°C
–20°C
Figure 67. OUTA vs. ADJA over Temp. Pin = −30 dBm, 1.9 GHz
The ADJ[A, B] input has high input impedance. The input can
be conveniently driven from an attenuated value of VREF using
a resistor divider, if desired.
Figure 68 shows a simplified schematic representation of the
ADJ[A, B] interface.
VPSR
VREF/2
ADJ[A, B]
COMR IADJ[A, B]
INTERNAL
CURRENT
05334-036
Figure 68. ADJ[A, B] Interface Simplified Schematic
DEVICE CALIBRATION AND ERROR CALCULATION
The measured transfer function of the AD8364 at 2.14 GHz is
shown in Figure 69. The figure shows plots of both output
voltage vs. input power and calculated error vs. input power. As
the input power varies from −50 dBm to 0 dBm, the output
voltage varies from 0.4 V to about 2.8 V.
04862-037
ERROR (dB)
–2.0
2.0
1.2
1.6
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
PIN MEAS (dBm) 10–60 –45 –40 –35–55 –50 –25 –20 –15–30 –5 0 5–10
VOUT (V)
3.50
2.80
3.15
2.10
2.45
1.40
1.75
0.70
0.35
1.05
0
PIN1
VOUT1
VOUT2
PIN2
ERROR CW +25°C
ERROR CW –40°C
ERROR CW +85°C
INTERCEPT
BLUE = –40°C
GREEN = +25°C
RED = +85°C
Figure 69. Transfer Function at 2.14 GHz.
Because slope and intercept vary from device to device, board-
level calibration must be performed to achieve high accuracy.
The equation for output voltage can be written as
VOUT = Slope × (PIN − Intercept)
Where Slope is the change in output voltage divided by the
change in power (dB), and Intercept is the calculated power at
which the output voltage would be 0 V. (Note that Intercept is a
theoretical value; the output voltage can never achieve 0 V).
In general, the calibration is performed by applying two known
signal levels to the AD8364’s input and measuring the
corresponding output voltages. The calibration points are
generally chosen to be within the linear-in-dB operating range
of the device (see the Specifications section for more details).
AD8364 Data Sheet
Rev. B | Page 32 of 44
Calculation of the slope and intercept is done using the
equations:
Slope = (VOUT1 − VOUT2)/(PIN1 − PIN2)
Intercept = PIN1 − (VOUT1/Slope)
Once slope and intercept have been calculated, an equation can
be written that will allow calculation of the input power based
on the output voltage of the detector.
PIN (unknown) = (VOUT1(measured)/Slope) + Intercept
The log conformance error of the calculated power is given by
Error (dB) = (VOUT(MEASURED) − VOUT(IDEAL))/Slope
Figure 69 includes a plot of the error at 25°C, the temperature at
which the log amp is calibrated. Note that the error is not zero.
This is because the log amp does not perfectly follow the ideal
VOUT vs. PIN equation, even within its operating region. The
error at the calibration points (−43 dBm and −23 dBm in this
case) will, however, be equal to zero by definition.
Figure 69 also includes error plots for the output voltage at
−40°C and +85 °C. These error plots are calculated using the
slope and intercept at 25°C. This is consistent with calibration
in a mass-production environment, where calibration at
temperature is not practical.
SELECTING CALIBRATION POINTS TO IMPROVE
ACCURACY OVER A REDUCED RANGE
In some applications, very high accuracy is required at one
power level or over a reduced input range. For example, in a
wireless transmitter, the accuracy of the high power amplifier
(HPA) is most critical at or close to full power.
Figure 70 shows the same measured data as Figure 69. Notice
that accuracy is very high from −10 dBm to −25 dBm. At
approximately −45 dBm, the error increases to about −0.3 dB
because the calibration points have been changed to −15 dBm
and −25 dBm.
Calibration points should be chosen to suit the application at
hand. In general, though, do not choose calibration points in
the nonlinear portion of the log amp’s transfer function (above
0 dBm or below −50 dBm in this case).
Figure 71 shows how calibration points can be adjusted to
increase dynamic range, but at the expense of linearity. In this
case, the calibration points for slope and intercept are set at
−1 dBm and −50 dBm. These points are at the end of the
device’s linear range. At 25°C, there is an error of 0 dB at the
calibration points. Note also that the range over which the
AD8364 maintains an error of <±0.4 dB is extended to 57 dB at
25°C. The disadvantage of this approach is that linearity suffers,
especially at the top end of the input range.
Another way of presenting the error function of a log amp
detector is shown in Figure 72. In this case, the dB error at hot
and cold temperatures is calculated with respect to the output
voltage at ambient. This is a key difference in comparison to the
previous plots, in which all errors have been calculated with
respect to the ideal transfer function at ambient.
When the alternative technique, the error at ambient becomes
by definition equal to 0 (see Figure 72).
This would be valid if the device transfer function perfectly
followed the ideal VOUT = Slope × (PIN − Intercept) equation.
However, since an rms amp, in practice, never perfectly follows
this equation (especially outside of its linear operating range),
this plot tends to artificially improve linearity and extend the
dynamic range, unless enough calibration points were taken to
remove the error. This plot is a useful tool for estimating temper-
ature drift at a particular power level with respect to the (nonideal)
output voltage at ambient.
Data Sheet AD8364
Rev. B | Page 33 of 44
04862-038
ERROR (dB)
–2.0
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
P
IN
MEAS (dBm) 10–60 –45 –40 –35–55 –50 –25 –20 –15–30 –5 0 5–10
P
IN
1
V
OUT
2
V
OUT
1
P
IN
2
INTERCEPT
V
OUT
(V)
3.50
2.80
3.15
2.10
2.45
1.40
1.75
0.70
0.35
1.05
0
ERROR CW +25°C
ERROR CW –40°C
ERROR CW +85°C
BLUE = –40°C
GREEN = +25°C
RED = +85°C
Figure 70. Output Voltage and Error vs. PIN with 2-Point Calibration at
−15 dBm and −25 dBm, 2.14 GHz
04862-039
57dB DYNAMIC RANGE
ERROR (dB)
–2.0
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
PIN MEAS (dBm) 10–60 –45 –40 –35–55 –50 –25 –20 –15–30 –5 0 5–10
VOUT (V)
3.50
2.80
3.15
2.10
2.45
1.40
1.75
0.70
0.35
1.05
0
ERROR CW +25°C
ERROR CW +85°C
P
IN
1 P
IN
2
V
OUT
2
V
OUT
1
ERROR CW –40°C
Figure 71. Dynamic Range Extension by Choosing Calibration Points that are
Close to the End of the Linear Range, 2.14 GHz
04862-040 ERROR (dB)
–2.0
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
P
IN
MEAS (dBm) 10–60 –45 –40 –35–55 –50 –25 –20 –15–30 –5 0 5–10
V
OUT
(V)
3.50
2.80
3.15
2.10
2.45
1.40
1.75
0.70
0.35
1.05
0
ERROR CW +25°C
ERROR CW –40°C
ERROR CW +85°C
Figure 72. Error vs. Temperature with Respect to Output Voltage at 25 °C,
2.14 GHz (Does Not Account for Transfer Function Nonlinearities at 25°C)
AD8364 Data Sheet
Rev. B | Page 34 of 44
ALTERING THE SLOPE
None of the changes to operating conditions discussed so far
affect the logarithmic slope, VSLOPE, in Equation 7. The slope can
readily be altered by controlling the fraction of OUT[A, B] that
is fed back to the setpoint interface at the VST[A, B] pin. When
the full signal from OUT[A, B] is applied to VST[A, B], the
slope assumes its nominal value of 50 mV/dB. It can be
increased by including a voltage divider between these pins, as
shown in Figure 73. Moderately low resistance values should be
used to minimize scaling errors due to the approximately 70 kΩ
input resistance at the VST[A, B] pin. Keep in mind that this
resistor string also loads the output, and it eventually reduces
the load-driving capabilities if very low values are used.
Equation 17 can be used to calculate the resistor values.
R1 = R2' (SD/50 − 1) (17)
where:
SD is the desired slope, expressed in mV/dB.
R2' is the value of R2 in parallel with 70 kΩ.
For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' =
1.649 kΩ), the nominal slope is increased to 100 mV/dB. This
choice of scaling is useful when the output is applied to a digital
voltmeter because the displayed number directly reads as a
decibel quantity with only a decimal point shift.
Operating at a high slope is useful when it is desired to measure
a particular section of the input range in greater detail. A
measurement range of 60 dB would correspond to a 6 V change
in VOUT at this slope, exceeding the capacity of the AD8364’s
output stage when operating on a 5 V supply. This requires that
the intercept is repositioned to place the desired input range
section within a window corresponding to an output range of
0.1 V ≤ VOUT ≤ 4.8 V, a 47 dB range.
Using the arrangement shown in Figure 74, an output of 0.4 V
corresponds to the lower end of the desired range, and an
output of 3.5 V corresponds to the upper limit with 3 dB of
margin at each end of the range, nominally −32 dBm to −1 dBm
with the intercept at −35.6 dBm. Note that R2 is connected to
VREF rather than ground. R3 is needed to ensure that the
AD8364’s reference buffer is correctly loaded.
When the slope is raised by some factor, the loop capacitor,
CLP[A, B], should be raised by the same factor to ensure
stability and to preserve a chosen averaging time. The slope can
be lowered by placing a voltage divider after the output pin,
following standard practice.
05334-041
R1
R2
V
OUT
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
12345678
CHPB
CLPB
VLVL
VREF
ADJA
ADJB
COMB
DECB
24 23 22 21 20 19 18 17
CHPA
CLPA
ACOM
TEMP
ACOM
VPSR
COMA
DECA
25
26
27
28
29
30
31
32
VPSA
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
16
15
14
13
12
11
10
9
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BIAS
TEMP
OUTA
OUTB
I
SIG2
I
TGT2
VGA
CONTROL
VGA
CONTROL
I
SIG2
I
TGT2
Figure 73. External Network to Raise Slope
05334-042
R1
4.02kΩ
R2
4.32kΩ
R3
2kΩ
V
OUT
CHANNEL A
TruPwr™
CHANNEL B
TruPwr™
123 4 5 67 8
CHPB
CLPB
VLVL
VREF
ADJA
ADJB
COMB
DECB
24 23 22 21 20 19 18 17
CHPA
CLPA
ACOM
TEMP
ACOM
VPSR
COMA
DECA
25
26
27
28
29
30
31
32
VPSA
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
16
15
14
13
12
11
10
9
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BIAS
TEMP
OUTA
OUTB
I
SIG2
I
TGT2
VGA
CONTROL
VGA
CONTROL
I
SIG2
I
TGT2
Figure 74. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to
300 mV Input Range
Data Sheet AD8364
Rev. B | Page 35 of 44
CHANNEL ISOLATION
Isolation must be considered when using both channels of the
AD8364 at the same time. The two isolation requirements that
should be considered are the isolation from one RF channel
input to the other RF channel input and the isolation from one
RF channel input to the other channel output. When using both
channels of the AD8364, care should be taken in the layout to
isolate the RF inputs from each other. Coupling on the PC
board affects both types of isolation.
In most applications, the designer has the ability to adjust the
power going into the AD8364 through the use of different
valued temperature-stable couplers and accurate temperature-
stable attenuators. When isolation is a concern, it is useful to
adjust the input power so the lowest expected detectable power
is not far from the lowest detectable power of the AD8364 at the
frequency of operation. The AD8364’s lowest detectable power
point has little variation from part to part and is not affected by
the balun. This equalizes the signals on both channels at their
lowest possible power level, which reduces the overall isolation
requirements and possibly adds attenuators to the RF inputs of
the device, reducing the RF channel input isolation requirements.
Measuring the RF channel input to the other RF channel input
isolation is straight forward, and the result of such an exercise is
shown in Figure 75. Note that adding an attenuator in series with
the RF signal increases the channel input-to-input isolation by
the value of the attenuator.
The isolation between one RF channel input and the other
channel output is a little more complicated. Do not assume that
worst-case isolation happens when one RF channel has high
power and the other RF channel is set at its lowest detectable
power. Worst-case isolation happens when the low power channel
is at a nominally low power level, as chosen in Figure 76. If the
inputs to both RF channels are at the same frequency, the isola-
tion also depends on the phase shift between the RF signals put
into the AD8364. This can be seen by placing a high power
signal on one RF channel input and another signal (low power)
slightly offset in frequency to the other RF channel. If the output
of the low power channel is observed with an oscilloscope, it
would have a ripple that would look similar to a full-wave rectified
sine wave with a frequency equal to the frequency difference
between the two channels, that is, a beat tone. The magnitude of
the ripple reflects the isolation at a specific phase offset (note
that two signals of slightly different frequencies act like two
signals with a constantly changing phase), and the frequency of
that ripple is directly related to the frequency offset. The data
taken in Figure 76 assumes worst-case amplitude and phase
offset. If the RF signals on Channel A and Channel B are at
significantly different frequencies, the input-to-output isolation
increase, depending on the capacitors placed on CLP[A, B] and
CHP[A, B] and the frequency offset of the two signals (Figure 77),
due to the response roll-off within AD8364.
05334-021
FREQUENCY (MHz) 10,00010 100 1,000
ISOLATION (dB)
–40
–50
–60
–70
–80
–90
–45
–55
–65
–75
–85
A->B
B->A
Figure 75. RF Channel Input-to-Input Isolation
05334-022
INTERFERING CHANNEL AMPLITUDE (dBm) 15–20 –10–15 0–5 5 10
PEAK DEVIATION FROM
–45dBm EQUIVALENT OUTPUTS (dB)
16
14
12
10
8
6
4
2
0
B–>A
450 MHz
A–>B
450 MHz
B–>A 880MHz
A–>B 880MHz
B–>A 1880MHz
A–>B 1880MHz
B–>A 2140MHz
A–>B 2140MHz
B–>A 2500 MHz
A–>B
2500MHZ
PEAK INTERFERENCE (IN dB) TO A–45dBm INPUT SIGNAL
DUE TO AN INTERFERING SIGNAL ON THE OTHER
CHANNEL. A->B = A INTERFERING WITH B, X-AXIS IS
CHANNEL A INPUT B->A = B INTERFERING WITH A, X-AXIS
IS CHANNEL B INPUT FREQUENCY SEPARATION OF THE
TWO CHANNELS = 1kHz. SEE CHARACTERIZATION
DESCRIPTION SECTION FOR MORE INFORMATION.
Figure 76. Apparent Measurement Error Due to Overall Channel-to-Channel
Cross-Coupling
0
1
2
3
4
5
6
7
–20 –15 –10 –5 0 5 10 15
INTERFERING CHANNEL AMPLITUDE (dBm)
PEAK DEVIATION FROM -45dBm EQUIVALENT
OUTPUT(dB)
B->A
A->B
PEAK INTERFERENCE (IN dB) TO A -45dBm INPUT
SIGNAL DUE TO AN INTERFERING SIGNAL ON THE
OTHER CHANNEL.
A->B = A INTERFERING WITH B, X-AXIS IS CHANNEL A
INPUT Freq chA = 2500 MHz Freq CHB = 1880MHz
B->A = B INTERFERING WITH A, X-AXIS IS
CHANNEL B INPUT Freq CHB = 2500 MHz
Freq CHA = 1880 MHz
FREQUENCY SEPARATION OF THE
TWO CHANNELS = 620 MHz.
SEE CHARCTERIZATION DESCRIPTION
SECTION FOR MORE INFORMATION
05334-085
Figure 77. Improved Measurement Error with Increased Frequency
Separation
AD8364 Data Sheet
Rev. B | Page 36 of 44
CHOOSING THE RIGHT VALUE
FOR CHP[A, B] AND CLP[A, B]
The AD8364’s VGA includes an offset cancellation loop, which
introduces a high-pass filter effect in its transfer function. The
corner frequency, fHP, of this filter must be below that of the lowest
input signal in the desired measurement bandwidth frequency
to properly measure the amplitude of the input signal. The
required value of the external capacitor is given by
CHP[A, B] = 200 µF/(2 × π × fHP )(fHP in Hz) (18)
Thus, for operation at frequencies down to 100 kHz, CHP[A, B]
should be 318 pF.
In the standard connections for the measurement mode, the
VST[A, B] pin is tied to OUT[A, B]. For small changes in input
amplitude (a few decibels), the time-domain response of this
loop is essentially linear with a 3 dB low-pass corner frequency
of nominally fLP = 1/(2 × π × CLP[A, B] × 1.1 kΩ). Internal time
delays around this local loop set the minimum recommended
value of this capacitor to about 300 pF, making fLP = 482 kHz.
For operation at lower signal frequencies, or whenever the
averaging time needs to be longer, use
CLP[A, B] = 900 µF/2 × π × fLP (fLP in Hz) (19)
When the input signal exhibits large crest factors, such as a
WCDMA signal, CLP[A, B] must be much larger than might at
first seem necessary. This is due to the presence of significant low
frequency components in the complex, pseudo random modu-
lation, which generates fluctuations in the output of the AD8364.
RF BURST RESPONSE TIME
RF burst response time is important for modulated signals that
have large steps in power, such as a single carrier EVDO that
has the potential for a greater than 20 dB burst of power (for
approximately 200 µs out of every 800 µs).
Accurate power detection for signals with RF bursts is achieved
when the AD8364 is able to respond quickly to the change in RF
power; however, the response time is limited by the capacitors
placed on Pins CLP[A, B], CHP[A, B], and DEC[A, B].
Capacitors placed on the DEC[A, B] pins affect the response time
the least and should be chosen as stated in the RF Input Interface
section. Capacitors placed on CHP[A, B] and CLP[A, B] should
be chosen according to the equations in the Choosing the Right
Value for CHP[A, B] and CLP[A, B] section and the response time
for the AD8364 should be evaluated. If the response time is not
fast enough to follow the burst response, the values for CLP[A, B]
should be decreased. The capacitor values placed on the CLP[A,
B] have the largest effect on the rise and fall times. The capacitor
values placed on CHP[A, B] affect the rising and falling corner
of the response (overshoot or under-shoot); however, the falling
corner is most likely swamped out by the effect of CLP[A, B].
Once the response time is set so that the AD8364 is just able to
follow the RF burst requirements (within the tolerance of the
capacitors), the output of the AD8364 should be evaluated with
an oscilloscope. If there is ripple on the output (due to the
modulated signal), averaging may need to be performed on
the DSP to achieve a true rms response. Figure 44 and Figure 45
may help in determining the proper CLP[A, B] values to use.
SINGLE-ENDED INPUT OPERATION
For optimum operation, the RF inputs to the AD8364 should be
driven differentially. However, the AD8364 RF inputs can also
be driven in a single-ended configuration with reduced dynamic
range. Figure 78 shows a recommended input configuration for
a single channel.
Figure 79 shows the performance obtained with the configuration
shown in Figure 78. The user should note that the dynamic
range performance suffers in single-ended configuration due to
the inherent amplitude and phase imbalance at the RF inputs.
However, at low frequency the dynamic range is quite good and
users trying to detect low frequency or baseband signals may
want to consider this as an option. At frequencies greater than
450 MHz, the dynamic range decreases to about 20 dB,
reducing the AD8364’s usefulness for many applications.
Performance in single-ended configuration is subject to circuit
board layout (see the Printed Circuit Board Considerations
section).
100Ω
100Ω
INHx
INLx
05334-044
Figure 78. Recommended Input Configuration for Single-Ended Input Drive
05334-045
RF INPUT (dBm) 20–60 –40 –30–50 –20 –10 0 10
OUTA (V)
5.0
4.0
3.0
2.0
4.5
3.5
2.5
1.5
1.0
0.5
0
50MHz
100MHz
45 MHz
50MHz Error
100MHz ERROR
450MHz ERROR
ERROR (dB)
Figure 79. Single-Ended Performance for
the Configuration Shown in Figure 78
Data Sheet AD8364
Rev. B | Page 37 of 44
PRINTED CIRCUIT BOARD CONSIDERATIONS
Each RF input pin of the AD8364 presents 100 Ω impedance
relative to their respective ac grounds. To ensure that signal
integrity is not seriously impaired by the printed circuit board
(PCB), the relevant connection traces should provide appropriate
characteristic impedance to the ground plane. This can be
achieved through proper layout. When laying out an RF trace
with controlled impedance, consider the following:
• When calculating the RF line impedance, take into account
the spacing between the RF trace and the ground on the
same layer.
• Ensure that the width of the microstrip line is constant and
that there are as few discontinuities, such as component
pads, as possible along the length of the line. Width variations
cause impedance discontinuities in the line and may result
in unwanted reflections.
• Do not use silkscreen over the signal line because it can
alter the line impedance.
• Keep the length of the RF input traces as short as possible.
Figure 80 shows the cross section of a PC board, and Table 6
shows two possible sets of dimensions that provide a 100 Ω line
impedance for FR-4 board material with εr = 4.6 and Rodgers 4003
board material with εr = 3.38.
Table 6. Possible Trace Dimensions for ZO = 100 Ω
Dimension FR-4 (mil) Rodgers 4003 (mil)
W 22 6
H 53 11
T 2 0.7
W3W
ER
3W
H
T
05334-046
Figure 80. Cross-Section View of a PC Board
It is possible to approximate a 100 Ω trace on a board designed
with the 50 Ω dimensions above by removing the ground plane
within three line widths of the area directly below the trace.
However, more predictable performance may be obtained with
precise ground plane spacing. It is possible to design a circuit
board with two ground planes, one plane for areas with 50 Ω
characteristic impedance and another for areas with 100 Ω
characteristic impedance. If the 100 Ω plane is placed below the
50 Ω plane, then an opening can be made in the 50 Ω plane to
allow the 100 Ω traces to work against the 100 Ω ground plane.
The two ground planes should be connected together with as
many vias as possible.
The accurate measurement range (that is, the dynamic range) of
AD8364’s detectors is sensitive to amplitude and phase matching
of the signals presented at the differential inputs. Care should be
taken to ensure matching of these parameters and to minimize
parasitic capacitance on the RF inputs when laying out the PC
board. It is also suggested that the two traces associated with
each differential input be mirror images, or duplicates, of one
another where possible. A high quality balun with known
output magnitude and phase characteristics is recommended to
perform single-ended to balanced conversions. It is possible to
improve the dynamic range by skewing the amplitude and
phase matching at the input. See the Typical Performance
Characteristics section for more details.
Stable, low ESR capacitors are mandatory in the RF circuitry of
the AD8364. This corresponds to capacitors connected to
Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. High
ESR capacitors may result in amplitude and phase mismatch at
the differential inputs, which in turn results in low dynamic range.
Capacitors with poor aging characteristics under temperature
cycling have been shown to accentuate the temperature drift
during operation of the AD8364. Use of Samsung CL10 series
multilayer ceramic capacitors (or similar) in the RF area are
recommended.
High transient and noise levels on the power supply, ground,
and inputs should be avoided. This reinforces the need for
proper supply bypassing and decoupling. See the Evaluation
Board section for suggestions.
A solder appropriate for either the lead-free or leaded version of
the AD8364 should be chosen. After the circuit board has been
soldered, it is important to thoroughly clean all excess solder
flux and residues from the board. Any residual material may act
as stray parasitic capacitance, which could result in degraded
performance.
PACKAGE CONSIDERATIONS
The AD8364 uses a compact 32-lead LFCSP. A large exposed
paddle on the bottom of the device provides both a thermal
benefit and a low inductance path to ground for the circuit. To
make proper use of this packaging feature, the PCB RF/dc
common ground reference needs to make contact directly
under the device with as many vias as possible to lower the
inductance and thermal impedance.
AD8364 Data Sheet
Rev. B | Page 38 of 44
DESCRIPTION OF CHARACTERIZATION
The general hardware configuration used for most of the
AD8362 characterization is shown in Figure 81. The signal
sources used in this example are the Rohde & Schwarz SMIQ03B
and Agilent E4438C. Input-matching baluns are used to transform
the single-ended RF signal to its differential form. Due to the
differential inputs’ sensitivity to amplitude and phase mismatch,
specific baluns were used for each characterization frequency to
achieve the best performance.
Other selected configurations are shown in Figure 82 and
Figure 83 as well.
COMPUTER
CONTROLLER
AGILENT
34970A
METER/
SWITCHING
AD8364
CHARACTERIZATION
BOARD
OUTA
OUTB
OUTP
OUTN
VREF
TEMP
INA
INB
–3dB
SIGNAL
SOURCE
–3dB
SIGNAL
SOURCE
05334-047
Figure 81. General Characterization Configuration
–8dB –6dB
INLA/B
50Ω
AGILENT 8648
RF SOURCE
–6dB SPLITTER
–8dB
–9dB
AD8340 OR
AD8341 VECTOR
MODULATOR –8dB –6dB
INHA/B
MINI-CIRCUITS
ZHL–42W
05334-052
Figure 82. Configuration for Amplitude and Phase Mismatch
Characterization
BASIS FOR ERROR CALCULATIONS
The slope and intercept are derived using the coefficients of a
linear regression performed on data collected in its central
operating range. Error is stated in two forms: (1) error from
linear response to CW waveform and (2) output delta from
25°C performance.
The error from linear response to CW waveform is the decibel
difference in output from the ideal output defined by the
conversions gain and output reference. This is a measure of the
linearity of the device response to both CW and modulated
waveforms. The error in dB is calculated by
Error (dB) =
( )
Slope
PPSlopeVZ
IN
OUT
−×−
where PZ is the x-axis intercept expressed in dBm. This is
analogous to the input amplitude that would produce an output
of 0 V, if such an output was possible.
Error from the linear response to the CW waveform is not a
measure of absolute accuracy, since it is calculated using the
slope and intercept of each device. However, it verifies the
linearity and the effect of modulation on the device’s response.
Similarly, error from 25°C performance uses the 25°C
performance of a given device and waveform type as the
reference from which all other performance parameters shown
alongside it are compared. It is predominantly (and most often)
used as a measurement of output variation with temperature.
Data Sheet AD8364
Rev. B | Page 39 of 44
26
27
28
29
30
32
31
15
14
13
12
11
9
10
7
6 854
31 2
25 16
1819 17
20
21
22
24 23
VPOS
C20
100pF
C21
0.1µF
C22
0.1µF
C1
0.1µFC24
100pF
R21
0ΩC16
CLPB
AD8364ACPZ
C9
0.1µF
C9
0.1µF
C15
CLPA
C23
100pF
C8
0.1µF
C10
100pF
C11
0.1µF
R5
0Ω
R4
0Ω
R24
0Ω
C12
100pF
C13
0.1µF
VPOS
VPOS
VPSA
CHPA CLPAACOMTEMPACOMVPSRCOMADECA
CHPB CLPBVLVLVREFADJAADJBCOMBDECB
VPSB
INHB
INLB
COMR
PWDN
INLA
INHA
VSTA
VSTB
OUTB
FBKB
OUTN
OUTP
FBKA
OUTA
BALUN
BALUN
HP6236B
POWER
SUPPLY
SMIQ06B
SIGNAL
GENERATOR
TEKTDS510
SCOPE
LECROY9213
PULSE
GENERATOR
3dB
05334-048
Figure 83. Configuration for RF Burst Measurement
AD8364 Data Sheet
Rev. B | Page 40 of 44
EVALUATION BOARD
AD8364-EVAL Z is a 4-layer, FR4-based printed circuit board.
For normal operation, it requires a 5 V/100 mA power supply.
The 5 V power supply should be connected to the clip leads
labeled VPS and COMM1. The two RF input signals are applied
to two edge-mounted SMA-type RF connectors. The output
signals are accessible via the OUTA, OUTB, OUTN, OUTP,
and TEMP clip leads. The circuit board can also accommodate
6-pin and 26-pin headers through which the power supply,
ground, temperature adjust nodes, and output signal pins are
accessible (the circuit board is shipped with these headers not
installed).
The two RF input signals are applied to two broadband baluns
(Anaren BD0826J50200A00), which, in turn, drive the AD8364
RF inputs. This device is specified to operate from 800 MHz to
2.6 GHz but is operational from 500 MHz to 2.7 GHz. To oper-
ate below 500 MHz, these baluns can be removed so that the
AD8364 is driven single-ended.
1.5K
BLK
OUTB
DNI DNI
DNI
0.1UF
BLK
BLK
DNI
0.1UF
BLK
1K 1K 0.1UF
100PF
VPS
0.1UF
0.1UF
JOHNSON142-0701-851
BLK
VPS
BD0826J50200A00
0.1UF
BD0826J50200A00
0.1UF
JOHNSON142-0701-851
0.1UF
VPS_SENSE
OUTN
OUTA
VPS
1K 0.1UF
DNI
DNIDNI
TBD0805
22UF
PWDN
1000PF
100PF
ADJA
1.5K
OUTB
PWDN
OUTN
VSTA
22UF
0.1UF 100PF
OUTP
0.1UF
VREF
100PF
VPS
OUTP
1K
0.1UF
1K
VREF
100PF
TEMP
VSTB
OUTA
1K
1K
3M3429-1302
VREF
DNI
DNI
DNI
DNI
1K
DNI
DNI
22-12-2064
VPS
BLK BLK
BLK
DNI
1K
DNI
1K
DNI
TEMP
BLK
BLK ADJB
BLK ADJA
0.1UF
ADJB
BLK
DUT
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
4
5
6
7
8
9
PAD
C22C1C8
C16
R35
R14
R32
R9
C14
R24
C9
C12
C24C23
C10
P1
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
3
4
5
6
7
8
9
R25
L1
C13C11
R41
C7C6
C21C19
C20
C3 C4
C5
C2
VPS
1
P2
1
2
3
4
5
6
T1
3
4
2 56
1
T2
3
4
2 56
1
R20 R18
R19
R17
R2
INB
1
2 3 4 5
INA
1
2345
COMM2
1
COMM1
1
COMM3
1
COMM4
1
OUTB
1
OUTN
1
OUTP
1
OUTA
1
TEMP
1
ADJA
1
ADJB
1
VREF
1
AGND AGND
AGND
AGND
G2G1NC6 BAL2
BAL1
UNBAL
G2G1NC6 BAL2
BAL1
UNBAL
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND AGND AGND
AGND
AGND
AGND AGND
AGND
AGND
AGND
AGND AGND
AGND
AD8364ACPZ
05334-086
Figure 84. AD8364 Evaluation Board Schematic
Data Sheet AD8364
Rev. B | Page 41 of 44
OUTLINE DIMENSIONS
3.45
3.30 S Q
3.15
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDE C S TANDARDS MO-220- V HHD- 2
1
32
8
9
25
24
1716
COPLANARITY
0.08
3.50 REF
0.50
BSC
PI N 1
INDICATOR
PIN 1
INDICATOR
0.30
0.25
0.18 0.20 REF
12° M AX 0.80 M AX
0.65 TYP
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
0.50
0.40
0.30
5.00
BSC SQ
4.75
BSC SQ
0.60 M AX
0.60 M AX
0.25 M IN
05-25-2011-A
TOP VIEW
EXPOSED
PAD
BOTTOM VIEW
Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes Temperature Range Package Description
Package
Option
Ordering
Quantity
AD8364ACPZ-WP 2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 36 Units
AD8364ACPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 1,500 Units
AD8364ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 250 Units
AD8364-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 WP = Waffle Pack.
AD8364 Data Sheet
Rev. B | Page 42 of 44
NOTES
Data Sheet AD8364
Rev. B | Page 43 of 44
NOTES
