| FAIRCHILD eapseqraaeresenpaenreaneseeuasgssseeasanrsee SEMICONDUCTOR NC7W2Z17 March 1999 Revised April 1999 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs General Description The NC7W2Z17 is a dual buffer with Schmitt trigger inputs from Fairchilds Ultra High Speed Series of TinyLogic in the SC70 6-lead package. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a very broad Voc operating range. The device is specified to operate over the 1.8V to 5.5V Voc range. The inputs and outputs are high impedance when Voc is OV. Inputs tolerate voltages up to 7V independent of Veco operating voltage. Schmitt trigger inputs typically achieve 1V hysteresis between the positive going and neg- ative going input threshold voltage at 5V Voc. Features Mf Space saving SC70 6-lead package M Ultra High Speed: tpp 3.6 ns Typ into 50 pF at 5V Veo W@ High Output Drive: +24 mA at 3V Voc W@ Broad Voc Operating Range; 1.8V to 5.5V lf Matches the performance of LCX when operated at 3.3V Voc @ Power down high impedance inputs/outputs Hf Overvoliage tolerant inputs facilitate 5V to 3V translation M@ Patented noise/EMI reduction circuitry implemented Ordering Code: Order Package Package ae . Number Number Top Mark Package Description Supplied As NC7WZ17P6 MAAO6A Z17 6-Lead SC70, EIAJ SC88, 1.25mm Wide 250 Units on Tape and Reel NC7WZ17P6X MAAO6A Z17 6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel Logic Symbol Connection Diagrams IEEE/IEC 4,00 [> Ts], soo Pt Ly, eno ET] TTS] Vcc A,[3 4lY. _to | 2 o> 2 (Top View) . sae Pin One Orientation Diagram Pin Descriptions Pin Names Description H H H Ay, Ao Data Inputs ; (Top View) AAA Y4, Yo Output Function Table A Cw Y=A Input Output Pin One A Y AAA represents Package Top Mark - see ordering code L L Note: Orientation of Top Mark determines Pin One location. Read the Top H H Package Mark left to right, Pin One is the lower left pin (see diagram). H =HIGH Logic Level L = LOW Logic Level TinyLogic is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS500217.prf www.fairchildsemi.com sindu] 4o66uL WIWYOS YUM J9INg [ENG SHN wIIHoTAUIL ZELZMZONNC7WZ17 Absolute Maximum Ratingsinote 1) Supply Voltage (Voc) 0.5V to +7V DC Input Voltage (Vin) 0.5V to +7V DC Output Voltage (VouT) -0.5V to +7V DC Input Diode Current (Ix) @ Vin <-0.5V -50 mA DC Output Diode Current (lox) @ Vout < -0.5V 50 mA DC Output Current (Ioyq) +50 mA DC Voeco/GND Current (Io/lanp) +100 mA Storage Temperature (Tst@) 65C to +150C Junction Temperature under Bias (Ty) 150C Junction Lead Temperature (T,) (Soldering, 10 seconds) 260C Power Dissipation (Pp) @ +85C 180 mW DC Electrical Characteristics Recommended Operating Conditions Supply Voltage Operating (Voc) 1.8V to 5.5V Supply Voltage Data Retention (Vgc) 1.5V to 5.5V Input Voltage (Vin) OV to 5.5V Output Voltage (Vout) OV to Voc Operating Temperature (Ta) 40C to +85C Thermal Resistance (04a) 350C/W Note 1: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. Fairchild does not recommend operation outside datasheet specifi- cations. Veco Ta =+25C Ta =40C to +85C Symbol Parameter Units Conditions (Vv) Min Typ Max Min Max Vp Positive Threshold 1.8 0.7 1.07 1.5 0.7 1.5 Voltage 2.3 1.0 1.38 1.8 1.0 1.8 3.0 1.3 1.74 2.2 1.3 2.2 Vv 45 1.9 2.43 3.1 1.9 3.1 5.5 22 2.88 3.6 22 3.6 VN Negative Threshold 1.8 0.25 0.56 0.9 0.25 0.9 Voltage 2.3 0.40 0.75 1.15 0.40 1.15 3.0 0.6 0.98 1.5 0.6 1.5 Vv 45 1.0 1.42 2.0 1.0 2.0 5.5 1.2 1.68 2.3 1.2 2.3 Vu Hysteresis Voltage 1.8 0.15 0.51 1.0 0.15 1.0 2.3 0.25 0.62 11 0.25 11 3.0 04 0.76 1.2 0.4 1.2 Vv 45 0.6 1.01 1.5 0.6 1.5 5.5 0.7 1.20 1.7 0.7 1.7 Vou HIGH Level Output 1.8 1.7 1.8 1.7 lo =100 LA Voltage 2.3 22 2.3 2.2 3.0 29 3.0 29 45 44 45 44 23 To 2.14 1.9 Vo Min=Yid Pan 3.0 24 2.75 24 low =16 mA 3.0 23 2.62 23 low =-24 mA 45 3.8 4.13 3.8 loy =-32 mA Voi LOW Level Output 1.8 0.0 0.1 0.1 lot = 100 LA Voltage 2.3 0.0 0.1 0.1 3.0 0.0 0.1 0.1 45 0.0 0.1 0.1 23 0.10 03 03 Vo |Yin= Yi Poana 3.0 0.16 0.4 0.4 lop =16 mA 3.0 0.24 0.55 0.55 lol =24 mA 4.5 0.25 0.55 0.55 lol =32 mA lI Input Leakage Current 010 5.5 +1 +10 HA | Vij =5.5V, GND lore Power Off Leakage Current 0.0 1 10 HA | Vix or Vout =5.5V loc Quiescent Supply Current | 1.8 to 5.5 1.0 10 HA |Vin=5.5V, GND www.fairchildsemi.comAC Electrical Characteristics Veco Ta =+25C Ta, =40C to +85C Symbol Parameter Units Conditions | Fig. No. (Vv) Min Typ Max Min Max tPLH Propagation Delay 1.8 2.0 6.9 11.9 2.0 13.1 CL = 15 pF, Figure 1 tPHL 2540.2 15 48 8.2 15 9.0 RL=1MQ Figure 3 3.3403 1.0 3.7 5.6 1.0 6.2 ns 5.0+0.5 0.8 3.0 47 0.8 5.2 tPLH Propagation Delay 3.3403 1.5 4.3 6.6 1.5 7.3 CL = 50 pF, Figure 1 tPHL 5.0405 1.0 3.6 5.6 1.0 6.2 ns R, = 5002 Figure 3 Cn Input Capacitance 0 25 pF Cpp Power Dissipation 3.3 10 pF (Note 2) Figure 2 Capacitance 5.0 12 Note 2: Cpp is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (Icep) at no output loading and operating at 50% duty cycle. (See Figure 2.) Cpp is related to Ip dynamic operating current by the expression: Icep = (Cpp)(Veo)fin) + (Ieestatic). AC Loading and Waveforms Veo INPUT OUTPUT T* = = Yeo C_ includes load and stray capacitance Input PRR = 1.0 MHz; tw = 500 ns FIGURE 1. AC Test Circuit 10% end Veo (4) Vou IwPut ohip> OUTPUT 50% Vou Input = AC Waveform, t, = t= 1.8 ns; PRR = variable; Duty Cycle = 50% FIGURE 3. AC Waveforms FIGURE 2. Iccp Test Circuit 3 www.fairchildsemi.com ZLZMZONNC7WZ17 Tape and Reel Specification TAPE FORMAT Fh FS tc TY zz UZ Z R 1.181 MIN. Package Tape Number Cavity Cover Tape Designator Section Cavities Status Status Leader (Start End) 125 (typ) Empty Sealed P6 Carrier 250 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed Leader (Start End) 125 (typ) Empty Sealed P6X Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) @ 0.06140.002 TYP. [1.5540.05] Ko *} 0.157 TYP. @ 0,07940.002 TYP. by wg 8 0.069 0.008 8 [2,040.05] | j l4] | 1.75] 0.2] "| _ eel mt | [ A e+ (+) G5 - t gowax. [PT To | BAT TYP. A 1 : Foy TANGENT + POINTS, 4 VP EE -|}-o- 4. on | | Pin 4 1 7 T T : p+ f Pt TYP > SECTION B-B DIRECTION OF FEED _____+ A TYP @ TANGENT POINTS CAVITY Uris. SYM 3 MAX TYP SECTION A-A \ a. BEND RADIUS NOT TO SCALE Package Tape Size DIMA DIM B DIM F DIM K, DIM P1 DIM W 0.093 0.096 0.138 + 0.004 | 0.053 + 0.004 0.157 0.315 +0.004 $C70-6 8mm (2.35) (2.45) (3.5+40.10) | (1.35 0.10) (4) (8 +0.1) www.fairchildsemi.comREEL DIMENSIONS inches (millimeters) TAPE SLOT tes, DETAIL X SCALE: 3X | lL Wo Tape A B c D N wi Ww2 W3 Size 8 7.0 0.059 0.512 0.795 2.165 |0.331 + 0.059/-0.000 0.567 W1 + 0.078/-0.039 mm (177.8) | (1.50) | (13.00) | (20.20) | (55.00) | (8.40 + 1.50/-0.00) (14.40) (W1 + 2.00/+1.00) www.fairchildsemi.com ZLZMZONNC7WZ17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs Physical DimensiON$ inches (millimeters) unless otherwise noted l EEN. 254+0.10 2.1029.30 B. DIMEN _e GAGE PLANE c. DIMEN 9, LAND PA bien mes 0.425 NOMINAL A iy an 6-Lead SC70, EIAJ SC88, 1.25mm Wide Package Number MAAO6A LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.