MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
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VIN, VCC, and VDD
The MAX5037A accepts an input voltage range of +4.75V
to +5.5V or +8V to +28V. All internal control circuitry oper-
ates from an internally regulated nominal voltage of 5V.
For input voltages of +8V or greater, the internal VCC reg-
ulator steps the voltage down to +5V. The VCC output
voltage is a regulated 5V output capable of sourcing up
to 80mA. Bypass VCC to SGND with 4.7µF and 0.1µF low-
ESR ceramic capacitors in parallel for high-frequency
noise rejection and stable operation (Figure 1).
VCC powers all internal circuitry. VDD is derived exter-
nally from VCC and provides power to the high-side and
low-side MOSFET drivers. VDD is internally connected
to the power source of the low-side MOSFET drivers.
Use VDD to charge the boost capacitors that provide
power to the high-side MOSFET drivers. Connect the
VCC regulator output to VDD through an R-C lowpass fil-
ter. Use a 1Ω(R3) resistor and a parallel combination of
1µF and 0.1µF ceramic capacitors to filter out the high
peak currents of the MOSFET drivers from the sensitive
internal circuitry.
Calculate power dissipation in the MAX5037A as a
product of the input voltage and the total VCC regulator
output current (ICC). ICC includes quiescent current (IQ)
and gate drive current (IDD):
PD = VIN x ICC
ICC = IQ+ fSW x (QG1 + QG2 + QG3 + QG4)
where, QG1, QG2, QG3, and QG4 are the total gate
charge of the low-side and high-side external
MOSFETs, IQis 4mA (typ), and fSW is the switching fre-
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the VCC regulator by connecting IN and VCC together.
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5037A includes an undervoltage lockout with
hysteresis and a power-on reset circuit for converter
turn-on and monotonic rise of the output voltage. The
UVLO circuit monitors the VCC regulator output while
actively holding down the power-good (PGOOD) out-
put. The UVLO threshold is internally set between
+4.0V and +4.5V with a 200mV hysteresis. Hysteresis
at UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5037A draws up to 4mA of current before the input
voltage reaches the UVLO threshold.
The compensation network at the current-error amplifi-
er, CLP1 and CLP2, provides an inherent soft-start to
the VRM power supply. It includes a parallel combina-
tion of capacitors (C34, C36) and resistors (R5, R6) in
series with other capacitors (C33, C35) (see Figure 1).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2VP-P
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to VCC to set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock for the phase-locked loop
(PLL). When driven externally, the internal oscillator
locks to the signal at CLKIN. A rising edge at CLKIN
starts the ON cycle of the PWM. Ensure that the exter-
nal clock pulse width is at least 200ns. CLKOUT pro-
vides a phase-shifted output with respect to the rising
edge of the signal at CLKIN. PHASE sets the amount of
phase shift at CLKOUT. Connect PHASE to VCC for
120° of phase shift, leave PHASE unconnected for 90°
of phase shift, or connect PHASE to SGND for 60° of
phase shift with respect to CLKIN.
The MAX5037A requires compensation on PLLCMP
even when operating from the internal oscillator. The
device requires an active PLL in order to generate the
proper clock signal required for PWM operation.
Control Loop
The MAX5037A uses an average-current-mode control
scheme to regulate the output voltage (Figure 3). The
main control loop consists of an inner current loop and
an outer voltage loop. The inner loop controls the out-
put currents (IPHASE1 and IPHASE2), while the outer
loop controls the output voltage. The inner current loop
absorbs the inductor pole reducing the order of the
outer voltage loop to that of a single-pole system.
(1)
(2)