General Description
The MAX5037A dual-phase, PWM controller provides
high-output-current capability in a compact package
with a minimum number of external components. The
MAX5037A utilizes a dual-phase, average-current-mode
control that enables optimal use of low RDS(ON)
MOSFETs, eliminating the need for external heatsinks
even when delivering high output currents.
Differential sensing enables accurate control of the
output voltage, while adaptive voltage positioning
provides optimum transient response. An internal regula-
tor enables operation with either +5V or +12V input volt-
age without the need for additional voltage sources. The
high switching frequency, up to 500kHz per phase, and
dual-phase operation allow the use of low output induc-
tor values and input capacitor values. This accommo-
dates the use of PC board-embedded planar magnetics
achieving superior reliability, current sharing, thermal
management, compact size, and low system cost.
The MAX5037A also features a clock input (CLKIN) for
synchronization to an external clock, and a clock output
(CLKOUT) with programmable phase delay (relative to
CLKIN) for paralleling multiple phases. The MAX5037A
also limits the reverse current in case the bus voltage
becomes higher than the regulated output voltage.
The MAX5037A operates over the extended temperature
range (-40°C to +85°C) and is available in 44-pin MQFP
or thin QFN packages. Refer to the MAX5038A/
MAX5041A and MAX5065/MAX5067 data sheets for
either a fixed output voltage controller or an adjustable
output voltage controller in an SSOP or thin QFN package.
Applications
Servers and Workstations
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
Networking Systems
Large-Memory Arrays
RAID Systems
High-End Desktop Computers
Features
♦+4.75V to +5.5V or +8V to +28V Input Voltage
Range
♦Up to 60A Output Current
♦Internal Voltage Regulator for a +12V or +24V
Power Bus
♦Internal 5-Bit DAC VID Control (VRM 9.0/VRM 9.1
Compliant, 0.8% Accuracy)
♦Programmable Adaptive Output Voltage
Positioning
♦True Differential Remote Output Sensing
♦Out-of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
Dissipation
♦Average-Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
Accurate Current Limit Eliminates MOSFET and
Inductor Derating
♦Limits Reverse-Current Sinking in Paralleled
Modules
♦Integrated High-Output-Current Gate Drivers
♦Selectable Fixed Frequency 250kHz or 500kHz per
Phase (Up to 1MHz for Two Phases)
♦External Frequency Synchronization from 125kHz
to 600kHz
♦Internal PLL with Clock Output for Paralleling
Multiple DC-DC Converters
♦Power-Good Output
♦Phase Failure Detector
♦Overvoltage and Thermal Protection
♦44-Pin MQFP or Thin QFN Packages
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
________________________________________________________________ Maxim Integrated Products 1
19-3033; Rev 1; 4/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX5037AEMH -40°C to +85°C 44 MQFP
MAX5037AETH -40°C to +85°C 44 Thin QFN
Pin Configuration appears at end of data sheet.
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = VDD = +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND…………………………………….… .-0.3V to +35V
DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V]
DL_ to PGND..............................................-0.3V to (VDD + 0.3V)
BST_ to LX_ ..............................................................-0.3V to +6V
VCC to SGND............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
SGND to PGND .....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA= +70°C)
44-Pin MQFP (derate 12.7mW/°C above +70°C).......1013mW
44-Pin Thin QFN (derate 27.0mW/°C
above +70°C) ...........................................................2162.2mW
Package Thermal Resistance, θJC (Thin QFN only) ........+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYSTEM SPECIFICATIONS
828
Input Voltage Range VIN Short IN and VCC together for 5V input
operation 4.75 5.5 V
Quiescent Supply Current IQEN = VCC or SGND, VID inputs
unconnected 46mA
Efficiency ηILOAD = 52A (26A per phase) 90 %
STARTUP/INTERNAL REGULATOR
VCC Undervoltage Lockout UVLO VCC rising 4.0 4.15 4.5 V
VCC Undervoltage Lockout
Hysteresis 200 mV
VCC Output Accuracy VIN = 8V to 28V, ISOURCE = 0 to 80mA 4.85 5.1 5.30 V
VOUT/ADAPTIVE VOLTAGE POSITIONING (AVP)
RREG = RF = 100kΩ, RIN = 1kΩ, no load,
Figure 3 -0.8 +0.8
Nominal Output Voltage
Accuracy (VID Setting) VIN = VCC = 4.75V to 5.5V, or VIN = 8V to
28V, RREG = RF = 100kΩ, RIN = 1kΩ,
no load, Figure 3
-1 +1
%
Maximum REG Loading IREG_MAX 50 µA
TA = 0°C to +85°C -3 +3
REG Accuracy (Voltage
Positioning) d (∆VOUT)TA = -40°C to +85°C -5 +5 %
Maximum CNTR Loading ICNTR_MAX 50 µA
TA = 0°C to +85°C -3 +3
Center Voltage Set-Point
Accuracy (Note 2) d (∆VCNTR)TA = -40°C to +85°C -5 +5 %
MOSFET DRIVERS
Output Driver Impedance RON Low or high output 1 3 Ω
Output Driver Peak Source/Sink
Current IDH_, IDL_4A
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDD = +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Nonoverlap Time tNO CDH_/DL_ = 5nF 60 ns
OSCILLATOR AND PLL
CLKIN = SGND 238 250 262
Switching Frequency fSW CLKIN = VCC 475 500 525 kHz
PLL Lock Range fPLL 125 600 kHz
PLL Locking Time tPLL 200 µs
PHASE = VCC 115 120 125
PHASE = unconnected 85 90 95
CLKOUT Phase Shift
(at fSW = 125kHz)
φ
CLKOUT
PHASE = SGND 55 60 65
Degrees
CLKIN Input Pulldown Current ICLKIN 357µA
CLKIN High Threshold VCLKINH 2.4 V
CLKIN Low Threshold VCLKINL 0.8 V
CLKIN High Pulse Width tCLKIN 200 ns
PHASE High Threshold VPHASEH 4V
PHASE Low Threshold VPHASEL 1V
PHASE Input Bias Current IPHASEBIAS -50 +50 µA
CLKOUT Output Low Level VCLKOUTL ISINK = 2mA (Note 3) 100 mV
CLKOUT Output High Level VCLKOUTH ISOURCE = 2mA (Note 3) 4.5 V
CURRENT LIMIT
Average Current-Limit Threshold VCL CSP_ to CSN_ 45 48 51 mV
Reverse Current-Limit Threshold VCLR CSP_ to CSN_ -3.9 -0.2 mV
Cycle-by-Cycle Current Limit VCLPK CSP_ to CSN_ (Note 3) 90 112 130 mV
Cycle-by-Cycle Overload
Response Time tRVCSP_ to VCSN_ = +150mV 260 ns
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance RCS_4kΩ
Common-Mode Range VCMR
(
CS
)
-0.3 +3.6 V
Input Offset Voltage VOS
(
CS
)
-1 +1 mV
Amplifier Gain AV(CS) 18 V/V
3dB Bandwidth f3dB 4 MHz
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance gmca 550 µS
Open-Loop Gain AVOL
(
CE
)
No load 50 dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range VCMR
(
DIFF
)
-0.3 +1.0 V
DIFF Output Voltage VCM VSENSE+ = VSENSE- = 0 0.6 V
Input Offset Voltage VOS
(
DIFF
)
-2 +2 mV
Amplifier Gain AV
(
DIFF
)
0.997 1 1.003 V/V
3dB Bandwidth f3dB CDIFF = 20pF 3 MHz
Minimum Output Current Drive IOUT
(
DIFF
)
1.0 mA
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDD = +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SENSE+ to SENSE- Input
Resistance RVS_ 50 100 kΩ
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain AVOL
(
EA
)
70 dB
Unity-Gain Bandwidth fUGEA 3 MHz
EAN Input Bias Current IB(EA) CNTR and REG = open, VEAN = 2.0V -100 +100 nA
Error-Amplifier Output Clamping
Voltage VCLAMP
(
EA
)
With respect to VCM 810 918 mV
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN
VOV +6 +8 +10
PGOOD Trip Level VUV
PGOOD goes low when VOUT is outside of
this window -12.5 -10 -8.5
% VO
(VID)
PGOOD Output Low Level VPGLO ISINK = 4mA 0.20 V
PGOOD Output Leakage Current IPG PGOOD = VCC 1µA
Phase Failure Trip Threshold VPH PGOOD goes low when CLP_ is higher than
VPH 2.0 V
OVPIN Trip Threshold OVPTH Above VID programmed output voltage +10 +13 +16 % VO
(VID)
OVPOUT Source/Sink Current IOVPOUT VOVPOUT = 2.5V 15 20 mA
OVPIN Input Resistance ROVPIN 190 280 370 kΩ
Thermal Shutdown TSHDN 150 °C
Thermal-Shutdown Hysteresis 8°C
LOGIC INPUTS FOR VID
Logic-Input Pullup Resistors RVID 81220kΩ
Logic-Input Low Voltage VIL 0.8 V
Logic-Input High Voltage VIH 1.7 V
VID Internal Pullup Voltage VVID All VID_ inputs unconnected 2.8 2.9 3.2 V
EN INPUT
EN Input Low Voltage VENL 1V
EN Input High Voltage VENH 3V
EN Pullup Current IEN 4.5 5 5.5 µA
Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2: CNTR voltage accuracy is defined as the center of the adaptive voltage-positioning window (see Adaptive Voltage
Positioning section).
Note 3: Guaranteed by design. Not production tested.
Note 4: See Peak-Current Comparator section.
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
_______________________________________________________________________________________ 5
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
MAX5037A toc01
IOUT (A)
η (%)
4844403632282420161284
50
60
70
80
90
100
40
052
f = 500kHz
f = 250kHz
VIN = +5V
VOUT = +1.8V
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5037A toc02
IOUT (A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VIN = +12V
VIN = +5V
VOUT = +1.8V
fSW = 250kHz
EFFICIENCY vs. OUTPUT CURRENT
MAX5037A toc03
IOUT (A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VIN = +24V
VOUT = +1.8V
fSW = 125kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5037A toc04
IOUT (A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VOUT = +1.1V
VOUT = +1.5V VOUT = +1.8V
VIN = +12V
fSW = 250kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5037A toc05
IOUT (A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VOUT = +1.1V
VOUT = +1.5V VOUT = +1.8V
VIN = +5V
fSW = 500kHz
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
MAX5037A toc06
FREQUENCY (kHz)
ICC (mA)
550500400 450200 250 300 350150
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
6.0
100 600
VIN = +24V
VIN = +12V
VIN = +5V EXTERNALCLOCK
NO DRIVER LOAD
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
MAX5037A toc07
TEMPERATURE (°C)
ICC (mA)
603510-15
10
20
30
40
50
60
70
80
90
100
0
-40 85
250kHz
125kHz
VIN = +12V
CDL_ = 22nF
CDH_ = 8.2nF
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
MAX5037A toc08
TEMPERATURE (°C)
ICC (mA)
603510-15
50
75
100
125
150
175
25
-40 85
600kHz
500kHz
VIN = +5V
CDL_ = 22nF
CDH_ = 8.2nF
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
MAX5037A toc09
CDRIVER (nF)
ICC (mA)
13117 953
10
20
30
40
50
60
70
80
90
100
0
115
VIN = +12V
fSW = 250kHz
Typical Operating Characteristics
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
MAX5037A toc10
VOUT (V)
(VCSP_ - VCSN_) (mV)
1.71.61.4 1.51.2 1.31.1
46
47
48
49
50
51
52
53
54
55
45
1.0 1.8
PHASE 2
PHASE 1
OVERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
MAX5037A toc11
VIN (V)
VOV (V)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
1.0
4.75 5.25
VOUT = +1.8V
VOUT = +1.1V
OVERVOLTAGE THRESHOLD (OVPOUT)
vs. INPUT VOLTAGE
MAX5037A toc12
VIN (V)
OVPTH (V)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
4.75 5.25
VOUT = +1.8V
VOUT = +1.1V
UNDERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
MAX5037A toc13
VIN (V)
VUV (V)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
0.75
0.85
0.95
1.05
1.15
1.25
1.35
1.45
1.55
1.65
1.75
4.75 5.25
VOUT = +1.8V
VOUT = +1.1V
OUTPUT VOLTAGE
vs. ILOAD AND RCNTR
MAX5037A toc14
ILOAD (A)
VOUT (V)
5045403530252015105
1.65
1.70
1.75
1.80
1.85
1.90
1.60
055
RCNTR = 50kΩ
RCNTR = 100kΩ
RCNTR = ∞
RCNTR = 200kΩ
VIN = +12V
VID SETTING = +1.75V
OUTPUT VOLTAGE
vs. ILOAD AND RCNTR
MAX5037A toc15
ILOAD (A)
VOUT (V)
5045403530252015105
1.35
1.30
1.25
1.40
1.45
1.50
1.55
1.60
1.20
055
RCNTR = 50kΩ
RCNTR = 100kΩ
RCNTR = ∞
RCNTR = 200kΩ
VIN = +12V
VID SETTING = +1.4V
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (RF / RIN)
MAX5037A toc16
ILOAD (A)
VOUT (V)
5045403530252015105
1.65
1.70
1.75
1.80
1.85
1.60
055
VIN = +12V
VOUT = +1.8V
Rf / RIN = 15
Rf / RIN = 12.5
Rf / RIN = 10
Rf / RIN = 7.5
DIFFERENTIAL AMPLIFIER BANDWIDTH
MAX5037A toc17
FREQUENCY (MHz)
GAIN (V/V)
PHASE (DEGREES)
10.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.01 10
-225
-270
-180
-135
-90
-45
0
45
90
PHASE
GAIN
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
_______________________________________________________________________________________ 7
VCC LOAD REGULATION
vs. INPUT VOLTAGE
MAX5037A toc19
ICC (mA)
VCC (V)
13512015 30 45 75 9060 105
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
4.80
0150
VIN = +24V
VIN = +12V
VIN = +8V
DC LOAD
VCC LINE REGULATION
MAX5037A toc20
VIN (V)
VCC (V)
262420 2212 14 16 1810
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
4.75
828
ICC = 0
ICC = 40mA
VCC LINE REGULATION
MAX5037A toc21
VIN (V)
VCC (V)
131291011
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
4.75
8
ICC = 80mA
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
MAX5037A toc22
CDRIVER (nF)
tR (ns)
312616 21116
10
20
30
40
50
60
70
80
90
100
110
120
0
136
DL_
DH_
VIN = +12V
fSW = 250kHz
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
MAX5037A toc23
CDRIVER (nF)
tR (ns)
312616 21116
10
20
30
40
50
60
70
80
90
100
110
120
0
136
DL_
DH_
VIN = +12V
fSW = 250kHz
100ns/div
HIGH-SIDE DRIVER (DH_)
SINK AND SOURCE CURRENT
DH_
1.6A/div
MAX5037A toc24
VIN = +12V
CDH_ = 22nF
100ns/div
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
DL_
1.6A/div
MAX5037A toc25
VIN = +12V
CDL_ = 22nF
100µs/div
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz
CLKOUT
5V/div
MAX5037A toc26
PLLCMP
200mV/div
VIN = +12V
NO LOAD
350kHz
250kHz
0
100µs/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz
CLKOUT
5V/div
MAX5037A toc27
PLLCMP
200mV/div
0
VIN = +12V
NO LOAD
500kHz
250kHz
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
100µs/div
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz
CLKOUT
5V/div
MAX5037A toc28
PLLCMP
200mV/div
0
VIN = +12V
NO LOAD
250kHz
150kHz
40ns/div
HIGH-SIDE DRIVER (DH_)
RISE TIME
MAX5037A toc29
VIN = +12V
CDH_ = 22nF
DH_
2V/div
40ns/div
HIGH-SIDE DRIVER (DH_)
FALL TIME
MAX5037A toc30
DH_
2V/div
VIN = +12V
CDH_ = 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIME
MAX5037A toc31
DL_
2V/div
VIN = +12V
CDL_ = 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
FALL TIME
MAX5037A toc32
DL_
2V/div
VIN = +12V
CDL_ = 22nF
500ns/div
OUTPUT RIPPLE
MAX5037A toc33
VOUT
(AC-COUPLED)
10mV/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
2ms/div
INPUT STARTUP RESPONSE
MAX5037A toc34
VIN
5V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
VPGOOD
1V/div
VOUT
1V/div
1ms/div
ENABLE STARTUP RESPONSE
MAX5037A toc35
VEN
2V/div
VPGOOD
1V/div
VOUT
1V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
40µs/div
LOAD-TRANSIENT RESPONSE
MAX5037A toc36
VIN = +12V
VOUT = +1.75V
ISTEP = 8A TO 52A
tRISE = 1µs
VOUT
50mV/div
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
REVERSE-CURRENT SINK vs.
TEMPERATURE
MAX5037A toc37
TEMPERATURE (°C)
IREVERSE (A)
603510-15
2.4
2.5
2.6
2.7
2.8
2.3
-40 85
VEXTERNAL = +3.3V
VEXTERNAL = +2V
VIN = +12V
VOUT = +1.5V
R1 = R2 = 1.5mΩ
200µs/div
REVERSE-CURRENT SINK
AT INPUT TURN-ON
MAX5037A toc38
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 2.5V REVERSE
CURRENT
5A/div
0A
R1 = R2 = 1.5mΩ
200µs/div
REVERSE-CURRENT SINK
AT INPUT TURN-ON
MAX5037A toc39
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 3.3V REVERSE
CURRENT
10A/div
0A
R1 = R2 = 1.5mΩ
200µs/div
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
MAX5037A toc40
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 2.5V REVERSE
CURRENT
5A/div
0A
R1 = R2 = 1.5mΩ
200µs/div
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
MAX5037A toc41
VIN = +12V
VOUT = +1.5V
VEXTERNAL = 3.3V
REVERSE
CURRENT
10A/div
0A
R1 = R2 = 1.5mΩ
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1–4, 44 VID3–VID0,
VID4
DAC Code Inputs. VID0 is the LSB and VID4 is the MSB for the internal 5-bit DAC (Table 1). Connect to
SGND for logic low or leave open circuit for logic high. These inputs have 12kΩ internal pullup
resistors to an internal 3V regulator.
5, 20, 35 SGND Signal Ground. Ground connection for the internal circuitry. QFN package exposed pad connected to
SGND.
6 OVPIN
Overvoltage Protection Circuit Input. Connect DIFF to OVPIN. When OVPIN exceeds +13% above the
VID programmed output voltage, OVPOUT latches DH_ low and DL_ high. Toggle EN low to high or
recycle the power to reset the latch.
7, 43 CLP1, CLP2 Current-Error Amplifier Output. Compensate the current loop by connecting an R-C network to ground.
8 OVPOUT Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a safety
device such as an SCR.
9 PGOOD
Power-Good Output. The open-drain, active-low PGOOD output goes low when the VID programmed
output voltage falls out of regulation or a phase failure is detected. The power-good window
comparator thresholds are +8% and -10% of the VID programmed output voltage. Forcing EN low also
forces PGOOD low.
10 SENSE+
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
VOUT+ at the load. The device regulates the difference between SENSE+ and SENSE- according to the
programmed VID code and adaptive voltage positioning.
11 SENSE- Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
VOUT- or PGND at the load.
12 DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
13 EAN Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
14 EAOUT Voltage-Error Amplifier Output. Connect to an external, gain-setting feedback resistor. The error
amplifier gain determines the output voltage load regulation for adaptive voltage positioning.
15 REG
REG Input. A resistor on REG applies the same voltage-positioning window at different VRM voltage
settings. For a no-load output voltage (VCORE) equal to VID, set RREG = RF, where the RF is the
feedback resistor of the voltage-error amplifier. VREG internally regulates to the programmed VID
output voltage.
16, 39 CSP1, CSP2 Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
17, 40 CSN1,
CSN2 Current-Sense Differential Amplifier Negative Input. Together with CSP_, senses the inductor current.
18 CNTR Adaptive Voltage Center Position Input. Connect a resistor between CNTR and SGND to program the
center of the adaptive VOUT position. VCNTR regulates to +1.22V.
19 EN Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current.
21, 33, 37 N.C. No Connection. Not internally connected.
22, 34 BST1, BST2 Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver
supply. Connect a 0.47µF ceramic capacitor between BST_ and LX_.
23, 32 DH1, DH2 High-Side Gate-Driver Output. Drives the gate of the high-side MOSFET.
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 11
Pin Description (continued)
PIN NAME FUNCTION
24, 31 LX1, LX2 Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal
for the high-side driver.
25, 30 DL1, DL2 Low-Side Gate-Driver Output. Synchronous MOSFET gate drivers for the two phases.
26 VDD
Supply Voltage for Low-Side and High-Side Drivers. VCC powers VDD. Connect a parallel combination
of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to VCC to filter out the high peak
currents of the driver from the internal circuitry.
27 VCC Internal 5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7µF
and 0.1µF ceramic capacitors.
28 IN Supply Voltage Connection. Connect IN to VCC for a 5V system.
29 PGND Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and VDD bypass capacitor
returns together.
36 CLKOUT Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use
CLKOUT to parallel additional MAX5037s.
38 CLKIN
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and
600kHz. Connect to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or
connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown current.
41 PHASE Phase Shift Setting Input. Drive PHASE high for 120°, leave PHASE unconnected for 90°, and force
PHASE low for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
42 PLLCMP External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see
Phase-Locked Loop section).
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
12 ______________________________________________________________________________________
MAX5037A
IN
EN
PHASE 1
CSP1
DRV_VCC
RAMP1
GMIN
CLK
CLP1
CSN1
OVPOUT
SHDN BST1
PGOOD
DL1
LX1
DH1
VCC
TO INTERNAL CIRCUITS
VDD
CSP1
CSN1
CLP1
PHASE 2
CSP2
DRV_VCC
GMIN
CLK
CLP2
CSN2
SHDN
BST2
DL2
LX2
DH2
CSP2
CSN2
CLP2
PHASE-
LOCKED
LOOP
RAMP
GENERATOR
RAMP2
CLKIN
PHASE
CLKOUT
PLLCMP
POWER-
GOOD
GENERATOR
DIFF
CLP1
CLP2
DAC_OUT
N
OVP
COMP
13% OF
DAC_OUT
DIFF
AMP
ERROR
AMP
SENSE-
SENSE+
DIFF
ADAPTIVE
VOLTAGE
POSITIONING
ROM
VOLTAGE-
POSITIONING
DAC
VID0
VID1
VID2
VID3
VID4
EAN
REG
CNTR
OVPIN
EAOUT
DAC_OUT
PGND
PGND
PGND
SGND
+0.6V
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
Functional Diagram
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 13
Detailed Description
The MAX5037A (Figures 1 and 2) average-current-
mode PWM controller drives two out-of-phase buck
converter channels. Average-current-mode control
improves current sharing between the channels while
minimizing component derating and size. Parallel multi-
ple MAX5037A regulators to increase the output current
capacity. For maximum ripple rejection at the input, set
the phase shift between phases to 90° for two paralleled
converters, or 60° for three paralleled converters. The
paralleling capability of the MAX5037A improves design
flexibility in applications requiring upgrades (higher load).
The programmable output voltage utilizes VID codes
compliant with Intel’s VRM 9.0/VRM 9.1 specifications.
MAX5037A
Q4
Q3
C39 C40
R3
D2
Q2
D1
VIN
C8–C11
Q1
VIN
VIN = +5V
VCC
D4
D3
C41
C12
C38
C3–C7
5 x 22µF
C14,
C15
C16–C25
C26–C30,
C37
LOAD
VOUT = +1.1V TO
+1.85V AT 52A
L2 R2
L1 R1
23
DH1
24
LX1
25
DL1
22
BST1
27
VCC
28
VDD
32
DH2
31
LX2
30
DL2
34
BST2
CSP2CSN2PGOODPHASESGNDPGNDCLP2CLP1
R11
PGOOD
VCC
R6
C35
C36
R5
C33
C34
39409415, 20, 3529437
C42
C1, C2
R13
VCC
C31
C32
R4
CSP1
16
CSN1
17
SENSE+
10
SENSE-
11
IN
28
CLKIN
38
PLLCMP
42
EN
19
R10
R8
R7
R9
R12C43
VIN
DAC
INPUTS
18 CNTR
15 REG
14 EAOUT
13 EAN
12 DIFF
6OVPIN
8OVPOUT
4VID0
3VID1
2VID2
1VID3
44 VID4
*SEE TABLE 2 FOR COMPONENT VALUES.
C13
IN
IN
Figure 1. Typical VRM Application Circuit, VIN = +5V
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
14 ______________________________________________________________________________________
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor rip-
ple current, effectively multiplying the switching fre-
quency by the number of phases. Each phase of the
MAX5037A consists of an inner average current loop
controlled by a common outer-loop voltage-error ampli-
fier (VEA). The combined action of the two inner current
loops and the output voltage loop corrects the output
voltage errors and forces the phase currents to be
equal.
MAX5037A
Q4
Q3
C39
1µF
C40
0.1µF
R3
D2
Q2
D1
VIN
C8–C11
4 x 22µF
Q1
VIN
VIN = +8V TO +28V
VCC
D4
D3
C41
0.1µF
C12
0.47µF
C38
4.7µF
C3–C7
5 x 22µF
LOAD
VOUT = +1.1V
TO +1.85V
AT 52A
L2
0.6µH
R2
1.35mΩ
L1
0.6µH
R1
1.35mΩ
23
DH1
24
LX1
25
DL1
22
BST1
27
VCC
28
VDD
32
DH2
31
LX2
30
DL2
34
BST2
CSP2CSN2PGOODPHASESGNDPGNDCLP2CLP1
R11
PGOOD
VCC
R6
C35
C36
R5
C33
C34
39409415, 20, 3529437
C42
0.1µF
C1, C2
2 x 47µF
R13
2.2Ω
VCC
C31
C32
R4
CSP1
16
CSN1
17
SENSE+
10
SENSE-
11
IN
28
CLKIN
38
PLLCMP
42
EN
19
R10
R8
R7
R9
R12C43
VIN
DAC
INPUTS
18 CNTR
15 REG
14 EAOUT
13 EAN
12 DIFF
6OVPIN
8OVPOUT
4VID0
3VID1
2VID2
1VID3
44 VID4
NOTE: SEE TABLE 2 FOR COMPONENT VALUES.
C13
0.47µF
C14, C15
2 x 100µF
C16–C25
2
x
270µF
C26–C30,
C37
6 x 10µF
Figure 2. Typical VRM Application Circuit, VIN = +8V to +28V
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 15
VIN, VCC, and VDD
The MAX5037A accepts an input voltage range of +4.75V
to +5.5V or +8V to +28V. All internal control circuitry oper-
ates from an internally regulated nominal voltage of 5V.
For input voltages of +8V or greater, the internal VCC reg-
ulator steps the voltage down to +5V. The VCC output
voltage is a regulated 5V output capable of sourcing up
to 80mA. Bypass VCC to SGND with 4.7µF and 0.1µF low-
ESR ceramic capacitors in parallel for high-frequency
noise rejection and stable operation (Figure 1).
VCC powers all internal circuitry. VDD is derived exter-
nally from VCC and provides power to the high-side and
low-side MOSFET drivers. VDD is internally connected
to the power source of the low-side MOSFET drivers.
Use VDD to charge the boost capacitors that provide
power to the high-side MOSFET drivers. Connect the
VCC regulator output to VDD through an R-C lowpass fil-
ter. Use a 1Ω(R3) resistor and a parallel combination of
1µF and 0.1µF ceramic capacitors to filter out the high
peak currents of the MOSFET drivers from the sensitive
internal circuitry.
Calculate power dissipation in the MAX5037A as a
product of the input voltage and the total VCC regulator
output current (ICC). ICC includes quiescent current (IQ)
and gate drive current (IDD):
PD = VIN x ICC
ICC = IQ+ fSW x (QG1 + QG2 + QG3 + QG4)
where, QG1, QG2, QG3, and QG4 are the total gate
charge of the low-side and high-side external
MOSFETs, IQis 4mA (typ), and fSW is the switching fre-
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the VCC regulator by connecting IN and VCC together.
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5037A includes an undervoltage lockout with
hysteresis and a power-on reset circuit for converter
turn-on and monotonic rise of the output voltage. The
UVLO circuit monitors the VCC regulator output while
actively holding down the power-good (PGOOD) out-
put. The UVLO threshold is internally set between
+4.0V and +4.5V with a 200mV hysteresis. Hysteresis
at UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5037A draws up to 4mA of current before the input
voltage reaches the UVLO threshold.
The compensation network at the current-error amplifi-
er, CLP1 and CLP2, provides an inherent soft-start to
the VRM power supply. It includes a parallel combina-
tion of capacitors (C34, C36) and resistors (R5, R6) in
series with other capacitors (C33, C35) (see Figure 1).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2VP-P
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to VCC to set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock for the phase-locked loop
(PLL). When driven externally, the internal oscillator
locks to the signal at CLKIN. A rising edge at CLKIN
starts the ON cycle of the PWM. Ensure that the exter-
nal clock pulse width is at least 200ns. CLKOUT pro-
vides a phase-shifted output with respect to the rising
edge of the signal at CLKIN. PHASE sets the amount of
phase shift at CLKOUT. Connect PHASE to VCC for
120° of phase shift, leave PHASE unconnected for 90°
of phase shift, or connect PHASE to SGND for 60° of
phase shift with respect to CLKIN.
The MAX5037A requires compensation on PLLCMP
even when operating from the internal oscillator. The
device requires an active PLL in order to generate the
proper clock signal required for PWM operation.
Control Loop
The MAX5037A uses an average-current-mode control
scheme to regulate the output voltage (Figure 3). The
main control loop consists of an inner current loop and
an outer voltage loop. The inner loop controls the out-
put currents (IPHASE1 and IPHASE2), while the outer
loop controls the output voltage. The inner current loop
absorbs the inductor pole reducing the order of the
outer voltage loop to that of a single-pole system.
(1)
(2)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
16 ______________________________________________________________________________________
The current loop consists of a current-sense resistor,
RS(an RC lowpass filter in the case of lossless inductor
current sensing), a current-sense amplifier (CA_), a
current-error amplifier (CEA_), an oscillator providing
the carrier ramp, and a PWM comparator (CPWM_).
The precision CA_ amplifies the sense voltage across
RSby a factor of 18. The inverting input to the CEA_
senses the output of the CA_. The output of the CEA_ is
the difference between the voltage-error amplifier out-
put (EAOUT) and the amplified voltage from the CA_.
The RC compensation network connected to CLP1 and
CLP2 provides external frequency compensation for
the respective CEA_. The start of every clock cycle
enables the high-side drivers and initiates a PWM ON
cycle. Comparator CPWM_ compares the output volt-
age from the CEA_ with a 0 to 2V ramp from the oscilla-
tor. The PWM ON cycle terminates when the ramp volt-
age exceeds the error voltage.
The outer voltage control loop consists of the differen-
tial amplifier (DIFF AMP), adaptive voltage-positioning
(AVP) block, digital-to-analog converter (DAC), and
voltage-error amplifier (VEA). The unity-gain differential
amplifier provides true differential remote sensing of the
output voltage. The differential amplifier output and the
AVP connect to the inverting input (EAN) of the VEA.
The noninverting input of VEA is internally connected to
the DAC output. The VEA controls the two inner current
loops (Figure 3). Use a resistive feedback network to
set the gain of the VEA as required by the adaptive
voltage-positioning circuit.
DRIVE 2
DRIVE 1
CPWM1
CPWM2
CEA1
CEA2
VEA
DIFF
AMP
CA1
CA2
DAC
CLP2
CSP2
CSN2
CLP1
CSN1
CSP1
SENSE+
SENSE-
VIN
VIN
LOAD
COUT
VOUT
RIN*
RF*
RS
RS
IPHASE1
IPHASE2
RCF
CCFF
CCF
RCF
CCCF
CCF
AVP
*RF AND RIN ARE EXTERNAL TO MAX5037A
(RF = R8, RIN = R7, FIGURES 1 AND 2).
MAX5037A
Figure 3. MAX5037A Control Loop
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 17
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense ampli-
fier senses the voltage across a current-sense resistor.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 4).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit condi-
tions. So to prevent inductor saturation, select an out-
put inductor with a saturation current specification
greater than the average current limit. Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a broken output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current com-
parator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5037A has a dedicated
transconductance current-error amplifier (CEA_) with a
typical gmof 550µS and 320µA output sink and source
current capability. The CEA_ outputs, CLP1 and CLP2,
serve as the inverting input to the PWM comparator.
CLP1 and CLP2 are externally accessible to provide
frequency compensation for the inner current loops
(Figure 3). Compensate CEA_ such that the inductor
current down slope, which becomes the up slope to the
inverting input of the PWM comparator, is less than the
slope of the internally generated voltage ramp (see the
Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the current-error amplifier
output to a 2VP-P ramp. At the start of each clock cycle,
an R-S flip-flop resets and the high-side driver (DH_)
turns on. The comparator sets the flip-flop as soon as
the ramp voltage exceeds the CLP_ voltage, thus termi-
nating the ON cycle (Figure 4).
Differential Amplifier
The unity-gain differential amplifier (DIFF AMP) facili-
tates the output voltage remote sensing at the load
(Figure 3). It provides true differential output voltage
sensing while rejecting the common-mode voltage
errors due to high-current ground paths. Sensing the
output voltage directly at the load provides accurate
load voltage sensing in high-current environments. The
VEA provides the difference between the differential
amplifier output (DIFF) and the desired VID pro-
grammed output voltage. The differential amplifier has
a unity-gain bandwidth of 3MHz. The difference
between SENSE+ and SENSE- regulates to the pro-
grammed VID output voltage.
Connect SENSE+ to an external resistor-divider network
at the output voltage to use the MAX5037A for output
voltages higher than those allowed by the VID codes.
2 x fS (V/s)
RAMP
CLK
CSP_
CSN_
GMIN
SHDN
CLP_
DRV_VCC
BST_
DH_
LX_
DL_
PGND
AV = 18
PWM
COMPARATOR
PEAK CURRENT
COMPARATOR
112mV
S
R
Q
Q
Gm =
550µS
Figure 4. Phase Circuit (Phase 1/Phase 2)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
18 ______________________________________________________________________________________
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop. The
VEA determines the error between the differential
amplifier output and the reference voltage generated
from the DAC.
The VEA output clamps to 0.9V relative to VCM (0.6V),
thus limiting the average maximum current from individ-
ual phases. The maximum average current-limit thresh-
old for each phase is equal to the maximum clamp
voltage of the VEA divided by the gain (18) of the cur-
rent-sense amplifier. This results in accurate settings
for the average maximum current for each phase. Set
the VEA gain using RFand RIN for the amount of output
voltage positioning required within the rated current
range as discussed in the Adaptive Voltage Positioning
section (Figure 3).
Adaptive Voltage Positioning
Powering new generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward voltage excursion when the output current sud-
denly decreases. A larger allowed voltage step excur-
sion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Voltage positioning and the ability to operate with the mul-
tiple reference voltages may require the output to regulate
away from a center value. Define the center value as the
voltage where the output equals the VID reference volt-
age at one half the maximum output current (Figure 5).
Set the voltage-positioning window (∆VOUT) using the
resistive feedback of the VEA. See the Adaptive
Voltage-Positioning Design Procedure section and use
the following equation to calculate the voltage-position-
ing window:
∆VOUT = IOUT x RIN / (2 x GCx RF)
where RIN and RFare the input and feedback resistors of
the VEA, GCis the current-loop transconductance, and
RSis the current-sense resistor or, if using lossless induc-
tor current sensing, the DC resistance of the inductor.
The voltage at CNTR (VCNTR) regulates to 1.2V (Figure
6). The current set by the resistor RCNTR is mirrored at
the inverting input of the VEA, centering the output volt-
age-positioning window on the VID programmed output
voltage. Set the center of the output voltage with a
resistor from CNTR to SGND in the following manner:
where VOUT is a required value of output voltage at the
corresponding IOUT. IOUT can be any value from no
load to full load.
RVR
IR
RG V VID
CNTR CNTR IN
OUT IN
FC OUT
=×
⎛
⎝
⎜⎞
⎠
⎟+−
()
2
GR
CS
=005.
LOAD (A)
VCNTR
NO LOAD 1/2 LOAD FULL LOAD
VOLTAGE-POSITIONING WINDOW
VCNTR + ∆VOUT/2
VCNTR - ∆VOUT/2
Figure 5. Defining the Voltage-Positioning Window
(3)
(4)
(5)
+1.2V
1X
1X
1X
1X
VCC VCC
EAN
DAC_OUT
REG
CNTR
Figure 6. Adaptive Voltage-Positioning Circuit
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 19
Applying the voltage-positioning window at different
VRM voltage settings requires that RREG = RF. The volt-
age on REG internally regulates to the programmed
VID output voltage. Choose RREG to limit the current at
REG to 50µA. For example, for a VID setting of 1.85V,
calculate the minimum allowed RREG as RREG =
1.85V/50µA = 37kΩ. To use larger values of RREG while
maintaining the required gain of the VEA, use larger
values for RIN.
In the case of a VID voltage setting equal to VCOREMAX
at IOUT = 0 (no load), RCNTR = ∞from the above equa-
tion (Figure 7). For systems requiring VCOREMAX as an
absolute maximum voltage when IOUT = 0 (no load),
calculate RREG using following the equation:
DAC Inputs (VID0–VID4)
The DAC programs the output voltage. The DAC typi-
cally receives a digital code, alternatively, the VID
inputs are hardwired to SGND or left open circuit.
VID0–VID4 logic can be changed while the MAX5037A
is active, initiating a transition to a new output voltage
level. Change VID0–VID4 together, avoiding greater
than 1µs skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong
voltage level followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. For any low-going VID step of 100mV or more, the
OVP can trip because the OVP trip reference changes
instantaneously with the VID code, but the converter
output does not follow immediately. The converter out-
put drops at a rate depending on the output capacitor,
inductor load, and the closed-loop bandwidth of the
converter. Do not exceed a maximum VID step size of
75mV.
The available DAC codes and resulting output voltages
(Table 1) comply with Intel’s VRM 9.0 specification.
Internal pullup resistors connect the VID inputs to a
nominal internal 3V supply. Force the VID inputs below
0.8V for logic low or leave unconnected for logic high.
Output voltage accuracy with respect to the pro-
grammed VID voltage is ±0.8% over the -40°C to +85°C
temperature range.
RRR
RR V
VID
REG IN F
IN F COREMAX
=×
+−
⎛
⎝
⎜
⎞
⎠
⎟
1
LOAD (A)
NO LOAD 1/2 LOAD FULL LOAD
VOLTAGE-POSITIONING WINDOW
VCOREMAX ≤ VID
VCOREMAX - ∆VOUT/2
VCOREMAX - ∆VOUT/2
Figure 7. Limiting the Voltage-Positioning Window
(6)
Table 1. Output Voltage vs. DAC Codes
VID INPUTS (0 = CONNECTED TO
SGND, 1 = OPEN CIRCUIT)
OUTPUT
VOLTAGE (V)
VID4 VID3 VID2 VID1 VID0 VOUT
11111 Output off
11110 1.100
11101 1.125
11100 1.150
11011 1.175
11010 1.200
11001 1.225
11000 1.250
10111 1.275
10110 1.300
10101 1.325
10100 1.350
10011 1.375
10010 1.400
10001 1.425
10000 1.450
01111 1.475
01110 1.500
01101 1.525
01100 1.550
01011 1.575
01010 1.600
01001 1.625
01000 1.650
00111 1.675
00110 1.700
00101 1.725
00100 1.750
00011 1.775
00010 1.800
00001 1.825
00000 1.850
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
20 ______________________________________________________________________________________
Phase-Locked Loop: Operation and
Compensation
The phase-locked loop (PLL) synchronizes the internal
oscillator to the external frequency source when driving
CLKIN. Connecting CLKIN to VCC or SGND forces the
PWM frequency to default to the internal oscillator fre-
quency of 500kHz or 250kHz, respectively. The PLL
uses a conventional architecture consisting of a phase
detector and a charge pump capable of providing
20µA of output current. Connect an external series
combination capacitor (C31) and resistor (R4) and a
parallel capacitor (C32) from PLLCMP to SGND to pro-
vide frequency compensation for the PLL (Figure 1).
The pole-zero pair compensation provides a zero at fZ
defined by 1 / [R4 x (C31 + C32)] and a pole at fP
defined by 1 / (R4 x C32). Use the following typical val-
ues for compensating the PLL: R4 = 7.5kΩ, C31 =
4.7nF, C32 = 470pF. When changing the PLL frequen-
cy, expect a finite locking time of approximately 200µs.
The MAX5037A requires compensation on PLLCMP even
when operating from the internal oscillator. The device
requires an active-phase-locked loop in order to generate
the proper internally shifted clock available at CLKOUT.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figure 1).
The drivers’ high-peak sink and source current capabil-
ity provides ample drive for the fast rise and fall times
of the switching MOSFETs. Faster rise and fall times
result in reduced cross-conduction losses. For modern
CPU applications where the duty cycle is less than
50%, choose high-side MOSFETs (Q1 and Q3) with a
moderate RDS(ON) and very low gate charge. Choose
low-side MOSFETs (Q2 and Q4) with very low RDS(ON)
and moderate gate charge.
The driver block also includes a logic circuit that pro-
vides an adaptive nonoverlap time to prevent shoot-
through currents during transition. The typical
nonoverlap time is 60ns between the high-side and
low-side MOSFETs.
BST_
VDD powers the low- and high-side MOSFET drivers.
The high-side drivers derive their power through a
bootstrap capacitor and VDD supplies power internally
to the low-side drivers. Connect a 0.47µF low-ESR
ceramic capacitor between BST_ and LX_. Bypass VDD
to PGND with 1µF and 0.1µF low-ESR ceramic capaci-
tors. Reduce the PC board area formed by these
capacitors, the rectifier diodes between VDD and the
boost capacitor, the MAX5037A, and the switching
MOSFETs.
Protection
The MAX5037A includes output overvoltage protection
(OVP), undervoltage protection (UVP), phase failure,
and overload protection to prevent damage to the pow-
ered electronic circuits.
Overvoltage Protection (OVP)
The OVP comparator compares the OVPIN input to the
overvoltage threshold. The overvoltage threshold is typ-
ically +13% above the programmed VID output voltage.
A detected overvoltage event latches the comparator
output forcing the power stage into the OVP state. In
the OVP state, the high-side MOSFETs turn off and the
low-side MOSFETs latch on. Use the OVPOUT high-
current-output driver to turn on an external crowbar
SCR. When the crowbar SCR turns on, a fuse must
blow or the source current for the MAX5037A regulator
must be limited to prevent further damage to the exter-
nal circuitry. Connect the SCR close to the input source
and after the fuse. Use an SCR large enough to handle
the peak I2t energy due to the input and output capaci-
tors discharging and the current sourced by the power
source output. Connect DIFF to OVPIN for differential
output sensing and overvoltage protection. Add an RC
delay to reduce the sensitivity of overvoltage circuit and
avoid nuisance tripping of the converter (Figure 8).
For any low-going VID step of 75mV or more, the OVP
can trip because the OVP trip reference changes instan-
taneously with the VID code, but the converter output
does not follow immediately. The converter output drops
at a rate depending on the output capacitor, inductor
load, and the closed-loop bandwidth of the converter.
MAX5037A
1kΩ
RF
RIN
0.1µF
OVPIN
DIFF
EAN
EAOUT
Figure 8. OVP Input Delay
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 21
Power-Good Generator (PGOOD)
The PGOOD output is high if all of the following condi-
tions are met (Figure 9):
1) The output is within 90% to 108% of the pro-
grammed output voltage.
2) Both phases are providing current.
3) EN is HIGH.
A window comparator compares the differential amplifi-
er output (DIFF) against 1.08 times the programmed
VID output voltage for overvoltage and 0.90 times the
programmed VID output voltage for undervoltage moni-
toring. The phase failure comparator detects a phase
failure by comparing the current-error amplifier output
(CLP_) with a 2.0V reference.
Use a 10kΩpullup resistor from PGOOD to a voltage
source less than or equal to VCC. An output voltage
outside the comparator window or a phase failure con-
dition forces the open-drain output low. The open-drain
MOSFET sinks 4mA of current while maintaining less
than 0.2V at the PGOOD output.
Phase Failure Detector
Output current contributions from the two phases are
within ±10% of each other. Proper current sharing
reduces the necessity to overcompensate the external
components. However, an undetected failure of one
phase driver causes the other phase driver to run con-
tinuously as it tries to provide the entire current require-
ment to the load. Eventually, the stressed operational
phase driver fails.
During normal operating conditions, the voltage level
on CLP_ is within the peak-to-peak voltage levels of the
PWM ramp. If one of the phases fails, the control loop
raises the CLP_ voltage above its operating range. To
determine a phase failure, the phase failure detection
circuit (Figure 9) monitors the output of the current
amplifiers (CLP1 and CLP2) and compares them to a
2.0V reference. If the voltage levels on CLP1 or CLP2
are above the reference level for more than 1250 clock
cycles, the phase failure circuit forces PGOOD low.
Overload Conditions
Average current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to 0.9V with respect to the common-mode
voltage (VCM = 0.6V) and is compared with the output
of the current-sense amplifiers (CA1 and CA2) (see
Figure 3). The current-sense amplifier’s gain of 18 limits
the maximum current in the inductor or sense resistor to
ILIMIT = 50mV/RS.
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5037As (six phases) to triple the avail-
able output current. The paralleled converters operating
at the same switching frequency but different phases
keep the capacitor ripple RMS currents to a minimum.
Three parallel MAX5037A converters deliver up to 180A
of output current. To set the phase shift of the on-board
PLL, leave PHASE unconnected for 90° of phase shift
(two paralleled converters), or connect PHASE to SGND
for 60° of phase shift (three converters in parallel).
Designate one converter as master and the remaining
converters as slaves. Connect the master and slave con-
trollers in a daisy-chain configuration as shown in Figure
10. Connect CLKOUT from the master controller to
CLKIN of the first slaved controller, and CLKOUT from
the first slaved controller to CLKIN of the second slaved
controller. Choose the appropriate phase shift for mini-
mum ripple currents at the input and output capacitors.
The master controller senses the output differential volt-
age through SENSE+ and SENSE- and generates the
DIFF voltage. Disable the voltage sensing of the slaved
controllers by leaving DIFF unconnected (floating).
Figure 11 shows a detailed typical parallel application
circuit using two MAX5037As. This circuit provides four
phases at an input voltage of 12V and an output voltage
range of 1.1V to 1.85V at 104A.
8% OF DAC
10% OF DAC
+2.0V
PHASE FAILURE DETECTION
CLP2
CLP1
DAC_OUT
DIFF PGOOD
Figure 9. Power-Good Generator
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
22 ______________________________________________________________________________________
Applications Information
Each MAX5037A circuit drives two 180° out-of-phase
channels. Parallel two or three MAX5037A circuits to
achieve four- or six-phase operation, respectively.
Figure 1 shows the typical application circuit for two-
phase operation. The design criteria for a two-phase
converter includes frequency selection, inductor value,
input/output capacitance, switching MOSFETs, sense
resistors, and the compensation network. Follow the
same procedure for the four- and six-phase converter
design, except for the input and output capacitance.
The input and output capacitance requirement varies
depending on the operating duty cycle.
The examples discussed in this data sheet pertain to a
typical VRM application with the following specifications:
VIN = +12V
VOUT = +1.1V to +1.85V
IOUT(MAX) = 52A
VCOREMAX = VID Programmed Output Voltage at No Load
AVP (∆VOUT) = 120mV
fSW = 250kHz
Peak-to-Peak Inductor Current (∆IL) = 10A
Table 2 shows a list of recommended external compo-
nents (Figure 1) and Table 3 provides component sup-
plier information.
Table 2. Component List
DESIGNATION QTY DESCRIPTION
C1, C2 2 47µF, 16V X5R input-filter capacitors, TDK C5750X5R1C476M
C3–C11 9 22µF, 16V input-filter capacitors, TDK C4532X5R1C226M
C12, C13 2 0.47µF, 16V capacitors, TDK C1608X5R1A474K
C14, C15 2 100µF, 6.3V output-filter capacitors, Murata GRM44-1X5R107K6.3
C16–C25 10 270µF, 2V output-filter capacitors, Panasonic EEFUE0D271R
C26–C30, C37 6 10µF, 6.3V output-filter capacitors, TDK C2012X5R0J106M
C31 1 4700pF, 16V X7R capacitor, Vishay-Siliconix VJ0603Y471JXJ
C32, C34, C36 3 470pF, 16V capacitors, Murata GRM1885C1H471JAB01
C33, C35, C43 3 0.01µF, 50V X7R capacitors, Murata GRM188R71H103KA01
C38 1 4.7µF, 16V X5R capacitor, Murata GRM40-034X5R475k6.3
C39 1 1.0µF, 10V Y5V capacitor, Murata GRM188F51A105
C40, C41, C42 3 0.1µF, 16V X7R capacitors, Murata GRM188R71C104KA01
D1, D2 2 Schottky diodes, ON-Semiconductor MBRS340T3
D3, D4 2 Schottky diodes, ON-Semiconductor MBR0520LT1
L1, L2 2 0.6µH, 27A inductors, Panasonic ETQP1H0R6BFX
Q1, Q3 2 Upper power MOSFETs, Vishay-Siliconix Si7860DP
Q2, Q4 2 Lower power MOSFETs, Vishay-Siliconix Si7886DP
R1, R2 4 Current-sense resistors, use two 2.70mΩ resistors in parallel, Panasonic ERJM1WSF2M7U
R3, R13 1 2.2Ω ±1% resistor
R4 1 7.5kΩ ±1% resistor
R5, R6 2 1kΩ ±1% resistors
R7 1 4.99kΩ ±1% resistor
R8, R9 2 37.4kΩ ±1% resistors
R11 1 10kΩ ±1% resistor
R12 1 10Ω ±1% resistor
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 23
CLKIN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
VCC
VIN
EAOUT
EAN
DIFF
SENSE-
SENSE+
CSP2
CSN2
CSP1
CSN1
VCC
VIN
VIN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
EAOUT
EAN
CLKIN
CSP2
CSN2
CSP1
CSN1
DIFF
VCC
VIN
VIN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
EAOUT
EAN
CLKIN
CSP2
CSN2
CSP1
CSN1
DIFF
VCC
VIN
VIN
TO OTHER MAX5037s
MAX5037A
MAX5037A
MAX5037A
LOAD
Figure 10. Parallel Configuration of Multiple MAX5037As
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
24 ______________________________________________________________________________________
MAX5037A
(MASTER)
Q4
Q3
C39
1µF
C40
0.1µF
R3
D2
Q2
D1
VIN
C8–C11
4 x 22µF
Q1
VIN
VIN = +12V
VCC
D4
D3
C41
0.1µF
C12
0.47µF
C38
4.7µF
C3–C7
5 x 22µF
L2
0.6µH
R2
1.35mΩ
L1
0.6µH
R1
1.35mΩ
23
DH1
24
LX1
25
DL1
22
BST1
27
VCC
28
VDD
32
DH2
31
LX2
30
DL2
34
BST2
CSP2CSN2PGOODPHASECLKOUTSGNDPGNDCLP2CLP1
R11
PGOOD
VCC
R6
C35
C36
R5
C33
C34
3940941365,
20,
35
29437
C42
0.1µF
C1, C2
2 x 47µF
R13
2.2Ω
C31
C32
R4
CSP1
16
CSN1
17
SENSE+
10
SENSE-
11
IN
28
CLKIN
38
PLLCMP
42
OVPOUT
8
R10
R8
R7
R9
R12C43
VIN
18 CNTR
15 REG
14 EAOUT
13 EAN
12 DIFF
6OVPIN
19 EN
4VID0
3VID1
2VID2
1VID3
44 VID4
C13
0.47µF
C14, C15,
C44, C45
2 x 100µF
C16–C25,
C57–C60
2 x 270µFC26–C30,
C37
6 x 10µF
LOAD VOUT = +1.1V TO
+1.85V AT 104A
VCC
MAX5037A
(SLAVE)
Q8
Q7
C62
1µF
C63
0.1µF
R16
D6
Q6
D5
VIN
C51–C54
4 x 22µF
Q5
VIN
D8
D7
C64
0.1µF
C55
0.47µF
C65
4.7µF
5 x 22µF
C46–C50
L4
0.6µH
R15
1.35mΩ
L3
0.6µH
R14
1.35mΩ
23
DH1
24
LX1
25
DL1
22
BST1
27
VCC
28
VDD
32
DH2
31
LX2
30
DL2
34
BST2
CSP2CSN2PGOODPHASESGNDPGNDCLP2CLP1
VCC
R19
C67
C66
R18
C68
C69
39409415, 20, 3529437
C61
0.1µF
R24
2.2Ω
C70
C71
R17
CSP1
16
CSN1
17
SENSE+
10
SENSE-
11
CLKIN
38
IN
28
PLLCMP
42
EN
19
R23
R21
R20
R22
18 CNTR
15 REG
14 EAOUT
13 EAN
12 DIFF
6OVPIN
8OVPOUT
4
VID4
3
VID3
2VID2
1
VID1
44
VID0
C56
0.47µF
VID4
VID3
VID2
VID1
VID0
DAC
INPUTS
R25
R24
Figure 11. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +1.1V to +1.85V at 104A)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 25
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancella-
tion depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
NPH ≈K/D
where K = 1, 2, or 3 and the duty cycle D = VOUT/VIN.
Choose K to make NPH an integer number. For exam-
ple, converting VIN = +12V to VOUT = +1.75V yields bet-
ter ripple cancellation in the six-phase converter than in
the four-phase converter. Ensure that the output load
justifies the greater number of components for multi-
phase conversion. Generally, limiting the maximum out-
put current to 25A per phase yields the most cost-
effective solution. The maximum ripple cancellation
occurs when NPH = K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switch-
ing MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipa-
tion in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
reducing the input/output capacitance requirement for
the same ripple performance. The lower inductance value
improves the large-signal response of the converter dur-
ing a transient load at the output. Consider all these
issues when determining the number of phases neces-
sary for the voltage regulator application.
Adaptive Voltage-Positioning Design
Procedure
The following steps outline the procedure for setting the
adaptive voltage positioning:
1) Choose the voltage-error amplifier input (EAN)
resistor RIN > 5kΩ.
2) Determine a reasonable amount of excursion from
the desired output voltage that the system can tol-
erate and use as an estimate for the voltage-posi-
tioning window, ∆VOUT (see Figures 5 and 7).
3) Calculate RFfrom equations 22 and 23. Use equa-
tion 3 to verify that ∆VOUT remains within tolerable
limits.
4) Calculate the centering resistor, RCNTR, from equa-
tion 5. RCNTR sets the center of the adaptive voltage
positioning such that at 1/2 full-load current, the
output voltage is the desired VID programmed out-
put voltage (Figure 5). Do not use values less than
24kΩfor RCNTR.
5) Choose the regulation resistor, RREG, to have the
same value as the feedback resistor, RF(RREG =
RF). RREG maintains the adaptive voltage-position-
ing window at all VID output voltage settings. Do
not use values less than 37kΩfor RREG.
Inductor Selection
The switching frequency per phase, peak-to-peak rip-
ple current in each phase, and allowable ripple at the
output determine the inductance value.
Selecting higher switching frequencies reduces the
inductance requirement, but at the cost of lower efficien-
cy. The charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs create switching
losses. The situation worsens at higher input voltages,
since switching losses are proportional to the square of
input voltage. Use 500kHz per phase for VIN = +5V,
250kHz or less per phase for VIN >+12V.
Table 3. Component Suppliers
SUPPLIER PHONE FAX WEBSITE
Murata 770-436-1300 770-436-3030 www.murata.com
ON Semiconductor 602-244-6600 602-244-3345 www.on-semi.com
Panasonic 714-373-7939 714-373-7183 www.panasonic.com
TDK 847-803-6100 847-390-4405 www.tcs.tdk.com
Vishay-Siliconix 1-800-551-6933 619-474-8920 www.vishay.com
(7)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
26 ______________________________________________________________________________________
Although lower switching frequencies per phase increase
the peak-to-peak inductor ripple current (∆IL), the ripple
cancellation in the multiphase topology reduces the RMS
ripple current of the input and output capacitor.
Use the following equation to determine the minimum
inductance value:
Choose ∆ILequal to about 40% of the output current
per phase. Since ∆ILaffects the output ripple voltage,
the inductance value may need minor adjustment after
choosing the output capacitors for full-rated efficiency.
Choose inductors from the standard high-current, sur-
face-mount inductor series available from various manu-
facturers. Particular applications may require
custom-made inductors. Use high-frequency core mate-
rial for custom inductors. High ∆ILcauses large peak-to-
peak flux excursion increasing the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance
making possible even the use of planar inductors. The
advantages of using planar magnetics include low-pro-
file design, excellent current sharing between phases
due to the tight control of parasitics, and low cost.
For example, calculate the minimum inductance at
VIN(MAX) = +13.2V, VOUT = +1.75V, ∆IL= 10A, and fSW =
250kHz:
The MAX5037A average current-mode control feature
limits the maximum peak-inductor current and prevents
the inductor from saturating. Choose an inductor with a
saturating current greater than the worst-case peak
inductor current. Use the following equation to determine
the worst-case inductor current for each phase:
where RSENSE is the sense resistor in each phase.
Switching MOSFETs
When choosing a MOSFET for voltage regulators, con-
sider the total gate charge, RDS(ON), power dissipation,
and package thermal impedance. The product of the
gate charge and on-resistance of the MOSFET is a figure
of merit, with a lower number signifying better perfor-
mance. Choose MOSFETs optimized for high-frequency
switching applications.
The average current from the MAX5037A gate-drive
output is proportional to the total capacitance it drives
from DH1, DH2, DL1, and DL2. The power dissipated in
the MAX5037A is proportional to the input voltage and
the average drive current. See the VIN, VCC, and VDD
section to determine the maximum total gate charge
allowed from all the driver outputs combined.
The gate charge and drain capacitance (CV2) loss, the
cross-conduction loss in the upper MOSFET due to
finite rise/fall time, and the I2R loss due to RMS current
in the MOSFET RDS(ON) account for the total losses in
the MOSFET. Estimate the power loss (PDMOS_) in the
high-side and low-side MOSFETs using the following
equations:
where QG, RDS(ON), tR, and tFare the upper switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively:
where D = VOUT/VIN, IDC = (IOUT -∆IL)/2 and IPK =
(IOUT +∆IL)/2.
where COSS is the MOSFET drain-to-source capaci-
tance.
IIIII
D
RMS LO DC PK DC PK−=++×
()
×−
()
22 1
3
PD Q V f
CVf RI
MOS LO G DD SW
OSS IN SW DS ON RMS LO
−
−
=××
()
+
×××
⎛
⎝
⎜
⎞
⎠
⎟+×
2
314
22
.()
IIIII
D
RMS HI DC PK DC PK−=++×
()
×
22
3
PD Q V f
VI tt f RI
MOS HI G DD SW
IN OUT R F SW DS ON RMS HI
−
−
=××
()
+
××+
()
×
⎛
⎝
⎜
⎞
⎠
⎟+×
414 2
.()
IR
I
L PEAK SENSE
L
_
.
=+
0 051
2
∆
LkH
MIN =−
()
×
××
=µ
13 2 1 75 1 75
13 2 250 10 06
.. .
..
LVVV
Vf I
MIN INMAX OUT OUT
IN SW L
=−
()
×
××
∆
(8)
(9)
(10)
(11)
(12)
(13)
(14)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 27
For example, from the typical VRM specifications in the
Applications Information section with VOUT = +1.75V,
the high-side and low-side MOSFET RMS currents are
9.9A and 24.1A, respectively. Ensure that the thermal
impedance of the MOSFET package keeps the junction
temperature at least +25°C below the absolute maxi-
mum rating. Use the following equation to calculate
maximum junction temperature:
TJ= PDMOS x θJ-A + TA
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. Increasing the number of phases increas-
es the effective switching frequency and lowers the
peak-to-average current ratio, yielding a lower input
capacitance requirement.
The input ripple comprises ∆VQ(caused by the capacitor
discharge) and ∆VESR (caused by the ESR of the capaci-
tor). Use low-ESR ceramic capacitors with high ripple-
current capability at the input. Assume the contributions
from the ESR and capacitor discharge are equal to 30%
and 70%, respectively. Calculate the input capacitance
and ESR required for a specified ripple using the follow-
ing equations:
where IOUT is the total output current of the multiphase
converter and N is the number of phases.
For example, at VOUT = 1.75V, the ESR and input
capacitance are calculated for the input peak-to-peak
ripple of 100mV or less yielding an ESR and capaci-
tance value of 1mΩand 200µF.
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple volt-
age, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
In multiphase converter design, the ripple currents from
the individual phases cancel each other and lower the
ripple current. The degree of ripple cancellation
depends on the operating duty cycle and the number of
phases. Choose the right equation from Table 4 to cal-
culate the peak-to-peak output ripple for a given duty
cycle of two-, four-, and six-phase converters. The maxi-
mum ripple cancellation occurs when NPH = K / D.
The allowable deviation of the output voltage during the
fast-transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (tRESPONSE) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
C
I
NDD
Vf
IN
OUT
QSW
=
×−
()
×
1
∆
ESR V
I
N
I
IN ESR
OUT L
=
()
+
⎛
⎝
⎜⎞
⎠
⎟
∆
∆
2
(15)
(16)
(17)
Table 4. Peak-to-Peak Output Ripple
Current Calculations
NO. OF
PHASES (N)
DUTY
CYCLE (D) (%) EQUATION FOR ∆IP-P
2< 50
2> 50
4 0 to 25
4 25 to 50
4> 50
6< 17
∆IVD
Lf
O
SW
=−
×
()12
∆IVVD
Lf
IN O
SW
=−
()
−
()
×
21
∆IVD
Lf
O
SW
=−
×
()14
∆IVDD
DLf
O
SW
=−−
×××
()()12 4 1
2
∆IVD D
DLf
O
SW
=−−
××
()( )2134
∆IVD
Lf
O
SW
=−
×
()16
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
28 ______________________________________________________________________________________
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
The average current-mode control technique of the
MAX5037A accurately limits the maximum output cur-
rent per phase. The MAX5037A senses the voltage
across the sense resistor and limits the peak inductor
current (IL-PK) accordingly. The ON cycle terminates
when the current-sense voltage reaches 45mV (min).
Use the following equation to calculate maximum cur-
rent-sense resistor value:
where PDRis the power dissipation in sense resistors.
Select 5% lower value of RSENSE to compensate for any
parasitics associated with the PC board. Also, select a
noninductive resistor with the appropriate wattage rating.
Reverse Current Limit
The MAX5037A limits the reverse current in the case that
VBUS is higher than the preset output voltage setting.
Calculate the maximum reverse current based on VCLR,
the reverse current-limit threshold, and the current-
sense resistor:
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5037A uses an
average current-mode control scheme to regulate the
output voltage (Figure 3). IPHASE1 and IPHASE2 are the
inner average current loops. The VEA output provides
the controlling voltage for these current sources. The
inner current loop absorbs the inductor pole reducing
the order of the outer voltage loop to that of a single-
pole system.
A resistive feedback network around the VEA provides
the best possible response, since there are no capaci-
tors to charge and discharge during large-signal excur-
sions. The required amount of adaptive voltage
positioning (∆VOUT) determines the VEA gain. Use the
following equation to calculate the value for RFwhen
using adaptive voltage positioning:
where GCis the current-source transconductance and
N is the number of phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid subharmonic oscillations
similar to those in peak current-mode control with insuffi-
cient slope compensation. Use the following equation to
calculate the resistor RCF:
For example, the maximum RCF is 12kΩfor RSENSE =
1.35mΩ.
RfL
VR
CF SW
OUT SENSE
≤×××
×
210
2
GR
CS
=005.
RIR
NG V
FOUT IN
C OUT
=×
××∆
IxV
R
REVERSE CLR
SENSE
=2
PD R
RSENSE
=×−
25 10 3
.
RI
N
SENSE OUT
=0 045.
CIt
V
OUT STEP RESPONSE
Q
=×
∆
ESR V
I
OUT ESR
STEP
=∆
(18)
(19)
(20)
(21)
(22)
(23)
(24)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
______________________________________________________________________________________ 29
CCF provides a low-frequency pole while RCF provides a
midband zero. Place a zero at fZto obtain a phase bump
at the crossover frequency. Place a high-frequency pole
(fP) at least a decade away from the crossover frequency
to reduce the influence of the switching noise and
achieve maximum phase margin. Use the following
equations to calculate CCF and CCFF:
PC Board Layout
Use the following guidelines to lay out the switching
voltage regulator.
1) Place the VIN, VCC, and VDD bypass capacitors
close to the MAX5037A.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative termi-
nal of the input filter capacitor.
6) Run the current-sense lines CS+ and CS- very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
7) Avoid long traces between the VDD bypass capaci-
tors, driver output of the MAX5037A, MOSFET
gates, and PGND. Minimize the loop formed by the
VDD bypass capacitors, bootstrap diode, bootstrap
capacitor, MAX5037A, and upper MOSFET gate.
8) Place the bank of output capacitors close to the load.
9) Distribute the power components evenly across the
board for proper heat dissipation.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
11) Use 4oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PC boards
can compromise efficiency since high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
Chip Information
TRANSISTOR COUNT: 5431
PROCESS: BiCMOS
CfR
CFF PCF
=×× ×
1
2π
CfR
CF ZCF
=×× ×
1
2π
VID3 1
VID2 2
VID1 3
VID0 4
SGND 5
OVPIN 6
CLP1 7
OVPOUT 8
PGOOD 9
SENSE+ 10
SENSE- 11
N.C
33
DH2
32
LX2
31
DL2
30
PGND
29
IN
28
VCC
27
VDD
26
DL1
25
LX1
24
DH1
23
VID4
44
CLP2
43
PLLCMP
42
PHASE
41
CSP2
39
CSN2
40
CLKIN
38
N.C.
37
CLKOUT
36
SGND
35
BST2
34
DIFF
12
EAN
13
EAEOUT
14
REG
15
CSP1
16
CSN1
17
CNTR
18
EN
19
SGND
20
N.C.
21
BST1
22
MAX5037A
MQFP/THIN QFN*
*CONNECT THE QFN EXPOSED PAD TO SGND GROUND PLANE.
Pin Configuration
(25)
(26)
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
30 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MQFP44.EP
S
D
11
21-0826
PACKAGE OUTLINE
44L MQFP, 1.60 LEAD FORM
MAX5037A
VRM 9.0/VRM 9.1, Dual-Phase,
Parallelable, Average-Current-Mode Controller
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
32, 44, 48L QFN.EPS
e
L
e
L
A1 A
A2
E/2
E
D/2
D
DETAIL A
D2/2
D2
b
L
k
E2/2
E2
(NE-1) X e
(ND-1) X e
e
C
L
C
L
C
L
C
L
k
DETAIL B
e
L
L1
PACKAGE OUTLINE
21-0144
2
1
E
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
PACKAGE OUTLINE
21-0144
2
2
E
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)