XR82C684 FEATURES ! "# $ % 3 (* '( .( -(% %& ' % '( %( $ 3( (" %6 $ (( % )** '(% %(% + , )(% ( -. ( ( ' % +( ' /001 /.0 1 $ )( 2 % 3( 44 )( % $ )( '( * ' %( '( 5" '6 ( (& "( )( 7 8 ' '6 -%# .8 ' '6 9 6-% : # 5;# < ' <+)= <+)= % $ >' '6 3 , + , $ !(%& ( ? ( & . 2 + % ( % . 2 + % $ ( % 3( , * % !' % 0 $ % ( ( 3( 09 :( )( '( %'( * &% & ' ( , + 3 ' < 3 + 3 ' ,& GENERAL DESCRIPTION 58 (% %& ' % '( %( (% ' ('( % (' (% * * & ( * " %& ' % ' ('( ' % ( %( , '6, (% %(, * % ( (' '%% % %&%% & % ( ( ( ( 80.0@ (' **% %( , $ % ( * ( % (' '%% *( (% /001 /.0 %1 * 00 .0 *( & * '%% %# %'( & ' % ' & &( , 5< ( >!! > (% *(' %( , ' 3 & # 3( (, * ' %(& 5+$- 0* '%% ( (, * ' 3 3 ' %( # (% '6, ( @@ ( +< .0 ( +< ORDERING INFORMATION Part No. Package Operating Temperature Range 80.0@A-@@ @@ ( +< B 80.0@A .0 ( +< B 80.0@A-@@ @@ ( +< @ 09 80.0@A .0 ( +< @ 09 XR82C684 PRINCIPLES OF OPERATION Figure 1 Figure 2 % '6 (, * 3 ( , ( .0 00 %# %'( & % ( % ( % '6 (,%# ' %(%% * * 3( , C * '( '6%7 ! )% )** ( $ (( , $ + + ( ('( % # )# # ! 8! 8! 8!) 8!) 8! 8! 8!! 8!! ; ; ; ; ; ; ; ,(%% ,(%% % ,(% % ,(% ) ,(%% ; ,(%% % ,(% % ,(% ! $+ $+B $+0 $+9 + +B +0 +9 $+ $+ + , * !' % $+ $+ + + '( ' < ,(' + $ + % + + % $ ! )% ( $ $> $> $ $ !' $ $ %% !' $ $ $=: $:: ) ! )% )** ! !B 9 E: : !=: 55: (( , ) ! )( 2 -( D -( D %'( 8-<= Figure 1. Block Diagram of the XR82C684 in the 68 Mode 8 XR82C684 8! 8! 8!) 8!) 8! 8! ; ; ; ; ; ,(%% ,(%% % ,(% 8!! ; ; ; ,(%% % ,(% 8!! ,(%% % ,(% % ,(% ) ! $+ $+B $+0 $+9 $+ + +B +0 +9 + + $+ , * !' % + '( ' < ,(' $+ $+ + $ + % + + % $ ! )% ( $ $> $> $ $ !' $ $ %% !' $ $ ) ! )% )** ! !B @ !: E: 5: 55 $5$ $5 $=: $:: (( , ) 4 ! )( 2 -( D -( D %'( 8-<= Figure 2. Block Diagram of the XR82C684 in the 88 Mode 8 8!! 8!! $5 $=: $:: + 2:! 2:! + +! +0 8! 8! $+9 $+@ $+4 $+ +4 8 8-<= 8!) 8!) +4 + 5< > > 55 +) + 8! 8! $+B $+. +9 +. +B ! ! ! !4 !@ !9 !. !B E: 5: +9 +@ +4 + 68 Pin PLCC @ $5$ 8! + 2:! +! +0) 8! 8!! $5 $=: $:: 8! +) + > 55 8!) +4 5< 8-<= 8!) 8 XR82C684 ! ! ! !4 8! !@ !9 !. !B -E: 5: 4 @ 9 8!! $+! !: $+) $+ $+0 44 Pin PLCC $+9 $+@ !: $+4 $+ $+) $+) 4 @ 9 $+0 $+! $+ $+ $5$ XR82C684 PIN DESCRIPTION Pin # 68 Pin PLCC Pin # 44 Pin PLCC Symbol Type > 4 Power Supply Pin. 5< $ Mode Select. /00 1 ' % ' & &( , (% ( 2:!F ' '( , (% ( > 3( % ' /.0 1 + Output Port 2 (General Purpose Output). (% ( ' % ' *(, * '( % / %( ." " ' '61 # / '( 8 ' '61 Output 3 (Active low). , % , % # / ) %( " ' '61 # / ) '( " ' '61 # ( / -( &1 8G.8 8G8 8G8 @ Description +4 8)G8 8)G8 -GG!H 9 4 8!) Transmitter Serial Data Output (Channel B). % %(, (*(' ( * '' (% %( *(% (% (% ( /(,1 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% %'(*(# 8)# %( (% %(* * %( (* ,(% * ( , , * (% ' '6 . @ 8!) $ Receiver Serial Data Input (Channel B). % %(, (*(' ( * '' (% '( *(% $* " '( ' '6# 8)# (% %'(*(# %( ( (% % (%( , , * (% ' '6 B 9 8-<= $ Crystal Output or External Clock Input. (% ( (% ' '( * %( * '&% ''( , 3 ( %'( (% % $* %'( (% %# " ' '6 %(, % % ( (% ( $ * 80.0@ (' * '( &# % % % & %(, 3( *I '(% 3 ;J 0 ;J (% I( ' & ( '&% %'( & " <' ( ' '6 %(, 0 . 8 $ Crystal Input. '( * %( * '&% %( * 8-<= $* %'( (% %# ''( % % ' ' * (% ( , (% ( % * (* " ' '6 (% % ( 8-<= ( +@ Output 4 (General Purpose Output). (% ( ' % ' *(, * '( % '( 3 /'(&-$ 1 ( (' * 8!H- < $ >' , (% ( % $* %%% != ( , E$5 '&' # ( (% ( * ( , + # %# % ' ( % ** * (' $5 00 Interrupt Enable Output (Z Mode; Active High). (% ( (% & /(,1 ; 3# ( * * 3( , 3 ' (( % ' '% (% ( , ,, / 31 $* $5$ $ 5 $ ( (% / 31 $* $5 (% / 31 '% * $5$ ( # $5 3( ,, /(,1 ' $5$ ( % ,, /(,1 % (%% $ I% + $: ( (% ,, / 31 $* $5 (% / 31 '% % I% $ # $5 3( ( / 31# , $ (' ( # ( + % ( 6 /55 $ 1 4 $=: $ .0 ? B Interrupt Acknowledge (Active Low). (% ( (% + K% % % ( I% (%% & (' E + %%% (% ( # ( ( ('% K% ( I% (% %('# & " % '&' 3( ( '6 3 , $= '&' 3( % + K% ( '6 3 , %(, & '( , ' % * $ >' ,(% $> % ! !B XR82C684 Pin # 68 Pin PLCC Pin # 44 Pin PLCC Symbol Type Description 4 $:: Interrupt Request Output (Active Low, Open-Drain). $: (% %% '' ' * * '(K% %6 ( ( , ' (( % (% %(, 3( ( %% , $ (' ( 3( , ' ' (( % '%( , $ I% % (( 4 + Output 11 (General Purpose Output). (% ( ' % ' *(, * '( % / ! %( 8 ' '61 8!G8# / ! '( 8 ' '61 # '( 3 / -( D &1 -GG!H Output 10 (General Purpose Output). (% ( ' ' *(, * '( % / %( 8 .8 ' '61 F % / '( ' '61 8!G8 8!G8 -GG!H 44 4 2:! 4@ 2:! 49 + 8G8 8G.8 8G8 4. @ + ! Output 9 (General Purpose Output). (% ( ' ' *(, * '( % '( 3# ( / !# I% 1 ! 4B 9 +0 Output 8 (General Purpose Output). (% ( ' ' *(, * '( % '( 3# ( / I% 1 40 . 8! Transmitter Serial Data Output (Channel D). % %(, (*(' ( * '' (% %( *(% (% (% ( (, 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% %'(*(# 8!# %( (% %(* * %( (* ,(% * ( , , * (% ' '6 4 B 8! $ Receive Serial Data Input (Channel D). % %(, (*(' ( (% '( *(% $* " '( ' '6 (% %'(*(# (% % (%( , , * ' '6 @ $+9 $ Input 15 (General Purpose Input). @ $+@ $ Input 14 (General Purpose Input). (% ( ( ' % ' *(, * '( % " ' '6 ( * '( * ! 8!G58 $ Input 13 (General Purpose Input). (% ( ( ' % ' *(, * '( % " ' '6 ( * %( * ! 8!G58 $ Input 12 (General Purpose Input). (% ( ( ' % ' *(, * '( % " ' '6 ( * '( * 8G58 8!G58 @ $+4 8!G58 @4 $+ 8G58 0 XR82C684 Pin # 68 Pin PLCC Pin # 44 Pin PLCC @@ 0 Symbol Type Description $5$ $ Interrupt Enable Input (Z-Mode; Active High). $* (% '((, ( (% ,(' /(,1# (% ' * , ( , %6 $ I%% + $* (% ( (% ,(' / 31# (% ( (( * , ( , & $ I%% + ? Note: if the user is operating this device in the "68 Mode" or in the "88 I-Mode," then this pin should be tied to VCC . @9 $+ $ Input 11 (General Purpose Input). (% ( ( ' % ' *(, * '( % " ' '6 ( * %( * 8G58 $ Input 10 (General Purpose Input). (% ( ( ' ' *(, * '( % " ' '6 ( * -( D $ Input 9 (General Purpose Input). (% ( ( ' ' *(, * '( % '( 3# / ! 1 ( ! $ Input 8 (General Purpose Input). (% ( ( ' ' *(, * '( % '( 3# / 1 ( 8G58 @. $+ G58 @B $+ ! @0 4 $+0 @ 4 9 $ MSB of Address Input.(% ( # , 3( %% ( %# 9 % % ' '( ,(%% 3(( (' ( , 3( ( % 3( + 9 4 @ $ Address Input. 9 44 4 $ Address Input. 9 4@ $ Address Input. 94 49 $ LSB of Address Input. 9@ 4. $+ $ Input 0 (General Purpose Input). (% ( ' ' *(, * '( % '( 3 / 1 ( * $ Input 1 (General Purpose Input). (% ( ' ' *(, * '( % '( 3 / 1 ( * ) ) $ Input 2 (General Purpose Input). (% ( ' ' *(, * '( % " ' '6 ( * -( D $ Input 3 (General Purpose Input). (% ( ' ' *(, * '( % " ' '6 ( * %( 99 4B $+ ) 9. $+ G58 9B $+4 8G58 90 40 ! Read Strobe ("88 Mode"; Active Low). / 31 (% ( 3( (% % / 31 '% ' % * %% ,(%# ! )% 00 Note: $* % (% ( , (% (' ( /.0 1 (% ( % ( > 9 $+@ $ 8G58 Input 4 (General Purpose Input). (% ( ' ' *(, * '( % " ' '6 ( * '( XR82C684 Pin # 68 Pin PLCC Pin # 44 Pin PLCC . Symbol Type Description $+9 $ Input 5 (General Purpose Input). (% ( ' ' *(, * '( % " ' '6 ( * ) %( $ Input 6 (General Purpose Input). (% ( ' ' *(, * '( % " ' '6 ( * ) '( $+B $ Input 7 (General Purpose Input). 8)G58 . $+. 8)G58 . .4 4 8! $ Reveive Serial Data Input (Channel A). % %(, (*(' ( * '' (% '( *(% $* " '( ' '6# 8# (% %'(*(# (% % (%( , , * (% ' '6 .@ @ 8! Transmitter Serial Data Output (Channel A). % %(, (*(' ( * '' (% %( *(% (% (% ( (, 6( , % 3 %( (% ( # (% # 3 ' (% ( , ( ' <+)= $* " %( ' '6 (% %'(*(# 8# %( (% %(* * %( (* ,(% * ( , , * (% ' '6 .9 @ + Output 0 (General Purpose Output). (% ( ' % ' *(, * '( % '( 3# ( I% * Output 1 (General Purpose Output). (% ( ' % ' *(, * '( % '( 3# ( I% * ) ) $ Master Reset (Active High for the "88 Mode", and Active Low for the "68 Mode"). %%( , (% ( ' % * 3( , ( ,(%%7 # $ # $ # + # + # ( (( (J% $> # % % * -(%# % + +9 ( (, %# '% * %( ' % ( ( '( % 3( 8!# 8!)# 8!# 8!! 6( , (, .. @ + ) .B @4 55 .0 @@ > XR82C684 DC ELECTRICAL CHARACTERISTICS 1, 2 Test Conditions: L 9# > L 9> 9M %% 3(% %'(*( Symbol Parameter Min. Typ. Max. Unit Conditions >$< $ < 3 > , 9 0 > >$; $ ;(, > , > > $ ;(, > , 8-<= @ > > @ > $< L @ > $; L @* >$;8 >< < 3 > , >; ;(, > , @ $ <6, 9 9 * >$: L > ' +( <6, 4 4 * >$: L > * >$: L $$< $$<5< $8< 8 $ < 3 $8< 8 $ < 3 B $8$; 8 $ ;(, * >$: L > $8; 8 $ ;(, * >$: L > $<< ! )% ( <6, * > L > $ !( <6, * > L > $ + 3 & 4 . 9 '( $ + 3 & 4 4 & Notes 1 Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V CC = 5V and typical processing parameters. 2 All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See NO TAG. 3 Measured operating with a 3.6864 MHz crystal and with all outputs open. 4 The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK period if either channel's Receiver is operating in external 1X clock mode. XR82C684 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 Test Conditions: L 9# > L 9> 9M %% 3(% %'(*( Symbol Parameter Min. Typ. Max. Unit Conditions Reset Timing (See Figure 56) 5 55 + % E( *% XR82C684 Read and Write Cycle Timing - 88 Mode (Figure 57) 7 @ ( !# E < 3 % ; @ ; ( * !# E < 3 % ( !# E < 3 % ; ; ( * !# E ;(, % E !# E + % E( 9 % !! ! > ( * ! < 3 ! ! )% ( , * ! ;(, ! ! ( E ;(, !; ! ; ( * E ;(, E! ;(, ( 3 % E(% 0# . B9 % % % 9 % % Z-Mode Interrupt Cycle Timing (Figure 58) !$ $5 ! & ( * $5$ $ $= ( ! < 3 : % $; $= ; ( * ! ;(, % 5$ $5$ ( ! < 3 9 % 5! $5 ! & ( * $: < 3 % % XR82C684 Read, Write and Interrupt Cycle Timing -68 Mode (Figure 59, Figure 60 and Figure 61) 9 ( < 3 % ; 9 ; ( * ;(, % E -E ( < 3 % E; -E ( * ;(, % % % # E ;(, + % E( ! $= ;(, * != < 3 !! ! > ( * $= < 3 ! ! )% ( , * $= ;(, ! ! ( < 3 % !; ! ; ( * < 3 9 % !< != < 3 * ! > ( % B9 % % XR82C684 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT'D) Symbol Parameter Min. Typ. Max. Unit Conditions XR82C684 Read, Write and Interrupt Cycle Timing -68 Mode (Figure 59, Figure 60 and Figure 61) (Cont'd) !; != ;(, * $= ;(, % ! != ;(, $ ' * $= ;(, 9 % Port Timing - XR82C684 (Figure 62) 7 + + $ ( ! < 3 % +; + $ ; ( * ! ;(, % +! + > ( * E- ;(, @ % 4 % 4 % Interrupt Output Timing - XR82C684 (Figure 63) $ $: +4 +B 3 % % $ % ;(, * 7 * $ % % )(% ( $ $+ * $ %6 ( $ Clock Timing (Figure 64) <= 8-<= 5" ;(, < 3 ( <= 8-<= &% 5" I '& -( 5" '6 ;(, < 3 ( $+ -( 5" '6 I '& 8 8 8 5" ;(, < 3 ( *8 8 8 5" I '& .8 8 % 4.0@ B4B ;J % B4B ;J % . ;J ;J Transmitter Timing (Figure 65) 8! 8! ! & 8 5" < 3 49 % 8! ! & 8 $ 9 % 4 XR82C684 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT'D) Symbol Parameter Min. Typ. Max. Unit Conditions Receiver Timing XR82C684 (Figure 66) 8 8! ! ( 8 5" ;(, @ % 8; 8! ! ; ( * 8 5" ;(, % Notes 1 Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V CC = 5V and typical processing parameters. 2 All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20 ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 50. 3 AC test conditions for outputs: CL = 50 pF, RL = 2.7 kohm to V . CC 4 If -CS is used as the strobing input, this parameter defines the minimum high time between -CSs. 5 Consecutive write operations to the same register require at least three edges of the X1 clock between writes. 6 This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. A higher 68000 clock can be used if this is not the case. 7 This specification imposes a lower bound on -CS and -IACK low, guaranteeing that they will be low for at least one CLK period. 8 This parameter is specified only to insure that -DTACK is asserted with respect to the rising edge of X1/CLK as shown in the timing diagram, not to guarantee operation of the part. If the specified setup time is violated, -DTACK may be asserted as shown or may be asserted one clock cycle later. 9 The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK period if either channel's Receiver is operating in external 1X clock mode. ABSOLUTE MAXIMUM RATINGS1 ! & > , B> , .9 9 > ,% 3( %' 2 9> NB> Notes 1 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the "Electrical Characteristics" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. @ XR82C684 SYSTEM DESCRIPTION 80.0@ ' %(%% * * ( # * " ' ('( ' %F ' ' %(%( , * ( 3 %( '( 5' ' * & ( & , * ( , * ' ( *' 3( , * '%% % 3( ( ( * ' % ( , % * ' '( %( & % ' * * 44 ( & , *(" ( %# * ' '6 ( * ( ' -(# * " & % ( " ." ' '6 ( , % ' * 44 (** *(" ( % ' (' & * '&% ' ' ' %% 3 ( % * " ' '6 ( (& ( & , ( , % * '( %( * ' ' 6% '( * % ( % ' ('( % %' % ' % ( %&%% B. OPERATION CONTROL BLOCK ' ,(' * ( '6 '(% ( , ' % * + , % %(, % ( % %'( % * ( ) '6 * '( % % % ( *' % * (' '(*(' &# ( (% % %( * ,(% %% !' ( ,# !' ( , * ' % % %# (&# ' ('( ' %# % % -( ( , /%% ,(%1 ( ' ('( * ' % , , ( ) '6 ( ) '6 3( ' * ' % * 3( , ( %(, %# ( , 3 ( (% ( ( /.01 /00 17 '( %( I ** ( '( $% ( ( ((J (%6 * '( ' ( ( ( ('( % % (% * 3 ' '( (& ( (( %(%%( * (' 3 ** * '(( , (% * # % ( , %% * 68 Mode 88 Mode %% $ %# 9 %% $ %# @ E ! E 55 55 % (% 3 , % .( ' -( 3(' & % % % , ( , %# . ( ( % ( ( % . ( ( % ( % /.0 1 % ( ' % %* '6 3 , != 3(' (% %% ( , 3( '&' % ( ( * + I% ( % ' %% != %(, ( ('% ( % ' ( , 3( '&' # I% (% % ( , '&' # ( ' (% % ( , ( '6 3 , '&' A. DATA BUS BUFFER E ( *'( , .0 *( & '%% # % ' *(, ( /00 1 (( &# 3( I( % , ,(' ( & ( *' .0 ( & Figure 3 % % %'(' * '%% ( , ,(' '('(& % ** (% ( *' 3 ( 3(( '( " %% $ (% ' & ( ' '6 3 %*% 6 ' 3 % + 9 XR82C684 -E E 5 ' '6 ! 55 55 Figure 3. External Logic Circuitry Required To Interface a 6800 Family Processor to an "88-Mode" XR82C684 Device B.1 Quart Register Addressing %%( , * ( ,(%% * (% % ( Table 1 Please note that some of the registers are "Read Only" and others are "Write Only". Each channel is provided with the following dedicated (addressable) registers. %6 $ % ,(% % O ! ,(%% "( (& ,(% % O ! $ >' ,(% % O ) $ >' ,(% % O ! "( (& ,(% % O ) ,(%% % ,(%% *( &# % ' ( % ,(%% % * '( % %( ' ('( # %' % % %-(% '6 ' ,(%% '( ; ( , ,(% ; %( ; ( , ,(% ; + + ,(% + + ,(% (( &# ' ( % * 3( , ,(%% % -' ' (% $+ $ + *(,( ,(% $ % ,(% % O ) $+ $ + *(,( ,(% $ % ,(% % O ! -( )& ,(% $ %6 ,(% % O ) -( )& ,(% $ %6 ,(% % O ! < -( < 3 )& ,(% %6 $ % ,(% % O ) < -( < 3 )& ,(% . XR82C684 Read Mode Registers Address (Hex) Register Name Write Mode Registers Symbol Register Name ,(%# Symbol ,(%# # % ,(%# %6 $ % ,(% $ ,(% 4 " ; ( , ,(%# ; " ; ( , ,(%# ; @ $ + , ,(% $+ "( (& ,(% 9 $ % ,(% $ $ %6 ,(% $ . -( )& ,(% B -( < 3 )& ,(% < 0 ,(%# ) )# ) % ,(%# ) ) 55>5! ) " ; ( , ,(%# ) $ >' ,(% ! $ + 5 -( + )(% +) -( + )(% +) ,(% # % ,(% %6 $ % ,(% $ ,(% 4 " ; ( , ,(% ; " ; ( , ,(% ; @ $ + , ,(% $+ "( (& ,(% 9 $ % ,(% $ $ %6 ,(% $ . -( # )& ,(% -( # )& ,(% B -( # < 3 )& ,(% < -( # < 3 )& ,(% < 0 ,(% ! !# ! ,(% ! !# ! % ,(% ! ! % ,(% ! ! 55>5! ,(% ! ! ) " ; ( , ,(% ! ;! " ; ( , ,(% ! ;! $ >' ,(% $ >' ,(% $> ! $ + 5 -( + )(% +) -( + )(% +) '6 ' ,(%# -( )& ,(% -( < 3 )& ,(% ,(%# ) '6 ' ,(%# ) # < )# ) ) ,(%# ) ) ;) " ; ( , ,(%# ) ;) $ >' ,(% $> $> $+ $> $+ + *(,( ,(% + +B ,(% '6 ' ,(% + *(,( ,(% +0 +9 Note: The shaded blocks are not Read/Write registers but are rather "Address-Triggered" Commands. Table 1. Quart Port And Register Addressing B + # + XR82C684 Table 1 ( ('% ' ' (% I( 3( 3 ,(%% %% '( 3( ' * % ,(% (% (% / ,(%1 ( ( '(-%&% 3 55 ' ( (% / ( ( , 1 ' ,(% Please note that the suffix "n" is used at the end of many of the QUART registers symbols in order to refer, generically, to any one of the four channels ; 3# ' % * ( 3( %(* * %% * ,(% * ,(%# (( & * 3( , & E( ''%% ,(% ( 3( ' ( / ( 1 ,(% ( 3 % ''% ( /55 +$:51 ' % ( 6 /55 +$:51 ' ' (%% & 3(( , ( ( ' K% ,(% * # ,(%%# 3(( ,( ' # % ,(' %% *% * '( % * ' & ,(%% (%'%% ( ( ( Section G.3 B.2 Command Decoding 5' ' (% I( 3( ,(% $ , # * % ,(%% -(% %(# -(% '(# , 3( *'( (( , %(% * (%' % ' '( ' % ( * * ' ,(% (% % 3 CRA, CRB, CRC, CRD Bit 6 Bit 7 Bit 5 Bit 4 Bit 3 Miscellaneous Commands 3( , " Bit 2 Enable/Disable Receiver Bit 1 Bit 0 Enable/Disable Transmitter L : , L : , L 5 " L 5 " L !(% " L !(% " L : ( % L : > ( ! % * '( * 3 ( * ,(%% (% *( & %(,* 3 (% ( (% % ( (% %( - '( *( % ' % %% '( 3( ( * ,(%% Please note that the upper nibble commands 116 through B effects only the performance of Command Register's Channel. However, commands C and D effects system (or chip) level operation. ( * ,(% (% % ( 6 %(% * (%' % ' % Table 2 Bit 7 Bit 6 Bit 5 Bit 4 Null Command: Description Reset MRn Pointer: %% K% ( ( Reset Receiver: % ( (( ' '( % (* ;3 % % ( '( (% (% $ (% * % Reset Transmitter: %% ( (( ' %( % (* ;3 % ( 8! (% * ' (, Reset Error Status: % '( )6 )# +(& 5 +5# ( , 5 5 5 5 %% (%# PB74Q '(*(' &# (* 5 # * (' ' (% % /) '61 5 # (% ' 3( % * '( 5 $ (' % ( % ,(% $ ) '6 5 # ' ( +5# 5# 5# ) ''%# 3( ' ( * ,, ( % ,(%# ( (% ' (% (%% $* 5 # * (' ' (% % /' 5 1# ' % * % ,(% * +5# 5# ) * ' '' & '' %(% $ /' 5 1# % * % ( (' % (% % & '' (% * ; : 7 5 ( (' (% 3&% % % /) '6 5 1 ( (' # I(% (% ' % Reset Break Change Interrupt: % ' K% 6 ' , ( %% (# 3(( ( $ % ,(% 0 XR82C684 Bit 7 Bit 6 Bit 5 Bit 4 Description Start Break: '% 8! 3 %( % % 6 $* %( (% &# % * 6 & & 3 ( (% $* %( (% '(# 6 ,( % 3 %(%%( * % ''% ( ; (% ' # (J# 85+ % * 6 3( ,( Stop Break: 8! ( 3( , (, 3(( 3 ( (% 8! 3( ( (, * ( ( * " ''# (* &# (% %( Set Rx BRG Select Extend Bit: % ' K% /'( )2 ' 5" )(1 Clear Rx BRG Select Extend Bit: % ' K% /'( )2 ' 5" )(1 Set Tx BRG Select Extend Bit: % ' K% / %( )2 ' 5" )(1 Clear Tx BRG Select Extend Bit: % ' K% / %( )2 ' 5" )(1 Set Standby Mode (Channel A): E (% ' (% ( 6 ( ,(%# 3 (% * ' * %(%# '(%# ' -( (( '('(% ' ( % & 3 3 Please note that this command effects the operation of the entire chip. Normal operation is restored by a hardware reset or by invoking the "SET ACTIVE MODE" command. Reset IUS Latch (Channel B): E (% ' (% ( 6 ( ) ,(%# (% ( , ( ? # ( '%% $ (' $ ' % (%# ( # 3( '% $5 ,, /(,1 Select Direct System Clock (Channel C): 3( , 3 55# ( ( 6( , (% ' # (% ( , ( /!(( &% '61 '(*(' &# (% % %'( ' '6 *I '& (% (( & 3 # ( ( , , ( * (( , ) '6 $* % ( /!(( &%% '61 # '( * * ' % 3( * * % ( Table 15 Table 15A $* % ( 6% (% ' ( ,(%# (% /!((&1 3 6 (% * /(( , %(, 1 # % 3( '( %# %'(*( ( Table 15 Table 15A Set Active Mode (Channel A): E (% ' (% ( 6 ( ,(%# (% * & %% ( Set Z-Mode (Channel B): E (% ' (% ( 6 ( ) ,(%# (% ' (( ( ? ( (%'%%( * K% ( 3( ( ? # + % % Section C.6.2 ( * 00 & Select Divided System Clock (Channel C): (% ' (% % * / ' !(' &%% '6 1 ' (% ' 3( /(( & 1 3 6 ( )2 (( , %(, **' * (% ' (% ' & * * % ( Table 15 Table 15A Please note that this command effects the baud rates for all four channels of the QUART. Reserved Reserved Table 2. Miscellaneous Commands, Upper Nibble of All Command Registers, Unless Otherwise Specified XR82C684 $ (( ' % 3(' ( , ' ,(%%# % **% /%%(,,1 /' % % ' % (% ( Table 1# / + ,(% %%( ,#1 * ( (*( & ( , /%1 ( (% '(*(' &# % ' % 7 + +B ' % * ( (( (% 3(( + <(63(%# % * ( % +0 +9 ' % * ( (( (% 3( + ; '# (* +PQ ,# ( 3(( + (% % /1# % * ' % ( , ( # +# (% 3 % ,(' /1 %I &# ' ( 6 * / + )(%1 ' % / + +( %1 ' ( (%'%%( ( ( * + %# % % Section F -( -( -( -( C. Interrupt Control Block + )(% $ ) '6 3% % & ( /$ !( 1 ( ( ' % '( 3# ( ( I% %(, $:# 3(' & , %% '' ' * & * * 3( , %7 + )(% + )(% + )(% 5' ' (% ( 6 & ( ( , 3(( , (% ' % ( , %%# % %'(*( ( Table 1 %( ; ,(% # )# # ! & '( ; ,(% # )# # ! & " # -( (% ( 6 & ' * ( , %% 5. Please note that this "Read Operation" will not result in placing the contents of a QUART register on the data bus. The only thing that will happen, in response to this procedure is the Counter/Timer #1 will initiate counting. For a detailed discussion into the operation of the Counter/Timers, please see Section D.2. '( $ # )# ! 5 * '( )6 ( % # )# ! 5 * -( ' * ( -( -( , * ( ( %# $+# $+# $+# $+4# $+0# $+# $+# $+ " * %%(,, ' % (% / + )(% 1 (% ' (% ( 6 & * ( , 3( * %% 5. E % ( 6% (% ' # -% (% %( , '( (% /1 3(( + + ,(% (%# 3(( + %'(*( %# ' , % * ( %# Register $ ) '6 ' %(%% * 3 $ % ,(%% $ $# 3 $ %6 ,(%% $ $# 3 %6 $ % ,(%% $ $ 3 $ >' ,(%% $> $> Table 3 (%% % ,(%% ( %% '( 3(( Address Location (in QUART Address Space) Description $ $ % ,(% 9. & $ $ % ,(% 9. & $ $ %6 ,(% 9. E( & $ $ %6 ,(% 9. E( & $ %6 $ % ,(% . & $ %6 $ % ,(% . & $> $ >' ,(% . $> $ >' ,(% . Table 3. Listing and Brief Description of Interrupt System Registers XR82C684 % *( 37 * ' ' (( % (% ''( , $ , # ' % * $ 3( ( (' '%% # % ' % * $ I% * * # & ( %(' ( * % ,( & ( , ( % ,(%% $% %6 $ % ,(%% (* * 3 $% % 37 * % ,(%% C.1 Interrupt Status Registers (ISR1 and ISR2) ' % * $% ( ('% %% * ( ( ' (( % $* & (% 3(( % ,(%% ,, /(,1# ' % ( , ISR1 Register Bit Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Port Change Delta Break B RXRDY/ FFULLB TXRDYB Counter #1 Ready Delta Break A RXRDY/ FFULLA TXRDYA L: L: L: L: L: L: L: L: L H% L H% L H% L H% L H% L H% L H% L H% ISR2 Register Bit Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Port Change Delta Break D RXRDY/ FFULL D TXRDY D Counter #2 Ready Delta Break C RXRDY/ FFULL C TXRDY C L: L: L: L: L: L: L: L: L H% L H% L H% L H% L H% L H% L H% L H% *( (( * ( , ( ' * % (% (% % 3 ISR1[6] Delta Break Indicator - Channel B: E (% ( (% %# ( ( ('% ) '( % ' ,( ( , * '( 6 ) (% ( (% ' % 3 + ( 6% ' ) /55 )5= ;:25 $:5 +1 ' % Table 2 ( * ( ( K% % % )5= ' (( # % % Section G.2 C.1.1 ISR1 Register - Channels A and B ISR1[7]: Input Port Change of State: $* (% ( (% ,(' /1# ' , * % 3% ' $ + ( % $+ $+4 % %('% (% ( & ( , $+ (* $PBQ L $PBQ (% ' 3 + % $ + *(,( ,(% D $+ )& ( , $+# % 3( ( 7 ISR1[5] RXRDY/FFULL B - Channel B Receiver Ready or FIFO Full * '( * (% ( (% % ' & ,( , )P.Q $* (% ( *( (% ' *(, * '( % '( & ( (' 8!H)# /1 ( (% (*( ( ('% % '' * (% ( ;) (% & & + (% ( (% % 3 '' (% %* * '( %(* ,(% ;) (% ' 3 + % ;) $* %( ''% ( ;) * ( # ( 3( % ,( * ;) (% / 1 $ + ( ' , % *( % * ( ( %# * 3( , , * ( %'(( Section E * $+# % % Please note that in order to enable this Interrupt Condition, the user must do two things: 1. Write the appropriate data to the lower nibble of the Auxiliary Control Register, ACR1[3:0]. In this step, the user is specifying which of the four Input Pins, IP0 - IP3, should trigger an "Input Port Change" Interrupt request. $* (% ( (% ' *(, * '( % /$ 1 $ (' <<)# ( (% % 3 '' (% %* * ;) %* '%% ;) ' * (% ( (% ' 3 + % ;)F & / ( ,1 $# 2. Write a logic "1" to IMR1[7]. XR82C684 6( , * " '' $* '' (% 3(( , ( '% ;) (% * # (% ( 3( % ,( * ( # 3 '' (% ( ;) ISR1[1] RXRDYA/FFULL A - Channel A Receiver Ready or FIFO Full * '( * (% ( (% % ' & ,( , P.Q $* (% ( *( (% ' *(, * '( % /'( &1 ( (' 8!H# /1 ( (% ( *( ( ('% (% % '' * ( ;# (% & & + (% ( (% % 3 '' (% %* * ; (% ' 3 + % / %1 ; $* %( ''% ( ;# * 3( , ( # ( 3( % ,( * ; (% / 1 Note: If this bit is configured to reflect the FFULLB indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRB, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. ISR1[4] TXRDYB - Channel B Transmitter Ready $* (% ( (% ' *(, * '( % $ ; * ( (' <<# ( (% % 3 '' (% %* * ; 3 & %* '' '%% ; ' * (% ( (% ' 3 + % ; $* '' (% 3(( , ( '% ; (% * # (% ( 3( % ,( # * 3( , ( # 3 '' (% ( ; (% ( (% (' * 8!H )# )PQ (% (# 3 %# ( ('% ;) (% & (% & '' '' * + ( (% ' 3 + 3(% 3 '' ;)F (% % ,( # 3 '' (% %* 8!H) (% % 3 %( (% ( (( & (% ' 3 %( (% (% '% ( ;) 3( %( (% (% 3( %( Note: If this bit is configured to reflect the FFULLA indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRA, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. Therefore, the user is advised to read RHRA until empty. ISR1[3] Counter #1 Ready $ $5 # - D -( D 3( % $P4Q ' * ' '&' * % %I 3 3(' (% ( +4 ( $P4Q 3( ' & ( 6( , %%(,, /+ :5 1 ' ) ( ( # ( $5 # /+ :51 ' 3( % - ISR1[0]: Channel A Transmitter Ready (% ( (% (' * 8!H # PQ (% (# 3 %# ( ('% ; (% & (% & '' '' * + ( (% ' 3 + 3(% 3 '' ;F (% % ,( # 3 '' (% %* 8!H (% % 3 %( (% ( (( & (% ' 3 %( (% (% '% ( ; 3( %( (% (% 3( %( $ :5 # (% ( (% % 3 ' D '% ( ' (% ' 3 ' (% % & /+ :51 ' E -( (% ( :5 # /+ :51 ' 3( % -( ( (%'%%( ( * -(% ' * ( Section D C.1.2 ISR2 Register - Channels C and D ISR1[2]: Delta Break A - Channel A Change in Break ISR2[7]: Input Port Change of State: $* (% ( (% ,(' /1# ' , * % 3% ' $ + ( % $+0 $+ % %('% (% ( & ( , $+ (* $PBQ L $PBQ (% ' 3 + % $ + *(,( ,(% $+ )& ( , $+# % 3( ( 7 %%( * (% ( ( ('% ' '( % ' ,( ( , * * '( 6 ) (% ( (% ' 3 + ( 6% ' /55 )5= ;:25 $:5 +1 ' ( * ( ( K% % % )5= ' (( # % % Section G.2 ( (( $ + ( ' , % XR82C684 *( % * ( ( %# * 3( , , * possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. ( %'(( * $+# % % Section E ISR2[4] TXRDYD - Channel D Transmitter Ready Please note that in order to enable this Interrupt Condition, the user must do two things: (% ( (% (' * 8!H !# !PQ (% (# 3 %# ( ('% ;! (% & (% & '' '' * + ( (% ' 3 + 3(% 3 '' ;!F (% % ,( # 3 '' (% %* 8!H! (% % 3 %( (% ( (( & (% ' 3 %( (% (% '% ( ;! 3( %( (% (% 3( %( 1. Write the appropriate data to the lower nibble of the Auxiliary Control Register, ACR2[3:0]. In this step, the user is specifying which of the four Input Pins (IP8 IP11) should trigger an "Input Port Change" Interrupt request. 2. Write a logic "1" to IMR2[7]. ISR2[6] Delta Break Indicator - Channel D: ISR2[3] Counter # 2 Ready E (% ( (% %# ( ( ('% ! '( % ' ,( ( , * '( 6 ) (% ( (% ' % 3 + ( 6% ' ! /% )6 , $ 1 ' % Table 2 ( * ( ( K% % % 6 ' (( # % % Section G.2 $ $5 # -D -( D 3( % $P4Q ' * ' '&' * % %I 3 3(' (% ( + ( $P4Q 3( ' & ( 6( , %%(,, / 1 ' ) ( ( # ( $5 # /+ :51 ' 3( % - $ :5 # (% ( (% % 3 ' '% ( ' (% ' 3 ' (% % & /+ :51 ' E -( (% ( :5 # /+ :51 ' 3( % -( ( (%'%%( ( * -( ' * ( Section D ISR2[5] RXRDY/FFULL D - Channel D Receiver Ready or FIFO Full * '( * (% ( (% % ' & ,( , !P.Q $* (% ( *( (% ' *(, * '( % /'( &1 ( (' 8!H!# /1 ( (% ( *( ( ('% % '' * (% ( ;) (% & & + (% ( (% % 3 '' (% %* * '( %(* ,(% ;! (% ' 3 + % ;! $* %( ''% ( ;! * ( # ( 3( % ,( * ;! (% / 1 ISR2[2]: Delta Break C - Channel C Change in Break %%( * (% ( ( ('% ' '( % ' ,( ( , * * '( 6 ) (% ( (% ' 3 + ( 6% ' /% )6 , $ 1 ' ( * ( ( K% % % )5= ' (( # % % Section G.2 $* (% ( (% ' *(, * '( % /$ 1 ( (' <% $> $> %# & + !( , ( # ' % * ' * $>% '( % ( &# 3 ( ( %(' ( % * ( ( , %(% C.4 Interrupt Vector Registers, IVR1 and IVR2 % ,(%% & % * $ >' , ( 3 (% ( , ( /.0 1 % ' ( %'( ? %% * /00 1 E( ( * % %# ' % * $> (% &(' & %( , %% * K% $ (' ( 3(%# ( $ # $ >' , ( (% &(' & * **'( E (% ( , ( $ # $>% ' % % , % -3( ,(%% * $>%# 3( (% ( , ( .0 ? (% % ( %'( . * # ( ' ( ('( %# ' % * $>% '' (% 3 ( ,%7 $ (*& ( ' % I%( , ( 3 + ( '( *F ' , ' '( # ( , &# ' ( % ( $ (' ( * ( ( , , * %( , />' $ 1 '%%( , / ( 1 '%%( , (% %(, (*(' ( ('((' ('( % %( , & ( % ('% $ / ( 1 '%%( ,# '( * $ I%# (' '%% 3( , , ' & ( (' ( ( (' '%( , ( & * (% ( , ' (% ' ' (' '%% ' , ' ( ( %(' ( ( I( ' * % ( ('% % ( '& ( 3(' 3 '' ( , ' ( '%%( , C.5 Limitations of the QUART Interrupt Structure $ ' ** & 3% % , , ( % ( % % '( ; ; $ ' (( %F -( & ' (( # ' ,% ( )6 (( '( ; 3# %( * /! )6 (( 1 )# % , ( % '( % %' % +(& 5 +5# '( 5 5# ( , 5 5 % % ** % ( (& ' *(, * % & '' ' * & * % % ' (( % * # %% % (% ( % % * /! <( 6 <&1 ''6( , %' %' % # % (% (% / (1 '( & *I & ( , % ,(%F ''6( , * & J ( % (% (% %'( & '% (* % % % 5 /'1 P9Q L %I &# ( , ( (( (J( * # % 3( ' * $>% 3( "'( % * % 3 @ , # ( ' %( & (% (% , * %# ( .0"K% "'( ' # % * / % $ >' 1 & '( * / 1 ( %(' ( % ' * & ( &( , ' % * $> & @ ; '# % % 6 ' 6 % $ (' ( * ( ' (( % %% & $# %% P % * $>Q@ ( + , & <(63(%# % % (%% $ (' ( * ( ' (( % %% & $# % P % * $>Q@ ( + , & C.6 Servicing QUART Interrupts $ %('( , 3( 80.0@ * % ( 3 ', (%7 /.0 1 /00 1 E(( /00 1# ( %('( , ' * (( 9 XR82C684 F / ( (( (J $ >' 1 "'( 3( , 80.0@# (6 & .0%(% ( ('% %(, %' * ' % * ( $> * 3( , 55 ' (( (% %I &# (*# ( , $ '6 3 , '&' % " %'( + % * Figure 4 % % %( ( %( * 3 ( *' .0 '%% * $ (' ' %(( % $ +( (& 5 ' $+< $:: '( !' $=: $+< $+< ! !B ! !B != != MC68000 Processor XR82C684 Figure 4. Simple Illustration Depicting the Interfacing of the XR82C684 QUART to a 68000 Processor ( ( (& (% 9 ,# K% ( I% 3( %(' ( ' ( * (, ( (& ( % ' (' '%% '(% %(' (% (' ( I%# ( 3( % & %%( , * '( % L # L # L # ( ( (' (% " % '&' 3( $ '6 3 , &' (( &# 3 .0 + (% ( # ( 3( %% )(% # # 4# $ +( (& # 3( ( ( , %% (% @ 4 % ,(' * # + 3( '6 3 , (% ( I% & %( , L # L # 4 L # @ 4 L ' * '( % %# ::! , B@< 3( %% * ( % * /$= !' 1 (( &# %% 3( % %% ( % " % '&' ' ( (% %%# ( * $= !' 3( % %% E 3 ( % %%# $= !' 3( %% /$=@# & %%( , $= ( * $ 3( $=@ %(, ( , %%# %% (%# 0 4# , %% ' % 3 ; 3# (* * % %% (% ,(' /1 # /$- ( ' !' 1 3( % $ (% *(,# Figure 5 % % ( %'(' * 80.0@ (' ( *'( , .0 (' '%% (% *(, % 3% & ( '%%( , ( * (' '%% - ( *' %% ' ( , '('(& * %% % (% 0 4 (% ( ' (% '('( ' %(%% * /$ +( (& 5 ' :B@<@0# 3 4<( 0<( !' % :B@<40 (%'%%( %%# * % :B@<40 ('% /$= !' 1 (% /$- ( ' !' 1 $ (% *(,# % ( ( (& * @ * '( %'(( * (% '('( * 3% $* I(% %(' * + # ( 3( %% '( 3# ( # %(, # $: E (% %(, ,, % / 31 $ +( (& 5 ' :B@<@0 3( , ( $ +( (& % (% ( (& + $ (% '%# $ +( (& (% @ $+< L # $+< L # $+< L $ % % +( (& < @ ( I%# + 3( ''6 $ %6 (% * (% 3 ( % ,(% ( ( % ( ( (& $* % ( ( (& (% @ %%F + 3( '6 3 , ,( %(' * (% 3 ( I% $* % . XR82C684 ,( , 3 .@ @. 99 .# + 3( ( & (% & @# ( ( '( # ( &# * $ (' ( *3% (% %% '( 3( ( + , * + + 3( ' , ' (% '( ( % &# % % % ( ( %(' ( "(%% '( ( %&% & $* % % *( ( (( (J $>%# ( ' % 3( & * . .0 80.0@ ('# (6 & .0 %(% ( % %(, * * ( $ >' ,(%% . $*# ( , $ &' # + % * * $>%# + 3( ( & (% & @# 3( ' , ' / ( (( (J $ >' 1 "'( %(' ( # ' 4. ( & 3( %%# & %%( , ( * Please note that the QUART does not requires that its -CS input be asserted in order to respond to an "Interrupt Acknowledge" cycle. The QUART only requires that its -IACK input be asserted. $ % % %%( * $= ( # 3( ' ' % * * $>% $ >' ,(%% % ! !B# 3 ( ' & + ' % ' ' % * ( $> %# ( 3( %% != ( ( * + (% & * % + 3( "' (% /1 ( (' 3( & '&' ' (% /1 '&' (% ' # + 3( , & ,( , $= ( * F 3( # ( # , != + ' != % , $ &' (% ' # " % 3( '&' % 3( (6 & (' %('( , ( E + % & %(' ( ' (( % '%( , ( I%% * (( # $: * 3( , $* % & ( (( (J $>%# 3( % -E -E != != ! !B @ $ 4 +( (& 5 ' B 4 . $+< $+< $+< $B $. $9 $4 $ $ SN74LS148 74LS10 ! !B >'' $@ $=@ $: $= 4 4 @ @ 9 9 0 4 9 B @ $= !' 4 4 @ 4 $=B $=. $=9 $=4 $= 9 $= : %% !' ( , ('(& %% !' ( , ('(& 9 B . $- ( B ' 0 4 !' 4 @ @ SN74LS138 MC68000 XR82C684 $ SN74LS138 B . 9 @ 4 9 Figure 5. Detailed Schematics of the XR82C684 Interfacing to the MC68000 Processor B XR82C684 $: $+< $+< 4 @ 4 $= ! !B >' != Figure 6. XR82C684/68000 CPU Interrupt Cycle Timing Figure 6 % % (( , (, ('( , %I ' * % 3( '' -+ ( *'# ( , $ '6 3 , )% &' E (% ( , ( ? # 3( ' 0 ( /( ' 1 %# + # ( , /$ '6 3 ,1 $= '&' + 3( (% ( ' * ! )%# ( * $ >' '( * ( ( %(' ( # ( %&% & (( &# ? ,(% % 3 ' ( ((J ( I%% , % ( ('% (% (% (%'%% ( , ( ( Section C.6.2.2 Interrupt Service Routine C'(% I('6 &7 * $ (' ( $ (*& ' (( '%( , $ I% (' ( & (( ( , ' (( '%( , $ E (% ( , ( 00 $ # 3( ( & ( ' ( * ( + # ( , $= '&' $ >' ( * ( # & % , ' ( $ (' ( # (% '' (% " $ ( (*& '% * $ # + % ( $ % ,(% %6 $ % ,(% * ' % * ' * $% ( (*(% ' (( % '%( , $ I% Section C.1 *( % ( * * $% (%'%%% 3 ' ' * (% 3(( $% 3( ( $ * 3( , 3 3 % % % ( 6 / ? 1 ' # ( ' ( ? , $ % * % /$ 1 # ? % /?( ,1 F (% % % % & ( ? 3 ( *'( , ?( , (' '%% # ( $ 3 ( *'( , $ (' '%% C.6.2 "88 Mode" Interrupt Servicing 00-$ 00-? $ % (% (' & * % /$ 1 <(63(%# ? % * % /?( ,1 0 XR82C684 ((%( 3 $ ? (% '%%& , /' 1 ( % $* & ( *'( , * 3( , (' '%% %-(' ' %# % ( $ Direct Interrupt Processing $* + &% /!(' $ + '%%( ,1 ' + % ' ( I%# % ' (% ' ( %'( # + 3( ' , ' %'(*(' '( ( %&% & + % & (' ( %# (% / '( 1 (% *(" & + '('(& (% * 09* 00* + 009* + " # (* $: ( I% ( ( # * 09* # (% %%# + 3( ' , ' '( 4. ( %&% & (% '( (% *(" & '('( %(, * 09* ' ' , & % .0;* ?0* + $ % ; 3# % ( , ( ? 3 ( *'( , * 3( , (' '%% % (' ' % 000* + (External) Vectored Interrupt Processing 00.* + + % & (% * * ( '%%( , &(' & $ '6 3 , ( (% /$=1 /$:1 3( % , /( ' 1 ( * ( ! )%# ( " 3 /5" 1 (% % %'( (% * * ' ( '%%( ,F '% '( * ( %(' ( (% ( & 3 /" 1 % + %# %' % 00 009* +# (% /( ' 1 ( * ( (% & ' * << ( %'( %'( /5 % ( 1 '( * (% /5 % ( 1 (% *(" & + '('( %(, $* % &% (% ' * ( '%%( ,# -% (% % %( * ( %( , ( ( %(' ( # ' (( ' ( %'( ( %(' ( %(% (% '( ( & 00. 0@0.* +% + (* + ?0* + $ % " *3 %'( % 3( ( ( (%'%%( % * -(' '%% ( *'( , ( '%%( , ' * ( (' '%% % (% (%'%%( # ( %'(( * $ $ '%%( , ? $ '%%( , 3( , C.6.2.1 I-Mode Interrupt Servicing 3( ( $ * 3( , 3 * $# 3 % $ , # + ( *'( , ( , ( $ # 3( * '( % * 3%# ( , ( %('( , 5' * % $ + '%%( , ' (I% 3( % ( , ( ( * 3( , %'( % $* I(% ( %(' * + # ( 3( %%% $: ( + ' + % ' ( I%# ( 3( ( '( * ( ( %(' ( # 3( ' , ' '( + 3( '' (% * (% 3( (( , /$ '6 3 ,1 %(, ( , % ('( (% ( * ( * ' + % (( '%% * K% ( I%# 3( , (% $: ( + 3( "( / 1 ( %(' ( 3( % '%%( , $ %&# % ( , ( $ # 3 ( *' * +-* % ( Table 4 Table 4 % % % & * ( '%%( , (% & & ' * % * +%-* % Comments on 88 I-Mode Interrupt Service Routines ( , ( 00 $ ( %% % (% , ( ( '%%( ,# 3 ' 3( .0 00 ? ) .0 00 ? % 3( ( + 3( ' % * ( $> $> ! %# ( , $= '&' (% * 3% /%'1 * '%% * ( I% 3 * * ' # $> (% ' ! )% (* '% * ( I% (% %% & $ ,(% $> (% ' $ , 3 '% + % ' & % ' ( ( %(' ( # 3 ( *' 3( $ !(' $ + '%%( , 5" >' $ + '%%( , XR82C684 ! )% (* '% * ( I% (% %% & $ ,(% ; '# + ( *' .0 ? & % * $% % * $ (' ( ; 3# + ( *' 00 $ & $%# ( , %' * '% * ( I%# % * ( %(' ( (% ' ( % % ( '% ( '& * %('( , $ * P* /C Type of Interrupt Processing 09* !(' 00+ 5" >' 00* + 3( 3 % * 0 (** ' % * /<<1 ( %' ( % $ (' ( % 00 + 3( ( '6 3 , # $:# 3(' ' % /,1 /<<1 ( %'( % ! )% 009* + !(' 5" >' 009* + % /!('1 " $ I% ( %7 B9# .9# 99 (( &# (% * + % "' % /' 1 ( % % % 00 * + .0;* !(' .0;* % %( , /%6 1 " $ I% ( F $ ?0* + $ 5" >' ?0 + %% "' % ' % % * 00 + ?0* + !(' $ ?0 3( ' 40; ( %&% & (* $: ( I% ( (% %% $ Comments 09* % 3 " $ I% ( %7 $: $: Table 4. Summary of * P/* C and Their Types of Interrupt Processing (I - Mode) ( * ( % ( Table 4 (% (%'%% ( ( ( * 3( , %'( % C.6.2.2 8051 Microcontroller 3 . ( (% 09 *( & * (' ' % (% *' & $ ' % 3( (& * ((% * % ((% ( ' 7 @6 &% * '( %( * 0 ( $- + +4 0 &% * 4 XR82C684 $: $: 58 ( 04-09 ( ( ( + $ 0 &% 04-09 ,(%% = 04-04 @= 09 0= 09 0 &% ( 04-09 ( ( + %'( ( + $- + % )% 5 <5 +5: + + + +4 8! 8! Figure 7. Block Diagram of the 8051 Microcontroller + + + +4 +@ +9 +. +B +4 8! +4 8! +4 $: +44 $: +4@ +49 +4. E +4B ! 8< 8< > @ 4 4 40 @ 4B 9 4. . 49 B 4@ 0 44 4 4 4 4 0 @ B 9 . . 9 B @ 0 4 09* ' %(%% * @ 0( $- % * % % * '( %# % 3( (%'%% 3 > + ! + ! + ! +4 !4 +@ !@ +9 !9 +. !. +B !B 5 <5 +5: +B 9 +. @ +9 4 +@ +4 + + + 0 Port 0 (P0.0 - P0.7) (% (% % ( % 4 4 * 09 $ $ ( ( ' %(, %# ( (% % % , % $- , %(, % 3( " &# ( ' % ( " %% % ! !B Port 1 (P1.0 - P1.7) + (% (' $- ( % 0 ( %# %(, % +# +# +# # ( * ( *'( , % I( : ( * '( % %%(, * + ( %F % & % % & * ( *'( , " ('% 5"'( % 04-09 $%# 3(' % + + ( % $- ( % % " ( % ( ( Figure 8. Pin Out of the 8051 Microcontroller 4 XR82C684 Port 2 (P2.0 - P2.7) -INT0 (P3.2) and -INT1 (P3.3) + +( % 0 (% % ' * '( % , % $-# % (, & * %% % * %(, % 3( " ' & * 9. &% * " & 0 9 $: $: " ( I% ( % 09* 5' * % ( ( % % /(' ( 1 '%%( , $ (% '%# /('1 % (* * % ( % %%# , ' 3( (' & ' %'(*(' *(" '( ( ' & (% '( (% ( & '('( %(, * 09* $ ' ' , Table 6 % % '( ( ' & , ' 3( ' # (* ( * % ( % %% Port 3: + 4 (% % ( % B $ (( * '( ( , % , % $-# % ( % ( * '( % 5' * % ( % %# % (% ( Table 5# 37 Bit Name Alternate Function +4 8! '( ! * ( + +4 8! %( ! * ( + +4 $: 5" $ +44 $: 5" $ +4@ (- 5" $ +49 (- 5" $ +4. E 5" ! & E( +4B ! 5" ! & Interrupt Location $: 4; $: 4; Table 6. Interrupt Service Routine Locations (in Code Memory) for -INT0 and -INT1 * # (* % (% %( , ( * % ( % % ( I% ( # % % ( % ( ( %(' ( ' (( ' ( %'( ( %(' ( (% ' * % %% '( % Table 5. Alternate Functions of Port 3 Pins $* 09* (% I( ( *' " ' % ( & %' * %(J% , 9. &%# + % + % % % %% ( % + 3( * '( % ( " %%- % !( , *(% * * & '&' # + 3( % 3 %% & !( , %' * * & '&' + 3( % (('( % + 3( % % %% & <5 % * B@<4B4 % ' (' ' % ( " %% ! % %(, % 09 % % % (( ( % 3(' ( *'( , 80.0@ ( % % ( % 7 ALE - Address Latch Enable $* + (% % ( (% % % 3 & * %% % <5 (% %(, '% %% ( " ,(% ( , *(% * * & '&' ' (% (% # + ( % ( * ( ( , %' * * & '&' # 3 %* 6% ' Figure 9 (% %'(' ( %( , 3 80.0@ ' ( *' 09* 4 XR82C684 $: $: ! ! E E + ! !B ! !B ! <5 @ @ 2 74HC373 9 B + 0 9 G %% !' ( , < ,(' XR82C684 00 8051 CPU $% Figure 9. An Approach to Interfacing the XR82C684 QUART to the 8051 Microcontroller (' '%% I(% 9># 9># > 3 % (% (( &# (% (' '%% I(% 3 '(%# ( ' /' 1 + &(' &# % ('% 3 0@ '6 2 00 &% 0@ '6 2 (% % %( * ' (( ( , , ( , '%%& (( , % ' * 00 + # * " '&% 00 &% (% % %( * **( , (('( ! )% (( &# %( ' 00 + (' % (' & ( ' % %(, %# 00 !(' (% % %( * % ( , %(, ( , ( * ( # * 00 ('# ( * 3( , )% %(, %F ( ''%% & ( ('% '('(& % Figure 9 3 * '( % * 3% ( , I% ( (' I%% ( * + & %%( , (% '( 3 $: ( (% 3( '% $: ( ( + , 3 E (% % 09 + 3( *( (% "'( , (% ' ( %'( # 3( ' , ' ( %(' ( $ '% * Figure 5# %( ' K% $: ( (% ( $: ( * * # ,( ( , * ( %(' ( 3( ' ( 4; ( ' & 09 + % (%% $ '6 3 , %(, '6 $ 3( C% ,( '%%( , , K% ( %(' ( ' + % (( '%% * ( I%# K% $: ( 3( , , /(,1 + 3( * ( %(' ( % ( $: $ '6 3 , 5 & 5E & E( C.6.2.3 8080A Microprocessor $ $ + 00 (' '%% (% * ( %( * $ '%% % $ , # ( (% 0( $E + E( 44 XR82C684 Figure 10 % % %'(' * 00 + 2:! 8080A CPU 9> 9> 9 > ; !9 55 9> !. !B 2:! H: % 2:! 9> ) 5: 8228 System Controller ! ! ! !4 !@ !9 !. !B $: 5 5E $ $E Figure 10. Schematic of 8080A CPU Module '6 3 ,1 %(, + % ( ( (( '%% * ( %('( , 00 + & % % /" 1 ' ( '%%( , ; '# 3 $: (% %%# + (% 3(( , /' 1 ( * ( ! % $ '% * 00 + # (% /' 1 ( * ( (% &(' & ' * * 5 ( %'( % 00 + % % (, (** ( %'( % , B % ( %'( % & ' % %'(*(' '( % 3(( + K% & %'# 3 ( ( %(' ( "(%% Table 7 % % (% * % 5 ( %'( %# ' %# ' % ( , 5 %% 8080A CPU Module Interrupt Structure /$ '1 * 00 + (% %'( 3 00 + (' ' %(%% * 3 %(, %7 $:5 $: (( &# 00 )(!('( )% ' %(%% * %( , %(, # $: $:5 (% '((, $ 5 # $: (% '((, $ I% ( $* /5 $ 1 ' % ( 6# $:5 3( /(,1 ( ('( , 00 + 3( ( I%% * ( % E $: ( (% %% & ( (' I%( , ( # + 3( ' (% ' ( %'( * ' ( * (% ( %'( # + 3( %% $: ( 00 )(!('( )% !( & ,, ( , $: / 31 $: (% '( 3 /$ 4@ XR82C684 Op-Code (hex) Mnemonic Restart Address (hex) B 0 !B ! 4 0 5B @ 5 9 0 B . 4 B 40 servicing. Other circuitry (such as the 8224 Clock Generator, the Address Bus, etc.) have been omitted from the schematic. In this schematic, the QUART Interrupt Service Routine is located at 002016 in memory. Additionally, the QUART has been configured to operate in the I-Mode. The function description of this circuit is presented below. 80.0@ 3( I% ( 00 + # & ,, ( , (% $: / 31 (% %(, (% ( ( '((, $: ( * + ' 00 + % ' (% ' ( %'( # ( 3( %% '( 3 $: %(, * 00 )(!('( )% !( (% (# $: %(, * $: %(, * 00 ' ,(' / 31 $: $: %(, % 3 ( , ; '# 3 $: $: ,(' / 31# * , 3( % ,(' / 31# & %%( , * 5 5 ( % * :B@<@@ ! )% ** 4 (% /( ,1 * $: $: %(, % (% % ( % & ( (' I%( , ( (% '(% %(' ,# % %( %% $: %(, ' 5 ( % * 4 %%# # ( ( * (% (' 4 3( 3 * (% ('# !B ! ( % * 00 (' Please note that, in this example, the value "E716 " is hard-wired into the input of U3. This value is the op-code for the "RST 4" command. Hence, once this data is gated into the CPU module, via the data bus, the CPU will load 002016 into its Program Counter and branch program control to that location. The Interrupt Service Routine for the QUART exists at this location in memory. Table 7. 8080A and 8085 CPU Restart Instructions Used with Vectored Interrupts * # ' + '(% ' * * % 5 ( %'( %# ( 3( ,( "'( , (% ( %'( & ( , + , 3( ( /% %%1 *3%# , ' 3( ' /% %%1 '( " # (* ' /5B.1 (% ! )% ( , $: '&' # (% ' ' % % 3( / @1 ' # + 3( . ( + , , ' 3( ' '( ( & % Table 7 Interfacing the 8080 CPU Module to the XR82C684 QUART for Interrupt Processing 00 + ' ' ' 80.0@ ( $ !( Figure 11 % % ' ' ( ( *'( , 80.0@ 00 + * /" 1 ' ( '%%( , Please note that Figure 11 only includes information pertaining to QUART interrupt 49 XR82C684 @ >'' 9 $:5 $: $: . 8080A CPU !)$: 5 ! ! ! !4 !@ !9 !. !B ! ! ! !4 !@ >'' 4 8228 Bi-directional Bus Driver !9 !. !B XR82C684 QUART 5 !$ !$ !$ !$4 !$@ !$9 !$. !$B SN74LS244 $: Figure 11. Circuit Schematic depicting approach to Interface the XR82C684 QUART to the 8080A CPU, for "External" Vectored Interrupt Processing (Interrupt Service Routine resides at 0020 in Memory) * ' % 3 ( %(( * 00 009 ( ' ' ( ( , '6 2 * '( % * 0@ + '(# ( , %6 ( I%# ( , 4 /('1 ( I% ( ( %# ( , % * * ( ( (& 009 %( I(% % , ,(' ( ' )% %(, % (# $# $E# 5# 5E # ( ( ((J ( ' # 009 ' ( % ( " %%-! )% ! !B '(*(' &# 3 0 (% * %% )% % ( % 3( 0 ( ! )% ; '# B@<4B4 0( ' (% ( ( " %% ! %% ( ' 00 + ' % 0 (** ( %'( %# ( ' % 0 (** ( ( ( ('% (% ' '( & ('( , '# % ( Figure 11# & 3(( , ' % * ' * 5 ( %'( % ( % * ! )**% % Table 7 % ! )**% % & ( , $: '&' # & 3 ( %% '( ( I% ( %(' C.6.2.4 8085 Microprocessor 009 + (% & $ (' '%% # , ( (% ' 00 + 4. XR82C684 Figure 12 % % %'(' * 009 + 8 8 + B9 .9 99 $: $: ! ! ! !4 !@ !9 !. !B ! ! ! !4 !@ !9 !. !B <5 ! ! 4! @! 9! .! B! 0! 4 @ 9 . B 0 4 @ 9 . B 74LS373 0 4 @ 9 0 4 @ 9 $ 5 $E $- ! E 5E 8085 CPU Figure 12. A Schematic of the 8085 CPU Module 4B XR82C684 ! !B ! !B @ ! 0! 8 0 <5 8 + B9 .9 99 $: 9 B 74LS373 @ G 0 9 %% !' ! $: 0 9 $- E 5 XR82C684 ! 5E E G;5G$ 8085 CPU Figure 13. Schematic of the XR82C684 Interface to the 8085 CPU Module (Memory Mapped) Figure 13 ( %% ' ( *'( , 80.0@ 009 + Note that the XR82C684 QUART, in this case, is memory mapped (e.g., the signals -MEMR and -MEMW of the CPU module are connected to the -RD and -WR pins of the QUART). ; 3# % ' C% % %( & ' ' 80.0@ (' + K% $- ,# %(, $ $E * + ' ' ! E ( % * # %'( & 8085 CPU Module Interrupt Structure 009 + % % !(' /5" 1 >' $ '%%( , 009 % @ %6 ( I% ( % 99# .9# B9# $:# %6 ( I% ( + E (%'%%( , ( *'( , * ( %('( , * ( ('% %' % # 3 & ' ' 3( %6 ( I% ( % * * %6 ( I% ( %F * % ( % % /!(' $ 1 '%%( , ( ( , ( I% % % /5" >' $ 1 '%%( , Table 8 (%% % $ I% ( % ( ''(%('% *% K% $: ( 3% ( & ( * (% *(,# '% (% % 3( %% ( " 3 *(,% 40 XR82C684 Input Name Trigger Priority Type Acknowledge Signal? Address (Hex) + %(( 5, (,, !(' : 4 .9 ;(, < ( % 4 !(' : 4@ 99 ;(, < ( % @ !(' : 9 5" >' $: L /< 31 Table 7 B9 $: ;(, < ( % Table 8. 8085 CPU Maskable Interrupt Request Inputs and their Features 009 + **% ( ( ((J( # 3(( % * %6 $ % (% ( (& (% * ' ( Table 8 $ % % ( (& % & & / ( ,1 ( I% ' (' ( % / * I1 (% ( , %(' & + # (% ( ((J( %' , (% (' ( %I &# ( (% %%( 99 ( I% ' /( 1 ( %(' ( * (, ( (& B9 ( I% * # % % , ,( % (% ( (%- *(3 Direct Interrupts 009 + ( % B9# .9# 99 /!(' $ 1 I% ( % '(*(' &# (* & * % ( % %%# , ' * + (%# ' ( * ' ( %'( # (' & 3( & '( ( & '('(& 3(( 009 ('# '% , ' '( % /!('1 ( % ( ( (' 3( & % * /$ '6 3 ,1 ; '# '' ( , Table 8# (* B9 ( 3 %%# /4.1 3 ( , ' * + # , ' 3 ' '( ( & % (% % %( ( % ' ' ( %(' ( ,( % '( ( & Table 8 % ( ('% 009 + 3( % /" 1 ' ( % ' % % ( " ' ( '%%( , ( (' % * 00 + % Section C.6.2.3 4 XR82C684 >'' $: .9 ! !B ! !B ! <5 @ 74LS373 B 9 %% !' ( , < ,(' 9 0 $ $- ! 5 ! E E $E 5E 8085 CPU XR82C684 Figure 14. The XR82C684/8085 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 0034 in system memory) Figure 14 % % %'(' 3 3( I% /!('1 .9 $ 009 + $ (% '%# $ (' ( * % ,( 4@. ( %&% & (% (% & %( ( *' ' (I# '% (% /$ '6 3 ,1 %(, ( *' Figure 14 Figure 15 % 3 (** '% ' % ( *' 80.0@ 009 + @ XR82C684 >'' @ 9 $: $: . >'' $: 4 ! ! ! !4 !@ !9 !. !B ! ! ! !4 !@ !9 !. !B 5 ! ! ! !4 !@ !9 !. !B 5 !$ !$ !$ !$4 !$@ !$9 !$. !$B SN74LS244 <5 4 @ 9 . B 0 ! ! 4! @! 9! .! B! 0! 4 @ 9 . B 74LS373 XR82C684 8085 CPU Figure 15. The XR82C684/8085 CPU Interface for Vectored Interrupt Processing (Interrupt Service Routine is Located at 002016 in System Memory) Figure 15 % % %'(' 3 3( I% /5" >' 1 $ 009 + $ (% '%# $ (' ( * % ,( . ( %&% & 9 ( '( + + % 5+ -! C.6.2.5 68HC11 Microcontroller *'% *( & * (' ' %# * % .0; (' ' % (% *( & * (' ' % **% % * * 3( , ((%7 @ XR82C684 ! !) 8< 58< 5 $ 8$ 55 %'( $ < ,(' '6 < ,(' 9. )&% + ( &% >; >< %%-! +$ -! "! = $ $ ; %6 + $- $ "! )% 5" %( %% 0 + + ) + + ! + 5 Figure 16. Block Diagram of the MC68HC11 Microcontroller Figure 16 (% '6 (, * .0;* Port A .0; ' ' *(, ( /( , (1 ( /5" ( " )%1 $* (' (% ' *(, ( /( , (1 # ( .@= &% * %% %' (% ( * $ Please note that this does not mean that there is 64K bytes of memory, or other addressable portions within the device. .0; ' *(, * /( , (1 ( ' %% & ' % " * # (* % %( ( *' (% * # * % ( /5" ( "1 .0; (% ' *(, ( 5" ( " & &( , ! !) ( >''# %( , (' + ' %(%% * 4 ( ( %# @ ( % (('( ( (% (% % % ( &% * ( ( % ' % * + % '' * ( ( % % ( ' * '( %F * * ( % % ' * '( % .0; ' %(%% * 9 (** (* '( % 5' * % % (* & (%'%% 3 Port C Port B + ) ' %(%% * 0 ( % $* .0; * (% ( , ( %( , '( # (% * '( % % , % ; 3# (* .0; (% ( , ( " ( " # (% 3( * '( % %% & * &-( (' ( *'( , 0 9 + ' %(%% * 0 (('( ( % E .0; (% ( , ( %( , '( # (% * '( % % @ XR82C684 ( ( %(' ( %(% (% '( ( & , % (('( ; 3# (* .0; (% ( , ( " ( " (% 3( * '( % ( " %%- % ! !B '(*(' &# ( , *(% * * & '&' # (% 3( * '( % 3 %% & + ) (% %% & * %%( , & ('% ( ' % !( , %' * * & '&' # (% 3( * '( % (('( % (% ' ( " ( % * %% ( B@<4B4 ' (' AS/STRA /%% 1 ' % ( " %%- % * + (% ( (% ,(' /(,1 ( , *(% * * & '&' F ,(' / 31 ( , %' * * & '&' -IRQ $* .0; (% ( ( " ( " ( *' 9. &% * %% & %'# + % ) I( % % 3 ( Figure 17. Figure 17 % ( %% 3 80.0@ ' ' ' .0; * * ( ( ( $* I%% ( # (% '( 3 $: ( 3( %% ,, 3# 3(' 3( # ( # '% $ ( * + %% E (% ''% * 3( ' ( "'( , (% ' ( %'( * ' ( * (% ( %'( # , ' 3( %(* '( # 4 ( %&% & % (% % %( ( % K% ( %(' ( %(% (% '( ( & * 3( (%% ( '6 3 , %(, $ %# * 3( C% '%%% , ( %(' ( ' * % (( '%% * K% ( I%# $: ( 3( , * 3( * $ (' ( % '%%( , (% (% /%6 1 ( I% ( $* (% ( (% %% ,# ,, / 31# .0; 3( ' , ' # 4 ( %&% & '( % (% % %( * ( %( , ( % ( Figure 17. , ,(' '('(& I( , E# !# 55 %(, % * # * -E# 55# 5 ' '6 % ( Figure 3. (% '('(& % % ( ' ( Figure 18. Port D + ! ' %(%% * 0 (('( ( % ; 3# (% ' ' *(, % '( ( +( $ *' +$# ( ('( % $ *' $ Port E + 5 ' %(%% * ( @ 0 ( % ( , '6,( , ( (% ' ' *(, * '( % , % ( % ( % '( -! ' % ( % ( * ( *'( , 80.0@ (' * % ( % (%'%% 3 @4 XR82C684 9> 5 -E ! !) $% 0 9 %% !' ! E $ R$: 9 B 2 ! @ @ 74HC373 ! !B ! !B XR82C684 68HC11 Figure 17. XR82C684/MC68HC11 Microcontroller Interfacing Approach -E E 5 ' '6 ! 55 55 Figure 18. Glue Logic Circuitry Required to Interface the MC68HC11 * C to the XR82C684 QUART ' *(, ( ? $ , # + ( *'( , ( , ( ? 3( * '( % * 3% ( , ( %('( , C.6.2.6 Z-80 CPU ?0 + ' ( *' ( , ( $ # (* ( + (% ( , ( $ % ; 3# * %6 * / '%% ' ( (&1# ( % %% '( 3( ?0 + 3( % ( Section C.6.2.1 $* I%% ( %('( , * + # ( 3( %% $: ( ,# ,, / 31 ' + % ' ( I%# ( 3( (%% $= $ '6 3 , %(, '6 E + % % $= %(, ( (% ( * ( , (% ( I% (% % E % '( ' $= %(, # ( 3( # ( % %# ' ' % * * $ >' ,(%% $> $> C.6.3 Z-Mode Interrupt Servicing 3( ( , ( $ * 3( , 3 3 % * $ % % ( 6 / ? 1 ' % Table 2# ( @@ XR82C684 ! )% + 3( (% /( ' 1 ( * ( F ( * 3( , 3 ( ,% % /( ' 1 ( * ( '( * ( %(' ( ''(%(' * ? ( (% ( 3% % ( ((J ( I%% * % ( ('%# ( 3 % < % % % 3 % ('%F ' * % ('% ' *(, ( ? % ' ( ((J $ I% * ' * % ('% & ' '( , % ('% ( /(%&'( 1 % % ( Figure 19. % ' * ( I% ,# 3(' ( % %(' ( '( * $ (' ( *3%# ,' 3( ' > $: $: $: > + $5$ $5 $5$ $= $: $: $5 $5$ $= $5 $= $5$ $5 $= $= ;$2;5 +$$H '' * # %6 ( I%%# * (% 3&% ('# ' C% (, * /(,% ( ( (&1 (' (% * 3 ( ( (& (% (% '% $5$ ( * (% 3 ( (& (' (% ' ' $5 * (,% ( (& E /(,% ( (&1 (' I%% ( # (% $5 3( ,, / 31 (% 3( ( # (% / 3 ( (&1 (' * (%%( , & ( I%% + (% / 3 ( (&1 3( (( * (%%( , ( % ( $5 ( * /(,% ( (&1 % ,, /(,1 *( ,# ' ,( # Figure 19# * (, (' (%# 3 (% ( ( (& (, % % 3%( ( (& '% (% /( I%1 '( (& ' (% & '( % * & * % * Figure 20 % % (( , (, ('( , %I ' * % 3( '' ( , * 3( , $ I% * $: $= ! ! !B : > ( >' $5$ $5 % $ Figure 20. Timing Diagram Illustrating the Sequence of Events occurring between the QUART and the CPU during an Interrupt Request/Acknowledge and Servicing Additional Notes About Z-Mode Operation ? ( (% % & ?( , +( ' % ?( , ( ' % $ >' ,(%# $ '6 3 , $= ( # $5$ ( # $5 * # Figure 20 ' %( & ( ' % * % ?( , ( ' %# ( (( ( ( * % @. XR82C684 % ( (# ? ( (% ' (* (% ( *' * 3( , '%% % ?0 + 3( % -E( ( % 3 & $- ?0 % I( % (( , ,(' ( ( *' (' & & ( ('% ( % '# ?0 + (' % ' 3( ' % %(, %7 5 & # 5E & E(# $ $- + # $E $- + E( $=-$: $ '6 3 , ( % 5' * % * '( % ' ( * !# E# $# 5 ( % Figure 22 % % %'(' * ?0 + # 3(' % 3% 3 ' ' "' ' % %(, % * % + ' ( % ?0 (' '%% $ 000* + 00.* + 00. 090.* + Please note that it is possible to interface the 80X86 Family of microprocessors to an I-Mode QUART, however, additional components and design complexity would be required in order to accomplish this ' (I- '% ( *'( , ? % (' '%% % (% % ( ( # ( * 3( , %'( % 2:! 9> C.6.3.1 Z-80 Microprocessor '6 ( ?0* + ' %(%% * 0 ( ! )%# . ( %% )% % ' ( % ?0* + (% & * "( '%% 3(' ' ' & ( *' ( ? $ (' (% (% '% ?0* + ' ' *(, ( * (** /( %1 ?0 (% % ( ( %% ' (' ( *' % * * +-* % ( % & ( '% (% %% % ( " Figure 21 % % %'(' * ( * ?0* + 4 @ 9 +;$ !@ !4 !9 !. > ! !B ! ! $: :$ ;< 5 $ @ 4 4 40 @ 4B 9 4. . 49 B 4@ 0 44 4 4 4 4 0 @ B 9 . . 9 B @ 0 4 9 +;$ ! !B $: :$ E$ ) E 5E ! 5 ;< 5 ; $ ) = $E $ $: 0 B . 9 @ 4 2:! ; 55 R) E$ ) = E ! 55 Figure 22. Schematic of Z-80 CPU Module Z-80 CPU Interrupt Servicing Capability ?0 + ' ( % 3 ( I% ( %7 :$ $: :$ (% /: %6 1 ( I% ( ( F $: (% /%6 1 ( I% ( ( %6 * ( *'( , # 3 & ' ' 3( $: ( ?0 + ' ' *(, (** ( %7 ( * 5" >' !(' /+( 1 >' Z80 CPU 5' * % ( % % $: ( * ?0 + 3( (%'%% ( * 3( , %'( % Figure 21 Pin Out of the Z80 CPU Device @B XR82C684 " * '('( (J( , (% * * ( '%%( ,# 3( ( *'( , # (% % ( Section C.6.2.3 (% %'( (%'%%% ( *'( , 00 + (% "' % ' ' % 3( ?0 + # ( (% ( , ( $ ?0 (% ( , ( $ External Vectored Interrupt Processing (Interrupt Mode 0) ?0 * + 3( ( (% ( (* /$ 1 ( %'( % "' E $: ( (% %% & ( (' I%( , ( # + 3( ' (% ' ( %'( * ' ( * (% ( %'( # + 3( %% $: ,, / 31 $: (% '( 3 /$ '6 3 ,1 %(, + % ( ( (( '%% * ( %('( , E ?0 + % ( $ # ( (% 3(( , /' ( * ( 1 ! )%# * 3( , %%( * $: $ (% '% * (% ( # (% /' 1 ( * ( (% ' * * 5 ( %'( % ?0 + % % (, (** ( %'( % 40; % ( %'( % & ' % %'(*(' '( % 3(( + K% & %'# 3 ( $ %(' ( %(% Table 9 % % (% * % 5 ( %'( %# ' % ' % ( , 5 %%% Op-Code (hex) Mnemonic B Restart Address (hex) 0 0 !B ! 0 0 5B ; 5 0; 0 B 4; 4 40; 40 Direct Interrupt Processing (Interrupt Mode 1) ?0* + 3( ( (% ( (* /$ 1 ( %'( % "' E $: ( (% %% & ( (' I%( , ( # + 3( ' (% ' ( %'( *3%# , ' 3( (' & 3( & '( ( & '('( %(, * ?0 + (' , ' 3( ' '( ( %&% & $ (% '%# , ' 3 ' 40. ( & % (% % %( * ( %( , ( ( %(' ( (% (' '( ( & ?0 + % ( ( (' 3( & % * /$ '6 3 ,1 + C% '%%% , $ (' ( # (( % '%% * ( I% % ( Peripheral Vectored Interrupt Processing (Interrupt Mode 2) ?0 * + 3( ( (% ( (* /$ 1 ( %'( % "' (% ( / 1 (% & %* (* % 3(%% ' ' ( I% % * % ( % $: ( * ?0 + (% ( 3% ( ( , (' ( (*& (% * '( (# C% ( ( %('( , E $: ( (% %% & ( (' I%( , ( # + 3( ' ( ' (% ' ( %'( ' (% ' ( %'( (% ' # + 3( %% $: %(, ( * ( (' ( %(' (% ,( ' ( ( , ( (' % ' $: %# ( 3( ' /( ' 1 ! )% (% ( ' 3( & + + 3( ' , ' '( * & ( ' Please note that if the IEI input to the QUART (or Zilog peripheral device) is "low" then the QUART (or Zilog peripheral device) will be disabled from generating any interrupt requests to the CPU. " * (% ' (% % 3 ( Figure 23 $ (% '% 80.0@ (% Table 9. Z-80 CPU Restart Instructions Used with Vectored Interrupts (Mode 0) * # ' + '(% ' * * % 5 ( %'( %# ( 3( ,( "'( , (% ( %'( & ( , + , 3( ( /%1 %% *3%# , ' 3( ' /% %%1 '( " # (* ' 5B. (% ! )% ( , $: '&' # (% ' ' % % 3( ; ( %'( # + 3( . ( , ' , ' 3( ' '( ( & % Table 9 % (% % %( * ( %( , ( %(' ( ,( % (% '( ( & @0 XR82C684 ' *(, ( ? (% ( *' ?0 + E I(% ( %('( ,# ( 3( %% (% $: (% '( 3( # ( # '% $: ( * + %% ' + % ' (% ' ( %'( # + 3( %% $: %(, (% 3( ( %% $= $ '6 3 , ( % * %% $= %(, (% ( * & " '&' 3( /$=1 /$ '6 3 ,1 '&' # ( % % $= %(, # 3( ' ' % * * $ >' ,(%% $> $> ! )% (% 3( & + # , ' 3( ' ( ( %(' ( $ '% * ?0 + # (% '( (% . ( %% 3(' (% ( * * 3( , Most Significant Byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Least Significant Byte Bit 9 % * $ ,(% 3(( + Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B % (, (*(' )(% 3(( $ >' ,(%% * Bit 0 Table 10. The Relationship Between the Contents of the Interrupt Vector Registers (of the QUART) and the Location of the Interrupt Service Routine (Z-80 CPU) Note: The LSB of the IVR is always set to "0" once read by the CPU. Interrupt Service Routines must begin at even addresses. (( &# % % 3 * ' % -% % ( $ ,(% * + # ( , ( 9 * >'' (, ( (& ( $5$ 3 ( (& ( $5 %% !' ('(& G 4 @ ! !B ! !B $: $: E 5E ! 5 E ! 5 $ $: Z80 CPU $= XR82C684 Figure 23. Schematic of an Approach to Interface the QUART to the Z-80 CPU (for Z-Mode Operation) @ XR82C684 ('( % ( 3(' 00.+ I(% % * 00B (' '%% :!+ $ (% # %'( % ' 000 (% I( , & $- ' % %(, % C.6.3.2 8086 Microprocessor 00. (' '%% (% . ( (' '%% *' & $ ( Figure 24 % % ( (, * (% $ Please note that in this figure, pins 24 - 31 have some additional labels, located off to the right of the package. These additional labels will be explained later in this text. 00.* + ' ( % 3 ( I% ( %7 $: :$ :$ (% '((, / %6 1 ( I% ( F $: (% /%6 1 ( I% ( $* 00.* + (% ( , ( /( 1 # $: $ '6 3 , ( (% ( +( @ % Figure 20 ; 3# (* 00.* + (% ( , ( /"1 # $: %(, % ( * # # ( % ( 000 % ' Table 12 % % '%% %% 000 '( % % # # /"1 %% %(, % $ 3 , ,% 6 ( ' * (% $ 3 & ( "( , * '( % * & * % ( % (% (' ' %(%% * . ( ! )% ( %% )% ! )% (% ( " 3( 3 . %% )(% 9 * ! !9 %% )(% . ( " 3( %% (% 4 . * .-4# B-@# 0-9 -. * % ( % %% ( % ( , *(% * * & '&' ; 3# ( , %' * * & '&' # % ( % 6 ( * '( % ,# ! !9 ' % ! !9# .-4 -. ' % 4 . %' , * ( " ( % (% ' & :-8 ( ( E (% ( (% (,# /( 1 (% % ' ( % @ , 4 6 ' *( (( % % 3 :-8 L ' ( Table 11 E 00.* + % ( (% # ( % % ' % & %(( * 009* +# I(% & %% ' ' '6 , * + 2:! !@ !4 ! ! ! ! !0 !B !. !9 !@ !4 ! ! ! :$ $: <= 2:! @ 4 4 40 @ 4B 9 4. . 49 B 4@ 0 44 4 4 4 4 0 @ B 9 . . 9 B @ 0 4 > !9 .-4 B-@ 0-9 -. );5-B :-8 ! -2 -2 <= 5 5!H 55 Pin Number MN/-MX = 1 (Min Mode) MN/-MX = 0 (Max Mode) @ ;'' ! $E :-8 E 5E 8086 CPU Figure 25. Schematic of the 8086 CPU Mode (Min Mode) 9 XR82C684 <= <= !5: ! 5 E 5E $ $E !- $ $E $: <5 $: 8288 Bus Controller ! !B ! !B ! B 74LS373 !0 !9 !0 !9 ! 0 9 8086 CPU :-8 74LS373 Figure 26. Schematic of the 8086 CPU Mode (Max Mode) 8086 * C Interrupt Processing $* ( ' I(% ( %(' * + # ( 3( %% + K% $: ( & ,, ( , ( (, ' + % ' (% ' ( %'( # ( 3( %% $: ( (* ( , ( /( 1 % # # ( % /1 % $ ( '%# $= ( * ( 3( %% ' (% %# ( ( , ( (% "' ' /( ' 1 & ! !B * % 00.* + 3( (% ( & (% & @ ( ( '( * ( %(' ( ( & ( ' (% /( ' 1 (% 0 (% 3(# 00.* + ' '' 9. (** ( ' % 99 (( &# %( ' ' ' (% ( ( & /@1# % (% "' % *(% = & * & * $ (' ( %-A Figure 27 % % %'(' * 80.0@ ( *'( , /( 1 00. + (' Please note that the QUART has been configured to operate in the Z-Mode. Therefore, the user must account for the IEI input to the QUART device. 9 XR82C684 ! !B ! !B ! ! !B @ @ 9 B 74LS373 !0 !9 !0 !9 ; :-8 ! 5 E 5E ! 8086 CPU E XR82C684 Figure 27. Schematic of the XR82C684 QUART Device Interfacing to a "Min" Mode 8086 CPU Device )'% * ' "(& * K% (( , ) '6# '6 (,# * (% '6 % (( ( 3 %# % % ( Figure 28 Figure 28A D. TIMING CONTROL BLOCK (( , ) '6 3% % %'(*& ( % -% 3(%% %( '( 3(( ' ' (( , ) '6 ' %(%% * * 3( , %7 %'( ('( )( 2 % . ( -(% 0 5" $ +( % ' '6 %(% '(%# (' & '6 ' ,(%% 47 8% 94 XR82C684 $+@ 8 $+4 8 +% ,(%% # < 47 8 " 47 8 " 47 8 ") 8 8) $+ G58 !(( & . ( D P@.Q !(( & . 8-<= 8 %'( ('( 47 8 )( 2 $+9 8) ") $+. 8) PBQ Figure 28. Block Diagram of the Portion of the QUART Timing Control Block Which Services Channels A and B 9@ XR82C684 $+ 8 $+ 8 +% ,(%% # < 47 8 " 47 8 " 47 8 "! 8 8! $+ G58 !(( & . ( D P@.Q !(( & . 8-<= 8 %'( ('( 47 8 )( 2 $+4 8! "! $+@ 8! PBQ Figure 28A. Block Diagram of the Portion of the QUART Timing Control Block Which Services Channels C and D 3(( '( * '( % % * % '&% %'( # **% % ( , %'( ( , %(, # * % & * )( 2 %# -(% '&% < %(, *I '& * 3 ;J 0 ;J (% I( * ( * ; 3# '&% < %(, *I '& * 4.0.@ ;J (% I( * , ( * % ( %# % ( Table 15# & )( 2 % (( &# *I '& * B4B ;J (% I( * , ( * % ( %# % ( Table 15# & )( 2 % Figure 29 % % 3 ' %'('% * 8< %'( '('(& * '&% % 3( *I '(% * 4.0.@ B4B ;J Figure 28 % % (, * ( * (( , ) '6 3(' %('% % ) E%# Figure 28A % % (, * ( * (( , ) '6 3(' %('% % ! Please note that each "half" of the Timing Control Block consists of a 16-bit Counter/Timer, a Baud Rate Generator, a set of four external clock inputs and four 32:1 MUX's. Each "half" of the Timing Control Block shares the output of the Oscillator Circuit. 5' * (( , ) '6 (% (%'%% 37 D.1 Oscillator Circuit: '&% %'( (% &(' & ' ' " & ' %% 8-<= 8 ( % %'( ('( 99 XR82C684 7 7 7 7 N & S 9 N & S 9 7 9 N & S 9 7 9 N & S 9 8 8 XR82C684 XR82C684 4.0.@;J 8 B4B;J + % &% 8 + % &% Figure 29. Recommended Schematics for the XTAL Oscillator Circuitry Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is used, the TTL must be driven into the X1/CLK pin, and the X2 pin must be left floating. $* % %(% % % * %( , '&% %'( # Figure 30 % % ' '%%& '('(& '' (% (% C'( XR82C684 8 8 H 8 ( % * % 4.0@;J 74HC14 Figure 30. A Recommended Schematic to Drive Multiple QUARTs from the Same Crystal Oscillator Note: The user is urged not to use the 74LS14 Schmitt Trigger Inverter in lieu of the 74HC14 device. The input of the 74LS14 tends to load down the oscillating signal from the QUART, to the point that the Schmitt Trigger inverter can no longer change state or respond to the oscillator signal. 9. XR82C684 D.2 Bit Rate Generator clock frequencies output from the BRGs are at 16 times these rates. 5' * 3 )2% )( 2 % ''% (( , * %'( ('( , ' '6 %(, * 44 ' & % ' ('( ( % ,( , * 9 % 4@ 6% Please note that the BRGs will only generate these standard bit rates if the Oscillator Circuit is running at 3.6864 MHz (for the bit rates presented in Table 15) or running at 7.3728 MHz (for the bit rates presented in Table 15A). The actual % ' % ' * 3 (** %% * ( %# , * )2 (% % '( (% & %( , ' ( , PBQ PBQ (%( , * % %% * )( %# * )2# (% % ( (%'%%( * '6 ' ,(%% % ( Section D.5 '6 (, * )2 '('(& * (% )# * (% ! % ( Figure 31 Figure 31# %'( & PB7@Q 47 8 8 P47Q PBQ 47 8 8-<= 8 %'( ('( 8 )( 2 % ) )PB7@Q 47 8 8) )P47Q 47 8 8) Figure 31. Block Diagram of the Bit Rate Generator portion of the Timing Control Block, for Channels A and B 9B XR82C684 PB7@Q 47 8 8 P47Q PBQ 47 8 8-<= 8 %'( ('( 8 )( 2 % ! !PB7@Q 47 8 8! !P47Q 47 8 8! Figure 31A. Block Diagram of the Bit Rate Generator portion of the Timing Control Block, for Channels C and D P.7@Q P.7@Q# %'( & Please see 4 and 4 for the relationship between the Counter/Timer mode, the Timing Source and ACR[6:4] for Counter/Timers #1 and #2, respectively. - # * -%# (% ( '6 ' ,(%% * % % , ( , * * %(% '(% Please note that the QUARTs, packaged in the 44 pin PLCC have limited options in regards to Timing Source, as depicted in Table 13 and Table 13A. D.3 Counter/Timers (( , ) '6 % ' ( % 3 . ( -(% -D -D 5' - (% , . ( 3 ' 3(' ' % * % (( , % '% % (% ( Figure 32 Figure 32A % % '6 (, * '('(& % ( , -D -D# %'( & % '( * % (( , % '% * -(% D D ' & 3(( , ( 90 XR82C684 %'( ('( +% ,(%% # < !(( & . 47 8% $+ !(( & . ( D 8 -GG!H +4 8) P@.Q Figure 32. A Block Diagram of the Circuitry Associated with Counter/Timer #1 %'( ('( +% ,(%% # < !(( & . 47 8% $+ !(( & . ( D 8 -GG!H + 8! P@.Q Figure 32A. A Block Diagram of the Circuitry Associated with Counter/Timer #2 9 XR82C684 C/T Mode 3(' ( ' '6 ( % * ' % * -( ,(%%# < - ' % % , ( , ( ' .8 ' '6 * & ( ( & )2 %I3# (,( ( , * -D (% + ( # +4 E%# %I3# (,( ( , * -D (% + ( # + Bit 6 Bit 5 Bit 4 5" $ $+ 8 8 '6 * %( 8) 8 '6 * ) %( 8-<= $ !(( & . ( 5" $ $+ ( 5" $ $+# !(( & . $* - (% , ( ( # *I '& * % ( , - %I 3 ' "%% % * 3%7 ( 8-<= $ - I '& L ( 8-<= $ !(( & . Timing Source Frequency of Selected Timing Source T PCTURQ T 0 + PCTLRQ Note: The "shaded" options are only available in the 68 pin PLCC. Table 13. ACR1[6:4] Bit Field Definition - C/T#1 37 P Q L ' % * ,(% ( '( * Bit 6 Bit 5 Bit 4 C/T Mode 5" $ $+ P5: (& (* /E( +(& 1 (% , % * * ' (& ( (* / ' +(&1 (% , $ (! ( % '% % * -! * , ( (% ( % **' (* /: +(&1 (% % ' ( P@74Q MR1n[6] - Receiver Interrupt Select (% ( % '% ( 8!H %% ( << %% ( * ' % % '(( * , ( , $ I% + # %( , * 3( , $ % ,(% (%7 $PQ# $P9Q# $PQ# $P9Q * % # )# !# %'( & MR1n[1:0] - Bits per Character Select '% * (% %( '( ( *( * '' (% % ( ' # +$H# + (% Mode Register 2 (Channels A, B, C and D) MR1n[5] - Error Mode Select * ' (% ''%% 3 K% + ( ( % # 3(' ''% * & ''%% K% ,(% %I /%1 /3(%1 % ' , ' % * ( (% ( ' % ( * $ %% (% +5# 5# '( )6 * $* (% ( (% % /1# (% (' ' 3( ( /'1 5 $* (% (% (% % /1# (% (' ' 3( ( /) '61 5 MR2n[7:6] - Channel Mode Select $ '' % %% (% & & '' (% ' & * $ $ '6 # % (% % ' ( ,(' * %% * ''% ' ( , * 5' ' ( * * % ( , PB7.Q L ' *(,% ' ( : $ (% # 0 XR82C684 '( %( ( & Figure 42 % % (, ('( , : ( ( , PB7.Q L '% ' ( (' 5' # 3(' (' & % (% '( Figure 44 % % ( , ('( , (' 5' ( * 3( , ' (( % & 3( ( (% 8 $ ' ( , ( ! 8! 8 '( (* ,(% %( (* ,(% 8! , ( , ( ! %( ; ( , ,(% '( ; ( , ,(% 0 0 ! )% + * + ! )% & + Figure 43. A Block Diagram Depicting Normal Mode Operation 0 XR82C684 8 $ ' ( , ( ! 8! 8 '( (* ,(% %( (* ,(% 8! , ( , ( ! %( ; ( , ,(% '( ; ( , ,(% 0 ! )% & + + ;% : ''%% %( Figure 44. A Block Diagram Depict Automatic Echo Mode '( (% %( ' K% 8! . '( 6 (% ' % '( ( " ( % ( (% ' '( % %( B + '( ' ('( % % &# + %( ( 6 (% (% 5' ' ' ' *(, ( (, %(' % 4 ' K% 8!H 85 %% (% ( '( @ '( (& (% ''6 (% , * %(%%( %# %( (& (% % '( * 3 Local Loopback Mode (% (% % ' & %( , PB7.Q L Figure 45 (% (, ('( , < ' < '6 ( 9 ' *( , (% ''6 % (% %( % '( 04 XR82C684 > 8 8! '( (* ,(% %( (* ,(% 8! %( ; ( , ,(% '( ; ( , ,(% 0 0 ! )% + * + ! )% & + Figure 45. A Block Diagram Depicting Local Loopback Mode Operation $ (% 7 @ ' K% 8! ( (% (, %( (% ( & ' ' '( ( 9 %( (% # '( %( ' '6 (% % * '( . + %( '( ' ('( % ' ( & 4 ' K% 8! (% 6( , (, 0@ XR82C684 Remote Loopback Mode (% (% % ' & %( , PB7.Q L Figure 46 % % (, ('( , < '6 ( $ ' ( , 8! ( ! 8 8 '( (* ,(% %( (* ,(% 8! , ( , ( ! %( ; ( , ,(% '( ; ( , ,(% Note: The CPU has no access ot the Serial Data during Remote Loopback Mode. Figure 46. A Block Diagram Depicting Remote Loopback Mode $ (% F MR2n[4] - Clear to Send Control '( (% %( ' K% 8! $* (% ( (% # ' % ( $+ * # $+ * )# $+0 * # $+ * ! % **' %( $* ( (% /1# %( 3( ''6 % * (% ( ' ( (% ( & % '' $* (% 3 /1# '' (% %( $* (% (, ,# 8! ( % ( 6( , % %(%%( * " '' (% & ( , % 3 ,% ( ( 3( '' (% ( , %( (J **' %(%%( * '' (% (% * ( % ( Figure 47 Figure 49 '( (% % + %% ' (( % ''6 4 +(& *( , % (% %( % '( @ '( % 9 '( 6 (% ' % '( ( " ( % ( (% ' MR2n[5] - Transmitter Request-to-Send Control MR2n[3:0] - Stop Bit Length ( ( &# I% (% %% , & ( 6( , / + )(% 1 / + )(% 1 ( ( # & %&% % *3 ; 3# %( , P9Q L 3% %( , (' &# ( ( * ''% ( ; %( 3 & (% ( *( ,% ( * % (% ' %( '' ( ( * -. ( ( -. ( (%# ( ( ' % * -. (% ' , * '' ,% * .# B 0 (% 9 ( ''# % ( ( ' , * -. ( (% $* " " ' '6 (% , * %( ' '6 8 # P4Q L % '% % ( ( * ( ( P4Q L % '% ( * 3 ( (% * %(%%( Figure 49 % % (, ( % 3 %( I% ' *(,( 3 * '( 09 XR82C684 '( $ % ( (' % %* ( %&%% 3% + ''6 % (* %( (% & - (% & * * + $ % ( (' % % ( (' 3 ; % ''# 3(' (% 3(( , & + # (% * ( ' * '(( , & ''% 3( %( '( $ %% ( (' % ' ( 3 ( * % ,(% '( & ''6% * 6 ' (( ' * *(% % ( (%# ( ( * % (& ( (% % , %% * , %( % ( , $* '( % % /61 / 5 1 5 (% * ,, ( % ,(% G.4 Status Register, SRn ' % ,(% (% % 3( %% ; ; '( %( $%# %'( &F %% ( + 3( % * I (& * '( * & ( * % ,(% % % * & '( % (* * % ,(% (%'%%( * ' ( * 3%7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Received Break Framing Error Parity Error Overrun Error TXEMT TXRDY FFULL RXRDY L: L: L: L: L: L: L: L: L H% L H% L H% L H% L H% L H% L H% L H% Table 27. Status Register - SRA, SRB, SRC, SRD % '( ''%# ( /% 5 %1 ' % ( 6 SRn[7] Received Break (% ( ( ('% J '' * , '' , 3% '( 3( % ( & %( , $ %(( (% ''( 3 6 (% '( (( %*% ( $ ( (( ( 8! ( % 6( , % * % * ( ( (% (% *( % 3 %''%%( ,% * ( " " ' '6 SRn[6] Framing Error 3( , '( * '' (%# & %% '( (& (# '( 3( ''6 * /61 ' (( (( * 3( , % (& ( (% /61 ' (( (% + ( $* '( % ' /61 (% (# ( (% ,, /(,1 * ,,( , '' ' * 5 5 E (% ( (% %# ' K% / , $ )6 %1 ( ( $ (% % ( ( $ (% % % 3 * 6 ' (( # % *( # (% ' $* 5 % % /'1 # (% ( & (% ' * ; $* (% ( (% % * ,( ''# ( 3( ' (* + ( (% & ' ( " '' '(K% 6 ' ,(' ' ' 6% ,( ( ( * '' ; 3# 6 % %(% ( * " '' ( ( * ( ' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( /% 5 %1 ' % ( 6 % % Table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( %# * %%I ''%# ( * ' (( * % '( ''%# ( /% 5 %1 ' % ( 6 $* 5 # * ' # % % /'1 # (% ( & (% ' * ; (% ( 3( ' (* 8! ( (% , ,(' /(,1 # ( " '' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( /% 5 %1 ' % ( 6 % % Table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( %# * %%I ''%# ( * ' (( * SRn[5] Parity Error (% ( (% % 3 /E( +(&1 / ' +(&1 % , (* ' % ( , '' ( $ 3% '( 3( ( ' ' (& 0. XR82C684 (# $ %(( % ''( $ (% % 3 + % ; $* '' (% 3(( , ( '% $ (% * # << 3( % 3 + % ; $* 5 % % /'1 # (% ( & (% ' * ; $* (% ( (% % * ,( ''# ( 3( ' (* '( (& (% ' ' ( " '' $* /5 1 % % /) '61 # (% (# ' % 3( ( %% ( /% 5 %1 ' % ( 6 % % Table 2 + % (* 5 (% /) '61 (% (# ( % ,(% 3( ( %# * %%I ''%# ( * ' (( * % '( ''%# ( /55 5 1 ' % ( 6 SRn[0] Receiver Ready (RXRDY) (% ( ( ('% % '' % '( (% 3(( , ( $ & + $ (% % 3 '' (% %* * ; (% ' 3( + % % '' ' & % ( $ + % % * ' (( % * ,, & % ,(% ' % , , $ I% + ; 3# % ' (( % * ,, & % ,(% ' , , $ % ' (( % (% 37 SRn[4] Overrun Error $* %# (% ( ( ('% ''% ( '( %# ( (% % '( * 3 '' 3 $ (% * '' (% & ( 3(( , * & $ %(( E (% ''%# '' ( (% 3( P.Q ( , 5 + % (6 % ,(% (% * 5 ( , 5 # +5 +(& 5 ) '( )6# 5 5 ( (' (% 3&% * ,, /) '61 5 %(% 5 ' (( (% * ,, '' '' %(%# & ' 3 /% 5 %1 ' (% ( 6 P9Q +(& 5 SRn[3] Transmitter Empty (TXEMT) H. Special Modes Of Operation P@Q 5 * # (* %&% ''6( , (% &# % (% ' ( ' '' & ''6( , % ,(% (% ( (% % 3 %( % $ (% % * %(%%( * % % ( * '' (* (% '' ( ; 3(( , %(%%( (% ( (% ' 3 %( (% (% # 3 + 3(% 3 '' ; H.1 RTS/CTS Handshaking ' , % - ; %6( ,# % % * * 3 ' 3( ('% (% %'( 3( %'( ' * ( % 3% % ( ( ( , - ; %6( , '(*(' &# % ( % 7 SRn[2] Transmitter Ready (TXRDY) (% (# 3 %# ( ('% ; (% & & '' '' * + ( (% ' 3 + 3(% 3 '' ;# (% % 3 '' (% %* 8!H (% % 3 %( (% ( (( & (% % 3 %( (% (% '% ( ; 3( %( (% (% 3( %( '( - ; %6( , %( - ; %6( , H.1.1 Receiver-Controlled RTS/CTS Handshaking $ (% # '( % ( (& (' & , %(( , (' '(*(' &# (% 3% '( , %(, (* (% ; (% * F # (% &# & **'( ( ( , '( 5 % Figure 47 % % (, * " ( %( , ( * '( ' *(,( SRn[1] FIFO Full (FFULL) (% ( (% % 3 '' (% %* * ; %* '%% ( ' * # 0B XR82C684 %(( , !(' '(( , !(' + << ) $+ 8! 8!) 8! 8!) $+ ) + +@ + << 8! Figure 47. Block Diagram and Timing Sequence of two QUARTs connected in the Receiver-RTS Controlled Configuration Figure 47 % 3% 3 ('%# /'(( , !('1 / %(( , !('1 % ('% %' '% * ( ( (% " %* * 3 (% " (% , ( , (, # * ( ( ,# *' /'(( , !('1 % %( / %(( , !('1 % '( # (% " # (% %( , * /'(( , !('1 ) * / %(( , !('1 $* ; * /'(( , !('1 (% * % (' & << ( , ,(' /(,1# 3( (' & , & ( * '( *% %I &# ) %( * / %(( , !('1 3( (% ) ( , 3( ( %( & 8! * /'(( , !('1 $* + % / %1 ; * '(( , !('# ; 3( , * # << ( (' 3( ,, * % $ (% '%# << ( (' (% ' ' % ( * + $ % % << ,, ( , * %# + 3 ( (% / ,(,1 * << % $ I% + 3 %(' (% /$ 1 & /3(( ,1 P!B##!Q L P# # # # # # # Q %% 5 (% '( "'% / + )(% D :!1 '%% +PQ ,, /(,1 + ( + ,, / 31 %I &# (% 3 %% " %% 3( %%( /'(( , !('1 % , %' PBQ L '' ( , Section G.3# (% % % ( ,( , /'(( , !('1 * '( (( &# / %(( , !('1 % , %' )P@Q L '' ( , Section G.3# %( * ) * / %(( , !('1 % 3 , ) ( ' $ (% " # /'(( , !('1 ' % %(, (% %(, (% * (' & ( ) ( * %(( , !(' E( * /'(( , !('1 ( , %% ( * / %(( , !('1 (% 00 XR82C684 3 %%# % 3 %(%%( * / %(( , !('1 /'(( , !('1 (% 3 ( !('1 (% 3 (' & , ( '( ' %(, * # %(%%( * ) * %(( , !(' (%# ' ,( # ( (( Figure 47 % 3% 8! ( '(( , * % %% ; 3# ( (% " # (% 3 & '( '' 3 '%% ; * /'(( , !('1 * << ( (' %% (% 3 %% * /'(( , Figure 48 % % * 3 (, ( %( , , ( ' % ( ( ( , '( - ; %6( , '(( , !(' PBQ L %(( , !(' )PBQ L %% E( %% 5 (% ( 6% /5 + + )$ D :!1 %% + ( # + ,(' /1 : $% << %%V : H% (% (' & :, & '( '( $% << :,V H% Figure 48. A Flow Diagram Depicting An Algorithm That Could Be Used to Apply The Receiver-controlled RTS/CTS Handshaking Mode 0 XR82C684 '(( , !(' '(*(' &# (% 3% %( , %(, # ( ( * &( , (% ; H.1.2 Transmitter-Controlled RTS/CTS Handshaking $ (% # %( 3 % ( (& , %(( , !(' '(( , !(' + $+ ( $+ +4 8! 8!) 8!HG +. + 8!HG 8! Figure 49. Block Diagram and Timing Sequence of Two QUARTs Connected in the Transmitter-RTS Controlled Configuration Figure 49 % 3% 3 ('%# / %(( , !('1 # /'(( , !('1 (% " %% 3( %%( / %( !('1 % , %' P9Q L # 3(' % % ( ,( , / %(( , !('1 * %( (% " * %%% / %(( , !('1 % , %' P@Q L '' ( , Section G.3# %( * * / %(( , !('1 % 3 , ( ' $ '% * /'(( , !('1# $+ ( % , , /$ + , * 1 ( I% + *(3 * $ (' ( % (% 3( %' (* $+ ( 3 ' , $+PQ L # + 3 /3(1 P!B## !Q L P# # # # # # # Q %% 5 $ (% %# $ (' ( 3 ( 6 /5 + + )$ D :!1# ( '%% ,, +P4Q ,(' /(,1 + ( # +4# ,(' / 31 (% 3 # ( # %% ( * XR82C684 + )$ D :!1# ( '%% ,, +4 /(,1 (% 3 ( , ( * / %(( , !('1 ( (( %(%%( * * * / %(( , !('1 / %(( , !('1 3 ( %( /'(( , !('1 ' %( % ( (% ; * # ( 3( , # ( / %( 1 * E / %(( , !('1 (% ,, /(,1# $+ ( (% % ,, /(,1# & , ( , /$ , * 1 ( I% + E( $+PQ L # (6 & $ (' ( 3 /E(1 P!B## !Q L P# # # # # # # Q %% $ (% %# $ (' ( 3 ( 6 /<5 + Figure 50 % % 3 !(, 3(' ('% , ( ' % ( %( - ; %6( , + % % '6 ( '' '% 3(( /'(( , !('1 E% /E(1 '6 ( ( 3(( / %(( , !('1 2 /$ + , * 1 $ $+ ( '(( , !(' 5 E( %% 5 $:+ $ 55! ! %(%%( (% 3 ( $% 85 %%V 22<5 +4 G +$: /% . !( , ( # ' % "'(% (* ' % * ' ,(%% ' ,# %( ' '( ' ,% & % ( ( ( " # ' ,( , * (% '' 3( (% ( , '( & % ( '( * % '' $ , # ' ,% ,(%% 3(' ' '( %( ( % & 3( %( '( (% # '( ' ,% % % & 3 -K% % ( (& & " ' '6 %(, % ( (( , ) '6 8-<= ( ( (& ' *(, % + % * '( % 8!H 8!H- << ( (' % J. PROGRAMMING # ' # ' '6 % '# %% ,(%% (' * ' ' ( ( ( NO TAG %(J% ( %%(, % * ' ,(% ( * (% , & 3(( , ' 3 % ( ( ,(%%# 3( ( *'6 (% ( & %% ,(%% Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rx RTS Control Rx Int Select Error Mode Parity Mode Select Parity Select Number of Bits/Char. L: L8!H L L E( +(& L 5 L 9 L H% L << L ) '6 L ' +(& L L . L : +(& L B L (! L 0 Table 28. Mode Registers 1: MR1A, MR1B, MR1C, MR1D Bit 7 Bit 6 Channel Mode L : L 5' L < ' < L < Bit 5 Bit 4 Tx RTS Control CTS Enable Tx Bit 3 Bit 2 Bit 1 Bit 0 Stop Bit Length L: L: L 9.4 0 L 9.4 L H% L H% L .9 L .9 L .00 L .00 4 L B9 ) L B9 @ L 04 L 04 9 L 0B9 ! L 0B9 . L 40 5 L 40 B L L Table 29. Mode Register 2: MR2A, MR2B, MR2C, MR2D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Receiver Clock Select Transmitter Clock Select Table 6 Table 6 Table 30. Clock Select Registers: CSRA, CSRB, CSRC, CSRD 9 Bit 0 XR82C684 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Miscellaneous Commands Enable/Disable Tx Enable/Disable Rx " ( Section B.2 L : , L : , L 5 " L 5 " L !(% " L !(% " L : 3 L : 3 ! : % ! : % Table 31. Command Registers: CRA, CRB, CRC, CRD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Received Break Framing Error Parity Error Overrun Error TXEMT TXRDY FFULL RXRDY L: L: L: L: L: L: L: L: L H% L H% L H% L H% L H% L H% L H% L H% Table 32. Status Registers: SRA, SRB, SRC, SRD Bit 7 Bit 6 Bit 5 Bit 4 OP7 OP6 OP5 OP4 Bit 3 Bit 2 Bit 1 OP3 Bit 0 OP2 L+PBQ L+P.Q L+P9Q L+P@Q L +P4Q L +PQ L8!H) L8!H L8!H <<) L8!H << L - D L 8 .8 L 8) 8 L 8 8 L 8) 8 L 8 8 Table 33. Output Port Configuration Register 1: OPCR1 Bit 7 Bit 6 Bit 5 Bit 4 OP7 OP6 OP5 OP4 Bit 3 Bit 2 Bit 1 OP3 Bit 0 OP2 L+PBQ L+P.Q L+P9Q L+P@Q L +P4Q L +PQ L8!H! L8!H L8!H <B $>. $>9 $>@ $>4 $> $> $> Table 45. Interrupt Vector Register: IVR (applies to IVR1 and IVR2) K. Timing Diagrams > @> > % < % 0> 0> Figure 55. Input and Output Levels for Timing Measurements Note: AC testing inputs are driven at 0.4V for a logic "0" and 2.4V for a logic "1" except for -40 to 85C and -55 to 125C, logic "1" shall be 2.6V. Timing measurements are made at 0.8V for a logic "0" and 2.0V for a logic "1". 0 XR82C684 55 .0 55 00 5 Figure 56. Reset Timing @ ; ; E! ! E !! ! !B < ! : ><$! ><$! < E! E ! !; ! !B E( ><$! Figure 57. XR82C684 Read and Write Cycle Timing (88 Mode) XR82C684 $: $; $= $ E ! 5$ ! !B ! !! : > ( >' $5$ $5 !$ 5! !$ % $ Figure 58. XR82C684 Z Mode Interrupt Cycle Timing (88 - Mode) XR82C684 8-<= ; 9 E E; -E E !! ! ! !B ! !< != !; ! Figure 59. XR82C684 Read Cycle Timing (68 - Mode) ; 9 E E; -E E ! ! !B !< ! != !; ! Figure 60. XR82C684 Write Cycle Timing (68 - Mode) XR82C684 8-<= $: $= !! ! ! !B >5 !< ! != !; ! ! Figure 61. XR82C684 Interrupt Cycle Timing (68 - Mode) ! +; + $+ $+9 E + +9 ! :3 ! +! Figure 62. Port Timing XR82C684 ! E $ $ Figure 63. Interrupt Timing 7 N & S 9 7 N & S 9 7 9 N & S 9 7 7 9 N & S 9 7 8 8 XR82C684 XR82C684 4.0.@;J 8 B4B;J 8 + % &% + % &% 8-<= - <= <= 8 8 8 <= 8 Figure 64. Clock Timing 4 XR82C684 )( ( . '6% 8 $ 8! 8! 8 8 Figure 65. Transmitter Timing 8 8 $ 8 8; 8! Figure 66. Receiver Timing @ XR82C684 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 C D D ( , + 45 x H1 45 x H2 A2 @@ B1 D D1 B D 2 D3 e R D3 A1 A INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX .9 0 @ @9B 49 RRR 9 RRR ) 4 44 94 ) . 4 .. 0 0 4 4 ! .09 .9 B@ B.9 ! .9 .9. .9 ... ! 9 .4 @ . !4 9 & 9 ) B & B ) ; @ 9. B @ ; @ @0 B 9 @9 .@ @ Note: The control dimension is the inch column 9 XR82C684 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 C D D ( , + 45 x H1 A2 45 x H2 .0 B1 B D D2 D3 D1 e R D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX .9 @ 90 4 44 RRR 9 RRR ) 4 44 94 ) . 4 .. 0 0 4 4 ! 09 9 9 9B ! 9 90 @4 @44 ! 0 4 . 4. !4 0 & 9 ) 4 & B ) ; @ 9. B @ ; @ @0 B 9 @9 .@ @ Note: The control dimension is the inch column . XR82C684 :$5 58 ( %% (, 6 ' ,% '% ' ( ( (% ('( ( ( %(, # * ' (( (& 58 ( %%% % %(( (& * % * & '('(% %'( ( # ' &% (' % & (,# 6% % ( '('(% * * ( *( , % %' % ' ( ( & * ( %( %% & & ( , %K% %'(*(' ('( E( ( * ( ( (% ('( % '* & ''6F % %(( (&# 3# (% %% * ( '''(% 58 ( % ' % * & * (% '% ( (* % ('( % 3 *( * '( * ' ' % & "' '% *( * (* % %&% %(, (*(' & **' (% %*& **'( %% + '% (J * % ( %' ('( % %% 58 ( '(%# ( 3(( ,# %% '% (% %(%*'( 7 (%6 * ( C& , % ( ((JF % %%% %' (%6%F ' ( (( (& * 58 ( (% I & ' '(' % '% &(, 58 ( !% '( # ( 3 # 3( ( 3( ' % * 58 ( (% (( B