Feature List, P re liminary, Apr. 2001 TC11IB 3 2 -B it S in g l e -C h i p M i c r o c o n t ro l l e r M i c r o c o n t ro l le r s N e v e r s t o p t h i n k i n g . Edition 2001-04 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Feature List, P re liminary, Apr. 2001 TC11IB 3 2 -B i t S i n g l e - C h i p M ic r o co n t ro l l e r M i c r o c o n t ro l le r s N e v e r s t o p t h i n k i n g . TC11IB Revision History: 2001-04 Previous Version: - Page Preliminary Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Advance Information TC11IB 32-Bit Single-Chip Microcontroller TriCore Family * High Performance 32-bit TriCore CPU with 4-Stage Pipeline running at 96MHz Clock * Dual Issue super-scalar implementation - MAC Instruction maximum triple issues * Circular Buffer and bit-reverse addressing modes for DSP algorithms * Flexible multi-master interrupt system * Very fast interrupt response time * Hardware controlled context switch for task switch and interrupts * Windows CE compliant Memory Management Unit (MMU) * 64 kByte of on-chip SRAM for data and time critical code * Independent Peripheral Control Processor (PCP) for low level driver support with 20 kByte code / parameter memory * eDRAM Local Memory Unit (LMU) with 512 KBytes Code/data Memory. * ComDRAM with 1MBytes DRAM Memeory * High Performance Local Memory Bus (LMB) for fast access between Caches and onlocal memories and Fast-FPI Interface. * Two On-chip Flexible Peripheral Interface Buses (Fast FPI Bus and Slow FPI Bus) for interconnections of functional units * Flexible External Bus Interface Unit (EBU) used for communication with external data memories such as PC 100 SDRAM, Burst Flash and SRAM etc. and external peripheral units , including Intel styple and Motorola style peripherals. * On-Chip Peripheral Units - Two Multifunctional General Purpose Timer Units (GPTU0 & GPTU1) with three 32bit timer/counters each - Asynchronous/Synchronous Serial Channels (ASC) with IrDA data transmission , receive/transmit FIFOs, parity, framing and overrun error detection - High Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - Asynchronous Serial Interface (16X50) with programmable XON/XOFF characters, Baudrate generator, receive/transmit FIFOs and standard modem interface support. - 16 MHz MultiMediaCard Interface (MMCI), a glueless interface to MultiMediaCard Bus, with bus clock generation, CRC protection and up to 2.5 MByte/s data communication. - Fast Ethernet Controller with 10/100 Mbit/s MII-Based physical devices support. - PCI V2.2 Interface with PCI Bus Power Management and DMA data transfer. - Watchdog Timer and System Timer * 16-bit digital I/O ports * On-Chip Debug Support (OCDS) Feature List 5 Preliminary, 2001-04 TC11IB Advance Information * * * * Power Management System Clock Generation Unit with PLL Ambient temperature under bias: -25 C to +85 C P-BGA-388-2 package Feature List 6 Preliminary, 2001-04 TC11IB Advance Information Logic Symbol A lternate F unctions G eneral C ontrol E B U C ontrol E thernet C lock TEST O scillator / P LL Figure 1 Feature List PORST HDRST NMI C F G [0:3] C P U C LK RD R D /W R W A IT SVM H LD A BREQ A LE RAS CAS C S [0:6] CSEMU C S G LB CSOVL CSFPI CKE M R _W RMW H O LD E B U C LK BAA ADV A C LK C M D E LA Y M II_T xC LK M II_R xC LK M II_M D IO TESTMODE T M _C T R L1 T M _C T R L2 C LK 42 P LL96_C trl P LL42_C trl X T A L1 X T A L2 V DDOSC V SSO SC V D D PLL96 V SS PLL96 V D D PLL42 V SS PLL42 P ort 0 16-B it P ort 1 16-B it 4 P ort 2 16-B it P ort 3 16-B it G P T U 0/1 S S C 0/1, M M C I, A S C , 16x50 E thernet, M M C I P ort 4 16-B it E xternal Interrupts P ort 5 16-B it MMCI A D [0:31] B C [0:3] A [0:23] OCDS/ JT A G C ontrol O C D S 2P S [0:4] 7 O C D S 2P C [0:7] E B U C ontrol O C D S / JT A G C ontrol O C D S 2B R K [0:2] P _A D [0:31] P _C /B E [0:3] TC 11IB 2 20 21 52 P _P A R P _S E R R P _P E R R P _S T O P P _D E V S E L P _T R D Y P _F R A M E P _IR D Y P _LO C K P _IN T A P _IN T B P _P M E P _R E Q P _G N T P _ID S E L P _C LK 33 V LM UR EF V C O M R EF V DDDRAM VDDP VDD V SS PCI D igital C ircuitry P ow er S upply M C B04945 TC11IB Logic Symbol 7 Preliminary, 2001-04 TC11IB Advance Information Pin Configuration 10 1 2 3 4 5 6 7 8 9 HD R ST P 1.15 P1.13 P1.11 P 1.7 P 1.4 P1.0 P2.12 P2.10 B OCDS 2 P S [2 ] NMI P1.14 V DD P 1.8 P 1.5 P1.1 P2.14 P2.11 P2.8 C OCDS 2 P C [7] CPU C LK PO RST P1.12 P 1.9 P 1.6 P1.2 P2.15 P2.13 P2.9 D OCDS OCDS OCDS 2 P C [4] 2P S [1] 2P S [4] V SS P 1.10 V DD P1.3 V DDP V SS VDD A 11 12 14 13 15 V DD V SS M II_ M II_ X T A L2 X T A L1 M D IO T x C LK P LL42 PLL96 V DD P LL42 V D D C T R L PLL96 V SS TM M II_ R x C LK C TR L2 PLL42 V DDP C LK 42 V SS 16 17 18 19 20 21 22 23 24 25 V LM U V DD P2.3 P 2.1 A LE CS G LB B AA H LD A A [20] A D [31] REF DRAM P LL96 CTRL P 2.7 P2.5 P2.2 ADV C S F PI CMDE BR E Q LAY A[21] A D [23 ] A D [30] A D [2 9] B V SS TM C T R L1 P 2.6 P2.4 P2.0 W A IT CS OVL M R _W H O LD A[22] A D [22 ] A D [21] A D [2 8] C V DDP R es er v ed V DDP V DD V SS V DDP S VM V DD OSC VDD A[23] E OCDS OCDS OCDS OCDS G OCDS 2 P C [0] V DD OCDS OCDS OCDS 2B R K 2 B R K 2B R K [0] [1] [2] A D [20 ] A D [27] A D [2 6] D 38 8 -P in P -B G A P ackag e P in C o nfig ura tion (to p view ) fo r TC 1 1IB V DD A D [17 ] A D [16] A D [1 5] F AD [7] A D [6] A D [14] A D [1 3] G H V DD OCDS _EN V DDP V DDP A D [5] A D [12] A D [1 1] H J CFG [2] CFG [3] BRK _O U T V SS V SS A D [4] AD [10] AD [9] J K P0.0 CFG [0] CFG [1] V DD V DD A D [2] A D [3] AD [8] K L P0.3 P0.2 P 0.1 V DDP V SS V SS V SS V SS V SS V SS V DDP A D [1] A D [0] BC [2] L M P0.4 P0.5 P 0.6 P0.7 V SS V SS V SS V SS V SS V SS A C LK B C [3] B C [0] BC [1] M V SS V SS RD/ WR CAS EB U C LK N C S [6] RAS C KE P N P P0.8 P0.11 P0.9 P 0.12 BRK _ IN V SS A D [1 9] A D [18 ] A D [25] A D [2 4] E 2 P C [3] 2P C [6 ] 2P S [0] 2 P S [3 ] F OCDS OCDS OCDS 2 P C [1] 2P C [2 ] 2 P C [5] 26 R eser A v ed P0.10 V DDP P0.13 V SS V SS V SS V SS V SS V SS V SS V DDP V SS V SS V SS V SS V SS A[17] A [18] A[19] C S[5] R V SS V SS V SS V SS V SS V DDP A [16] A[15] A [14] T V SS V SS V SS V SS V SS R P0.14 P 0.15 P 3.0 P3.1 V SS T P3.2 VDD P 3.3 V DDP V SS U P3.4 P3.5 P 3.6 V DD V DD A [12] A[11] A [13] U V P3.7 P3.8 P 3.9 V SS V SS A[1] A [9] A [10] V W V DD P 3.10 P3.11 V DDP V DDP A[2] A [7] A[8] W Y P3.12 P 3.13 P3.14 P3.15 C S[4] A[3] A [4] A[6] Y AA P4.0 P4.1 P 4.2 V DD V DD C S [3] A [5] A[0] AA AB P4.3 P4.4 P 4.5 P4.6 RMW C S [0] C S [2] RD AB AC AD P4.7 P4.10 P4.8 P 4.11 P 4.9 P4.14 V SS P5.2 P 5.3 P 5.6 V DD P 5.9 P 5.10 P 5.13 V SS VDD V DDP P_ PM E V DDP V SS P_ ID S E L V DDP P_ STOP VDD P _A D [13 ] V SS P_ C B E [0] CS EM U C S[1] AC TMS TDI VC OM R EF P_ GNT P_AD [30] P _A D [28] P_AD [26] P _A D [22] P_A D [20] P_ P_AD P_ [18] F R A M E T R D Y P_ PA R P _A D [15] P_AD [11] P _AD [9] P _A D [6] P_AD [2] P _A D [0] AD P_ IN T A P_ R EQ P_AD [29] P _A D [27] P_AD [24] P _A D [23] P_A D [19] P_AD [16] P_ SERR P _A D [14] P_AD [10] P _AD [7] P _A D [4] P_AD [1] R eser AE v ed P _ C L K P_AD [31] 33 D R AM P_ P_AD P _ C B E P _D E V P _ C B E P_AD [2] [1] [17] [12] SEL PERR P _AD [8] P _A D [5] P_AD [3] R eser A F v ed 23 24 25 V DDP AE P4.12 P 4.13 P 5.1 P5.5 P 5.8 P5.12 P 5.15 T R ST TEST MODE AF P5.0 P 4.15 P 5.4 P5.7 P 5.11 P5.14 TCK TDO R es er v ed P_ IN T B 1 2 3 4 5 6 7 8 9 10 11 12 VDD 13 V DDP P_AD P _C B E P_A D [3] [25] [21] 14 15 16 V DD 17 V SS P_ IR D Y 18 P_ LO C K 19 20 21 22 26 M C P 0 4 9 50 Figure 2 Feature List TC11IB Pinning: P-BGA-338 Package (Top view) 8 Preliminary, 2001-04 TC11IB Advance Information Table 1 Symbol Pin Definitions and Functions Pin P0 P0.01) P0.11) P0.21) P0.31) P0.4 P0.5 P0.6 P0.7 P0.81) P0.92) P0.102) P0.111) P0.121) P0.131) P0.141) P0.151) Feature List In Functions Out I/O K1 L3 L2 L1 M1 M2 M3 M4 N1 N2 N3 P1 P2 P3 R1 R2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Port 0 Port 0 serves as 16-bit general purpose I/O port , which is also used as input/output for the General Purpose Timer Units (GPTU0 & GPTU1) GPTU0IO0 GPTU0 I/O line 0 GPTU0IO1 GPTU0 I/O line 1 GPTU0IO2 GPTU0 I/O line 2 GPTU0IO3 GPTU0 I/O line 3 GPTU0IO4 GPTU0 I/O line 4 GPTU0IO5 GPTU0 I/O line 5 GPTU0IO6 GPTU0 I/O line 6 GPTU0IO7 GPTU0 I/O line 7 GPTU1IO0 GPTU1 I/O line 0 GPTU1IO1 GPTU1 I/O line 1 GPTU1IO2 GPTU1 I/O line 2 GPTU1IO3 GPTU1 I/O line 3 GPTU1IO4 GPTU1 I/O line 4 GPTU1IO5 GPTU1 I/O line 5 GPTU1IO6 GPTU1 I/O line 6 GPTU1IO7 GPTU1 I/O line 7 9 Preliminary, 2001-04 TC11IB Advance Information Table 1 Symbol Pin Definitions and Functions (cont'd) Pin P1 In Functions Out I/O P1.01) P1.11) A7 B7 I/O I/O P1.21) C7 I/O P1.31) P1.41) P1.51) P1.61) P1.71) P1.81) P1.91) P1.101) P1.111) P1.121) P1.131) P1.141) P1.151) D7 A6 B6 C6 A5 B5 C5 D5 A4 C4 A3 B3 A2 O I/O I/O I/O O I O O I I O I I Feature List Port 1 Port 1 serves as 16-bit general purpose I/O port, which also is used as input/output for the serial interfaces (SSC,ASC,16X50) and MultiMediacard Interface (MMCI) SCLK SSC clock input/output line MRST SSC master receive / slave transmit input/output MTSR SSC master transmit / slave receive input/output CLK MMCI clock output line CMD MMCI command input/output line DAT MMCI data input/output line ASCRXD ASC receiver input/output line ASCTXD ASC transmitter output line RXD 16X50 receiver input line TXD 16X50 transmitter output line 16X50 request to send output line RTS DCD 16X50 data carrier detection input line DSR 16X50 data set ready input line DTR 16X50 data terminal ready output line CTS 16X50 clear to send input line RI 16X50 ring indicator input line 10 Preliminary, 2001-04 TC11IB Advance Information Table 1 Symbol Pin Definitions and Functions (cont'd) Pin P2 In Functions Out I/O P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 C18 A19 B18 A18 C17 B17 O O O O O O P2.6 C16 O P2.71) P2.82) B16 B10 O I P2.92) P2.101) P2.112) P2.122) P2.132) P2.142) P2.152) C10 A9 B9 A8 C9 B8 C8 I I I I I I I Feature List Port 2 Port 2 serves as 16-bit general purpose I/O port , which is also used as input/output for Ethernet controller and MultiMediaCard (MMCI). MIITXD0 Ethernet controller transmit data output line 0 MIITXD1 Ethernet controller transmit data output line 1 MIITXD2 Ethernet controller transmit data output line 2 MIITXD3 Ethernet controller transmit data output line 3 MIITXER Ethernet controller transmit error output line MIITXEN Ethernet controller transmit enable output line MIIMDC Ethernet controller management data clock output line VDDEN MMCI power supply enable output line MIIRXDV Ethernet Controller receive data valid input line MIICRS Ethernet Controller carrier input line MIICOL Ethernet Controller collision input line MIIRXD0 Ethernet Controller receive data input line 0 MIIRXD1 Ethernet Controller receive data input line 1 MIIRXD2 Ethernet Controller receive data input line 2 MIIRXD3 Ethernet Controller receive data input line 3 MIIRXER Ethetrnet Controller receive error input line 11 Preliminary, 2001-04 TC11IB Advance Information Table 1 Symbol Pin Definitions and Functions (cont'd) Pin P3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 I/O R3 R4 T1 T3 U1 U2 U3 V1 V2 V3 W2 W3 Y1 Y2 Y3 Y4 Feature List I I I I I I I I I I I I I I I I I/O P4 P4.02) P4.12) P4.22) P4.32) P4.41) P4.51) P4.61) P4.71) P4.81) P4.91) P4.101) P4.111) P4.121) P4.131) P4.141) P4.151) In Functions Out AA1 AA2 AA3 AB1 AB2 AB3 AB4 AC1 AC2 AC3 AD1 AD2 AE1 AE2 AD3 AF2 I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O Port 3 Port 3 serves as 16-bit general purpose I/O port ,which is also used as input for external interrupts. INT0 External interrrupt input line 0 INT1 External interrrupt input line 1 INT2 External interrrupt input line 2 INT3 External interrrupt input line 3 INT4 External interrrupt input line 4 INT5 External interrrupt input line 5 INT6 External interrrupt input line 6 INT7 External interrrupt input line 7 INT8 External interrrupt input line 8 INT9 External interrrupt input line 9 INT10 External interrrupt input line 10 INT11 External interrrupt input line 11 INT12 External interrrupt input line 12 INT13 External interrrupt input line 13 INT14 External interrrupt input line 14 INT15 External interrrupt input line 15 Port 4 Port 4 is used as general purpose I/O port , 9 pins of which (P4.0 ~ P4.8) also serve as inputs for external interrupts. INT16 External interrrupt input line 16 INT17 External interrrupt input line 17 INT18 External interrrupt input line 18 INT19 External interrrupt input line 19 INT20 External interrrupt input line 20 INT21 External interrrupt input line 21 INT22 External interrrupt input line 22 INT23 External interrrupt input line 23 INTSKAN2 External PCI interrupt input line 12 Preliminary, 2001-04 TC11IB Advance Information Table 1 Symbol Pin Definitions and Functions (cont'd) Pin P5 In Functions Out I/O Port 5 Port 5 serves as 16-bit general purpose I/O port, 3 pins of which (P5.0, P5.2 and P5.15) serve as output lines for MultiMediaCard Interface (MMCI) also. DATRW MMCI data direction indicator output line P5.01) P5.11) P5.21) AF1 AE3 AD4 O I/O O P5.31) P5.41) P5.52) P5.61) P5.71) P5.82) P5.91) P5.10 P5.11 P5.12 P5.13 P5.14 P5.151) AC5 AF3 AE4 AD5 AF4 AE5 AD6 AC7 AF5 AE6 AD7 AF6 AE7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O HDRST1) A1 I/O Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog, power-down wake-up reset and eDRAM reset for a specific period of time. For a software reset, activation of this pin is programmable. PORST1) C3 I Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. NMI1) B2 I Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU. Feature List CMDRW MMCI command direction indicator output line ROD MMCI command line mode indicator output line 13 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out CFG02) CFG12) CFG21) CFG31) K2 K3 J1 J2 I I I I Operation Configuration Inputs The configuration inputs define the boot options of the TC11IB after a hardware-invoked reset operation. CPU CLK1) C2 O Clock Output TRST2) AE8 I JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. TCK1) AF7 I JTAG Module Clock Input TDI1) AD9 I JTAG Module Serial Data Input TDO AF8 O JTAG Module Serial Data Output AD8 I JTAG Module State Machine Control Input H2 I OCDS Enable Input A low level on this pin during power-on reset (PORST = 0) enables the on-chip debug support (OCDS). In addition, the level of this pin during power-on reset determines the boot configuration. H3 I OCDS Break Input A low level on this pin causes a break in the chip's execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. BRKOUT J3 O OCDS Break Output A low level on this pin indicates that a programmable OCDS event has occurred. E3 O Pipeline Staus Signal Outputs D2 O B1 O E4 O D3 O TMS1) OCDSE 1) BRKIN1) OCDS2 PS01) OCDS2 PS11) OCDS2 PS21) OCDS2 PS31) OCDS2 PS41) Feature List 14 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out OCDS2 PC01) OCDS2 PC11) OCDS2 PC21) OCDS2 PC31) OCDS2 PC41) OCDS2 PC51) OCDS2 PC61) OCDS2 PC71) G1 O F1 O F2 O E1 O D1 O F3 O E2 O C1 O OCDS2 BRK01) OCDS2 BRK11) OCDS2 BRK21) G2 O G3 O G4 O MII TXCLK2) A11 I Ethernet Controller Transmit Clock MII RXCLK2) C11 I Ethernet Controller Receive Clock MII MDIO2) A10 I/O Ethernet Controller Management Data Input / Output P_C/BE0 P_C/BE1 P_C/BE2 P_C/BE3 AC24 AF21 AF18 AF15 I/O I/O I/O I/O PCI Interface Command / Byte Enable Inputs / Outputs P_IDSEL AC15 I PCI Interface ID Select Input P_CLK33 AF11 I PCI Interface Clock Input P_REQ AE11 O PCI Interface Bus Request Output P_GNT AD11 I PCI Interface Bus Grant Input Feature List Indirect PC Address Outputs Break Qualification Lines outputs 15 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 AD26 AE25 AD25 AF25 AE24 AF24 AD24 AE23 AF23 AD23 AE22 AD22 AF22 AC22 AE21 AD21 AE17 AF17 AD17 AE16 AD16 AF16 AD15 AE15 AE14 AF14 AD14 AE13 AD13 AE12 AD12 AF12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCI Interface Address /Data Bus Input / Output Lines PCI Interface Address / Data Bus Line 0 PCI Interface Address / Data Bus Line 1 PCI Interface Address / Data Bus Line 2 PCI Interface Address / Data Bus Line 3 PCI Interface Address / Data Bus Line 4 PCI Interface Address / Data Bus Line 5 PCI Interface Address / Data Bus Line 6 PCI Interface Address / Data Bus Line 7 PCI Interface Address / Data Bus Line 8 PCI Interface Address / Data Bus Line 9 PCI Interface Address / Data Bus Line 10 PCI Interface Address / Data Bus Line 11 PCI Interface Address / Data Bus Line 12 PCI Interface Address / Data Bus Line 13 PCI Interface Address / Data Bus Line 14 PCI Interface Address / Data Bus Line 15 PCI Interface Address / Data Bus Line 16 PCI Interface Address / Data Bus Line 17 PCI Interface Address / Data Bus Line 18 PCI Interface Address / Data Bus Line 19 PCI Interface Address / Data Bus Line 20 PCI Interface Address / Data Bus Line 21 PCI Interface Address / Data Bus Line 22 PCI Interface Address / Data Bus Line 23 PCI Interface Address / Data Bus Line 24 PCI Interface Address / Data Bus Line 25 PCI Interface Address / Data Bus Line 26 PCI Interface Address / Data Bus Line 27 PCI Interface Address / Data Bus Line 28 PCI Interface Address / Data Bus Line 29 PCI Interface Address / Data Bus Line 30 PCI Interface Address / Data Bus Line 31 P_PAR AD20 I/O PCI Interface Parity Input / Output P_SERR AE20 I/O PCI Interface System Error Input / Output P_PERR AF20 I/O PCI Interface Parity Error Input / Output P_STOP AC20 I/O PCI Interface Stop Input / Output Feature List 16 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out P_DEVS EL AF19 I/O PCI Interface Device Select Input / Output P_TRDY AD19 I/O PCI Interface Target Ready Input / Output P_FRAM E AD18 I/O PCI Interface Frame Input / Output P_IRDY AE18 I/O PCI Interface Initiator Ready Input / Output P_LOCK AE19 I PCI Interface Lock Input P_INTA AE10 O PCI Interface Interrupt A Output P_INTB AF10 O PCI Interface Interrupt B Output P_PME AC12 O PCI Interface Power Management Event Output CS01) CS11) CS21) CS31) CS41) CS51) CS61) AB24 AC26 AB25 AA24 Y23 R26 P24 O O O O O O O EBU_LMB Chip Select Output Line 0 EBU_LMB Chip Select Output Line 1 EBU_LMB Chip Select Output Line 2 EBU_LMB Chip Select Output Line 3 EBU_LMB Chip Select Output Line 4 EBU_LMB Chip Select Output Line 5 EBU_LMB Chip Select Output Line 6 Each corresponds to a programmable region. Only one can be active at one time. CSEMU1) AC25 O EBU_LMB Chip Select Output for Emulator Region CSGLB1) A21 O EBU_LMB Chip Select Global Output CSOVL1) C20 O EBU_LMB Chip Select Output for Overlay Memory B20 I EBU_LMB Chip Select Input for Internal FPI Bus For external master to select EBU_LMB as target in the slave mode N26 O EBU_LMB External Bus Clock Output Derived from LMBCLK as equal, half or one-fourth of the frequency. CSFPI 1) EBUCLK Feature List 17 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out AD01) AD11) AD21) AD31) AD41) AD51) AD61) AD71) AD81) AD91) AD101) AD111) AD121) AD131) AD141) AD151) AD161) AD171) AD181) AD191) AD201) AD211) AD221) AD231) AD241) AD251) AD261) AD271) AD281) AD291) AD301) AD311) L25 L24 K24 K25 J24 H24 G24 G23 K26 J26 J25 H26 H25 G26 G25 F26 F25 F24 E24 E23 D24 C25 C24 B24 E26 E25 D26 D25 C26 B26 B25 A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EBU_LMB Address / Data Bus Input / Output Lines EBU_LMB Address / Data Bus Line 0 EBU_LMB Address / Data Bus Line 1 EBU_LMB Address / Data Bus Line 2 EBU_LMB Address / Data Bus Line 3 EBU_LMB Address / Data Bus Line 4 EBU_LMB Address / Data Bus Line 5 EBU_LMB Address / Data Bus Line 6 EBU_LMB Address / Data Bus Line 7 EBU_LMB Address / Data Bus Line 8 EBU_LMB Address / Data Bus Line 9 EBU_LMB Address / Data Bus Line 10 EBU_LMB Address / Data Bus Line 11 EBU_LMB Address / Data Bus Line 12 EBU_LMB Address / Data Bus Line 13 EBU_LMB Address / Data Bus Line 14 EBU_LMB Address / Data Bus Line 15 EBU_LMB Address / Data Bus Line 16 EBU_LMB Address / Data Bus Line 17 EBU_LMB Address / Data Bus Line 18 EBU_LMB Address / Data Bus Line 19 EBU_LMB Address / Data Bus Line 20 EBU_LMB Address / Data Bus Line 21 EBU_LMB Address / Data Bus Line 22 EBU_LMB Address / Data Bus Line 23 EBU_LMB Address / Data Bus Line 24 EBU_LMB Address / Data Bus Line 25 EBU_LMB Address / Data Bus Line 26 EBU_LMB Address / Data Bus Line 27 EBU_LMB Address / Data Bus Line 28 EBU_LMB Address / Data Bus Line 29 EBU_LMB Address / Data Bus Line 30 EBU_LMB Address / Data Bus Line 31 BC01) BC11) BC21) BC31) M25 M26 L26 M24 I/O I/O I/O I/O EBU_LMB Byte Control Line 0 EBU_LMB Byte Control Line 1 EBU_LMB Byte Control Line 2 EBU_LMB Byte Control Line 3 Feature List 18 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out A01) A11) A21) A31) A41) A51) A61) A71) A81) A91) A101) A111) A121) A131) A141) A151) A161) A171) A181) A191) A201) A211) A221) A231) AA26 V24 W24 Y24 Y25 AA25 Y26 W25 W26 V25 V26 U25 U24 U26 T26 T25 T24 R23 R24 R25 A24 B23 C23 D22 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RD1) AB26 I/O EBU_LMB Read Control Line Output in the master mode Input in the slave mode. RD/WR1) N24 I/O EBU_LMB Write Control Line Output in the master mode Input in the slave mode. WAIT1) EBU_LMB Address Bus Input / Output Lines EBU_LMB Address Bus Line 0 EBU_LMB Address Bus Line 1 EBU_LMB Address Bus Line 2 EBU_LMB Address Bus Line 3 EBU_LMB Address Bus Line 4 EBU_LMB Address Bus Line 5 EBU_LMB Address Bus Line 6 EBU_LMB Address Bus Line 7 EBU_LMB Address Bus Line 8 EBU_LMB Address Bus Line 9 EBU_LMB Address Bus Line 10 EBU_LMB Address Bus Line 11 EBU_LMB Address Bus Line 12 EBU_LMB Address Bus Line 13 EBU_LMB Address Bus Line 14 EBU_LMB Address Bus Line 15 EBU_LMB Address Bus Line 16 EBU_LMB Address Bus Line 17 EBU_LMB Address Bus Line 18 EBU_LMB Address Bus Line 19 EBU_LMB Address Bus Line 20 EBU_LMB Address Bus Line 21 EBU_LMB Address Bus Line 22 EBU_LMB Address Bus Line 23 C19 I/O EBU_LMB Wait Control Line 1) D20 O EBU_LMB Supervisor Mode Output 2) A20 O EBU_LMB Address Latch Enable Output RAS1) P25 O EBU_LMB SDRAM Row Address Strobe Output CAS1) N25 O EBU_LMB SDRAM Column Address Strobe Output SVM ALE Feature List 19 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out CKE1) P26 O EBU_LMB SDRAM Clock Enable Output 1) C21 O EBU_LMB Motorola-style Read / Write Output HOLD1) C22 I EBU_LMB Hold Request Input In External Master Mode: While HOLD is high,Tricore is operating in normal mode (is owner of the external bus). A high-to-low transition indicates a hold request from an external master.Tricore backs off the bus and activates HLDA and goes into hold mode. A low-to-high transitions causes an exit from hold mode.Tricore deactivates HLDA and takes over the bus and enters the normal operation again. In External Slave Mode: While both HOLD and HLDA are high,Tricore is in hold mode,the external bus interface signals are tristated. When Tricore is released out of hold mode (HLDA =0) and has completely taken over control of the external bus, a low level at this pin requests Tricore to go into hold mode again. But in any case Tricore will perform at least one external bus cycle before going into hold mode again. HLDA1) A23 I/O EBU_LMB Hold Acknowledge Input / Output In External Master Mode: OutPut. High during normal operation.When Tricore enters hold mode, it sets HLDA to low after releasing the bus. On exit of hold mode, Tricore first sets HLDA to high and then goes onto the bus again (to avoid collisions). In External Slave Mode: Input. A high-to-low transition at this pin releases Tricore from hold mode. MR/W Feature List 20 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out BREQ1) B22 O EBU_LMB Bus Request Output In External Master Mode: High during normal operation.Tricore activates BREQ earliest one clock cycle after activating HLDA, if it has to perform an external bus access. If Tricore has regained the bus, BREQ is set to high one clock cycle after deactivation of HLDA. In External Slave Mode: This signal is high as long as Tricore operates from internal memory. When it detects that an external access is required , it sets BREQ to low and waits for signal HLDA to become low. BREQ will go back to high when the slave has backed off the bus after it was requested to go into hold mode. RMW1) AB23 I/O EBU_LMB Read-Modify-Write Signal Line 1) BAA A22 O EBU_LMB Burst Address Advance Output For advancing address in a burst flash access ADV1) B19 O EBU_LMB Burst Flash Address Valid Output ACLK M23 O EBU_LMB Additional Clock Output Additional clock running equal, 1/2, 1/3 or 1/4 frequency of EBUCLK CMDELA B21 Y1) I EBU_LMB Command Delay Input For inserting delays between address and command. TEST MODE2) AE9 I Test Mode Select Input For normal operation of the TC11IB, this pin should be connected to Vss. TM CTRL1 C15 I Test Mode Control Input 1 For normal operation of the TC11IB, this pin should be connected to Vss. TM CTRL2 C12 I Test Mode Control Input 2 For normal operation of the TC11IB, this pin should be connected to Vss. CLK422) D12 I Test Clock 42 MHz Input For normal operation of the TC11IB, this pin should be connected to Vss. Feature List 21 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out PLL96 CTRL1) B15 I/O Test PLL96 Digital Input/Analog Output For normal operation of the TC11IB, this pin should be connected to Vss. PLL42 CTRL1) B12 I/O Test PLL42 Digital Input/Analog Output For normal operation of the TC11IB, this pin should be connected to Vss. XTAL1 XTAL2 A15 A14 I O Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. VDDOSC VSSOSC VDDPLL96 VSSPLL96 VDDPLL42 B14 - Main Oscillator Power Supply (1.8V) C14 - Main Oscillator Ground B13 - PLL96 Power Supply (1.8V) A13 - PLL96 Ground A12 - Test PLL42 Power Supply (1.8V) For normal operation of the TC11IB, this pin must not be connected. VSSPLL42 C13 - Test PLL42 Ground For normal operation of the TC11IB, this pin must be connected to Vss. VLMUREF A16 - LMU Reference Voltage VCOMREF AD10 - ComDRAM Reference Voltage VDDDRAM A17, AF13 - eDRAM Power Supply (1.8V) Feature List 22 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin VDD H1,W1 - T2,B4 B11, D6,F4 D10, D17, D21, F23, K4, K23, U4, U23, AA4, AA23, AC6, AC10, AC17, AC21 Core and Logic Power Supply (1.8V) VDDP D8, - D11, D14, D16, D19, H4, H23, L4, L23, N4, P23, T4, T23, W4, W23, AC8, AC11, AC13, AC16, AC19 Ports Power Supply (3.3V) Feature List In Functions Out 23 Preliminary, 2001-04 TC11IB Advance Information Table 1 Pin Definitions and Functions (cont'd) Symbol Pin In Functions Out VSS D4,D9 - ,D13, D18, D23, J4, J23, N23 P4,V4, V23, AC4 AC9 AC14, AC18 AC21 L14 to L16 M11 to M16 N11 to N16 P11 to P16 R11 to R16 T11 to T16 N.C. A15, A26, AE26, AF9, AF26 - Ground Not Connected These pins must not be connected. 1) These pins have an internal pull-up device connected. 2) These pins have an internal pull-down device connected. Feature List 24 Preliminary, 2001-04 1.8-3.3 V A[23:0] EBU_Control 24 EBU_LMB DMU (Data Memory Unit) 24 KB Scratch Pad RAM 8 KB Data Cache LFI Bridge 33 128 TriCore 1.3 CPU PMU (Program Memory Unit) 24 KB Scratch Pad RAM 8 KB Instruction Cache 64 Trace & OCDS Interrupt VDD LMU 512 KB eDRAM VSS 16 OCDS2 OCDSE SCU (PWR) Power Management, Watchdog Timer, Reset 25 BCU0 Fast FPI BUS ComDRAM 1 MB, 96 MHz FFI Bridge OCDS 4 K Data SRAM FPI Interface TC11IB Block Diagram 32 AD[31:0] Advance Information TC11IB Block Diagram MMU Block Diagram Figure 3 Feature List LMB (Local Memory Bus) 96 MHz, 64 Bit PCP Interrupt BCU1 Slow FPI BUS 8 Control BRKIN BRKOUT XTAL1 PLL 96 & 48 MHz Cerberus XTAL2 JTAG 5 JTAG I/O 16 K Code SRAM Fast FPI Bus 96 MHz, 32 Bit Slow FPI Bus (Flexible Peripheral Interface) 48 MHz, 32 Bit Boot-ROM 16 Kbytes 32 P_AD[31:0] P_Control 20 PORT4 16 MMCI 15 9 PORT5 16 Fast Ethernet PORT3 16 External External Interrupts Interrupts MDIO 1 3 16x50 XON/ XOFF 8 ASC FIFO, IrDA 2 SSC 3 GPTU1 3 Timers 8 GPTU0 3 Timers 8 PORT2 PORT1 PORT0 16 16 16 RxCLK TxCLK MCB04939 TC11IB Preliminary, 2001-04 3 PCI V2.2 33 MHz (DMA Support) + Power Management TC11IB Advance Information Parallel Ports The TC11IB has 96 digital input/output port lines, which are organized into six parallel 16-bit ports, Port P0 to Port P5 with 3.3V nominal voltage. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. An overview on the port-toperipheral unit assignment is shown in Figure 4. A lte rn a te F u n ctio n s G P IO G P IO G P T U 0 / G P T U 1 G P IO 0 A lte rn a te F u n ctio n s G P IO 3 E xte rn a l In te rru p ts TC 11IB A S C / S S C / M M C I / 1 6 x 5 0 G P IO 1 G P IO 4 E xte rn a l In te rru p ts P a ra lle l P o rts E th e rn e t / M M C I G P IO 2 G P IO 5 M M C I M C A 0 4951 Figure 4 Feature List Parallel Ports of the TC11IB 26 Preliminary, 2001-04 TC11IB Advance Information Serial Interfaces The TC11IB includes three serial peripheral interface units: - Asynchronous/Synchronous Serial Interface (ASC) - High-Speed Synchronous Serial Interface (SSC) - Asynchronous Serial Interface (16X50) Asynchronous/Synchronous Serial Interface Figure 5 shows a global view of the functional blocks of the Asynchronous/Synchronous Serial interface ASC. C lo c k C o n tro l fA SC R xD A d d re ss D ecoder ASC M o d u le P o rt C o n tro l T xD P 1 .6 / ASC _R xD P 1 .7 / A S C _ T xD In te rru p t C o n tro l M C B 04938 Figure 5 General Block Diagram of the ASC Interfaces ASC Module communicates with the external world via one pair of I/O lines. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC Module kernel. The Asynchronous/Synchronous Serial Interface provides serial communication between the TC11IB and other microcontrollers, microprocessors or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator Feature List 27 Preliminary, 2001-04 TC11IB Advance Information provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider Features: * Full duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baudrate from 3 MBaud to 0.71 Baud (@ 48 MHz clock) * Multiprocessor mode for automatic address/data byte detection * Loop-back capability * Support for IrDA data transmission. * Half-duplex 8-bit synchronous operating mode - Baudrate from 6 MBaud to 488.3 Baud (@ 48 MHz clock) * Double buffered transmitter/receiver * Interrupt generation - On a transmitter buffer empty condition - On a transmit last bit of a frame condition - On a receiver buffer full condition - On an error condition (frame, parity, overrun error) * FIFO - 8 bytes receive FIFO (RXFIFO) - 8 bytes transmit FIFO (TXFIFO) - Independent control of RXFIFO and TXFIFO - 9-bit FIFO data width - Programmable Receive/Transmit Interrupt Trigger Level - Receive and transmit FIFO filling level indication - Overrun error generation Feature List 28 Preliminary, 2001-04 TC11IB Advance Information High-Speed Synchronous Serial Interface Figure 6 shows a global view of the functional blocks of the High-Speed Synchronous Serial interface SSC. In te rru p t C o n tro l SSC M o d u le Slave Master A d d re s s D ecoder fSSC R xD T xD SCLK C lo c k C o n tro l S la ve M a s te r R xD T xD P 1 .2 / M T S R P o rt C o n tro l P 1 .1 / M R S T P 1 .0 / S C L K M C B 0 4952 Figure 6 General Block Diagram of the SSC Interfaces The SSC Module has three I/O lines, located at Port 1. The SSC Module is further supplied by separate clock control, interrupt control, address decoding, and port control logic. The SSC supports full-duplex and half-duplex serial synchronous communication up to 24 MBaud (@ 48 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Feature List 29 Preliminary, 2001-04 TC11IB Advance Information Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits: 2 to 16 bit - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock * Baud rate generation from 24 MBaud to 366.2 Baud (@ 48 MHz module clock) * Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) * Three-pin interface - Flexible SSC pin configuration Feature List 30 Preliminary, 2001-04 TC11IB Advance Information Asynchronous Serial Interface (16X50) The 16X50 is a universal asynchronous receiver/transmitter (UART) which is fully prorammable.It supports word lengths from five to eight bits, an optional parity bit and one or two stop bits.If enabled, the parity can be odd,even or forced to a defined state. The 16X50 includes a 16-bit programmable baud rate generator and an 8-bit scratch register, together with two 16-byte FIFOs -one for transmit and one for receive. It has six modem control lines and supports a diagnostic loop-back mode. An interrupt can be generated from any one of 10 sources. Figure 7 shows a global view of the functional blocks of the Asynchronous Serial Interface (16X50). C lo c k C o n tro l P 1 .1 5 / 1 6 x 5 0 _ R I f 1 6x5 0 P 1 .1 4 / 1 6 x 5 0 _ C T S P 1 .1 3 / 1 6 x 5 0 _ D T R A d d re s s D ecoder 1 6 x5 0 M o d u le P o rt C o n tro l P 1 .1 2 / 1 6 x 5 0 _ D S R P 1 .1 1 / 1 6 x 5 0 _ D C D P 1 .1 0 / 1 6 x 5 0 _ R T S P 1 .9 / 1 6 x5 0 _ T xD In te rru p t C o n tro l P 1 .8 / 1 6 x5 0 _ R xD M C B 04 937 Figure 7 General Block Diagram of the SDLM Interface The 16X50 Module communicates with the external world via five input and three output lines located at Port 1 The 16X50 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 16X50 represents such an integration with greatly enhanced features. The 16X50 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The 16X50 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 16X50 by the larger transmit and receive FIFO's. This allows the external processor to handle more networking tasks within a Feature List 31 Preliminary, 2001-04 TC11IB Advance Information given time. The 4 selectable levels of FIFO trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 16X50 is capable of operation to 3 Mbps with a 48 MHz clock input (f16X50). Features: * * * * * * * * * * * Software upward compatible with the NS16550A Standard modem interface Programmable word length, stop bits and parity Programmable baud rate generator Interrupt generation Diagnostic loop-back mode Scratch register Automatic hardware/software flow control Programmable XON/XOFF characters Independent transmit and receive control FIFO - 16 byte transmit FIFO - 16 byte receive FIFO with error flags - Four selectable receive FIFO interrupt trigger levels Feature List 32 Preliminary, 2001-04 TC11IB Advance Information Timer Units The TC11IB includes two timer units: - General Purpose Timer Units, GPTU0 and GPTU1. General Purpose Timer Unit Figure 8 shows a global view of all functional blocks of the two General Purpose Timer Unit (GPTU0 & GPTU1) Modules. IN 0 C lo ck C o n tro l fG P T U0 IN 1 IN 2 IN 3 P 0 .0 / G P T U 0 _ IO 0 IN 4 A d d re s s D ecoder IN 5 P 0 .1 / G P T U 0 _ IO 1 IN 6 P 0 .2 / G P T U 0 _ IO 2 IN 7 SR0 In te rru p t C o n tro l G PTU0 M o d u le P o rt C o n tro l OU T0 SR1 OU T1 SR2 OU T2 SR3 OU T3 SR4 OU T4 SR5 OU T5 SR6 OU T6 SR7 OU T7 P 0 .3 / G P T U 0 _ IO 3 P 0 .4 / G P T U 0 _ IO 4 P 0 .5 / G P T U 0 _ IO 5 P 0 .6 / G P T U 0 _ IO 6 P 0 .7 / G P T U 0 _ IO 7 IN 0 C lo ck C o n tro l fG P T U1 IN 1 IN 2 IN 3 P 0 .8 / G P T U 1 _ IO 0 IN 4 A d d re s s D ecoder IN 5 P 0 .9 / G P T U 1 _ IO 1 IN 6 P 0 .1 0 / G P T U 1 _ IO 2 IN 7 SR0 In te rru p t C o n tro l G PTU1 M o d u le P o rt C o n tro l OU T0 SR1 OU T1 SR2 OU T2 SR3 OU T3 SR4 OU T4 SR5 OU T5 SR6 OU T6 SR7 OU T7 P 0 .1 1 / G P T U 1 _ IO 3 P 0 .1 2 / G P T U 1 _ IO 4 P 0 .1 3 / G P T U 1 _ IO 5 P 0 .1 4 / G P T U 1 _ IO 6 P 0 .1 5 / G P T U 1 _ IO 7 M C B04943 Figure 8 Feature List General Block Diagram of the GPTU Interface 33 Preliminary, 2001-04 TC11IB Advance Information Each GPTU module, GPTU0 and GPTU1, consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. And each GPTU module communicates with the external world via eight I/O lines located at Port 1. The three timers in each GPTU Module T0, T1, and T2, can operate independently from each other or can be combined: General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU. Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events * Two input pins can determine a count option Features of T2: * Count up or down is selectable * Operating modes: - Timer - Counter - Quadrature counter (incremental/phase encoded counter interface) * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers Feature List 34 Preliminary, 2001-04 TC11IB Advance Information * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins * T2 events are freely assignable to the service request nodes. Feature List 35 Preliminary, 2001-04 TC11IB Advance Information MultiMediaCard Interface (MMCI) The MultiMdeiaCard Interface module provides interface to MultiMediaCard bus. It supports the full MultiMediaCard bus protocol as defined in MultiMediaCard system specification version 1.3. Figure 9 shows a global view of the MMCI module with the module specific interface connections. C lo ck C o n tro l fM M CI P 5 .1 5 / M M C I_ R O D P 5 .2 / M M C I_ C M D _ R W P 5 .0 / M M C I_ D A T _ R W A d d re ss D e co d e r MMCI M o d u le P o rt C o n tro l P 2 .7 / M M C I_ V D D E N _ N P 1 .5 / M M C I_ D A T P 1 .4 / M M C I_ C M D In te rru p t C o n tro l P 1 .3 / M M C I_ C L K M C B 049 46 Figure 9 MMCI Module with Interconnections The MMCI module communicates with external world via two IO lines and five output lines which are located at Port 1, 2 and 5. Clock control, interrupt service and address decoding are managed outside the MMCI module Kernel. MMCI handles the data transfer on CMD and DAT of the MMC Bus. It performs the transfer from bit serial to byte parallel or vice versa and sustains a 20Mbit/s data rate. To fulfil the MMC Bus protocol, special bytes are modified via inserting start and stop bits or CRC bits. A clock controller is implemented to divide the clock to the necessary MMC Bus clock frequency. Features * * * * * * * * * 3 line serial interface --- Glueless interface to MultiMediaCard Bus Pointer based data transfer Block and sequential card access 16MHz MultiMediacard bus clock generation CRC protection for the MultiMediaCard bus communication Optional programming voltage control Buffered data transfer Power management Data communication with a data rate up to 2.5 Mbyte/s Feature List 36 Preliminary, 2001-04 TC11IB Advance Information Ethernet Controller The MAC controller implements the IEEE 802.3 and operates either at 100 Mbit/s or 10 Mbit/s. Figure 10 shows a global view of the Ethernet Controller module with the module specific interface connections. E th ern et C on trolle r P 2 .1 5 / M II_ R xE R P 2 .1 4 / M II_ R xD [3 ] P 2 .1 3 / M II_ R xD [2 ] P 2 .1 2 / M II_ R xD [1 ] P 2 .1 1 / M II_ R xD [0 ] P 2 .1 0 / M II_ C O L DMUR RB P 2 .9 / M II_ C R S P o rt C o n tro l P 2 .8 / M II_ R xD V P 2 .6 / M II_ M D C FAST FPI (M /S ) MAC M II P 2 .5 / M II_ T xE N P 2 .4 / M II_ T xE R P 2 .3 / M II_ T xD [3 ] DMUT TB P 2 .2 / M II_ T xD [2 ] P 2 .1 / M II_ T xD [1 ] P 2 .0 / M II_ T xD [0 ] M II_ T xC L K M II_ T xC L K M II_ T D IO M C B 04942 Figure 10 Ethernet Controller Module with Interconnections The Ethernet controller comprises the following functional blocks: 1. 2. 3. 4. 5. Media Access Controller (MAC) Receive Buffer (RB) Transmit Buffer (TB) Data Management Unit in Receive Direction (DMUR) Data Management Unit in Transmit Direction (DMUT) RB as well as TB provides on-chip data buffering whereas DMUR and DMUT perform data transfer from/to the shared memory. Feature List 37 Preliminary, 2001-04 TC11IB Advance Information Two interfaces are provided by the Ethernet Controller Module: 1. MII interface for connection of Ethernet PHYs via eighteen Input / Output lines 2. Master/slave FPI bus interface for connection to the on-chip system bus for data transfer as well as configuration. Features * * * * * * * Media Independent Interface (MII) according to IEEE 802.3 Support 10 or 100 Mbit/s MII-based Physical devices. Support Full Duplex Ethernet. Support data transfer between Ethernet Controller and COM-DRAM. Support data transfer between Ethernet Controller and SDRAM via EBU. 256 x 32 bit Recieve buffer and Transmit buffer each. Support burst transfers up to 8 x 32 Byte. Media Access Controller (MAC) * * * * * * * * * * * 100/10-Mbit/s operations Full IEEE 802.3 compliance Station management signaling Large on-chip CAM (Content Addressable Memory) Full duplex mode 80-byte transmit FIFO 16-byte receive FIFO PAUSE Operation Flexible MAC Control Support Support Long Packet Mode and Short Packet Mode PAD generation Media Independent Interface (MII) * * * * * * * * * Media independence. Multi-vendor point of interoperability. Support connection of MAC layer and Physical (PHY) layer devices. Capable of supporting both 100 Mb/s and 10 Mb/s data rates. Data and delimiters are synchronous to clock references. Provides independent four bit wide transmit and receive data paths. Support connection of PHY layer and Station Management (STA) devices. Provides a simple management interface. Capable of driving a limited length of shielded cable. Feature List 38 Preliminary, 2001-04 TC11IB Advance Information PCI The PCI Interface module of the SAF- TC11IB-64D96 basically is a bus bridge between the on-chip FPI bus and the external PCI bus of the system. The PCI Interface is fully compliant to PCI Local Bus Specification Rev. 2.2. Figure 11 shows a global view of the PCI module with the module specific pin connections. P _ A D [3 1 :0 ] P _ C /B E [3 :0 ] P_PAR P_SERR P_PERR P_STO P P_DEVSEL P_TRDY FAST FPI (M /S ) PCI M o d u le P_FRAM E P _ IR D Y P_LO CK P _ IN T A P _ IN T B P_PM E P_REQ P_G NT P _ ID S E L P_CLK33 M C B 04 94 9 Figure 11 PCI Module with pin interconnections The PCI-FPI bridge is able to execute a number of various data transfers between the FPI bus and the PCI bus. Beside the standard PCI functions (configuration transactions), there are two main types of transfers which the bridge supports. Firstly, it will forward a transaction that any PCI initiator directs to the TC11IB PCI interface to the on-chip FPI bus. Secondly the bridge will forward certain transactions that a FPI master initiates on the FPI bus to the PCI bus. Depending on configuration, these transfers may be a single Feature List 39 Preliminary, 2001-04 TC11IB Advance Information data or burst transfers on both PCI and FPI bus. In addition, the bridge is able to handle a direct data transfer between PCI bus and FPI bus utilizing it's programmable DMA channel. The DMA channel can only be activated by a FPI master. In order to work as a PCI host bridge on the PCI bus, the variety of PCI transactions issued by the bridge includes configuration transactions of type 0 and type 1 when acting as a PCI master. Features * PCI V2.2 compliant, 32 bit, 33 MHz * Multifunction Device, Support both PCI Master/Host functions. These functions can be activated by: - TriCore - Fast Ethernet - DMA Channel * Support Burst Transfer from PCI to ComDRAM, SDRAM and Code DRAM. Burst length up to 256 bytes. * Support DMA Channel data transfers between PCI and FPI * Loading of PCI Configuration Registers done by TriCore via FPI Bus access * Support PCI Command * Support Card-Bus. * Power management - according to PCI Bus Power Management Interface Specification V1.1 - Support Multiple PCI power management states D0, D1, D2, D3cold - PME#-Signalling from Fast Ethernet in D1, D2. * PCI Reset - All tristatable PCI outputs of the bridge are set to "Tristate" upon PCI Reset, compliant to PCI Local Bus Specification V2.2 Feature List 40 Preliminary, 2001-04 TC11IB Advance Information On-Chip Memories The TC11IB provides the following on-chip memories: * Program Memory Unit (PMU) with - 24 KBytes Scratch-pad Code RAM (SRAM) - 8 KBytes Instruction Cache Memory (I-CACHE) * Data Memory Unit (DMU) with - 24 KBytes Scratch-pad Data RAM ( SRAM) - 8 KBytes Data Cache Memory (D-CACHE) * 16 KBytes Boot ROM (BROM) * eDRAM Local Memory Unit (LMU) with - 512 KBytes Code/Data Memory * ComDRAM with - 1MBytes Code/Data Memory * Peripheral Control Processor (PCP) with - 16 KBytes Data Memory (PCODE) - 4 KBytes Parameter RAM (PRAM) Feature List 41 Preliminary, 2001-04 TC11IB Advance Information Address Map Table 2 defines the specific segment oriented address blocks of the TC11IB with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of the Segment 15 which includes on-chip peripheral units and ports. Table 2 TC11IB Block Address Map Seg- Address ment Range 0 - 7 0000 0000H - 7FFF FFFFH Size Description DMU Acc. 2 GB MMU/ FPI Space via via F_FPI F_ FPI 8 8000 0000H - 8FFF FFFFH 256 MB External Memory Space mapped from Segment 10 9 9000 0000H - 9FDF FFFFH 254 MB PCI Space mapped from Segment 11 9FE0 0000H - 9FEF FFFFH 9FF0 0000H - 9FFF FFFFH 1 MB A000 0000H - AFBF FFFFH 252 MB External Memory Space AFC0 0000H - AFFF FFFFH 4 MB B000 0000H - BFDF FFFFH 254 MB PCI Space mappable into segment 9 BFE0 0000H - BFEF FFFFH BFF0 0000H - BFFF FFFFH 1 MB ComDRAM Space via via F_FPI F_FPI 1 MB Reserved - - C000 0000H - C007 FFFFH C008 0000H - CFFF FFFFH 512 KB Local Memory Unit eDRAM Space Reserved via LMB - via LMB - 10 11 12 Feature List 1 MB 255.5 MB Com-DRAM Space mapped from Segment 11 Reserved LMU Space 42 via LMB PMU Acc. via LMB via via F_FPI F_FPI - - via LMB via LMB c a c h e d n o nc a c h e d c a c h e d Preliminary, 2001-04 TC11IB Advance Information TC11IB Block Address Map (cont'd) Seg- Address ment Range D000 0000H - D000 7FFFH 13 14 Size Description DMU Acc. PMU Acc. 32 KB Local Data Memory (SRAM) DMU local - via LMB - via LMB - PMU local - via LMB via LMB DF00 0000H - ~16 MB Reserved DFFF BFFFH DFFF C000H - 16 KB Boot ROM Space DFFF FFFFH - - E000 0000H - E7FF FFFFH 128 MB External Memory Space via LMB E800 0000H - E83F FFFFH 4 MB Local Memory Space mapped to LMB Segement 12 E840 0000H - E84F FFFFH 1 MB Local Data Memory (SRAM) mapped to LMB Segment 13 E850 0000H - E85F FFFFH E860 0000H - EFFF FFFFH 1 MB D000 8000H - D3FF FFFFH D400 0000H - D400 7FFFH ~ 64 MB Reserved D400 8000H - D7FF FFFFH ~64 MB Reserved D800 0000H - DDFF FFFFH 96 MB DE00 0000H - DEFF FFFFH 16 MB Feature List 32 KB Local Code Memory (SRAM) External Memory Space Emulator Memory Space via via S_FPI S_FPI - non-cached Table 2 - Local Code Memory (SRAM) mapped to LMB Segment 13 122 MB Reserved 43 Preliminary, 2001-04 TC11IB Advance Information TC11IB Block Address Map (cont'd) Seg- Address ment Range F000 0000H - F00F FFFFH 15 Size Description DMU Acc. PMU Acc. 1 MB On-Chip Peripherals & Ports via via S_FPI S_FPI F010 0000H - F03F FFFFH F040 0000H - F04F FFFFH 3 MB1) Reserved 1 MB PCI/FPI-Bridge Registers F050 0000H - F0FF FFFFH ~11 MB Reserved F100 0000H - F1FF FFFFH 16 MB PCI Configuration Space F200 0000H - F200 05FFH 6 x 256 B BCU0 and Fast Ethernet Registers F200 0600H - F7E0 FEFFH F7E0 FF00H - F7E0 FFFFH ~94 MB Reserved 256 B CPU Slave Interface Registers via (CPS) F_FPI F7E1 0000H - F7E1 FFFFH 64 KB Core SFRs F7E2 0000H - F7FF FFFFH 15 x 128 Reserved KB - F800 0000H - F87F FFFFH 8 MB via LMB F880 0000H - FFFF FFFFH 120 MB Reserved - LMB Peripheral Space (EBU_LMB and local memory eDRAM control registers) via F_FPI - - non-cached Table 2 - 1) Any access to this area will result in unpredicted behaviors of PORTs. Note: Accessses to address defined as "Reserved" in Table 2 lead to a bus error. The exceptions are marked with 1) Feature List 44 Preliminary, 2001-04 TC11IB Advance Information Table 3 Block Address Map of Segment 15 Symbol Description Address Range Size SCU System Control Unit F000 0000H - F000 00FFH 256 Bytes PCISIR PCI Software Interrupt Request F000 0100H - F000 01FFH 256 Bytes BCU1 Slow FPI Bus Control Unit 1 F000 0200H - F000 02FFH 256 Bytes STM System Timer F000 0300H - F000 03FFH 256 Bytes OCDS On-Chip Debug Support F000 0400H - F000 04FFH 256 Bytes - Reserved F000 0500H - F000 05FFH - GPTU0 General Purpose Timer Unit 0 F000 0600H - F000 06FFH 256 Bytes GPTU1 General Purpose Timer Unit 1 F000 0700H - F000 07FFH 256 Bytes ASC Async./Sync. Serial Interface F000 0800H - F000 08FFH 256 Bytes 16X50 Asynchronous Serial Interface F000 0900H - F000 09FFH 256 Bytes SSC High-Speed Synchronous Serial F000 0A00H - F000 0AFFH Interface 256 Bytes MMCI MultiMediaCard Interface F000 0B00H - F000 0BFFH 256 Bytes SRU Service Request Unit F000 0C00H - F000 0DFFH 512 Bytes - Reserved F000 0E00H - F000 27FFH - P0 Port 0 F000 2800H - F000 28FFH 256 Bytes P1 Port 1 F000 2900H - F000 29FFH 256 Bytes P2 Port 2 F000 2A00H - F000 2AFFH 256 Bytes P3 Port 3 F000 2B00H - F000 2BFFH 256 Bytes P4 Port 4 F000 2C00H - F000 2CFFH 256 Bytes P5 Port 5 F000 2D00H - F000 2DFFH 256 Bytes - Reserved F000 2E00H - F000 3EFFH - PCP PCP Registers F000 3F00H - F000 3FFFH 256 Bytes Reserved F000 4000H - F000 FFFFH - PCP Data Memory (PRAM) F001 0000H - F001 0FFFH 4 KBytes Reserved F001 1000H - F001 FFFFH - PCP Code Memory (PCODE) F002 0000H - F002 3FFFH 16 KBytes - Reserved F002 4000H - F00F FFFFH - - Reserved F010 0000H - F03F FFFFH 3 MBytes1) PCIBC R PCI Bridge Configuration Registers F040 0000H - F04F FFFFH 1 MBytes Feature List 45 Preliminary, 2001-04 TC11IB Advance Information Table 3 Block Address Map of Segment 15 (cont'd) Symbol Description Address Range Size - Reserved F050 0000H - F0FF FFFFH - PCICS PCI Configuration Space Registers F100 0000H - F1FF FFFFH 16 MBytes BCU0 Fast FPI Bus Control Unit 0 F200 0000H - F200 00FFH 256 Bytes ECU Ethernet Controller Unit F200 0100H - F200 05FFH 1280 Bytes - Reserved F200 0600H - F7E0 FEFFH - CPU Slave Interface Registers (CPS) F7E0 FF00H - F7E0 FFFFH 256 Bytes Reserved F7E1 0000H - F7E1 7FFFH - MMU F7E1 8000H - F7E1 80FFH 256 BYTES Reserved F7E1 8100H - F7E1 BFFFH - Memory Protection Registers F7E1 C000H - F7E1 EFFFH 12 KBytes Reserved F7E1 F000H - F7E1 FCFFH - Core Debug Register (OCDS) F7E1 FD00H - F7E1 FDFFH 256 Bytes Core Special Function Registers F7E1 FE00H - F7E1 FEFFH 256 Bytes (CSFRs) General Purpose Register (GPRs) F7E1 FF00H - F7E1 FFFFH 256 Bytes - Reserved F7E2 0000H - F7FF FFFFH - EBU EBU_LMB External Bus Unit F800 0000H - F800 01FFH 512 Bytes - Reserved F800 0200H - F800 03FFH - LMU Local Memory Unit F800 0400H - F800 04FFH 256 Bytes - Reserved F800 0500H - F87F FBFFH - DMU Local Data Memory Unit F87F FC00H - F87F FCFFH 256 Bytes PMU Local Program Memory Unit F87F FD00H - F87F FDFFH 256 Bytes LCU LMB Bus Control Unit F87F FE00H - F87F FEFFH 256 Bytes LFI LMB to FPI Bus Bridge (LFI) F87F FF00H - F87F FFFFH 256 Bytes - Reserved F880 0000H - FFFF FFFFH - 1) Any access to this area will result in unpredicted behaviors of PORTs. Note: Accessses to address defined as "Reserved" in Table 3 lead to a bus error.The exceptions are marked with 1) Feature List 46 Preliminary, 2001-04 TC11IB Advance Information Memory Protection System The TC11IB memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. In SAF-T11IB-64D96, TriCore supports two address spaces: The virtual address space and The physical address space. Both address space are 4GB in size and divided into 16 segments with each segment being 256MB. The upper 4 bits of the 32-bit address are used to identify the segment. Virtual segments are numbered 0 - 15. But a virtual address is always translated into a phsical address before accessing memory. The virtual address is translated into a physical address using one of two translation mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If the virtual address belongs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translation). If the virtual address belongs to the lower half of the address space, then the virtual address is used directly as the physical address if the processor is operating in Physical mode (direct translation) or translated using a Page Table Entry if the processor is operating in Virtual mode (PTE translation). These are managed by Memory Management Unit (MMU) Memory protection is enforced using separate mechanisms for the two translation paths. Protection for direct translation Memory protection for addresses that undergo direct translation is enforced using the range based protection that has been used in the previous generation of the TriCore architecture. The range based protection mechanism provides support for protecting memory ranges from unauthorized read, write, or instruction fetch accesses. The TriCore architecture provides up to four protection register sets with the PSW.PRS field controlling the selection of the protection register set. Because the TC11IB uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Feature List 47 Preliminary, 2001-04 TC11IB Advance Information Mode Register) which determines the memory access modes which apply to the specified range. Protection for PTE based translation Memory protection for addresses that undergo PTE based translation is enforced using the PTE used for the address translation. The PTE provides support for protecting a process from unauthorized read, write, or instruction fetches by other processes. The PTE has the following bits that are provided for the purpose of protection: l XE (Execute Enable) enables instruction fetch to the page. l WE (Write Enable) enables data writes to the page. l RE (Read Enable) enables data reads from the page. Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual address space are disallowed when operating in Virtual mode. In Physical mode, User0 accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual address that is restricted to User-1 or Super-visor mode will cause a Virtual Address Protection (VAP) Trap in both the Physical and Virtual modes. Feature List 48 Preliminary, 2001-04 TC11IB Advance Information Local Memory Bus (LMB) The Local Memory Bus interconnects the memory units and functional units, such as CPU and LMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMU and PMU fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. Via External Bus Unit, it interconnects TC11IB and external components. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8,16,32 & 64 bits single beat transactions and variable length 64 bits block transfers. The LMB-to-FPI Interface (LFI) block provides the circuitry to interface (bridge) the FPI bus to the Local Memory Bus (LMB). Key Features The LMB provides the following features: * * * * * * Synchronous, Pipelined, Multi-master, 64-bit high performance bus Support multiple bus masters Support Split transactions Support Variable block size transfer Burst Mode Read/Write to Memories Connect Caches and on-chip memory and Fast FPI Bus LFI Features * * * * * * * * Compatible with the FPI 3.2 and LMB bus Specification V2.4 Supports Burst/Single transactions, from FPI to LMB. Supports Burst/Single transactions, from LMB to FPI High efficiency and performance: - fastest access across the bridge takes three cycles, using a bypass. - There are no dead cycles on arbitration. Acts as the default master on FPI side. Supports abort, error and retry conditions on both sides of the bridge. Supports FPI's clock the same, or half, as the LMB's clock frequency. LMB clock is shut when no transactions are issue to LFI from both buses and none are in process in the LFI to minimize the power consumption. Feature List 49 Preliminary, 2001-04 TC11IB Advance Information On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC11IB, such as the PCP and onchip peripheral components. The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 800 MBytes/s can be achieved with a 100 MHz bus clock and 32bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Via External Bus Unit ( EBU), FPI Bus also interconnects the external components to TC11IB. There are two FPI buses in TC11IB, Fast FPI Bus and Slow FPI Bus. In order to improve the system performance, the peripherals are splitted into two FPI buses based on their performace. The fast FPI bus runs at a speed of 96 MHz where most of the high performance peripheral like ComDram, PCI-FPI, Ethernet Controller, LFI etc. are connected. The slow FPI bus runs at half speed of its fast counter part. And it is used to connect some standard peripherals. There is a FPI-FPI bridge between them to transfer data. Each of FPI buses has its own Bus Control Unit (BCU). Features * * * * * * * * Supports multiple bus masters Supports demultiplexed address/data operation Address bus up to 32 bits and data buses are 64 bits wide Data transfer types include 8-, 16-, 32- and 64 bit sizes Supports Burst transfer Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption Controlled by an Bus Control Unit (BCU) - Arbitration of FPI Bus master requests - Handling of bus error. FFI-Bridge Features * * * * * Supports Single/Block* Data Read/Write Transactions (8/16/32 Bit) Supports FPI- Read Modify Write Transactions (RMW) Internal FIFO Interfaces between FPI master and FPI slave. Optimized for FPI-Bus frequency ratios 2:1 Special Retry/Abort functionality Note: Block Transaction support depends on generic settings and the depth of the bridge internal read- and write data buffer. Feature List 50 Preliminary, 2001-04 TC11IB Advance Information LMB External Bus Unit The LMB External Bus Control Unit (EBU_LMB) of the TC11IB is the interface between external resources, like memories and peripheral units, and the internal resources connected to on-chip buses if enabled. The basic structure and external interconnections of the EBU are shown in Figure 12. 32 4 24 A D [3 1 :0 ] B C [3 :0 ] A [2 3 :0 ] RD PMU LM U R D /W R W A IT SVM T riC o re 1 .3 LM B MMU H LD A BREQ ALE DMU RAS LFI 7 C S [6 :0 ] CSEM U EBU _LM B C SGLB FAST FPI CSOVL CAS T o P e rip h e ra ls CKE M R /W FFI RMW HOLD CSFPI S LO W FPI EBUC LK BAA T o P e rip h e ra ls and PC P ADV AC LK C M D ELAY M C B 049 41 Figure 12 Feature List EBU Structure and Interfaces 51 Preliminary, 2001-04 TC11IB Advance Information The EBU is mainly used for the following two operations: * Masters on LMB bus access external memories through EBU_LMB * An external (off-chip) master access internal (on-chip) devices through FPI Bus. The EBU controls all transactions required for these two operations and in particular handles the arbitration of the external bus between multi-masters. The types of external resources accesseded by the EBU are: * * * * * * * INTEL style peripherals (separate RD and WR signals) Motorola style peripherals (MR/ W signals) ROMs, EPROMs Static RAMs PC 100 SDRAMs ( Burst Read/Write Capacity / Multi-Bank/Page support) Specific types of Burst Mode Flashes (Intel 28F800F3/28F160F3, AMD 29BL162) Special support for external emulator/debug hardware Features * Support Local Memory Bus (LMB 64-bit) * Support External bus frequency up to 96 MHz and internal LMB frequency up to 166 MHz. External bus frequency :LMB frequency =1:1 or 1:2 or 1:4 * Highly programmable access parameters * Support Intel-and Motorola-style peripherals/devices * Support PC 100 SDRAM (burst access,multibanking,precharge,refresh) * Support 16-and 32-bit SDRAM data bus and 64,128 and 256MBit devices * Support Burst flash (Intel 28F800F3/160F3,AMD 29BL162) * Support Multiplexed access (address &data on the same bus) when PC 100 SDRAM is not implemented * Support Data Buffering :Code Prefetch Buffer,Read/Write Buffer. * External master arbitration compatible to C166 and other Tricore devices * 8 programmable address regions (1 dedicated for emulator) * Support Little-and Big-endian * Signal for controlling data flow of slow-memory buffer * Slave unit for external (off-chip)master to access devices on FPI bus * Data Mover Engine. Feature List 52 Preliminary, 2001-04 TC11IB Advance Information Peripheral Control Processor The Peripheral Control Processor (PCP) performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor's first line of defense as an interrupt-handling engine. The PCP can offload the CPU from having to service time-critical interrupts. This provides many benefits, including: * Avoiding large interrupt-driven task context-switching latencies in the host processor * Lessening the cost of interrupts in terms of processor register and memory overhead * Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations * Easing the implementation of multitasking operating systems. The PCP has an architecture which efficiently supports DMA type transactions to and from arbitrary devices and memory addresses within the TC11IB and also has reasonable stand alone computational capabilities. The PCP is made up of several modular blocks as follows: * * * * * * PCP Processor Core Code Memory (PCODE) Parameter Memory (PRAM) PCP Interrupt Control Unit (PICU) PCP Service Request Nodes (PSRN) System bus interface to the FPI Bus The PCP is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor. Feature List 53 Preliminary, 2001-04 TC11IB Advance Information C ode M e m o ry PCODE P a ra m e te r M e m o ry PRAM PCP P ro c e s s o r C o re P C P S e rv ic e R eq. N odes PSRNs F P I-In te rfa c e FPI Bus P C P In te rru p t C o n tro l U n it P IC U P C P In te rru p t A rb itra tio n B u s C P U In te rru p t A rb itra tio n B u s Figure 13 PCP Block Diagram Table 4 PCP Instruction Set Overview M C B04784 Instruction Group Description DMA primitives Efficient DMA channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Arithmetic Add, subtract, compare and complement Divide/Multiply Divide and multiply Logical And, Or, Exclusive Or, Negate, MCLR and MSET Shift Shift right or left, rotate right or left, prioritize Bit Manipulation Set, clear, insert and test bits Flow Control jump conditionally, jump long, exit, No operation Miscellaneous Debug Feature List 54 Preliminary, 2001-04 TC11IB Advance Information System Timer The STM within the TC11IB is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock, fSTM (identical with the system clock fSYS = 48MHz). Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset The STM is an upward counter, running with the system clock frequency. It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is no possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256 fSTM. At fSTM = 48 MHz, for example, the STM counts 47.6 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflow. STM M odule 55 fSTM 47 39 31 PORST C lock C ontrol 23 15 7 56-B it S ys tem T im er E nable / D is able 00 H CAP 00 H T IM 6 TIM 5 A ddres s D ec oder T IM 4 T IM 3 T IM 2 T IM 1 TIM 0 M C A 0 4795 Figure 14 Feature List Block Diagram of the STM Module 55 Preliminary, 2001-04 TC11IB Advance Information Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC11IB in a user-specified time period. When enabled, the WDT will cause the TC11IB system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC11IB system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard "Watchdog" function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). A further enhancement in the TC11IB's Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features * 16-bit Watchdog counter * Selectable input frequency: fSYS/256 or fSYS/16384 (fSYS = 48MHz) * 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes * Incorporation of the ENDINIT bit and monitoring of its modifications * Sophisticated password access mechanism with fixed and user-definable password fields * Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. * Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. * Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. * Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. * Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC11IB is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed. Feature List 56 Preliminary, 2001-04 TC11IB Advance Information * Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. System Control Unit The System Control Unit (SCU) of the TC11IB handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: * PLL Control - PLL_CLC Clock Control Register - fSYS = 96MHz clock generation. - fSYS = 48MHz clock generation. * Reset Control - Generation of all internal reset signals - Generation of external HDRST reset signal - Generation of LMU eDRAM reset signals * Boot Scheme - Hardware Booting Scheme - Software Booting Scheme * Power Management Control - Enabling of several power-down modes - Control of the PLL in power-down modes * Watchdog Timer * OCDS2 Trace Port Control * Selection between PCI and Cardbus (PCMCIA) Standard Compliance * FFI Bridge Control * Device Identification Registers Feature List 57 Preliminary, 2001-04 TC11IB Advance Information Interrupt System An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called "Service Providers". Interrupt requests are called "Service Requests" rather than "Interrupt Requests" in this document because they can be serviced by either of the Service Providers. Each peripheral in the TC11IB can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 15, each TC11IB unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where "mod" is the identifier of the service requesting unit and "x" an optional index. Two buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: * The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. * The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus. Units which can generate service requests are: - - - - - - - - - - - - General Purpose Timer Units (GPTU 0 and GPTU 1) with 8 SRNs each High-Speed Synchronous Serial Interfaces (SSC) with 3 SRNs Asynchronous/Synchronous Serial Interfaces (ASC) with 4 SRNs Asynchronous Serial Interface (16X50) with 1 SRN PCI with 33 SRNs Ethernet Controller with 9 SRNs MultiMediaCard (MMCI) with 1 SRN External Interrupts with 24 SRNs Bus Control Units (BCU0 and BCU1) with 1 SRN each Peripheral Control Processor (PCP) with 12 SRNs Central Processing Unit (CPU) with 4 SRNs Debug Unit (OCDS) with 1 SRN The PCP can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. Feature List 58 Preliminary, 2001-04 TC11IB Advance Information CPU In te rru p t A rb itra tio n B u s PCP In te rru p t A rb itra tio n B u s S e rvice R e q u e sto rs G PTU 0 G PTU 1 1 16x50 33 PCI E th e rn e t 9 1 MMCI E x te rn a l OCDS 8 4 ASC BCU1 8 3 SSC BCU0 S e rv ice R equest N odes 24 1 1 1 8 SRNs 8 SRNs In te rru p t C o n tro l U n its 8 8 In t. R e q . 8 P IP N 8 2 3 4 4 SRNs 2 4 5 1 3 33 33 SRNs 2 SRNs 2 SRNs 5 1 1 SRN In t. A ck. CCPN PIC U 3 3 SRNs In te rru p t S e rv ice P ro v id e rs 5 SRNs 3 SRNs 2 PC P 2 5 3 33 9 9 SRNs 9 4 1 1 SRN 4 1 4 SRNs 4 S o ftw a re In te rru p t 24 24 SRNs 24 IC U In t. R e q . 1 1 SRN 1 P IP N 1 1 SRN C PU In t. A ck. CCPN 1 1 1 SRN 1 M C B 049 44 Figure 15 Feature List Block Diagram of the TC11IB Interrupt System 59 Preliminary, 2001-04 TC11IB Advance Information Boot Options The TC11IB booting schemes provides a number of different boot options for the start of code execution. Table 5 shows the boot options available in the TC11IB. Table 5 Boot Selections OCDSE BRKIN CFG CFG [3] [2:0] Type of Boot Boot Source Initial PC Value 1 000B Start directly in core scratchpad memory SRAM (Only via SW Reset) D400 0000H Not ( 000 or 100) Start from Boot ROM Boot ROM, SSC BSL mode1) ( BootStrap Loader) or ASC BSL mode1) DFFF FFFCH 0 100B 1 100B External memory as External A000 0000H slave directly via EBU Memory (non-cached, External memory as CS0) master directly via 1 X EBU 1 0 don't care Tri-state chip (deep sleep) - - 0 1 0 Go to halt with EBU enabled as slave - - - DE00 0000H 0 0 100B 1 Go to halt with EBU enabled as master all other combinations Go to halt with EBU disabled don't care Go to external emulator space 1) SSC/ASC BootStrap Loader is built in BOOT ROM which provides a mechanism to load the startup program, which is executed after reset, via the SSC/ASC interface. After successfully loaded, the startup program will be executed from the address at 0xC000 0004H. Feature List 60 Preliminary, 2001-04 TC11IB Advance Information Power Management System The TC11IB power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: * * * * Run Mode Idle Mode Sleep Mode Deep Sleep Mode Table 6 describes these features of the power management modes. Table 6 Power Management Mode Summary Mode Description Run The system is fully operational. All clocks and peripherals are enabled, as determined by software. Idle The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. Sleep The system clock continues to be distributed only to those peripherals programmed to operate in Sleep Mode. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. Deep Sleep The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM). Besides these explicit software-controlled power-saving modes, TC11IB supports automatic power-saving in that operating units, which are currently not required or idle, are shut off automatically until their operation is required again. Feature List 61 Preliminary, 2001-04 TC11IB Advance Information On-Chip Debug Support The On-Chip Debug Support of the TC11IB consists of four building blocks: * OCDS module in the TriCore CPU - On-chip breakpoint hardware - Support of an external break signal * OCDS module in the PCP - Special DEBUG instruction for program execution tracing * Trace module of the TriCore - Outputs 16 bits per cycle with pipeline status information, PC bus information, and breakpoint qualification information * Debugger Interface (Cerberus) - Provided for debug purposes of emulation tool vendors - Accessible through a JTAG standard interface with dedicated JTAG port pins Figure 16 shows a basic block diagram of the building blocks. . FPI Bus B R K IN PC P BRKOUT SC U T ra ce C o n tro l 16 OCDS2 OCDS O C D S 2 [1 5 :0 ] TriC ore C PU OCDSE OCDS TDI TDO C erberus & JTA G JTA G I/O L in e s TM S TCK TRST M C B04947 Figure 16 Feature List OCDS Support Basic Block Diagram 62 Preliminary, 2001-04 TC11IB Advance Information Clock Generation Unit The Clock Generation Unit in the TC11IB, shown in Figure 17, consists of an oscillator circuit and one Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it losses the lock on the external clock. PLL can provide the 96MHz and 48MHz clocks. In general, the Clock Generation Unit (CGU) is controlled through the System Control Unit (SCU) module of the TC11IB. C lock G eneration U nit CGU XTAL1 1 O scilla to r f O S C C ircu it >1 P h a se D e te c t. fV CO VC O 1 MUX 0 K :1 D iv id e r MUX 0 S ys te m _ CLK fSY S = 96 M H z XTAL2 N D iv id e r PLL 1 K :2 D iv id e r MUX 0 S ys te m _ CLK fSY S = 48 M H z L o ck D e te cto r O S C _ F A IL PLL D e e p N D IV V C O _ V C O _ K D IV P L L _ P L L _ P L L _ L o c ke d S le e p [5 :0 ] S E L B Y P A S S [3 :0 ] 2 E N 2 S E L B Y P A S S [1 :0 ] R e g is te r P L L _ C L C System C ontrol U nit SCU M C A 04 9 4 0 Figure 17 Feature List Clock Generation Unit Block Diagram 63 Preliminary, 2001-04 TC11IB Advance Information Recommended Oscillator Circuits V DDOSC V DDOSC E x te rn a l C lo c k S ig n a l XTAL1 12 MHz TC 11IB O s c illa to r TC 11IB O s c illa to r XTAL2 C1 XTAL1 XTAL2 C2 V SSOSC V SSOSC M C S 0 4 9 48 Figure 18 Oscillator Circuitries For the main oscillator of the TC11IB the following external passive components are recommended: - Crystal: 12 MHz - C1, C2: 10 pF A block capacitor between VDDOSC and VSSOSC is recommended, too. Feature List 64 Preliminary, 2001-04 TC11IB Advance Information Power Supply The TC11IB provides an ingenious power supply concept in order to improve the EMI behavior as well as to minimize the crosstalk within on-chip modules. Figure 19 shows the TC11IB's power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. V S S (1 .8 V ) V DD PCP M e m o ry DMU C om D RAM V DDDRAM V CO M REF V SS V SS PM U PCI P o rts V SS V DDDRAM CPU & P e rip h e ra l L o g ic G P IO P o rts (P 0 -P 5 ) V D D P (3 .3 V ) V SS EBU P o rts V SS V LM UREF LM U PLL V DDPLL96 V SSPLL96 OSC V DDO SC V SSOSC M C B 04953 Figure 19 Feature List TC11IB Power Supply Concept 65 Preliminary, 2001-04 TC11IB Advance Information Package Outline Plastic Package, P-BGA-338-2 (SMD) (Plastic Ball Grid Array Package) Figure 20 P-BGA-338-2 Package Sorts of Packing Package outlines for tubes, trays, etc. are contained in Data Sheet Information" "Package SMD = Surface Mounted Device Feature List 66 Preliminary, 2001-04 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG