ISL70227SRHX/SAMPLE - Intersil Corporation

1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

36V Rad Hard Dual Precision Operational Amplifier

ISL70227SRH

The ISL70227SRH is a high precision dual operational

amplifier featuring very low noise, low offset voltage, low input

bias current and low temperature drift. These features plus its

radiation tolerance make the ISL70227SRH the ideal choice

for applications requiring both high DC accuracy and AC

performance. The combination of precision, low noise, and

small footprint provides the user with outstanding value and

flexibility relative to similar competitive parts.

Applications for these amplifiers include precision and

analytical instrumentation, active filters, precision power

supply controls, and industrial controls.

The ISL70227SRH is available in a 10 Ld hermetic ceramic

flatpack and operates over the extended temperature range of

-55°C to +125°C.

Applications

• Precision Instruments

• Industrial Controls

• Active Filter Blocks

• Data Acquisition

• Power Supply Control

Features

• Wide Supply Range . . . . . . . . . . . . . . . . . . . .4.5V to 36V Max.

• Very Low Voltage Noise . . . . . . . . . . . . . . . . . .2.5nV/√Hz, Typ.

• Gain-bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . 10MHz

• Superb Offset Drift . . . . . . . . . . . . . . . . . . . . . . . . 1µV/°C, Max

• Operating Temperature Range. . . . . . . . . . . . -55°C to +125°

• Low Input Voltage Offset. . . . . . . . . . . . . . . . . . . . . . 10µV, Typ.

• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1nA, Typ.

• Unity Gain Stable

• No Phase Reversal

• Radiation Tolerance

- High Dose Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)

- Low Dose Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)

- SEL/SEB LETTH . . . . . . . . . . . . . . . . . . . . . . 86MeV/mg/cm2

Related Literature

• See AN1669, “ISL70227SRH Evaluation Board User’s

Guide”

OUTPUT

V+

V-

Sallen-Key Low Pass Filter (1MHz)

VIN

95.3 232

68.3nF

1.5nF

FIGURE 1. TYPICAL APPLICATION

ISL70227SRH

FIGURE 2. OFFSET VOLTAGE vs RADIATION

-30

-25

-20

-15

-10

-5

0 102030405060708090100

(µV)

TOTAL DOSE (krad(Si))

GROUNDED

BIASED

September 23, 2011

FN7925.1

ISL70227SRH

2FN7925.1

September 23, 2011

Pin Configuration

Ordering Information

ORDERING NUMBER PART MARKING TEMP RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL70227SRHMF (Notes 1, 2) ISL70227 SRHMF -55 to +125 10 Ld FLATPACK K10.A

ISL70227SRHF/PROTO (Notes 1, 2) ISL70227 SRHF/PROTO -55 to +125 10 Ld FLATPACK K10.A

ISL70227SRHMX -55 to +125 DIE

ISL70227SRHX/SAMPLE -55 to +125 DIE

ISL70227MHEVAL1Z Evaluation Board

NOTES:

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70227SRH. For more information on MSL please see techbrief TB363.

ISL70227SRH

(10 LD FLATPACK)

TOP VIEW

Pin Descriptions

PIN NUMBER PIN NAME EQUIVALENT CIRCUIT DESCRIPTION

3 +IN_A Circuit 1 Amplifier A non-inverting input

5 V- Circuit 3 Negative power supply

7 +IN_B Circuit 1 Amplifier B non-inverting input

8 -IN_B Circuit 1 Amplifier B inverting input

9 OUT B Circuit 2 Amplifier B output

10 V+ Circuit 3 Positive power supply

1 OUT A Circuit 2 Amplifier A output

2 -IN_A Circuit 1 Amplifier A inverting input

4, 6 NC - Not Connected – This pin is not electrically connected internally.

1OUTA

-IN A

+IN A

V-

V+

OUT B

-IN B

+IN B

V+

V-

OUT

CIRCUIT 2CIRCUIT 1

V+

V-

CIRCUIT 3

IN-

V+

V-

IN+ CAPACITIVELY

TRIGGERED ESD

CLAMP

ISL70227SRH

3FN7925.1

September 23, 2011

Absolute Maximum Ratings Thermal Information

Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V

Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V

Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V

Max/Min Input Current for

Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Output Short-Circuit Duration

(1 Output at a Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite

ESD Tolerance

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV

Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 300V

Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V

Di-electrically Isolated PR40 Process . . . . . . . . . . . . . . . . . . . Latch-up free

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

10 Ld Ceramic Flatpack (Notes 3, 4) . . . . . 130 20

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Recommended Operating Conditions

Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V (±2.5V) to 30V (±15V)

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply over the

operating temperature range, -55°C to +125°C, and over the radiation tolerance limit with exposure at a high dose rate.

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNIT

VOS Offset Voltage -75 -10 75 µV

-100 -100 µV

TCVOS Offset Voltage Drift -1 .1 1µV/°C

IOS Input Offset Current -10 1 10 nA

-12 -12 nA

IB Input Bias Current -10 1 10 nA

-12 - 12 nA

VCM Input Voltage Range Guaranteed by CMRR -13 - 13 V

-12 -12 V

CMRR Common-Mode Rejection Ratio VCM = -13V to +13V 115 120 - dB

VCM = -12V to +12V 115 - - dB

PSRR Power Supply Rejection Ratio VS = ±2.25V to ±5V 110 117 - dB

VS = ±3V to ±15V 110 -- dB

AVOL Open-Loop Gain VO = -13V to +13V

RL = 10kΩ to ground

1000 1500 - V/mV

VOH Output Voltage High RL = 10kΩ to ground 13.5 13.65 - V

13.2 -- V

RL = 2kΩ to ground 13.4 13.5 - V

13.1 - - V

VOL Output Voltage Low RL = 10kΩ to ground - -13.65 -13.5 V

-- -13.2 V

RL = 2kΩ to ground - -13.5 -13.4 V

---13.1 V

ISL70227SRH

4FN7925.1

September 23, 2011

ISSupply Current/Amplifier - 2.2 2.8 mA

- - 3.7 mA

ISC Short-Circuit RL = 0Ω to ground - ±45 - mA

VSUPPLY Supply Voltage Range Guaranteed by PSRR ±2.25 - ±15 V

AC SPECIFICATIONS

GBW Gain Bandwidth Product - 10 - MHz

enp-p Voltage Noise 0.1Hz to 10Hz - 85 - nVP-P

enVoltage Noise Density f = 10Hz - 3 - nV/√Hz

enVoltage Noise Density f = 100Hz - 2.8 - nV/√Hz

enVoltage Noise Density f = 1kHz - 2.5 - nV/√Hz

enVoltage Noise Density f = 10kHz - 2.5 - nV/√Hz

in Current Noise Density f = 10kHz - 0.4 - pA/√Hz

THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS,

RL = 2kΩ

- 0.00022 - %

TRANSIENT RESPONSE

SR Slew Rate AV = 10, RL = 2kΩ, VO = 4VP-P - ±3.6 - V/µs

tr, tf, Small

Signal

Rise Time

10% to 90% of VOUT

AV = -1, VOUT = 100mVP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 36 - ns

Fall Time

90% to 10% of VOUT

AV = -1, VOUT = 100mVP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 38 - ns

tsSettling Time to 0.1%

10V Step; 10% to VOUT

AV = -1, VOUT = 10VP-P

Rg = Rf = 10k, RL = 2kΩ to VCM

- 3.4 - µs

Settling Time to 0.01%

10V Step; 10% to VOUT

AV = -1, VOUT = 10VP-P

RL = 2kΩ to VCM

- 3.8 - µs

tOL Output Overload Recovery Time AV = 100, VIN = 0.2V,

RL = 2kΩ to VCM

- 1.7 - µs

Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating

temperature range, -55°C to +125°C.

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNIT

VOS Offset Voltage - -10 - µV

TCVOS Offset Voltage Drift - .1 - µV/°C

IOS Input Offset Current - 1 - nA

IB Input Bias Current -1- nA

CMRR Common-Mode Rejection Ratio VCM = -3V to +3V - 120 - dB

PSRR Power Supply Rejection Ratio VS = ±2.25V to ±5V - 125 - dB

AVOL Open-Loop Gain VO = -3V to +3V

RL = 10kΩ to ground

- 1500 - V/mV

VOH Output Voltage High RL = 10kΩ to ground - 3.65 - V

RL = 2kΩ to ground - 3.5 -

Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply over the

operating temperature range, -55°C to +125°C, and over the radiation tolerance limit with exposure at a high dose rate. (Continued)

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNIT

ISL70227SRH

5FN7925.1

September 23, 2011

VOL Output Voltage Low RL = 10kΩ to ground - -3.65 - V

RL = 2kΩ to ground - -3.5 -

ISSupply Current/Amplifier - 2.2 - mA

ISC Short-Circuit - ±45 - mA

AC SPECIFICATIONS

GBW Gain Bandwidth Product - 10 - MHz

THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, Vo = 2.5VRMS,

RL = 2kΩ

- 0.0034 - %

TRANSIENT RESPONSE

SR Slew Rate AV = 10, RL = 2kΩOH - ±3.6 - V/µs

tr, tf, Small

Signal

Rise Time

10% to 90% of VOUT

AV = -1, VOUT = 100mVP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 36 - ns

Fall Time

90% to 10% of VOUT

AV = -1, VOUT = 100mVP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 38 - ns

tsSettling Time to 0.1% AV = -1, VOUT = 4VP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 1.6 - µs

Settling Time to 0.01% AV = -1, VOUT = 4VP-P

Rf = Rg = 2kΩ, RL = 2kΩ to VCM

- 4.2 - µs

NOTE:

5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating

temperature range, -55°C to +125°C. (Continued)

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNIT

Post Radiation Characteristics VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. This data is ATE test

data of the ISL70227SRH post radiation exposure at a high dose rate of 50 to 300rad(Si)/s, these are not limits nor are they guaranteed.

PARAMETER DESCRIPTION CONDITIONS 50k RAD 75k RAD 100k RAD UNIT

VOS Offset Voltage 34 30 30 µV

IOS Input Offset Current -1 -1 -2 nA

IBInput Bias Current -1 -2 -3 nA

CMRR Common-Mode Rejection Ration VCM = -13V to +13V 155 155 155 dB

PSRR Power Supply Rejection Ratio VS = ±2.25V to ±15V 116 116 116 dB

AVOL Open-Loop Gain VO = -13V to +13V

RL = 10kΩ to ground

3500 3500 3500 V/mV

ISSupply Current/Amplifier 2.2 2.2 2.2 mA

ISL70227SRH

6FN7925.1

September 23, 2011

Post Radiation Characteristics VS ±15V, VCM = 0V, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. This data

is ATE test data of the ISL70227SRH post radiation exposure at a low dose rate of <10mrad(Si)/s, these are not limits nor are they guaranteed.

FIGURE 3. OFFSET VOLTAGE vs RADIATION FIGURE 4. POSITIVE INPUT BIAS CURRENT vs RADIATION

FIGURE 5. NEGATIVE INPUT BIAS CURRENT vs RADIATION FIGURE 6. OFFSET CURRENT vs RADIATION

FIGURE 7. TOTAL SUPPLY CURRENT vs RADIATION

-30

-25

-20

-15

-10

-5

0 102030405060708090100

(µV)

TOTAL DOSE (krad(Si))

GROUNDED

BIASED

-5

0 102030405060708090100

TOTAL DOSE (krad(Si))

B+

(nA)

GROUNDED

BIASED

-5

0 102030405060708090100

B-

(nA)

TOTAL DOSE (krad(Si))

GROUNDED

BIASED

-5

0 102030405060708090100

TOTAL DOSE (krad(Si))

(nA)

GROUNDED

BIASED

0 102030405060708090100

TOTAL DOSE (krad(Si))

SUPPLY CURRENT (mA)

GROUNDED

BIASED

ISL70227SRH

7FN7925.1

September 23, 2011

Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.

FIGURE 8. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz FIGURE 9. INPUT NOISE VOLTAGE SPECTRAL DENSITY

FIGURE 10. INPUT NOISE CURRENT SPECTRAL DENSITY FIGURE 11. PSRR vs FREQUENCY, VS = ±5V, ±15V

FIGURE 12. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V FIGURE 13. VOS vs TEMPERATURE

TIME (s)

INPUT NOISE VOLTAGE (nV)

-60

-40

-20

100

012345678910

-80

-100

V+ = 38V

RL = 10k

Rg = 10, Rf = 100k

AV = 10,000

CL = 3.5pF

FREQUENCY (Hz)

100

0.1 1 10 100 1k 10k 100k

VS = ±19V

AV = 1

INPUT NOISE VOLTAGE (nV/√Hz)

FREQUENCY (Hz)

100

INPUT NOISE CURRENT (pA/√Hz)

0.1 1 10 100 1k 10k 100k

0.1

VS = ±19V

AV = 1

PSRR (dB )

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

100

120

-10

110

130

RL = INF

AV = +1

VS = 1VP-P

CL = 5.25pF

PSRR+ and PSRR- VS = ±15V

PSRR+ AND PSRR- VS = ±5V

CMRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

100

120

-10

110

130

RL = INF

AV = +1

VCM = 1VP-P

CL = 5.25pF

VS = ±15V

VS = ±2.25V

VS = ±5V

-60 -40 -20 0 20 40 60 80 100 120 140

VOS (µV)

TEMPERATURE (°C)

VS = ±15V

ISL70227SRH

8FN7925.1

September 23, 2011

FIGURE 14. IB+ vs TEMPERATURE FIGURE 15. IB- vs TEMPERATURE

FIGURE 16. IOS vs TEMPERATURE FIGURE 17. SUPPLY CURRENT vs TEMPERATURE

FIGURE 18. VOH vs TEMPERATURE, VS = ±15V FIGURE 19. VOL vs TEMPERATURE, VS = ±15V

Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-60 -40 -20 0 20 40 60 80 100 120 140

IB+ (nA)

IB+

TEMPERATURE (°C)

= ±15V

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

-60 -40 -20 0 20 40 60 80 100 120 140

IB- (nA)

IB-

TEMPERATURE (°C)

= ±15V

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

-60 -40 -20 0 20 40 60 80 100 120 140

IIO (nA)

IIO

TEMPERATURE (°C)

= ±15V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-60 -40 -20 0 20 40 60 80 100 120 140

ICC

ICC (mA)

TEMPERATURE (°C)

= ±15V

12.2

12.3

12.4

12.5

12.6

12.7

12.8

12.9

13.0

13.1

13.2

-60 -40 -20 0 20 40 60 80 100 120

VOUT (V)

TEMPERATURE (°C)

VOH @ RL = 100k

VOH @ RL = 2k

AV = 10,

VIN = 1.31V

VS = ±15V

-13.2

-13.1

-13.0

-12.9

-12.8

-12.7

-12.6

-12.5

-12.4

-12.3

-12.2

-60 -40 -20 0 20 40 60 80 100 120

VOUT (V)

TEMPERATURE (°C)

VOL @ RL = 2k

VOL @ RL = 100k

= 10,

= - 1.31V

15V

ISL70227SRH

9FN7925.1

September 23, 2011

FIGURE 20. VOH vs OUTPUT CURRENT FIGURE 21. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL=10kΩ,

CL = 10pF

FIGURE 22. VOL vs OUTPUT CURRENT FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL=10kΩ,

CL = 100pF

FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 25. GAIN vs FREQUENCY vs TEMPERATURE

Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)

0.0001 0.001 0.01 0.1 1 10

VOH (V)

OUTPUT CURRENT (mA)

VOUT (V) 0°C

VOUT (V) +25°C

VOUT (V) +125°C

VOUT (V) -55°C

AV = 10,

VIN = 1.31V

VS = ±15V

OPEN LOOP GAIN (dB)/PHASE (°)

FREQUENCY (Hz)

-100

-80

-60

-40

-20

100

120

140

160

180

200

0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M

RL = 10k

SIMULATION

CL = 10pF

GAIN

PHASE

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.0001 0.001 0.01 0.1 1 10

VOUT (V) 0°C

VOUT (V) +25°C

VOUT (V) +125°C

VOUT (V) -55°C

VOL (V)

OUTPUT CURRENT (mA)

AV = 10,

VIN = - 1.31V

VS = ±15V

OPEN LOOP GAIN (dB)/PHASE(°)

FREQUENCY (Hz)

-100

-80

-60

-40

-20

100

120

140

160

180

200

0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M

RL = 10k

SIMULATION

CL = 100pF

GAIN

PHASE

FREQUENCY (Hz)

GAIN (dB)

100k 1M 10M 100M

10k

-10

100

AV = 1

AV = 100

AV = 1000

VS = ±15V

VOUT = 100mVP-P

CL = 3.5pF

RL = INF

Rg = 100, Rf = 100k

Rg = 10k, Rf = 100k

AV = 10

Rg = 1k, Rf = 100k

Rg = OPEN, Rf = 0

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

GAIN (dB)

= 10,

OUT

= 100mV

P-P

= +-15V, R

= 2kΩ

+25°C

-60°C

+125°C

+130°C

ISL70227SRH

10 FN7925.1

September 23, 2011

FIGURE 26. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE

Rf/Rg

FIGURE 27. GAIN vs FREQUENCY vs RL

FIGURE 28. GAIN vs FREQUENCY vs CLFIGURE 29. GAIN vs FREQUENCY vs SUPPLY VOLTAGE

FIGURE 30. LARGE SIGNAL 10V STEP RESPONSE, VS= ±15V FIGURE 31. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V vs

TEMPERATURE

Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)

NORMALIZED GAIN (dB)

-5

-3

-1

FREQUENCY (Hz)

100k 1M 10M 100M

10k

Rf = Rg = 100k

Rf = Rg = 100

Rf = Rg = 10k

Rf = Rg = 1k

VS = ±15V

RL = 10k

AV = +2

VOUT = 100mVP-P

CL = 3.5pF

-5

-4

-3

-2

-1

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

100k 1M 10M 100M

10k

VS = ±15V

AV = +1

VOUT = 100mVP-P

CL = 3.5pF

RL = 100

RL = 49.9

RL = 10k

RL = 1k

RL = 499

NORMALIZED GAIN (dB)

FREQUENCY (Hz)

100k 1M 10M 100M

10k

-3

-2

-1

VS = ±15V

RL = 10k

AV = +1

VOUT = 100mVP-P

CL = 1000pF

CL = 220pF

CL = 100pF

CL = 25.5pF

CL = 3.5pF

NORMALIZED GAIN (dB)

FREQUENCY (Hz)

100k 1M 10M 100M

10k

-3

-2

-1

CL = 3.5pF

RL = 10k

AV = +1

VOUT = 100mVP-P

VS = ±2.25V

VS = ±5V

VS = ±15V

-6

-5

-4

-3

-2

0 5 10 15 20 25 30

TIME (µs)

LARGE SIGNAL (V)

VS = ±15V

AV = 1

CL = 3.5pF

VOUT = 10VP-P

Rf = 0 Rg = inf

RL = 2k

RL = 10k

-6

-5

-4

-3

-2

-1

0 10203040

LARGE SIGNAL (V)

TIME (µs)

OUTPUT -55°C

OUTPUT +125°C

OUTPUT +25°C

VS = ±15V

AV = 1

RL = 2k

VOUT = 10VP-P

Rf = 0 Rg = inf

ISL70227SRH

11 FN7925.1

September 23, 2011

FIGURE 32. LARGE SIGNAL TRANSIENT RESPONSE vs RL,

VS= ±5V, ±15V

FIGURE 33. SMALL SIGNAL TRANSIENT RESPONSE,

VS= ±5V, ±15V

FIGURE 34. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,

VS= ±15V

FIGURE 35. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,

VS=±15V

FIGURE 36. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V

Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)

TIME (µs)

LARGE SIGNAL (V)

-2.4

-2.0

-1.6

-1.2

-0.8

-0.4

0.4

0.8

1.2

1.6

2.0

2.4

0 5 10 15 20 25 30 35 40

AV = 1

CL = 3.5pF

VOUT = 4VP-P

VS = ±15V, RL = 2k, 10k

VS = ±5V, RL = 2k, 10k

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TIME (ms)

SMALL SIGNAL (mV)

RL = 2k

AV = 1

CL = 3.5pF

VOUT = 100mVP-P

VS = ±5V, ±15V

TIME (µs)

-0.26

-0.20

-0.18

-0.14

-0.10

-0.06

-0.02

0.02

0.06

0 5 10 15 20 25 30 35 40

-1

OUTPUT (V)

INPUT (V)

INPUT

OUTPUT

VS = ±15V

RL = 10k

AV = 100

CL = 3.5pF

Rf = 100k, Rg = 1k

VIN = 200mVP-P

TIME (µs)

-0.06

-0.02

0.02

0.06

0.10

0.04

0.08

0.22

0.26

0 5 10 15 20 25 30 35 40

-14

-12

-10

-8

-6

-4

-2

OUTPUT (V)

INPUT (V)

INPUT

OUTPUT

VS = ±15V

RL = 10k

AV = 100

CL = 3.5pF

Rf = 100k, Rg = 1k

VIN = 200mVP-P

CAPACITANCE (pF)

10 100 1000 10000

OVERSHOOT +

VS = ±15V

RL = 10k

AV = 1

VOUT = 100mVP-P

OVERSHOOT -

OVERSHOOT (%)

ISL70227SRH

12 FN7925.1

September 23, 2011

Applications Information

Functional Description

The ISL70227SRH is a dual, low noise 10MHz BW precision

op amp fabricated in a new precision 40V complementary

bipolar DI process. A super-beta NPN input stage with input bias

current cancellation provides low input bias current (1nA typical),

low input offset voltage (10µV typ), low input noise voltage

(3nV/√Hz), and low 1/f noise corner frequency (5Hz). These

amplifiers also feature high open loop gain (1500V/mV) for

excellent CMRR (120dB) and THD+N performance (0.0002% @

3.5VRMS, 1kHz into 2kΩ). A complimentary bipolar output stage

enables high capacitive load drive without external

compensation.

Operating Voltage Range

The devices are designed to operate over the 4.5V (±2.25V) to

36V (±18V) range and are fully characterized at 30V (±15V).

Parameter variation with operating voltage is shown in the

“Typical Performance Curves” beginning on page 7.

Input ESD Diode Protection

The input terminals (IN+ and IN-) have internal ESD protection

diodes to the positive and negative supply rails, and an additional

anti-parallel diode pair across the inputs (see Figures 37 and 38).

For unity gain applications (see Figure 37) where the output is

connected directly to the non-inverting input a current limiting

resistor (RIN) will be needed under the following conditions to

protect the anti-parallel differential input protection diodes.

• The amplifier input is supplied from a low impedance source.

• The input voltage rate-of-rise (dV/dt) exceeds the maximum

slew rate of the amplifier (±3.6V/µs).

If the output lags far enough behind the input, the anti-parallel

input diodes can conduct. For example, if an input pulse ramps

from 0V to +10V in 1µs, then the output of the ISL70227SRH will

reach only +3.6V (slew rate = 3.6V/µs) while the input is at 10V,

The input differential voltage of 6.4V will force input ESD diodes to

conduct, dumping the input current directly into the output stage

and the load. The resulting current flow can cause permanent

damage to the ESD diodes. The ESD diodes are rated to 20mA,

and in the previous example, setting RIN to 1k resistor (see

Figure 37) would limit the current to <6.4mA, and provide

additional protection up to ±20V at the input.

In applications where one or both amplifier input terminals are at

risk of exposure to high voltage, current limiting resistors may be

needed at each input terminal (see Figure 38 RIN+, RIN-) to limit

current through the power supply ESD diodes to 20mA.

Output Current Limiting

The output current is internally limited to approximately ±45mA

at +25°C and can withstand a short circuit to either rail as long

as the power dissipation limits are not exceeded. This applies to

only 1 amplifier at a time. Continuous operation under these

conditions may degrade long term reliability.

Output Phase Reversal

Output phase reversal is a change of polarity in the amplifier

transfer function when the input voltage exceeds the supply

voltage. The ISL70227SRH are immune to output phase reversal,

even when the input voltage is 1V beyond the supplies.

Power Dissipation

It is possible to exceed the +150°C maximum junction

temperatures under certain load and power supply conditions. It

is therefore important to calculate the maximum junction

temperature (TJMAX) for all applications to determine if power

supply voltages, load conditions, or package type need to be

modified to remain in the safe operating area. These parameters

are related using Equation 1:

where:

•P

DMAXTOTAL is the sum of the maximum power dissipation of

each amplifier in the package (PDMAX)

•PD

MAX for each amplifier can be calculated using Equation 2:

where:

•T

MAX = Maximum ambient temperature

•θJA = Thermal resistance of the package

•PD

MAX = Maximum power dissipation of 1 amplifier

•V

S = Total supply voltage

•I

qMAX = Maximum quiescent supply current of 1 amplifier

•V

OUTMAX = Maximum output voltage swing of the application

•R

L = Load resistance

FIGURE 37. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN

RIN

VIN

VOUT

V+

V-

FIGURE 38. INPUT ESD DIODE CURRENT LIMITING - DIFFERENTIAL

INPUT

RIN-

VIN-VOUT

V+

V-

RIN+

VIN+

TJMAX TMAX θJAxPDMAXTOTAL

+= (EQ. 1)

PDMAX VSIqMAX VS

( - VOUTMAX )VOUTMAX

------------------------

×+×=(EQ. 2)

ISL70227SRH

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7925.1

September 23, 2011

For additional products, see www.intersil.com/product_tree

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL70227SRH

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

REVISION DATE CHANGE

FN7925.1 9/20/11 Added “Related Literature” on page 1.

Made correction to Ordering Information - Eval board name changed from "ISL70227SRHEVAL1Z" TO

"ISL70227MHEVAL1Z"

FN7925.0 9/7/11 Initial Release.

ISL70227SRH

14 FN7925.1

September 23, 2011

Ceramic Metal Seal Flatpack Packages (Flatpack)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark. Alternately, a tab (dimension k)

may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the lim-

its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass

overrun.

4. Dimensions b1 and c1 apply to lead base metal only . Dimension

M applies to lead plating and finish thickness. The maximum lim-

its of lead dimensions b and c or M shall be measured at the cen-

troid of the finished lead surfaces, when solder dip or tin plate

lead finish is applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric mate-

rials shall be molded to the bottom of the package to cover the

leads.

8. Dimension Q shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension Q minimum

shall be reduced by 0.0015 inch (0.038mm) maximum when sol-

der dip lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D-

-C-

0.004 H A - B

S S

-A- -B-

0.036 H A - B

S S

SEATING AND

LE2

E3 E3

BASE PLANE

-H-

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

PIN NO. 1

ID AREA

K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)

10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.045 0.115 1.14 2.92 -

b 0.015 0.022 0.38 0.56 -

b1 0.015 0.019 0.38 0.48 -

c 0.004 0.009 0.10 0.23 -

c1 0.004 0.006 0.10 0.15 -

D - 0.290 - 7.37 3

E 0.240 0.260 6.10 6.60 -

E1 -0.280-7.113

E2 0.125 - 3.18 - -

E3 0.030 - 0.76 - 7

e 0.050 BSC 1.27 BSC -

k 0.008 0.015 0.20 0.38 2

L 0.250 0.370 6.35 9.40 -

Q 0.026 0.045 0.66 1.14 8

S1 0.005 - 0.13 - 6

M - 0.0015 - 0.04 -

N10 10-

Rev. 0 3/07