QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
1
LTC4267CDHC-3
DESCRIPTION
Demonstration circuit 1249 is a PoE to 3.3V@3.0A
Isolated Converter featuring the LTC4267CDHC-3.
The board provides a complete IEEE 802.3af
power device (PD) interface and isolated 3.3V
power supply solution for use in Power-over-
Ethernet (PoE) applications in a very small printed
circuit board footprint.
The LTC4267-3 integrates the 25k
Ω
signature re-
sistor, classification current source, thermal over-
load protection, signature disable and power good
signal along with an undervoltage lockout opti-
mized for use with the IEEE required diode bridge.
The precision dual level input current limit allows
the LTC4267-3 to charge load capacitors and in-
terface with legacy PoE systems.
The LTC4267-3 combines the above features with
a current mode switching controller designed for
driving a N-channel MOSFET. It features pro-
grammable slope compensation, soft-start, and
constant frequency operation, minimizing electrical
noise even with light loads.
Design files for this circuit board are available.
Call the LTC factory.
Table 1. Performance Summary (T
A
= 25°C)
PARAMETER CONDITION VALUE
Turn-on Voltage Input from PSE -37V
Maximum Turn-off Voltage Input from PSE, PD switch turns off -31V
Minimum operating voltage I
OUT
= 3A -33V
Power Converter Input operating range V
OUT
= 3.3V, I
OUT
= 0 to 3.0A -37V to -57V
Maximum Input Current Input from PSE, PD high level current limit 375mA, typical
Maximum Output Current V
OUT
= 3.3V 3.0A
Output Voltage V
IN
= 48VDC from PSE, I
OUT
= 3.0A 3.3V, typical
Line (0% to 100% full load) 2%
Output Regulation
Load (0% to 100% of rated full load) 2%
QUICK START PROCEDURE
Demonstration circuit 1249 is easy to set up to
evaluate the performance of the LTC4267-3. For
proper equipment setup, refer to figure 1 and fol-
low the procedure below:
1. With the power source to the PSE turned off,
connect the input power supply to the board
through the J1 filtered Ethernet connector.
2. In addition to a PSE, the DC1249 board can
be powered by an alternate input power supply
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
2
through the VPORTP (TP16) and VPORTN
(TP15) terminals. Do not connect more than
one power source.
3. Connect the SIGNATURE DISABLE signal to
VPORTN.
4. Turn on the PSE or alternate input power sup-
ply and increase the voltage until the power
converter turns on. Be careful not to exceed
57VDC. NOTE: Make sure that the input volt-
age does not exceed 57VDC. If a higher volt-
age is required, power components with higher
voltage ratings should be used.
5. Verify proper classification and signature de-
tection.
6. Check the output voltage. It should be 3.3V,
typical. If there is no output, temporarily dis-
connect the load to make sure that the load is
not too high.
7. Once the proper output voltage is established,
adjust the load current within the appropriate
range and observe the output regulation, ripple
voltage, efficiency and other parameters.
OPERATION
Demonstration circuit 1249 interfaces with a cus-
tomer’s Power-over-Ethernet test setup per Figure
1. The front end of the demo circuit implements
the required Ethernet input interface transformer
coupling and common-mode termination through
the integrated connector J1. The demonstration
circuit is set up to allow data to pass in and back
out of the demo circuit while the DC1249 performs
IEEE 802.3af interface functions. The Power
Sourcing Equipment (PSE) is connected to J1 and
the PHY is optionally connected to J2.
The PD is required to have 0.1uF of capacitance
during detection; this is provided by C2. It is also
required to have at least 5uF of capacitance after
the in-rush circuit, provided by capacitors C1 and
C9.
This demo circuit allows detection and power
classification of the PD per the IEEE 802.3af
specification. During the detection process of a
PD, the LTC4267-3 displays the proper 25k
Ω
sig-
nature resistor. Signature detection may be dis-
abled, if so desired, by pulling the SIGNATURE
DISABLE line (TP10) up to VPORTP. If signature
classification is disabled, all interface functions of
the LTC4267-3 are disabled. Signature detection,
classification and the internal power MOSFET
switch are all disabled.
Note that the SIGNATURE DISABLE signal at
TP10 is an open circuit. While it is true that this
signal is internally pulled down within the
LTC4267-3, the data sheet explicitly states that
this signal must be tied to VPORTN or VPORTP.
This signal is left open only for the convenience of
the user when operating the demonstration circuit.
The SIGNATURE DISABLE signal must be prop-
erly terminated in a production application.
Classification is programmed by the selection of a
single external resistor, R17, connected to the
RCLASS pin.
After detection and classification, the PD is pow-
ered up when the input voltage exceeds the
LTC4267-3 turn-on under-voltage lock out (UVLO)
through a dual-level current-limited power switch.
While the voltage between POUT and VPORTN is
above the Power Good trip point, the amperage
through the power switch is held below the low-
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
3
level current limit. When the voltage between
POUT and VPORTN falls below the Power Good
trip point, the Power Good signal goes active low
and the amperage through the power switch is
held below the high-level current limit.
For the PD to remain powered on, it must present
to the PSE both AC and DC components of the
Maintain Power Signature (MPS). The PD must
hold the DC MPS by drawing at least 10mA or the
PSE may disconnect power. The DC1249 demo
board does implement a minimum load option with
the JP2 jumper. By enabling this jumper the the
circuit will draw approximately 16.5mA to satisfy
the DC disconnect requirements.
The synchronous Flyback converter operates at a
typical switching frequency of 300kHz, controlled
by the current mode controller portion of the
LT4267-3. Galvanic isolation is achieved through
transformer T1 and opto-isolator U4.
The primary side power path is comprised of C1,
L1, Cin1, ½ of T1, Q2, and RCS. These compo-
nents should be as close to each other as possible
when laying out the printed circuit board. The
secondary side power path is made up of the
other ½ of T1, D1, and Cox. These parts should
also be laid out as close to each other as possible,
without overlapping any of the circuitry or traces of
the primary side.
IN ORDER TO ENSURE PROPER OPERATION,
THE DESIGNER MUST ENSURE THAT THE PD
INPUT CURRENT REQUIREMENT DOES NOT
EXCEED THE LTC4267-3 CURRENT LIMIT
OVER THE UNIT’S OPERATING VOLTAGE
RANGE.
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
4
Figure 1. Proper Measurement Equipment Setup
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1249
POE TO 3.3V@3.0A ISOLATED
5
[2]
RX+
Co4
100uF
6.3V
O P T
TP16
I MIN
NOTES: UN LESS OTHERWISE SPECIFIED ,
TX+
E1
JP2
1 3
2
L1
3.3uH
R7
4.7K
Q2
FDC2512
3
4 1
2
5
6
VOUT
VCC
57V
TP9
R19
150
VPORTN
VOUT
R3
68
1206
Co1
100uF
6.3V
DI S A BL E
3 .3 V /3 A
ITH
D6
BAS516
1 2
U1
LTC4267CDHC-3
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
ITH/RUN
PGND
NGATE
PVCC
RCLASS
NC
VPORTN
NC NC
POUT
PWRGD
SIGDISA
VPORTP
SENSE
PGND
VFB
+VOUT
E NA B L E
R16
10
TP14
TP10
C11
150pF
VOUT
FOR NON-ISLATED DESIGN
C12
2200pF
250V
VPORTP
FOR NO-OPTO DESIGN S.
C13
22nF
R2
100K
1206
C4
0.1uF
R4
22
PWR GD
R15 100K
ADD C13 ON TOP OF R11.
R5
680
Co2
100uF
6.3V
C9 1uF
C7
0.33uF
SIGNATUR E DISABLE
R10 80.6k 1%
R9 OPT 1206
RX-
R6 OPT 0805
T1
PA1277NL
4
3 7
5
6
8
1
2
D8
PDZ6.8B
C2
100nF
C3
0.1uF
10V
E4
C10
0.1uF
Q1
MMBTA42
1
32
VCC
C5
22nF
ITH
U4
PS2801-1-L
1
2
4
3
[1]
Vu1
D2
SMAJ58A
12
R1
220K
1206
Co3
100uF
6.3V
[1]
U3
LT4430ES6
1
2
3 4
5
6
VIN
GND
OC FB
COMP
OPTO
Rcs
0.040
1206
to
VOUT
D5
BAS516
VU1
R11
1.5K
PGND
R18
20
1W
1%
Cin1
2.2uF
100V
D7
BAT760
D3
BAS516
1 2
R14
22.1K
[3]
[2]
[3]
J1
HFJ11-RP28E-L12
1
2
3
5
7
8
9
10
13
14
6
11
4
12
FROM
D9
GRN
+
C1
4.7uF
100V
TP15
R17
45.3 1% R13
5.1K
J2
RJ45
1
2
3
4
5
6
7
8
R12
6.8K
PHY
37V
TX-
-VOUT
C6
47pF
PSE
D1
PDS1040
TO
D4
BAS516
12
VCC
