Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3418
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
1 PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to
float output per Intel® VRM 10 specification
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
GENERAL DESCRIPTION
The ADP3418 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated, synchronous, buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns pro-
pagation delay and a 30 ns transition time. One of the drivers
can be bootstrapped, and is designed to handle the high voltage
slew rate associated with floating high-side gate drivers. The
ADP3418 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs. The OD pin
shuts off both the high-side and the low-side MOSFETs to pre-
vent rapid, output capacitor discharge during system
shutdowns.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C, and is available in an 8-lead SOIC
package.
FUNCTIONAL BLOCK DIAGRAM
14
2IN
OD
DRVH
BSTVCC
SW
PGND
DRVL
3
6
5
7
8
ADP3418
OVERLAP
PROTECTION
CIRCUIT
03229-0-001
Figure 1. Functional Block Diagram
IN
VCC C
VCC
ADP3418
BST
D1
DRVH
SW
DRVL
PGND
TO INDUCTOR
DELAY
1V
1V
12V
C
BST
Q1
Q2
36
5
7
8
1
4
03229-0-002
OD
Figure 2. General Application Circuit
ADP3418
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Low-Side Driver............................................................................ 9
High-Side Driver ...........................................................................9
Overlap Protection Circuit...........................................................9
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit........................................................................ 10
PC Board Layout Considerations............................................. 10
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
Revision A
4/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated format....................................................................... Universal
Change to General Description ...........................................................1
Change to Figure 14 ..............................................................................8
Change to Ordering Guide.................................................................12
3/03—Revision 0: Initial Version
ADP3418
Rev. A | Page 3 of 12
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range VCC 4.15 13.2 V
Supply Current ISYS BST = 12 V, IN = 0 V 3 6 mA
OD INPUT
Input Voltage High 2.8 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
Propagation Delay Time1 tpdhOD See Figure 4 20 40 ns
t
pdlOD See Figure 4 15 40 ns
PWM INPUT
Input Voltage High 3.5 V
Input Voltage Low 0.8 V
Input Current –1 +1 µA
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current VBST − VSW = 12 V 1.8 3.0 Ω
Output Resistance, Sinking Current VBST − VSW = 12 V 1.0 2.5 Ω
Transition Times1 t
rDRVH See Figure 5, VBST − VSW = 12 V,
CLOAD = 3 nF
35 45 ns
t
fDRVH See Figure 5, VBST − VSW = 12 V,
CLOAD = 3 nF
20 30 ns
Propagation Delay1
, 2 tpdhDRVH See Figure 5, VBST − VSW = 12 V 40 65 ns
t
pdlDRVH VBST − VSW = 12 V 20 35 ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current 1.8 3.0 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Transition Times1 trDRVL See Figure 5, CLOAD = 3 nF 25 35 ns
t
fDRVL See Figure 5, CLOAD = 3 nF 21 30 ns
Propagation Delay1
,
2 tpdhDRVL See Figure 5 30 60 ns
t
pdlDRVL See Figure 5 10 20 ns
1 AC specifications are guaranteed by characterization, but not production tested.
2 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
ADP3418
Rev. A | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC –0.3 V to +15 V
BST –0.3 V to VCC + 15 V
BST to SW –0.3 V to +15 V
SW
DC –5 V to +15 V
<200 ns –10 V to +15 V
DRVH SW – 0.3 V to BST + 0.3 V
DRVL (<200 ns) –2 V to VCC + 0.3 V
All Other Inputs and Outputs –0.3 V to VCC + 0.3 V
Operating Ambient Temperature
Range
0°C to 85°C
Operating Junction Temperature
Range
0°C to 150°C
Storage Temperature Range –65°C to +150°C
Junction-to-Air Thermal Resistance
(θJA)
2-Layer Board 123°C/W
4-Layer Board 90°C/W
Lead Temperature
(Soldering, 10 sec)
300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all voltages
are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADP3418
Rev. A | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP3418
TOP VIEW
(Not to Scale)
BST
IN
OD
V
CC
DRVH
SW
PGND
DRVL
1
2
3
8
7
6
4 5
03229-0-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF.
2 IN Logic Level Input. This pin has primary control of the drive outputs.
3 OD Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for the
upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn on of the lower MOSFET
until the voltage is below ~1 V. Thus, according to operating conditions, the high-low transition delay is determined
at this pin.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
ADP3418
Rev. A | Page 6 of 12
TIMING CHARACTERISTICS
OD
DRVH
OR
DRVL
90%
t
pdlOD
10%
t
pdhOD
03229-0-004
Figure 4. Output Disable Timing Diagram
IN
DRVL
DRVH-SW
SW
t
pdlDRVL
t
fDRVL
t
pdhDRVH
t
rDRVH
t
pdlDRVH
t
rDRVL
t
fDRVH
t
pdhDRVL
V
TH
1V
V
TH
03229-0-005
Figure 5. Nonoverlap Timing Diagram. Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted.
ADP3418
Rev. A | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
2
3
1
DRVL
DRVH
IN
03229-0-006
Figure 6. DRVH Rise and DRVL Fall Times
2
3
1
DRVL
DRVH
IN
03229-0-007
Figure 7. DRVH Fall and DRVL Rise Times
40
35
30
25
20
RISETIME (ns)
JUNCTIONTEMPERATURE (°C)
0255075100125
V
CC
= 12V
C
LOAD
= 3nF DRVH
DRVL
03229-0-008
Figure 8. DRVH and DRVL Rise Times vs. Temperature
26
24
22
20
18
16
FALL TIME (ns)
JUNCTIONTEMPERATURE (
°C)
0 25 50 75 100 125
V
CC
= 12V
C
LOAD
= 3nF
DRVL
DRVH
03229-0-009
Figure 9. DRVH and DRVL Fall Times vs. Temperature
60
50
40
30
20
10
RISE TIME– ns
LOAD CAPACITANCE – nF
134
T
A
= 25
°C
V
CC
= 12V
DRVH
DRVL
5
03229-0-010
2
Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance
35
30
25
20
15
10
FALL TIME (ns)
LOAD CAPACITANCE (nF)
134
T
A
= 25
°C
V
CC
= 12V
DRVL
DRVH
5
03229-0-011
2
Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance
ADP3418
Rev. A | Page 8 of 12
60
40
20
0
SUPPLY CURRENT (mA)
TA = 25
°C
V
CC
= 12V
C
LOAD
= 3nF
IN FREQUENCY (kHz)
0 1000 1200
03229-0-012
200 400 600 800
Figure 12. Supply Current vs. Frequency
16
15
14
13
12
SUPPLY CURENT (mA)
JUNCTIONTEMPERATURE (
°C)
0 25 50 75 100 125
V
CC
= 12V
C
LOAD
= 3nF
f
IN
= 250kHz
03229-0-013
Figure 13. Supply Current vs. Temperature
5
4
3
2
1
0
DRVL OUTPUTVOLTAGE (V)
V
CC
VOLTAGE (V)
01 2 3 4 5
03229-0-014
T
A
= 25°C
C
LOAD
= 3nF
Figure 14. DRVL Output Voltage vs. Supply Voltage
ADP3418
Rev. A | Page 9 of 12
THEORY OF OPERATION
The ADP3418 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter top-
ology. A single PWM input signal is all that is required to pro-
perly drive the high-side and the low-side MOSFETs. Each dri-
ver is capable of driving a 3 nF load at speeds up to 500 kHz.
A more detailed description of the ADP3418 and its features
follows. Refer to the Functional Block Diagram.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced
low RDS(ON) N-channel MOSFET. The bias to the low-side driver
is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180 degrees
out of phase with the PWM input. When the ADP3418 is
disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating, low RDS(ON)
N-channel MOSFET. The bias voltage for the high-side driver is
developed by an external bootstrap supply circuit, which is
connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3418 is starting up, the SW pin is
at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high-side
driver will begin to turn on the high-side MOSFET, Q1, by
pulling charge out of CBST. As Q1 turns on, the SW pin will rise
up to VIN, forcing the BST pin to VIN + VC(BST), which is enough
gate-to-source voltage to hold Q1 on. To complete the cycle, Q1
is switched off by pulling the gate down to the voltage at the SW
pin. When the low-side MOSFET, Q2, turns on, the SW pin is
pulled to ground. This allows the bootstrap capacitor to charge
up to VCC again.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on-off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from Q1’s
turn-off to Q2’s turn-on, and by internally setting the delay
from Q2’s turn-off to Q1’s turn-on.
To prevent the overlap of the gate drives during Q1’s turn-off
and Q2’s turn-on, the overlap circuit monitors the voltage at the
SW pin. When the PWM input signal goes low, Q1 will begin to
turn-off (after a propagation delay), but before Q2 can turn on,
the overlap protection circuit waits for the voltage at the SW pin
to fall from VIN to 1 V. Once the voltage on the SW pin has fal-
len to 1 V, Q2 will begin turn-on. By waiting for the voltage on
the SW pin to reach 1 V, the overlap protection circuit ensures
that Q1 is off before Q2 turns on, regardless of variations in
temperature, supply voltage, gate charge, and drive current.
To prevent the overlap of the gate drives during Q2’s turn-off
and Q1’s turn-on, the overlap circuit provides an internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn off (after a propagation delay), but before Q1
can turn on, the overlap protection circuit waits for the voltage
at DRVL to drop to around 10% of VCC. Once the voltage at
DRVL has reached the 10% point, the overlap protection circuit
will wait for a 20 ns typical propagation delay. Once the delay
period has expired, Q1 will begin turn-on.
ADP3418
Rev. A | Page 10 of 12
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3418, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3418.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST) and
a diode, as shown in Figure 2. These components can be
selected after the high-side MOSFET has been chosen. The
bootstrap capacitor must have a voltage rating that is able to
handle twice the maximum supply voltage. A minimum 50 V
rating is recommended. The capacitance is determined using
the following equation:
BST
GATE
BST V
Q
C∆
= (1)
where QGATE is the total gate charge of the high-side MOSFET,
and ∆VBST is the voltage droop allowed on the high-side
MOSFET drive. For example, an IPD30N06 has a total gate
charge of about 20 nC. For an allowed droop of 200 mV, the
required bootstrap capacitance is 100 nF. A good quality
ceramic capacitor should be used.
A small-signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
(2)
MAX
GATE
AVGF fQI ×=
)(
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked in-
circuit, since this is dependent on the source impedance of the
12 V supply and the ESR of CBST.
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards.
1. Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
2. Connect the PGND pin of the ADP3418 as close as
possible to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to the VCC and PGND pins.
4. Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 16 shows how three drivers can be
combined with the ADP3168 to form a total power conversion
solution for generating VCC(CORE) for an Intel CPU that is VRD 10
compliant.
Figure 15 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the ADP3168 data sheet.
D1 C
BST
C
VCC
03229-0-016
Figure 15. External Component Placement Example for the ADP3418 Driver
ADP3418
Rev. A | Page 11 of 12
V
IN
12V
V
IN
RTN
ENABLE
POWER
GOOD
R
LIM
200k
Ω
R
PH1
124k
Ω
FROM CPU
R
R
412k
Ω
Q2
IPD06N03L
Q5
IPD06N03L
Q8
IPD06N03L
Q1
IPD12N03L
Q3
IPD06N03L
Q4
IPD12N03L
C
DLY
39nF
V
CC(CORE)
0.8375V – 1.6V
65A AVG, 74A PK
V
CC(CORE) RTN
820
µ
F/2.5V × 8
FUJITSU RE SERIES
14m
Ω
ESR (EACH)
+
L2
600nH/1.6m
Ω
L1
1.6
µ
H
C1
R
T
249k
Ω
C12
100nF
C21
+
C28
L3
600nH/1.6mΩ
U3
ADP3418
BST
IN
VCC
DRVH
SW
PGND
DRVL
C11
4.7
µ
F
D2
1N4148WS
D3
1N4148WS
D4
1N4148WS
C8
100nF
C7
4.7
µ
F
C9
4.7
µ
F
C13
4.7
µ
F
C17
4.7
µ
F
U2
ADP3418
1
2
3
8
7
6
4 5
1
2
3
8
7
6
4 5
1
2
3
8
7
6
4 5
BST
IN
OD
VCC
DRVH
SW
PGND
DRVL
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
FB
COMP
PWRGD
EN
DELAY
RT
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT
26
25
24
28
27
19
22
21
20
23
3
1
4
5
2
6
10
14
7
8
9
11
12
13
15
18
17
16
U1
ADP3168
Q7
IPD12N03L
C16
100nF
L4
600nH/1.6mΩ
U4
ADP3418
BST
IN
VCC
DRVH
SW
PGND
DRVL
C15
4.7
µ
F
C19
1
µ
F
R4
10
Ω
C20
33
µ
F
C
FB
33pF
C
A
390pF
C
CS1
2.2nF
C
CS2
1.5nF
C6
470
µ
F/16V × 6
NICHICON PW SERIES
+ +
10µF×20
MLCC
IN
SOCKET
C18
4.7nF
C14
4.7nF
C10
4.7nF
R3
2.2
Ω
R
TH
100k
Ω
, 5%
R2
2.2
Ω
R1
2.2
Ω
D1
1N4148WS
R
CS1
35.7k
Ω
C
B
1.5nF
R
PH3
124k
Ω
RDLY
390k
Ω
Q9
IPD06N03L
Q6
IPD06N03L
R
SW1
R
SW3
R
SW2
RCS2
73.2k
Ω
+
R
PH2
124k
Ω
R
B
1.33k
Ω
R
A
16.9k
Ω
OD
OD
03229-0-015
Figure 16. VRD 10 Compliant Intel CPU Supply Circuit
ADP3418
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARIT
Y
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 17. 8-Lead Standard Small Outline Package [SOIC]
(RN-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option Quantity Per Reel
ADP3418JR 0°C to 85°C 8-Lead SOIC RN-8 N/A
ADP3418JR–REEL 0°C to 85°C 8-Lead SOIC RN-8 2500
ADP3418JRZ* 0°C to 85°C 8-Lead SOIC RN-8 N/A
ADP3418JRZ–REEL* 0°C to 85°C 8-Lead SOIC RN-8 2500
*Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective owners.
C03229-0-4/04(A)
