Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J FEATURES Few external components required High efficiency fully DC coupled vertical bridge output circuit Vertical flyback switch with short rise and fall times Built-in guard circuit Thermal protection circuit Improved EMC performance due to differential inputs East-west output stage. QUICK REFERENCE DATA GENERAL DESCRIPTION The TDA8358UJ is a power circuit for use in 90 and 110 colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. The east-west output stage is able to supply the sink current for a diode modulator circuit. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown. SYMBOL PARAMETER CONDITIONS | MIN. | TYP. | MAX. | UNIT Supplies Vp supply voltage 7.5 12 18 Vv VeB flyback supply voltage 2Vp 45 66 Vv la(P)(av) average quiescent supply current during scan - 10 15 mA lo(FB)(av) average quiescent flyback supply current during scan - - 10 mA Pew east-west power dissipation - - 4 W Prot total power dissipation - - 15 W Inputs and outputs Viait)(p-p) differential input voltage (peak-to-peak value) - 1000 |1500 | mV lo(p-p) output current (peak-to-peak value) - - 3.2 A Flyback switch lo(peak) maximum (peak) output current [t <1.5ms | - |- {+1 8 | A East-west amplifier Vo output voltage - - 68 Vv Viwbias) input bias voltage 2 - 3.2 Vv lo output current - - 750 mA Thermal data; in accordance with IEC 747-1 Tstg storage temperature 55 - +150 |C Tamb ambient temperature 25 - +75 C Tj junction temperature - - 150 C 1999 Dec 22Philips Semiconductors Product specification Full bridge vertical deflection output circuit . . ge TDA8358J in LVDMOS with east-west amplifier ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6 BLOCK DIAGRAM Vi(p-p) Vi(bias) N i INA 0 Vi(p-p) Vi(bias) Ze li(p-p) COMP GUARD Vp VFB & 13 "1 3 9 vy COMP, GUARD | circuit | | ciRcUIT a | M5 D2 p3 jm | I $ a > Lf |e -e INPUT 12 AND < FEEDB FEEDBACK CIRCUIT | . | pe, M1 ~ 4jours | rm M3 | I TDA8358J Iv) AAA INEW yv thy 8 ty Fig.1 VGND EWGND Block diagram. OUTEW KAA MGL866 1999 Dec 22Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J PINNING SYMBOL PIN DESCRIPTION INA 1 input A INB 2 input B Vp 3 supply voltage OUTB 4 output B INEW 5 east-west input VGND 6 vertical ground EWGND 7 east-west ground OUTEW 8 east-west output Ves 9 flyback supply voltage OUTA 10 | output A GUARD 11 guard output FEEDB 12 | feedback input COMP 13 | compensation input INA [4 | U INB [ 2 | vp [3 | outs [4 | INEW [5 | vanp [6 | TDA8358J EWGND [7 | ouTew [8 | Vee [| OUTA [110] GuARD [17] FEEDB [12] COMP | 13 ra MGL867 The die has been glued to the metal block of the package. If the metal block is not insulated from the heatsink, the heatsink shall only be connected directly to pin VGND. Fig.2 Pin configuration. 1999 Dec 22 FUNCTIONAL DESCRIPTION Vertical output stage The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors Rovi and Reve (see Fig.3) connected to pins INA and INB. The differential input voltage is compared with the voltage across the measuring resistor Ry, providing internal feedback information. The voltage across Rr is proportional with the output current. The relationship between the differential input current and the output current is defined by: 2 x lidinyp-p) X Rov = loip-p) x Rv The output current should measure 0.5 to 3.2 A (p-p) and is determined by the value of Ry and Rey. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the value of Ry and the internal bondwire resistance (typical value 50 mQ) the actual value of the current in the deflection coil will be about 5% lower than calculated. Flyback supply The flyback voltage is determined by the flyback supply voltage Veg. The principle of two supply voltages (class G) allows to use an optimum supply voltage Vp for scan and an optimum flyback supply voltage Veg for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to Vrg, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/us. Protection The output circuit contains protection circuits for: e Too high die temperature e Overvoltage of output A.Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J Guard circuit A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: During thermal protection (Tj = 170 C) e During an open-loop condition. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. Damping resistor compensation HF loop stability is achieved by connecting a damping resistor Rp1 (see Fig.4) across the deflection coil. The current values in Rp; during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor Ry, resulting in a too low deflection coil current at the start of the scan. The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. 1999 Dec 22 For that purpose a compensation resistor Rewp is connected between pins OUTA and COMP. The value of Remp is calculated by: (Veg Vioss(eB) ~ Vp) X Rp x (Rg + 300) (Veg Vioss(FB) ~ !coilcpeaky * Reoit) Riv Romp = where: Reoi is the coil resistance * Vioss(FB) is the voltage loss between pins Vrg and OUTA at flyback. East-west amplifier The east-west amplifier is a current driver sinking the current of a diode modulator circuit. A feedback resistor Rewer (see Fig.4) has to be connected between the input and output of the inverting east-west amplifier in order to convert the east-west correction input current into an output voltage. The output voltage of the east-west circuit at pin OUTEW is given by: Vo= lj x Rewe + Vj The maximum output voltage is Voymax) = 68 V, while the maximum output current of the circuit is lomax = 750 mA.Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYDMOS with east-west amplifier TDAB358 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. | MAX. | UNIT Vp supply voltage - 18 Vv VeB flyback supply voltage - 68 Vv AVvenp-Ewenp | voltage difference between - 0.3 Vv pins VGND and EWGND Vn DC voltage pins OUTA and OUTEW note 1 - 68 Vv pin OUTB = Vp Vv pins INA, INB, INEW, GUARD, -0.5 |Vp Vv FEEDB, and COMP n DC current pins OUTA and OUTB during scan (p-p) - 3.2 A pins OUTA and OUTB at flyback (peak); t< 1.5 ms - +18 =A pins INA, INB, INEW, GUARD, -20 +20 mA FEEDB, and COMP pin OUTEW - 750 mA lu latch-up current input current into any pin; - +200 |mA pin voltage is 1.5 x Vp; Tj = 150 C input current out of any pin; -200 |- mA pin voltage is 1.5 x Vp; Tj = 150C Ves electrostatic handling voltage machine model; note 2 -300 |+300 |V human body model; note 3 2000 | +2000 | V Pew east-west power dissipation note 4 - 4 W Prot total power dissipation - 15 W Tstg storage temperature 55 +150 |C Tamb ambient temperature 25 +75 C Tj junction temperature note 5 - 150 C Notes 1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage. Equivalent to 200 pF capacitance discharge through a 0 Q resistor. 2 3. Equivalent to 100 pF capacitance discharge through a 1.5 kQ resistor. 4 For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west power dissipation Pewipeak) = 15 W. 5. Internally limited by thermal protection at Tj = 170 C. THERMAL CHARACTERISTICS In accordance with IEC 747-1. SYMBOL PARAMETER CONDITIONS VALUE UNIT Rih(-c) thermal resistance from junction to case 4 K/W Rih(-a) thermal resistance from junction to ambient in free air 40 K/W 1999 Dec 22 6Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYVDMOS with east-west amplifier TDAB358 CHARACTERISTICS Vp = 12 V; Veg = 45 V; frert = 50 HZ; Viipiasy = 880 MV; Tamp = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS | min. | Typ. | MAX. | UNIT Supplies Vp operating supply voltage 7.5 12 18 Vv VeB flyback supply voltage note 1 2Vp 45 66 Vv la(P)(av) average quiescent supply current during scan - 10 15 mA lap) quiescent supply current no signal; no load - 55 75 mA la(FB)(av) average quiescent flyback supply during scan - - 10 mA current Inputs A and B Viqaity(p-p) differential input voltage note 2 - 1000 {1500 | mV (peak-to-peak value) Viqbias) input bias voltage note 2 100 880 1600 | mV I\(bias) input bias current - 25 35 HA Outputs A and B Vioss(1) voltage loss first scan part note 3 lb=l.1A = = 4.5 Vv lb=1.6A = = 6.6 Vv Vioss(2) voltage loss second scan part note 4 o=-1.1A = = 3.3 Vv lb=-1.6A = = 4.8 Vv lo(p-p) output current (peak-to-peak value) - - 3.2 A LE linearity error lo(p-p) = 3.2 A; notes 5 and 6 adjacent blocks - 1 2 % non adjacent blocks - 1 3 % Vottset offset voltage across Ry; Viqit) = 0 V Viwiasy = 200 mV - - +H15 mV Viqbias) = 1 V = = +20 mV AVottse(T) | offset voltage variation with across Ry; Vii) = 0 V - - 40 yV/K temperature Vo DC output voltage Vii) = OV - 0.5Vp |- Vv Gyo open-loop voltage gain notes 7 and 8 - 60 - dB f_gaB(h) high 3 dB cut-off frequency open-loop - 1 - kHz Gy voltage gain note 9 - 1 - AGyt) voltage gain variation with - - 104 |K"1 temperature PSRR power supply rejection ratio note 10 80 90 - dB 1999 Dec 22 7Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYVDMOS with east-west amplifier TDAB3584 SYMBOL | PARAMETER | CONDITIONS | min. | Typ. | MAX. | UNIT Flyback switch lo(peak) maximum (peak) output current t< 1.5 ms - - +18 =A Vioss(FB) voltage loss at flyback note 11 lb=1.4A - 75 8.5 V lb=1.6A - 8 9 Vv Guard circuit Voigra) guard output voltage lowgray = 100 WA 5 6 7 Vv Voigrdy(max) | allowable guard voltage maximum leakage current - - 18 Vv lL(max) = 10 WA lowgra) output current Voygra) = 0 V; not active - - 10 HA Voigra) = 4.5 V; active 1 - 2.5 mA East-west amplifier Vo output voltage at pin OUTEW - - 68 Vv Vioss voltage loss ly = 750 mA; note 12 - - 5 Vv Viqbias) input bias voltage 2 2.5 3.2 Vv I\(bias) input bias current into pin INEW; note 13 ly = 100 mA - 2.5 - HA lp = 500 mA - 114.5 |- HA Gyo open-loop voltage gain - - 30 dB THD harmonic distortion - 0.5 1 % f_3aB(h) high 3 dB cut-off frequency - - 1 MHz Notes 1. To limit Vouta to 68 V, Veg must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA and Vrz at the first part of the flyback. Allowable input range for both inputs: Vitbias) + Viqait) (peak) < 1600 mV and Vivvias) _ Viqdit\(peak) > 100 mV. This value specifies the sum of the voltage losses of the internal current paths between pins Vp and OUTA, and between pins OUTB and GND. Specified for Tj = 125 C. The temperature coefficient for Viogg(1) is a positive value. This value specifies the sum of the voltage losses of the internal current paths between pins Vp and OUTB, and between pins OUTA and GND. Specified for T; = 125 C. The temperature coefficient for Vigggi2) is a positive value. The linearity error is measured for a linear input signal without S-correction and is based on the on screen measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists of two successive parts. The voltage amplitudes are measured across Ry, starting at k = 1 and ending at k = 10, where V; and V,,1 are the measured voltages of two successive blocks. Vinin, Vmax and Vayg are the minimum, maximum and average voltages respectively. The linearity errors are defined as: _ Vi ~ Vi at : a) LE = , x 100% (adjacent blocks) Vavg _ Vmax _ Vinin : b) LE = x 100% (non adjacent blocks) Vavg 1999 Dec 22 8Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYDMOS with east-west amplifier TDA8358J 6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to voltage dependent S-distortion in the input stage. _ Vouta ~ Vouts 7. Gyeon ~ V V FEEDB *OUTB 8. Pin FEEDB not connected. 9 Ge Vreepe ~ Vout Vina~ Vine 10. Vprrippiey = 500 mV (RMS value); 50 Hz < ferrippiey < 1 KHZ; measured across Rwy. 11. This value specifies the internal voltage loss of the current path between pins Veg and OUTA. 12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND. 13. Measured for Rewe = 10 kQ; Rew. = 302; V,=6V. a) Forl, = 100 mA and a voltage of 9 V at Rew. connected to the line output transformer, the east-west amplifier input current (see Fig.4) is |; = 300 HA. b) For l, = 500 mA and a voltage of 21 V at Rew. connected to the line output transformer, the east-west amplifier input current (see Fig.4) is |; = 350 WA. 1999 Dec 22 9Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYDMOS with east-west amplifier TDA8358J APPLICATION INFORMATION RerRpD a Vp 4.7 kQ VFB cOMP___fGUARD| Vp ter bee Vy i 100 nF 100 nF 13 11 3 9 y . COMP. GUARD CIRCUIT | | CIRCUIT me x m4 Vi(p-p) D2 V INK, b3 Vv I(bias) \ |e M2 lpi 11 | pt t L oe INA | 14 T 10] OUTA _ D Sr, Tt Revi |K RL 2.2 ka | R 3.22 (1%) INPUT _12| FEEDB Ss , AND - a 2.7 kQ lvaiy) O FEEDBACK CIRCUIT Loy Ruy (bias) at 10 nF 0.52 D INB 2 4 Reve 4] OUTB > }_] > 2.2 kQ. _ |41.- (1%) re M3 _ Vv, , 4 TDA8358J i(P-p) Vi(bias) Z I i. } = A) A = INEW5 M6] g| OUTEW TT 0 > 4 > {__}- * to line output REWL __ transformer lip. ; 30 0. | __(e-P) I 6 7 a VGND EWGND Kav) EX 2 EWF + 10 kQ , Qi a MGL873 Fig.3 Test diagram. 1999 Dec 22 10Product specification Philips Semiconductors Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J weibelp uolyeaddy 64 uoljoe}oud JeAO USBI, pepuse}xe JeuolidO (gE) jue|eBainbe JO GSECA {UO!}Oe}O1d YeAO Yse|} PepUa|xXy (Z) eOUBPEdUU! [10D UOJOa|Jep OU} UO PUedep sen|ea jUeUOdWOD feUCIIdO (1) yt org = Oy yr oz = ueyldwe jsem-sey Woe = O99 tyr ogz = OREDUP)Y Ayr Gay = (S| srl Ov = 84 !ZH OG = 4*4y INOW! LOOSE vLeTOW {__} 0 we Oy e8 _ | AM3y (ae)l, aNoMa CNDA / oral 9 \ (d-d)y el JOUUOJSUeL} TWSy tH I < < Indino Sul O} Maino |8 |9w mal mn MANI 0 VV V 7 (SeIq)I, resesval re (d-d)1, ew 4 ano | (%L) 4u 22, G4 w1z2[] 7 )5 o s" | WW ZADY T ez 4 edu LINOUIO aN ; ywovadsas (48399M) OAL . aN a T " LNNI Hu g Sy S0SSH |21 YATIOULNOOD jjoo 3 OE Gal NOILO31430 | se YW *N (%b) Lb suzz < , wriz2!] 95 wino or Lt CL LADY TI la . 04 028 [ WNI ANDY zn a A <a 0 gay r Gn X icon) SW IDI + NN | Linowio | | Linoulo N (A S2) (A 001) du auyvno dNOO (d-d)ia, sn ozz duoor | sdzy 001 T co == = 79 1o 9 6 a el * | so | T da da | GHVND y doo hoe =n dd a 019g dy (e)H Lz , HOY AvL=da 11 1999 Dec 22Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J Supply voltage calculation For calculating the minimum required supply voltage, several specific application parameter values have to be known. These parameters are the required maximum (peak) deflection coil current Iogiipeak), the coil parameters Reo and Loi, and the measuring resistance of Ry. The required maximum (peak) deflection coil current should also include the overscan. The deflection coil resistance has to be multiplied with 1.2 in order to take account of hot conditions. Chapter Characteristics supplies values for the voltage losses of the vertical output stage. For the first part of the scan the voltage loss is given by Viogg1). For the second part of the scan the voltage loss is given by Viogg(2). The voltage drop across the deflection coil during scan is determined by the coil impedance. For the first part of the scan the inductive contribution and the ohmic contribution to the total coil voltage drop are of opposite sign, while for the second part of the scan the inductive part and the ohmic part have the same sign. For the vertical frequency the maximum frequency occurring must be applied to the calculations. The required power supply voltage Vp for the first part of the scan is given by: Vey = lcoipeaky X (Reoii + Ru) hoi x coil(peak) x fyertmax) + Vioss(1) The required power supply voltage Vp for the second part of the scan is given by: Vevey = lcoil(peak) x (Rei + Rw) + Loi x2 lcoil(peak) x fyertmax) + Vioss(2) The minimum required supply voltage Vp shall be the highest of the two values Vp,1) and Vp,2). Spread in supply voltage and component values also has to be taken into account. Flyback supply voltage calculation If the flyback time is known, the required flyback supply voltage can be calculated by the simplified formula: Vie =l.. Roo + Ru FB ~ coil(pp) tpp/X -e where: X= Leoil Rooil + Riv 1999 Dec 22 The flyback supply voltage calculated this way is about 5% to 10% higher than required. Calculation of the power dissipation of the vertical output stage The power dissipation of the vertical output stage is given by the formula: Py = Pgup ~ PL The power to be supplied is given by the formula: Poup = Vp sup lL. x sone + Vp x 0.015 [A] + 0.3 [W] In this formula 0.3 [W] represents the average value of the losses in the flyback supply. The average external load power dissipation in the deflection coil and the measuring resistor is given by the formula: 2 P, _ (coil(peaky) x(R 3 coil + Ry) Example Table 1 Application values SYMBOL VALUE UNIT Icoil(peak) 1.2 A looil(p-p) 2.4 A Leoil 5 mH Reoil 6 Q Ru 0.6 Q fyert 50 Hz teB 640 ys Table 2 Calculated values SYMBOL VALUE UNIT Vp 14 Vv Ru + Reoil (hot) 7.8 Q tvert 0.02 s x 0.000641 VeB 30 Vv Peup 8.91 Ww PL 3.74 Ww Py 5.17 WwPhilips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J Power dissipation calculation for the east-west stage In general the shape of the east-west output wave form is a parabola. The output voltage will be higher at the beginning and end of the vertical scan compared to the voltage at the scan middle, while the output current will be higher at the scan middle. This results in an almost uniform power dissipation distribution during scan. Therefore the power dissipation can be calculated by multiplying the average values of the output voltage and the output current of pin OUTEW. When verifying the dissipation also the start-up and stop dissipation should be taken into account. Power dissipation during start-up can be 3 to 5 times higher than during normal operation. Heatsink calculation The value of the heatsink can be calculated in a standard way with a method based on average temperatures. The required thermal resistance of the heatsink is determined by the maximum die temperature of 150 C. In general we recommend to design for an average die temperature not exceeding 130 C. It should be noted that the heatsink thermal resistance Rin(n-a) found by performing a standard calculation will be lower then normally found for a vertical deflection stand alone device, due to the contribution of the EW power dissipation to this value. EXAMPLE Measured or known values: Pew =3 W; Py =6 W; Tamb = 40 C; Tj = 130 C; Rith(-c) =4 K/W; Rih(c-h) =1K/W. 1999 Dec 22 13 The required heatsink thermal resistance is given by: T,-Tamb Pewt Py (Ringe) + Rhee ny) Rincha) = When we use the values known we find: 130 40 Rthcha) = 376 4+7) = 5 K/W The heatsink temperature will be: Th = Tamb + Rin(h-a) X Piot = 40 + 5x 9 = 85 C Equivalent thermal resistance network The TDA8358J has two independent power dissipating systems, the vertical output circuit and the east-west circuit. It is recommended to verify the individual maximum (peak) junction temperatures of both circuits. Therefore the maximum (peak) power dissipations of the circuits and also the heatsink temperature should be measured. The maximum (peak) junction temperatures can be calculated by using an equivalent thermal network (see Fig.5). The network does only consist the contribution of the maximum (peak) power dissipation PTRy(peak), being the dissipation of the most critical transistor internally connected to pins OUTB and VGND. The model assumes equivalent maximum (peak) power dissipations during the different vertical scan stages for all the functionally paired transistors. The calculated maximum (peak) junction temperatures should not exceed Tj = 150 C.Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J TEW(M) TTRy(M) Rih(EW-P1) R. th(TRv-P1) PEeWy 1 PTRY(M) Rih(P1-c) 2.2 KW +Ptot To MGL872 Fig.5 Equivalent thermal resistance network. 1999 Dec 22 14 EXAMPLE Measured or known values: e The east-west power dissipation: Pew = 3 W e The vertical power dissipation: Py = 6 W e The maximum (peak) power dissipation of the most critical transistor: Ptry(peak) = 5 W e The case temperature: T, = 85 C. The IC total power dissipation is: Piot = Pew+ Py=6+3=9W It should be noted that the allowed IC total power dissipation is Pio; = 15 W (maximum value). The maximum (peak) temperature Tp1(peak) is given by: Tpi(peak) = To + (Pew + Prrvpeak)) X Rin(Pt-c) =85 +(34+5)x2.2=102.6C The maximum (peak) junction temperatures for the output circuits are given by: TiEwypeak) = TPt(peak) + Rincew-p1) x Pew = 102.6+105x3=134.1 C TjctRvy(peak) = T Pt (peak) + Rihctrv-p1) X PTRv(peak) = 102.6+5.2x5=128.6CPhilips Semiconductors Product specification Full bridge vertical deflection output circuit TDA8358J in LVDMOS with east-west amplifier INTERNAL PIN CONFIGURATION PIN SYMBOL EQUIVALENT CIRCUIT 1 INA a 300 2 : 2 MBL 100 2 INB 300 2 MBL102 3 Vp 4 OUTB ar vend | 4 FB 10 OUTA it f o | ______@ MGL869 5 INEW 7 EWGND 300 8 OUTEW : : MGL868 (8) 1999 Dec 22Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYDMOS with east-west amplifier TDA8358J PIN SYMBOL EQUIVALENT CIRCUIT 11 | GUARD eA 300 MGL870 12 | FEEDB 300 0 LY MGL871 13 COMP 300.2 MGL875 1999 Dec 22 16Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LYDMOS with east-west amplifier TDA8358J PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) $O0T141-6 non-concave | Ty UVUUUNUWUUUUUY view B: mounting base side d | pe AD mj 1 T 1 1 | Ll. Y | | | || L Ly t | 0 5 10 mm Looiirtiriit J scale DIMENSIONS (mm are the original dimensions) UNIT | A | Ao] bo | | DM! d | dD, | EM) e | ey |eo | En} j | LE] bs] m}| @] vj wx {2m 17.0| 4.6 | 0.75 | 0.48 | 24.0 | 20.0 12.2 3.4 | 12.4] 24 2.4 2.00 mm |455| 44 |o60|038| 236) 196] 1 Jite| 24 | 17 1598) & | oy Jato] 16] 43 | 49 | O8 | 0-25 | 0.03 | 45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SO1141-6 =} 99-12-17 1999 Dec 22 17Philips Semiconductors Product specification Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier TDA8358J SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our Data Handbook IC 26; Integrated Circuit Packages (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tatgmax)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods PACKAGE SOLDERING METHOD DIPPING WAVE DBS, DIP, HDIP, SDIP, SIL suitable suitable) Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Dec 22 18