3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-06059 Rev. *I Revised June 03, 2004
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Organization of 2M and 4.5M devices
— 128K × 36 (CY7C0852V)
— 64K × 36 (CY7C0851V)
— 256K × 18 (CY7C0832V)
— 128K × 18 (CY7C0831V)
• Pipelined output mode allows fast 167-MHz operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access: 4.0 ns (max.)
• 3.3V low operating power
— Active = 225 mA (typical)
— Standby = 55 mA (typical)
• Interrupt flags for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-ball BGA (1 mm pitch) (15 mm × 15 mm)
• 120-pin TQFP (14 mm × 14 mm × 1.4 mm)
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)
•FLEx36™ devices are footprint upgradeable from 2M to
4M to 9M
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
Functional Description
The CY7C0851V/CY7C0852V/CY7C0831VCY7C0832V are
2M and 4.5M pipelined, synchronous, true dual-port static
RAMs that are high-speed, low-power 3.3V CMOS. Two ports
are provided, permitting independent, simultaneous access for
Reads from any location in memory. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow
for minimal set-up and hold time.
During a Read operation, data is registered for decreased
cycle time. Clock to data valid tCD2 = 4.0 ns at 167 MHz. Each
port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the
counter will increment the address internally (more details to
follow). The internal Write pulse width is independent of the
duration of the R/W input signal. The internal Write pulse is
self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
New features added to the CY7C0851V/CY7C0852V/
CY7C0831V/CY7C0832V devices include: readback of
burst-counter internal address value on address lines,
counter-mask registers to control the counter wrap-around,
counter interrupt (CNTINT) flags, readback of mask register
value on address lines, retransmit functionality, interrupt flags
for message passing, JTAG for boundary scan, and
asynchronous Master Reset (MRST).
Cypress offers an upgrade to a 9M synchronous Dual Port with
a compatible footprint. Please see the application note
Upgrading the 4-Meg (CY7C0852) Dual-Port to a 9-Meg
(CY7C0853) Dual-Port for more details.
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18
Synchr onous Dual-Por t RAM
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 2 of 32
Note:
1. CY7C0851V has 16 address bits instead of 17. CY7C0832V has 18 address bits instead of 17. CY7C083XV does not have B2 and B3 inputs. CY7C083XV
does not have DQ18–DQ35 data bits. JTAG not implemented on CY7C083XV.
Logic Block Diagram[1]
A0L–A16L
CLKL
ADSL
CNTENL
CNTRSTL
True
RAM Array
17
Addr.
Read
Back
CNTINTL
Mask Register
Counter/
Address
Register
CNT/MSKL
Address
Decode
Dual-Ported
Interrupt
Logic
INTL
Reset
Logic JTAG
TDO
TMS
TCK
TDI
MRST
DQ
9L
–DQ
17L
DQ
0L
–DQ
8L
I/O
Control
9
9
9
9
DQ
18L
–DQ
26L
DQ
27L
–DQ
35L
CE
0L
CE
1L
R/W
L
B0
L
B1
L
B2
L
B3
L
OE
L
A0R–A16R
CLKR
ADS
CNTEN
CNTRSTR
17
Addr.
Read
Back
CNTINTR
Mask Register
Counter/
Address
Register
CNT/MSKR
Address
Decode
Interrupt
Logic
INTR
DQ
9R
–DQ
17R
DQ
0R
–DQ
8R
I/O
Control
9
9
9
9
DQ
18R
–DQ
26R
DQ
27R
–DQ
35R
CE
0R
CE
1R
R/W
R
B0
R
B1
R
B2
R
B3
R
OE
R
Mirror Reg Mirror Reg
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 3 of 32
Pin Configurations
123 4567891011121314
A
DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R
B
A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
C
NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC
D
A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
E
A4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R
F
VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
G
OEL B2L B3L CE0L CY7C0851V
CY7C0852V
CE0R B3R B2R OER
H
VSS R/WLA8L CLKL CLKR A8R R/WR VSS
J
A9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R
K
A11L A12L A15L CNTRSTL VDD VDD VSS VDD CNTRSTR A15R A12R A11R
L
CNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR
M
A16L[2] A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R[2]
N
DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
P
DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Note:
2. For CY7C0851V, pins M1 and M14 are NC.
Top View
172-ball BGA
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 4 of 32
Pin Configurations (continued)
132
131
130
129
128
127
126
125
124
123
122
104
121
120
119
118
117
116
115
114
113
112
111
110
109
103
108
107
106
105
NC
A6R
A5R
A4R
VDD
VSS
DQ35R
DQ34R
A1R
A2R
A3R
A0R
A7R
B0R
B1R
CE1R
B2R
B3R
OER
CE0R
VDD
VDD
VSS
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
A8R
CNTRSTR
CNT/MSKR
A9R
A10R
A11R
A12R
VSS
VDD
A13R
A14R
A15R
A16R
DQ24R
DQ20R
NC
A6L
A5L
A4L
VDD
VSS
DQ35L
DQ34L
A1L
A2L
A3L
A0L
A7L
B0L
B1L
CE1L
B2L
B3L
OEL
CE0L
VDD
VDD
VSS
VSS
R/WL
CLKL
VSS
ADSL
CNTENL
A8L
CNTRSTL
CNT/MSKL
A9L
A10L
A11L
A12L
VSS
VDD
A13L
A14L
A15L
A16L
DQ24L
DQ20L
DQ33L
DQ32L
DQ31L
VDD
VSS
DQ30L
DQ28L
DQ29L
DQ27L
INTL
CNTINTL
DQ16L
DQ15L
DQ17L
DQ14L
DQ13L
VSS
VDD
DQ12L
DQ11L
DQ10L
DQ9L
DQ9R
DQ10R
DQ11R
DQ12R
VDD
VSS
DQ13R
DQ14R
DQ17R
DQ15R
DQ16R
CNTINTR
INTR
DQ27R
DQ29R
DQ28R
DQ30R
VSS
VDD
DQ31R
DQ32R
DQ33R
DQ26L
DQ23L
DQ22L
VDD
VSS
DQ21L
DQ25L
DQ19L
DQ18L
TDI
TDO
DQ8L
DQ7L
DQ6L
DQ5L
DQ4L
VSS
VDD
DQ3L
DQ2L
DQ1L
DQ0L
DQ0R
DQ1R
DQ2R
DQ3R
VDD
VSS
DQ4R
DQ5R
DQ6R
DQ7R
DQ8R
TMS
TCK
DQ18R
DQ19R
DQ25R
DQ21R
VSS
VDD
DQ22R
DQ23R
DQ26R
102
91
101
100
99
98
97
96
90
95
94
93
92
89
1
2
3
4
5
6
7
8
9
10
11
29
12
13
14
15
16
17
18
19
20
21
22
23
24
30
25
26
27
28
31
42
32
33
34
35
36
37
43
38
39
40
41
44
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
CY7C0851V
CY7C0852V
176-pin Thin Quad Flat Pack (TQFP)
Top View
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 5 of 32
Pin Configurations (continued)
Selection Guide
-167 -133 Unit
fMAX 167 133 MHz
Max. Access Time (Clock to Data) 4.0 4.4 ns
Typical Operating Current ICC 200 200 mA
Typical Standby Current for ISB3
(Both Ports CMOS Level)
55 55 mA
Notes:
3. NC for CY7C0831V.
CY7C0831V
CY7C0832V
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
DQ11L
CNTINTL
INTL
DQ9L
DQ10L
DQ12L
VSS
VDD
DQ13L
DQ14L
DQ15L
DQ16L
DQ17L
A0L
A1L
DQ16R
A1R
A0R
DQ17R
DQ15R
DQ14R
DQ13R
VDD
VSS
DQ12R
DQ11R
DQ10R
DQ9R
INTR
CNTINTR
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B1R
VSS
VDD
CE0R
OER
B0R
CE1R
A7R
A6R
A5R
A4R
VDD
VSS
A3R
A2R
A12R
A13R
VDD
VSS
A11R
A10R
A9R
A8R
CNT/MSKR
CNTRSTR
CNTENR
ADSR
MRST
CLKR
R/WR
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
DQ0L
DQ1L
DQ2L
DQ3L
VDD
DQ4L
DQ5L
DQ6L
DQ7L
DQ8L
A17L[3]
A16L
A15L
A14L
A17R[3]
A14R
A15R
A16R
DQ8R
DQ7R
DQ6R
DQ5R
DQ4R
VDD
VSS
DQ3R
DQ2R
DQ1R
DQ0R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B1L
VSS
VDD
CE0L
OEL
B0L
A7L
A6L
A5L
A4L
VDD
VSS
A3L
A2L
A12L
A13L
VDD
VSS
A11L
A10L
A9L
A8L
CNT/MSKL
CNTRSTL
CNTENL
ADSL
VSS
CLKL
R/WL
CE1L
120-pin Thin Quad Flat Pack (TQFP)
Top View
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 6 of 32
Pin Definitions
Left Port Right Port Description
A0L–A16L[1] A0R–A16R[1] Address Inputs.
ADSLADSRAddress Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
CE0LCE0RActive LOW Chip Enable Input.
CE1LCE1RActive HIGH Chip Enable Input.
CLKLCLKRClock Signal. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
CNTRSTLCNTRSTRCounter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
CNT/MSKLCNT/MSKRAddress Counter Mask Register Enable Input. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
DQ0L–DQ35L[1] DQ0R–DQ35R[1] Data Bus Input/Output.
OELOEROutput Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTLINTRMailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINTLCNTINTRCounter Interrupt Output. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WLR/WRRead/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L B0R–B3R Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
TCK JTAG Test Clock Input.
TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS Ground Inputs.
VDD Power Inputs.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 7 of 32
Master Reset
The CY7C0831V undergoes a complete reset by taking its
MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the CY7C0831V after
power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports. The highest
memory location, 1FFFF is the mailbox for the right port and
1FFFE is the mailbox for the left port. Table 2 shows that in
order to set the INTR flag, a Write operation by the left port to
address 1FFFF will assert INTR LOW. At least one byte has to
be active for a Write to generate an interrupt. A valid Read of
the 1FFFF location by the right port will reset INTR HIGH. At
least one byte has to be active in order for a Read to reset the
interrupt. When one port Writes to the other port’s mailbox, the
INT of the port that the mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox Reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)[ 4, 5]
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
X L X X X X Master Reset Reset address counter to all 0s and mask
register to all 1s.
H H L X X Counter Reset Reset counter unmasked portion to all 0s.
H H H L L Counter Load Load counter with external address value
presented on address lines.
H H H L H Counter Readback Read out counter internal value on
address lines.
H H H H L Counter Increment Internally increment address counter
value.
H H H H H Counter Hold Constantly hold the address value for
multiple clock cycles.
H L L X X Mask Reset Reset mask register to all 1s.
H L H L L Mask Load Load mask register with value presented
on the address lines.
H L H L H Mask Readback Read out mask register value on address
lines.
H L H H X Reserved Operation undefined
Table 2. Interrupt Operation Example [1, 6, 7, 8]
Function
Left Port Right Port
R/WLCELA0L–16LINTLR/WRCERA0R–16R INTR
Set Right INTR Flag L L 1FFFF X X X X L
Reset Right INTR FlagXXXXHL1FFFFH
Set Left INTL Flag X X X L L L 1FFFE X
Reset Left INTL Flag H L 1FFFE H X X X X
Notes:
4. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
5. Counter operation and mask register operation is independent of chip enables.
6. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
7. OE is “Don’t Care” for mailbox operation.
8. At least one of B0, B1, B2, or B3 must be LOW.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 8 of 32
Address Counter and Mask Register
Operations[9]
Each port of the CY7C0851V/CY7C0852V/CY7C083XV has a
programmable burst address counter. The burst counter
contains three 17-bit registers: a counter register, a mask
register, and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 1 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Ta ble 1
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines. This value
ranges from 0 to 1FFFF.
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. This value ranges from 0 to 1FFFF,
although not all values permit correct increment operations.
Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[10] An increment that results
in one or more of the unmasked bits of the counter being “0”
will de-assert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Notes:
9. This section describes the CY7C0852V and CY7C0831V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0832V has 18 address
bits, register lengths of 18 bits, and a maximum address value of 3FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum
address value of FFFF.
10. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 9 of 32
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0851V/CY7C0852V as a 72-bit single port SRAM in
which the counter of one port counts even addresses and the
counter of the other port counts odd addresses. This even-odd
address scheme stores one half of the 72-bit data in even
memory locations, and the other half in odd memory locations.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 10 of 32
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines To Readback
and Address
Decode
17
17
MRST
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 11 of 32
IEEE 1149.1 Serial Boundary Scan (JTAG)[12]
The CY7C0851V/CY7C0852V incorporates an IEEE 1149.1
serial boundary scan test access port (TAP). The TAP
controller functions in a manner that does not conflict with the
operation of other devices using 1149.1-compliant TAPs. The
TAP operates using JEDEC-standard 3.3V I/O logic levels. It
is composed of three input connections and one output
connection required by the test logic defined by the standard.
Disabling the JTAG Feature
It is possible to operate the CY7C0851V/CY7C0852V without
using the JTAG feature. To disable the TAP controller, TCK
must be tied LOW (VSS) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be unconnected.
They may alternatively be connected to VDD through a pull-up
resistor. TDO should be left unconnected.
Test Access Port–Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the MSB on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram [FSM]). The output changes on the falling edge of
TCK. TDO is connected to the LSB of any register.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
CY7C0851V/CY7C0852V, and may be performed while the
device is operating. An MRST must be performed on the
CY7C0851V/CY7C0852V after power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the
CY7C0851V/CY7C0852V in a scan test. Therefore the tester
should be configured to never enter the PAUSE-DR state.
Notes:
11. The “X” in this diagram represents the counter upper bits.
12. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
216 215 2621
2522
242320
H
H
L
H
11
0s 1
01
0101
00
Xs 1
X0
X0X0
11
Xs 1
X1
X1X1
00
Xs 1
X0
X0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[1, 11]
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 12 of 32
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the
CY7C0851V/CY7C0852V test circuitry. Only one register can
be selected at a time through the instruction registers. Data is
serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register (IR)
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in Figure 4, the JTAG/BIST
Controller Block Diagram. On power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed in a reset
state, as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test path.
Bypass Register (BYR)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
CY7C0851V/CY7C0852V with minimal delay. The bypass
register is set to “0” on the rising edge of TCK following entry
into the Capture-DR state, if the current instruction causes the
bypass register to be in the serial path between TDI and TDO.
Boundary Scan Register (BSR)
The boundary scan register is connected to all the input and
output pins on the CY7C0851V/CY7C0852V, except the
MRST pin. The boundary scan register is loaded with the
contents of the CY7C0851V/CY7C0852V input and output ring
when the TAP controller is in the Capture-DR state. It is then
placed between the TDI and TDO pins when the controller is
moved to the Shift-DR state. The EXTEST and
SAMPLE/PRELOAD instructions can be used to capture the
contents of the input and output ring.
Identification Register (IDR)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
in the instruction register. The IDCODE is hardwired into the
CY7C0851V/CY7C0852V and can be shifted out when the
TAP controller is in the Shift-DR state. The ID register has a
vendor code and other information described in the Identifi-
cation Register Definitions table.
TAP Instruction Set
Sixteen different instructions are possible with the four-bit
instruction register. All combinations are listed in Table 5.
Other code combinations are listed as RESERVED and should
not be used.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST allows circuitry external to the CY7C0851V/
CY7C0852V package to be tested. Boundary- scan register
cells at output pins are used to apply test stimuli, while those
at input pins capture test results.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register on power-up or whenever
the TAP controller is given a test logic reset state. The
IDCODE value for the CY7C0851V is 0C001069h. The
IDCODE value for the CY7C0852V is 0C002069h.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all CY7C0851V/
CY7C0852V outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the
CY7C0851V/CY7C0852V clock operates more than an order
of magnitude faster. Because there is a large difference in the
clock frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The TAP may
then try to capture a signal while in transition (metastable
state). This will not harm the device, but there is no guarantee
as to the value that will be captured. Repeatable results may
not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the CY7C0851V/CY7C0852V signal
must be stabilized long enough to meet the TAP controller's
capture set-up plus hold times. Once the data is captured, it is
possible to shift out the data by putting the TAP into the
Shift-DR state. This places the boundary scan register
between the TDI and TDO pins. If the TAP controller goes into
the Update-DR state, the sampled data will be updated.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected on
a board.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 13 of 32
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from CY7C0851V/CY7C0852V pins to be determined
from the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
NBSRST
This is the Non-Boundary Scan Reset instruction. NBSRST
places the Bypass Register (BYR) between TDI and TDO
when selected. Its function is to reset every logic (similar to
MRST) except that it does not reset the JTAG logic.
Boundary Scan Cells (BSC)
Every CY7C0851V/CY7C0852V output has two boundary
scan cells; one for data, and one for three-state control. JTAG
TAP pins (TDI, TMS, TDO, TCK), MRST, and all power and
ground pins have no scan cell. Other CY7C0851V/
CY7C0852V inputs have only the data scan cell.
Active and Standby Supply Current[13]
When the instruction in the JTAG instruction register selects
the Boundary Scan Register (BSR) and the TAP controller is
in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE,
then the device supply current (ICC or ISB1/2/3/4) will increase.
With the JTAG logic in this state, and both ports inactive with
CMOS input levels, it is possible for the supply current to
exceed the ISB3 value given in the Electrical Characteristics
section of this data sheet.
Notes:
13. ISB3 values only if JTAG pins are not active and master reset (MRST) not enabled.
14. The “0”/”1” next to each state represents the value at TMS at the rising edge of CLK.
TEST-LOGIC
RESET
RUN_TEST/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
Figure 3. TAP Controller State Diagram (FSM)[14]
1
[12]
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 14 of 32
0
0
0n-1
Bypass Register (BYR)
Instruction Register (IR)
Identification Register (IDR)
Boundary Scan Register (BSR)
TDI Selection
Circuitry TDO
TCK
TMS
TAP
CONTROLLER
MRST
(MUX)
Figure 4. JTAG TAP Controller Block Diagram
3210
31 30 29
Table 3. Identification Register Definitions
Instruction Field Value Description
Revision Number (31:28) 0h Reserved for version number.
Cypress Device ID[15] (27:12) C002h Defines Cypress part number for CY7C0852V.
Cypress JEDEC ID (11:1) 034h Allows unique identification of CY7C0851V/CY7C0852V vendor.
ID Register Presence (0) 1 Indicates the presence of an ID register.
Note:
15. Cypress Device ID is C001h for Cypress part CY7C0851V.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 15 of 32
Table 4. Scan Registers Sizes
Register Name Bit Size
Instruction 4
Bypass 1
Identification 32
Boundary Scan n
Table 5. Instruction Identification Codes
Instruction Code Description
EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS 1111 Places the BYR between TDI and TDO.
IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ 0111 Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/
CY7C0853V output drivers to a High-Z state.
CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED All other codes Other combinations are reserved. Do not use other than the above.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 16 of 32
Maximum Ratings [16]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[17]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current..................................................... > 200 mA
Operating Range
Range Ambient Temperature VDD
Commercial 0°C to +70°C 3.3V ± 165 mV
Industrial –40°C to +85°C 3.3V ± 165 mV
Electrical Characteristics Over the Operating Range
Parameter Description
-167 -133
UnitMin. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage
(VDD = Min., IOH= –4.0 mA)
2.4 2.4 V
VOL Output LOW Voltage
(VDD = Min., IOL= +4.0 mA)
0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 µA
IIX1 Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 µA
IIX2 Input Leakage Current TDI, TMS, MRST –0.1 1.0 –0.1 1.0 mA
ICC Operating Current
(VDD = Max.,IOUT = 0 mA), Outputs Disabled
225 300 225 300 mA
ISB1 Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
90 115 90 115 mA
ISB2 Standby Current
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
160 210 160 210 mA
ISB3[13] Standby Current
(Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
55 75 55 75 mA
ISB4 Standby Current
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
160 210 160 210 mA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V
13 pF
COUT Output Capacitance 10 pF
Note:
16. The voltage on any input or I/O pin can not exceed the power pin during power-up.
17. Pulse width < 20 ns.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 17 of 32
AC Test Load and Waveforms
Switching Characteristics Over the Operating Range
Parameter Description
-167 -133
UnitMin. Max. Min. Max.
fMAX2 Maximum Operating Frequency 167 133 MHz
tCYC2 Clock Cycle Time 6.0 7.5 ns
tCH2 Clock HIGH Time 2.7 3.0 ns
tCL2 Clock LOW Time 2.7 3.0 ns
tR[18] Clock Rise Time 2.0 2.0 ns
tF[18] Clock Fall Time 2.0 2.0 ns
tSA Address Set-up Time 2.3 2.5 ns
tHA Address Hold Time 0.6 0.6 ns
tSB Byte Select Set-up Time 2.3 2.5 ns
tHB Byte Select Hold Time 0.6 0.6 ns
tSC Chip Enable Set-up Time 2.3 2.5 ns
tHC Chip Enable Hold Time 0.6 0.6 ns
tSW R/W Set-up Time 2.3 2.5 ns
tHW R/W Hold Time 0.6 0.6 ns
tSD Input Data Set-up Time 2.3 2.5 ns
tHD Input Data Hold Time 0.6 0.6 ns
tSAD ADS Set-up Time 2.3 2.5 ns
tHAD ADS Hold Time 0.6 0.6 ns
tSCN CNTEN Set-up Time 2.3 2.5 ns
tHCN CNTEN Hold Time 0.6 0.6 ns
tSRST CNTRST Set-up Time 2.3 2.5 ns
tHRST CNTRST Hold Time 0.6 0.6 ns
tSCM CNT/MSK Set-up Time 2.3 2.5 ns
tHCM CNT/MSK Hold Time 0.6 0.6 ns
tOE Output Enable to Data Valid 4.0 4.4 ns
tOLZ[19, 20] OE to Low Z 0 0 ns
R1 = 590 Ω
R2 = 435 Ω
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0V
Vss
90%
10%
<2ns <2ns
ALL INPUT PULSES
3.3V
VTH = 1.5V
R = 50Ω
Z0 = 50Ω
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 18 of 32
tOHZ[19, 20] OE to High Z 0 4.0 0 4.4 ns
tCD2 Clock to Data Valid 4.0 4.4 ns
tCA2 Clock to Counter Address Valid 4.0 4.4 ns
tCM2 Clock to Mask Register Readback Valid 4.0 4.4 ns
tDC Data Output Hold After Clock HIGH 1.0 1.0 ns
tCKHZ[19, 20] Clock HIGH to Output High Z 0 4.0 0 4.4 ns
tCKLZ[19, 20] Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 ns
tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 ns
tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 ns
tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 ns
tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 ns
Port to Port Delays
tCCS Clock to Clock Skew 5.2 6.0 ns
Master Reset Timing
tRS Master Reset Pulse Width 7.0 7.5 ns
tRSS Master Reset Set-up Time 6.0 6.0 ns
tRSR Master Reset Recovery Time 6.0 7.5 ns
tRSF Master Reset to Outputs Inactive 6.0 6.5 ns
tRSCNTINT Master Reset to Counter Interrupt Flag Reset Time 5.8 7.0 ns
JTAG Timing
Parameter Description
CY7C0851V/CY7C0852V
Unit
-167/-133
Min. Max.
fJTAG Maximum JTAG TAP Controller Frequency 10 MHz
tTCYC TCK Clock Cycle Time 100 ns
tTH TCK Clock HIGH Time 40 ns
tTL TCK Clock LOW Time 40 ns
tTMSS TMS Set-up to TCK Clock Rise 10 ns
tTMSH TMS Hold After TCK Clock Rise 10 ns
tTDIS TDI Set-up to TCK Clock Rise 10 ns
tTDIH TDI Hold After TCK Clock Rise 10 ns
tTDOV TCK Clock LOW to TDO Valid 30 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
Notes:
18. Except JTAG signals (tr and tf < 10 ns [max.]).
19. This parameter is guaranteed by design, but it is not production tested.
20. Test conditions used are Load 2.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
-167 -133
UnitMin. Max. Min. Max.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 19 of 32
JTAG Switching Waveform
Switching Waveforms
Master Reset
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Tes t Da ta-O ut
TDO
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOX tTDOV
MRST
tRSR
tRS
INACTIVE ACTIVE
TMS
TDO
INT
CNTINT
tRSF
tRSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 20 of 32
Read Cycle[6, 21, 22, 23, 24]
Notes:
21. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
22. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
23. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
24. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
B0–B3
tSB tHB
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 21 of 32
Bank Select Read[25, 26]
Read-to-Write-to-Read (OE = LOW)[24, 27, 28, 29, 30]
Notes:
25. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
sheet. ADDRESS(B1) = ADDRESS(B2).
26. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
27. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
28. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
29. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
30. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0A1A2A3A4A5
Q4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ
tCD2
NO OPERATION WRITEREAD READ
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 22 of 32
Read-to-Write-to-Read (OE Controlled)[24, 27, 29, 30]
Read with Address Counter Advance[29]
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3
Qn
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
OE
Qn+4
tCD2
tSA tHA
tCH2 tCL2
tCYC2
CLK
ADDRESS An
COUNTER HOLD
READ WITH COUNTER
tSAD tHAD
tSCN tHCN
tSAD tHAD
tSCN tHCN
Qx–1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATAOUT
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 23 of 32
Write with Address Counter Advance [30]
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRITE EXTERNAL WRITE WITH COUNTER
ADDRESS
WRITE WITH
COUNTER
WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
DATAIN
ADDRESS
tSA tHA
CNTEN
ADS
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 24 of 32
Counter Reset [31, 32]
Notes:
31. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
32. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Switching Waveforms (continued)
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT
AnAmAp
Ax01AnAmAp
Q1Qn
Q0
D0
tCH2 tCL2
tCYC2
tSA tHA
tSW tHW
tSRST tHRST
tSD tHD
tCD2 tCD2
tCKLZ
[44]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS AnADDRESS Am
READ
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 25 of 32
Readback State of Address Counter or Mask Register[33, 34, 35, 36]
Notes:
33. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
34. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
35. Address in input mode. Host can drive address bus after tCKHZ.
36. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms (continued)
CNTEN
CLK
tCH2 tCL2
tCYC2
ADDRESS
ADS
An
Qx-2 Qx-1 Qn
tSA tHA
tSAD tHAD
tSCN tHCN
LOAD
ADDRESS
EXTERNAL
tCD2
INTERNAL
ADDRESS An+1 An+2
An
tCKHZ
DATAOUT
A
n*
Q
n+3
Qn+1 Qn+2
An+3 An+4
tCKLZ
tCA2 or tCM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A0–A16
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 26 of 32
Left_Port (L_Port) Write to Right_Port (R_Port) Read[37, 38, 39]
Notes:
37. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
38. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
39. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock.
If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Switching Waveforms (continued)
tSA tHA
tSW tHW
tCH2 tCL2
tCYC2
CLKL
R/WL
An
Dn
tCKHZ tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD tCKLZ
tCH2
tCL2
tCYC2
tCD2
L_PORT
ADDRESS
L_PORT
DATAIN
CLKR
R/WR
R_PORT
ADDRESS
R_PORT
DATAOUT
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 27 of 32
Counter Interrupt and Retransmit[40, 41, 42, 43, 44]
Notes:
40. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
41. CNTINT is always driven.
42. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
43. The mask register assumed to have the value of 1FFFFh.
44. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
1FFFD 1FFFF
INTERNAL
ADDRESS Last_Loaded Last_Loaded +1
t
HCM
COUNTER
1FFFE
CNTINT
tSCINT tRCINT
1FFFC
CNTEN
ADS
CNT/MSK
t
SCM
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 28 of 32
MailBox Interrupt Timing[45, 46, 47, 48, 49]
Switching Waveforms (continued)
t
CH2
t
CL2
t
CYC2
CLK
L
tCH2 tCL2
tCYC2
CLKR
1FFFF
tSA tHA
An+3
AnAn+1 An+2
L_PORT
ADDRESS
AmAm+4
Am+1 1FFFF Am+3
R_PORT
ADDRESS
INTR
tSA tHA
tSINT
tRINT
Table 6. Read/Write and Enable Operation (Any Port)[1, 4, 50, 51, 52]
Inputs Outputs
OperationOE CLK CE0CE1R/W DQ0 – DQ35
X H X X High-Z Deselected
X X L X High-Z Deselected
XLHLD
IN Write
LLHHD
OUT Read
H X L H X High-Z Outputs Disabled
Notes:
45. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
46. Address “1FFFF” is the mailbox location for R_Port.
47. L_Port is configured for Write operation, and R_Port is configured for Read operation.
48. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
49. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
50. OE is an asynchronous input signal.
51. When CE changes state, deselection and Read happen after one cycle of latency.
52. CE0 = OE = LOW; CE1 = R/W = HIGH.
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 29 of 32
Ordering Information
256K
×
18 (4M) 3.3V Synchronous CY7C0832V Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0832V-167AC A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
133 CY7C0832V-133AC A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
CY7C0832V-133AI A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Industrial
128K
×
36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM
167 CY7C0852V-167BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Commercial
CY7C0852V-167AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
133 CY7C0852V-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Commercial
CY7C0852V-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Industrial
CY7C0852V-133AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0852V-133AI A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Industrial
128K
×
18 (2M) 3.3V Synchronous CY7C0831V Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0831V-167AC A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
133 CY7C0831V-133AC A120
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
64K
×
36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM
Speed
(MHz) Ordering Code
Package
Name Package Type
Operating
Range
167 CY7C0851V-167BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Commercial
CY7C0851V-167AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
133 CY7C0851V-133BBC BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Commercial
CY7C0851V-133AC A176
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
CY7C0851V-133BBI BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA)
Industrial
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 30 of 32
Package Diagrams
120-pin thin Quad Flatpack (14 × 14 × 1.4 mm) A120
51-85100-**
51-85132-**
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 31 of 32
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
FLEx36 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks
of their respective holders.
Package Diagrams (continued)
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I Page 32 of 32
Document History Page
Document Title: CY7C0851V/CY7C0852V/CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchro-
nous Dual-Port RAM
Document Number: 38-06059
REV. ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 111473 11/27/01 DSG Change from Spec number: 38-01056 to 38-06059
*A 111942 12/21/01 JFU Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B 113741 04/02/02 KRE Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
*C 114704 04/24/02 KRE Added discussion of Pause/Restart for JTAG boundary scan
*D 115336 07/01/02 KRE Revised speed offerings for all densities
*E 122307 12/27/02 RBI Power up requirements added to Maximum Ratings Information
*F 123636 1/27/03 KRE Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
*G 126053 08/11/03 SPN Separated out 4M and 9M data sheets
Updated Isb and ICC values
*H 129443 11/03/03 RAZ Updated Isb and ICC values
*I 231993 See ECN YDT Removed “A particular port can write to a certain location while another port
is reading that location.” from Functional Description.
