Vishay Siliconix
Si4816BDY
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
www.vishay.com
1
Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
• Halogen-free According to IEC 61249-2-21
Available
• LITTLE FOOT® Plus Power MOSFET
• 100 % Rg Tested
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)I
D (A) Qg (Typ.)
Channel-1
30
0.0185 at VGS = 10 V 6.8 7.8
0.0225 at VGS = 4.5 V 6.0
Channel-2 0.0115 at VGS = 10 V 11.4 11.6
0.016 at VGS = 4.5 V 9.5
SCHOTTKY PRODUCT SUMMARY
VDS (V)
VSD (V)
Diode Forward Voltage IF (A)
30 0.50 V at 1.0 A 2.0
G1D1
A/S2D2/S1
A/S2D2/S1
G2D2/S1
SO-8
5
6
7
8
Top View
2
3
4
1
Ordering Information: Si4816BDY-T1-E3 (Lead (Pb)-free)
Si4816BDY-T1-GE3 (Lead (Pb)-free and Halogen-free)
G2
S2
N-Channel 2
MOSFET
Schottky Diod
e
A
G1
D1
N-Channel 1
MOSFET S1/D2
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol
Channel-1 Channel-2
Unit 10 s Steady State 10 s Steady State
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS 20
Continuous Drain Current (TJ = 150 °C)aTA = 25 °C ID
6.8 5.8 11.4 8.2
A
TA = 70 °C 5.5 4.6 9.0 6.5
Pulsed Drain Current IDM 30 40
Continuous Source Current (Diode Conduction)aIS1 0.9 2.2 1.15
Single Pulse Avalanche Current L = 0.1 mH IAS 10 20
Avalanche Energy EAS 520mJ
Maximum Power DissipationaTA = 25 °C PD
1.4 1.0 2.4 1.25 W
TA = 70 °C 0.9 0.64 1.5 0.8
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol
Channel-1 Channel-2 Schottky
Unit Typ. Max. Typ. Max. Typ. Max.
Maximum Junction-to-Ambientat ≤ 10 s RthJA
72 90 43 53 48 60
°C/W
Steady State 100 125 82 100 80 100
Maximum Junction-to-Foot (Drain) Steady State RthJF 51 63 25 30 28 35
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Vishay Siliconix
Si4816BDY
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ.aMax. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA Ch-1 1.0 3.0 V
Ch-2 1.0 3.0
Gate-Body Leakage IGSS VDS = 0 V, VGS = 20 V Ch-1 100 nA
Ch-2 100
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V Ch-1 1
µA
Ch-2 100
VDS = 30 V, VGS = 0 V, TJ = 85 °C Ch-1 15
Ch-2 2000
On-State Drain CurrentbID(on) V
DS = 5 V, VGS = 10 V Ch-1 20 A
Ch-2 30
Drain-Source On-State ResistancebRDS(on)
VGS = 10 V, ID = 6.8 A Ch-1 0.0155 0.0185
Ω
VGS = 10 V, ID = 11.4 A Ch-2 0.0093 0.0115
VGS = 4.5 V, ID = 6.0 A Ch-1 0.0185 0.0225
VGS = 4.5 V, ID = 9.5 A Ch-2 0.013 0.016
Forward Transconductancebgfs
VDS = 15 V, ID = 6.8 A Ch-1 30 S
VDS = 15 V, ID = 11.4 A Ch-2 31
Diode Forward VoltagebVSD
IS = 1 A, VGS = 0 V Ch-1 0.73 1.1 V
IS = 1 A, VGS = 0 V Ch-2 0.47 0.5
Dynamica
Total Gate Charge Qg Channel-1
VDS = 15 V, VGS = 5 V, ID = 6.8 A
Channel-2
VDS = 15 V, VGS = 5 V, ID = - 11.4 A
Ch-1 7.8 10
nC
Ch-2 11.6 18
Gate-Source Charge Qgs
Ch-1 2.9
Ch-2 4.8
Gate-Drain Charge Qgd Ch-1 2.3
Ch-2 3.7
Gate Resistance Rg
Ch-1 1.5 3.0 4.5 Ω
Ch-2 0.9 1.8 2.7
Tur n - O n D e l ay Time td(on) Channel-1
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Channel-2
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Ch-1 11 17
ns
Ch-2 13 20
Rise Time tr
Ch-1 9 15
Ch-2 9 15
Turn-Off Delay Time td(off) Ch-1 24 40
Ch-2 31 50
Fall Time tf
Ch-1 9 15
Ch-2 11 17
Source-Drain Reverse Recovery Time trr
IF = 1.3 A, dI/dt = 100 A/µs Ch-1 20 35
IF = 2.2 A, dI/dt = 100 µA/µs Ch-2 25 40
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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3
Vishay Siliconix
Si4816BDY
Stresses beyond those listed under “A bsolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, an d functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Forward Voltage Drop VF
IF = 1.0 A 0.47 0.50 V
IF = 1.0 A, TJ = 125 °C 0.36 0.42
Maximum Reverse Leakage Current Irm
VR = 30 V 0.004 0.100
mA
VR = 30 V, TJ = 100 °C 0.7 10
VR = - 30 V, TJ = 125 °C 3.0 20
Junction Capacitance CTVR = 10 V 50 pF
Output Characteristics
On-Resistance vs. Drain Current
0
5
10
15
20
25
30
35
40
012345
VGS = 10 thru 4 V
3 V
VDS – Drain-to-Source Voltage (V)
– Drain Current (A)I
D
2 V
0.00
0.01
0.02
0.03
0.04
0.05
0 5 10 15 20 25 30 35 40
– On-Resistance (Ω)
R
DS(on)
ID – Drain Current (A)
VGS = 4.5 V
VGS = 10 V
Transfer Characteristics
Capacitance
0
5
10
15
20
25
30
35
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
TC = 125 °C
- 55 °C
25 °C
VGS – Gate-to-Source Voltage (V)
– Drain Current (A)I
D
0
200
400
600
800
1000
1200
0 5 10 15 20 25 30
VDS – Drain-to-Source Voltage (V)
Crss
Coss
Ciss
C – Capacitance (pF)
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Vishay Siliconix
Si4816BDY
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Gate Charge
Source-Drain Diode Forward Voltage
Threshold Voltage
0
1
2
3
4
5
6
0246810
VDS = 15 V
ID = 6.8 A
– Gate-to-Source Voltage (V)
Qg – Total Gate Charge (nC)
VGS
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
TJ = 150 °C
40
10
1
VSD – Source-to-Drain Voltage (V)
– Source Current (A)I
S
TJ = 25 °C
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
- 50 - 25 0 25 50 75 100 125 150
ID = 250 µA
Variance (V)VGS(th)
TJ – Temperature (°C)
On-Resistance vs. Junction Temperature
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 6.8 A
TJ – Junction Temperature (°C)
RDS(on) – On-Resistance
(Normalized)
0.00
0.01
0.02
0.03
0.04
0.05
0246810
VGS – Gate-to-Source Voltage (V)
ID = 6.8 A
– On-Resistance (Ω)
R
DS(on)
0.001
0
1
100
40
60
10 0.1
Time (s)
20
80
Power (W)
0.01
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Vishay Siliconix
Si4816BDY
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Safe Operating Area
100
1
0.1 1 10 100
0.01
10
TC = 25 °C
Single Pulse
– Drain Current (A)ID
0.1
IDM Limited
ID(on)
Limited
BVDSS Limited
1 ms
10 ms
100 ms
1 s
*
DS(on)
Limited by R
VDS –
>
Drain-to-Source Voltage (V)
* VGS minimum VGS at which RDS(on) is specified
DC
10 s
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
0.1
0.01
10-410-310-210-11 10 600
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 100 °C/W
3. T JM - TA = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
100
Normalized Thermal Transient Impedance, Junction-to-Foot
10-310-211010-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Vishay Siliconix
Si4816BDY
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current
Gate Charge
0
8
16
24
32
40
012345
VGS = 10 thru 5 V
3 V
VDS – Drain-to-Source Voltage (V)
– Drain Current (A)ID
2 V
4 V
0.000
0.004
0.008
0.012
0.016
0.020
0 5 10 15 20 25 30
VGS = 4.5 V
VGS = 10 V
– On-Resistance (Ω)RDS(on)
ID – Drain Current (A)
0
1
2
3
4
5
6
0 3 6 9 12 15
VDS = 15 V
ID = 9.5 A
– Gate-to-Source Voltage (V)
Qg – Total Gate Charge (nC)
V
GS
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
8
16
24
32
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
25 °C
TC = 125 °C
- 55 °C
VGS – Gate-to-Source Voltage (V)
– Drain Current (A)I
D
0
400
800
1200
1600
2000
0 6 12 18 24 30
Crss
Coss
Ciss
VDS – Drain-to-Source Voltage (V)
C – Capacitance (pF)
0.6
0.8
1.0
1.2
1.4
1.6
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 9.5 A
TJ – Junction Temperature (°C)
RDS(on) – On-Resistance
(Normalized)
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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Vishay Siliconix
Si4816BDY
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Reverse Current vs. Junction Temperature
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
TJ = 150 °C
40
10
1
VSD – Source-to-Drain Voltage (V)
– Source Current (A)I
S
TJ = 25 °C
0 25 50 75 100 125 150
VDS = 30 V
10
1
0.00001
TJ – Temperature (°C)
IR – Reverse Current (mA)
VDS = 24 V
1
0.1
0.01
0.0001
0.001
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
0.00
0.01
0.02
0.03
0.04
0.05
0246810
VGS – Gate-to-Source Voltage (V)
ID = 9.5 A
– On-Resistance (Ω)
R
DS(on)
Time (s)
0.001
0
1
100
40
60
10
0.1
20
80
Power (W)
0.01
Safe Operating Area
100
1
0.1 1 10 100
0.01
10
TC = 25 °C
Single Pulse
– Drain Current (A)I
D
0.1
IDM Limited
ID(on)
Limited
*
DS(on)
Limited by R
BVDSS Limited
1 ms
10 ms
100 ms
DC
1 s
10 s
VDS –
>
Drain-to-Source Voltage (V)
* VGS minimum VGS at which RDS(on) is specified
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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Vishay Siliconix
Si4816BDY
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Thermal Transient Impedance, Junction-to-Ambient
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
2
1
0.1
0.01
10-310-21 10 60010-1
10-4
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
100
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 82 °C/W
3. T
JM
-
T
A
= P
DM
Z
thJA(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
Normalized Thermal Transient Impedance, Junction-to-Foot
10-310 211010-- 1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
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9
Vishay Siliconix
Si4816BDY
SCHOTTKY TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73026.
Reverse Current vs. Junction Temperature
0 25 50 75 100 125 150
20
10
0.0001
– Reverse Current (mA)I
R
TJ Temperature (°C)
30 V
24 V
0.001
0.01
0.1
1
–
Forward Voltage Drop
0.0 0.3 0.6 0.9 1.2 1.5
10
1
−)A( tnerruC drawroF I F
VF− Forward Voltage Drop (V)
TJ = 150 °C
TJ = 25 °C
Capacitance
VDS – Drain-to-Source Voltage (V)
C – Capacitance (pF)
0
40
80
120
160
200
0 6 12 18 24 30
Coss
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
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Revision: 12-Mar-12 1Document Number: 91000
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