1
Data sheet acquired from Harris Semiconductor
SCHS150A
Features
• Complementary Data Outputs
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC151 and ’HCT151 are single 8-channel digital
multiplexers having three binary control inputs, S0, S1 and
S2 and an active low enable (E) input. The three binary
signals select 1 of 8 channels. Outputs are both inverting (Y)
and non-inverting (Y).
Pinout
CD54HC151, CD54HCT151
(CERDIP)
CD74HC151, CD74HCT151
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC151F3A -55 to 125 16 Ld CERDIP
CD74HC151E -55 to 125 16 Ld PDIP
CD74HC151M -55 to 125 16 Ld SOIC
CD54HCT151F3A -55 to 125 16 Ld CERDIP
CD74HCT151E -55 to 125 16 Ld PDIP
CD74HCT151M -55 to 125 16 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Waferor diefor thispart numberis availablewhich meetsall elec-
trical specifications. Please contact your local TI sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
I3
I2
I1
I0
Y
Y
GND
E
VCC
I5
I6
I7
S0
S1
S2
I4
September 1997 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC151,
CD54/74HCT151
High Speed CMOS Logic
8-Input Multiplexer
[ /Title
(CD74H
C151,
CD74H
CT151)
/
Subject
(High
Speed
CMOS
Logic 8-
Input
Multi-
2
Functional Diagram
TRUTH TABLE
SELECT INPUTS DATA INPUTS ENABLE OUTPUT
S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 E YY
XXXXXXXXXXX H HL
LLLLXXXXXXX L HL
LLLHXXXXXXX L LH
LLHXLXXXXXX L HL
LLHXHXXXXXX L LH
LHLXXLXXXXX L HL
LHLXXHXXXXX L LH
LHHXXXLXXXX L HL
LHHXXXHXXXX L LH
HLLXXXXLXXX L HL
HLLXXXXHXXX L LH
HLHXXXXXLXX L HL
HLHXXXXXHXX L LH
HHLXXXXXXLX L HL
HHLXXXXXXHX L LH
HHHXXXXXXXL L HL
HHHXXXXXXXH L LH
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
5
6
Y
Y
4
3
2
1
14
12
13
15
I0
I7
I6
I5
I4
I3
I2
I1
11
S010
S19
S2
E7GND = 8
VCC = 16
CD54/74HC151, CD54/74HCT151
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC151, CD54/74HCT151
4
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
Select 1.5
Data 0.45
Enable 0.3
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay (Figure 1) tPLH, tPHL CL= 50pF 2 - - 170 - 215 - 255 ns
Any Data Input to Y 4.5 - - 34 - 43 - 51 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 29 - 37 - 43 ns
CD54/74HC151, CD54/74HCT151
5
Any Data Input to Yt
PLH, tPHL CL= 50pF 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL=15pF 5 - 15 - - - - - ns
CL= 50pF 6 - - 31 - 39 - 48 ns
Any Select to Y tPLH, tPHL CL= 50pF 2 - - 185 - 230 - 280 ns
4.5 - - 37 - 46 - 56 ns
CL=15pF 5 - 15 - - - - - ns
CL= 50pF 6 - - 31 - 39 - 48 ns
Any Select to Yt
PLH, tPHL CL= 50pF 2 - - 205 - 255 - 310 ns
4.5 - - 41 - 51 - 62 ns
CL=15pF 5 - 17 - - - - - ns
CL= 50pF 6 - - 35 - 43 - 53 ns
Enable to Y tPLH, tPHL CL= 50pF 2 - - 140 - 175 - 210 ns
4.5 - - 28 - 35 - 42 ns
CL=15pF 5 - 11 - - - - - ns
CL= 50pF 6 - - 24 - 30 - 36 ns
Enable to Yt
PLH, tPHL CL= 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
CL=15pF 5 - 12 - - - - - ns
CL= 50pF 6 - - 25 - 31 - 38 ns
Output Transition Time
(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD -5-59-----pF
HCT TYPES
Propagation Delay (Figure 2) tPLH, tPHL
Any Data Input to Y CL= 50pF 4.5 - - 38 - 48 - 57 ns
CL=15pF 5 - 16 - - - - ns
Any Data Input to Yt
PLH, tPHL CL= 50pF 4.5 - - 36 - 45 - 54 ns
CL=15pF 5 - 15 - - - - - ns
Any Select to Y tPLH, tPHL CL= 50pF 4.5 - 41 - 51 - 62 ns
CL=15pF 5 - 17 - - - - - ns
Any Select to Yt
PLH, tPHL CL= 50pF 4.5 - - 43 - 54 - 65 ns
CL=15pF 5 - 18 - - - - - ns
Enable to Y tPLH, tPHL CL= 50pF 4.5 - - 29 - 36 - 44 ns
CL=15pF 5 - 12 - - - - - ns
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC151, CD54/74HCT151
6
Enable to YC
L= 50pF CL= 50pF 4.5 - - 36 - 46 - 54 ns
CL=15pF CL=15pF 5 15 - - - - - - ns
Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD - 5 58-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per gate.
5. PD = VCC2 fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuit and Waveform
FIGURE 1.
ENABLE
SELECT
In
Y OUTPUT
tPHL
tPLH
Y OUTPUT
INPUT LEVEL
GND
VS
tTLH
tTHL
tPHL
tPLH 10%
90%
VS
tf = 6nstr = 6ns
tTLH
tTHL
10%
90%
VS
CD54/74HC151, CD54/74HCT151
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
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Copyright 2000, Texas Instruments Incorporated
