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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DIndependent Dual-Outputs Operate 180°
Out of Phase
DWide Input Voltage Range: 4.5-V – 28-V
DAdjustable Output Voltage Down to 0.9 V
DPin-Selectable PWM/SKIP Mode for High
Efficiency Under Light Loads
DSynchronous Buck Operation Allows up to
95% Efficiency
DSeparate Standby Control and Overcurrent
Protection for Each Channel
DProgrammable Short-Circuit Protection
DLow Supply (1 mA) and Shutdown (1 nA)
Current
DPower Good Output
DHigh-Speed Error Amplifiers
DSequencing Easily Achieved by Selecting
Softstart Capacitor Values.
D5-V Linear Regulator Power Internal IC
Circuitry
D30-Pin TSSOP Packaging
description
The TPS5120 is a dual channel, high-efficiency synchronous buck controller where the outputs run 180 degrees
out of phase, which lowers the input current ripple, thereby reducing the input capacitance cost. The PWM/SKIP
pin allows the operating mode to switch from PWM mode to skip mode under light load conditions. The skip
mode enables a lower operating frequency and shortens the pulse width to the low-side MOSFET, increasing
the e fficiency under light load conditions. These two modes, along with synchronous-rectifier drivers, dead time,
and very low quiescent current, allow power to be conserved and the battery life to be extended under all load
conditions. The 1.5 A (typical) high-side and low-side MOSFET drivers on-chip are designed to drive less
expensive N-channel MOSFETs. The resistorless current protection and fixed high-side driver voltage simplify
the power supply design and reduce the external parts count. Each channel is independent, offering a separate
controller, overcurrent protection, and standby control. Sequencing is flexible and can be tailored by choosing
different softstart capacitor values. Other features, such as undervoltage lockout, power good, overvoltage,
undervoltage, and programmable short-circuit protection promote system reliability.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INV1
FB1
SOFTSTART1
PWM/SKIP
CT
5V_STBY
GND
REF
STBY1
STBY2
FLT
POWERGOOD
SOFTSTART2
FB2
INV2
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VCC
TRIP2
VREF5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
DBT PACKAGE
(TOP VIEW)
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical design
22
GND L1
L2
Q1
Q2
Q3
Q4
D1
D2
C1
C3
C4
C5
C6
C7
C8
C10
C11
C12
C13
C14
R1 R2
R3
R4
R5 R6
R7
R8
R9
R10
C15
U1
TPS5120DBT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
21
20
19
18
17
16
INV1
FB1
SOFTSTART1
PWM/SKIP
CT
5V_STBY
GND
REF
STBY1
STBY2
FLT
POWERGOOD
SOFTSTART2
FB2
INV2
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
Vcc
TRIP2
VREF5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
VO1
VI
VO2
C15
C16
Figure 1. EVM Typical Design
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functional block diagram
SOFTSTART1
DLY
DLY
OSC
Timer
SOFTSTART2
DLY
DLY
Phase
V5 VREG
Current
Protection
Trigger
Skip Comp. PWM Comp.
Err Amp.
0.85 V
STBY1
UVLO
SIGNAL
STBY2
OVP1
OVP2
UVP1
UVP2
0.85 V+12%
Err Amp.
Skip Comp.
0.85 V UVLO
SIGNAL
UVLO
Comp.
0.85 V
INV2 INV1
PGcomp4 PGcomp3INV2
PGcomp2
INV1
0.85 V–7% PGcomp1
4.5 V
5.0 V
PWM Comp.
Current Comp.
VCC
SOFTSTART1
FB1
INV1
CT
FLT
FB2
INV2
PWM/SKIP
SOFTSTART2
STBY1
STBY2
REF
5V_STBY
GND
POWERGOOD
REG5V_IN
VREF5
LH2
OUT2_u
LL2
OUT2_d
OUTGND2
TRIP2
TRIP1
V
OUTGND1
OUT1_d
LL1
OUT1_u
LH1
SFT1 SFT2
Inverter
0.85 V+12%
0.85 V –19.4%
0.85 V –19.4%
ref
0.85 V –7%
0.85 V +7%
0.85 V +7%
CC
_
+
_
+
_
+
_
+
_
+
_
+
_
+
+
_
+
_
+
+
_
+
_
+
_
+
_
+
_
+
_
+
_
+
_
+_
+
_
+
–(VCC
– VTRIP1VCC
LSD Trip
HSD Trip
_
+
HSD Trip
LSD Trip
– VTRIP1)
– VTRIP2VCC
–(VCC– VTRIP2)
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TATSSOP
(DBT) EVM
40°Cto85°C
TPS5120DBT TPS5120EVM-151
–40°C to 85°CTPS5120DBTR
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
CT 5 I/O External capacitor from CT to GND for adjusting the triangle oscillator
FB1 2 O Feedback output of CH1 error amplifier
FB2 14 O Feedback output of CH2 error amplifier
GND 7 Control GND
INV1 1 I Inverting input of the CH1 error amplifier, skip comparator, and OVP1/UVP1 comparator
INV2 15 I Inverting input of the CH2 error amplifier, skip comparator, and OVP2/UVP2 comparator
LH1 30 I/O Bootstrap capacitor connection for CH1 high-side gate drive
LH2 16 I/O Bootstrap capacitor connection for CH2 high-side gate drive
LL1 28 I/O Bootstrap this pin low for CH1 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
LL2 18 I/O Bootstrap this pin low for CH2 high-side gate driving return and output current protection. Connect this pin to
the junction of the high-side and low-side FETs for a floating drive configuration.
OUT1_d 27 O Gate drive output for CH1 low-side gate drive
OUT2_d 19 O Gate drive output for CH2 low-side gate drive
OUT1_u 29 O Gate drive output for CH1 high-side switching FETs
OUT2_u 17 O Gate drive output for CH2 high-side switching FETs
OUTGND1 26 Ground for CH1 FET drivers
OUTGND2 20 Ground for CH2 FET drivers
POWERGOOD 12 O Power good open-drain output. When low, POWERGOOD reports an output fail condition. PG comparators
monitor both SMPS’s over voltage and UVLO of VREF5. The threshold is ±7%. When the SMPS starts up, the
POWERGOOD pin’s output goes high. POWERGOOD also monitors VREF5’s UVLO output.
PWM/SKIP 4 I PWM/SKIP mode select pin. The PWM/SKIP pin is used to change the output’s operating mode. If this terminal
is lower than 0.5 V, it works in PWM mode. When a minimum voltage of 2 V is applied, the device operates in
skip mode. In light load condition (< 0.2 A), the skip mode gives a short pulse to the low-side FETs instead of a
full pulse. With this control, switching frequency is lowered and switching loss is reduced. Also, the output
capacitor energy discharging through the output inductor and low-side FETs is stopped. Therefore, TPS5120
achieves a higher efficiency in light load conditions.
REF 8 O 0.85-V reference voltage output. The 0.85-V reference voltage is used for setting the output voltage and the
voltage protection. This reference voltage is dropped down from a 5-V regulator.
REG5V_IN 21 I External 5-V input
FLT 11 I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time up.
SOFTSTART1 3 I/O External capacitor from SOFTSTART1 to GND for CH1 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
SOFTSTART2 13 I/O External capacitor from SOFTSTART 2 t o GND for CH2 softstart control. Separate soft-start terminals make it
possible to set the start-up time of each output independently.
STBY1 9 I Standby control for CH1. SMPS1 can be switched into standby mode separately by grounding the STBY1 pin.
STBY2 10 I Standby control for CH2. SMPS2 can be switched into standby mode separately by grounding the STBY2 pin.
TRIP1 25 I External resistor connection for CH1 output current control
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Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
TRIP2 23 I External resistor connection for CH2 output current control
VCC 24 Supply voltage input
VREF5 22 O 5-V internal regulator output
5V_STBY 6 I 5-V linear regulator control
detailed description
switching-mode power supply (SMPS) 1, 2
TPS5120 includes dual SMPS controllers that operate 180° out of phase and at the same frequency. Both
channels have standby and softstart.
5-V regulator
An internal linear voltage regulator is used for the high-side driver bootstrap voltage and source of VREF
(0.85 V). When the 5-V regulator is disconnected from the MOSFET drivers, it is only used for the source of
VREF. Since the input voltage range is from 4.5 V to 28 V, this feature offers a fixed voltage for the bootstrap
voltage so that the drive design is much easier. It is also used for powering the low-side driver. The tolerance
is 4%. The 5-V regulator is disabled when STBY1, STBY2, and 5V_STBY are all set low.
5-V switch
If the internal 5-V switch senses the 5-V input from the REG5V_IN pin, the internal 5-V linear regulator is
disconnected from the MOSFET drivers. The external 5 V is then used for both the low-side driver and the
high-side bootstrap, thus, increasing the efficiency.
error amplifier
Each channel has its own error amplifier to regulate the output voltage of the synchronous buck converter. It
is used in the PWM mode for the high output current condition (> 0.2 A). The unity gain bandwidth is 2.5 MHz.
This decreases the amplifier delay during fast load transients and contributes to a fast transient response.
skip comparator
In skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the synchronous
buck converter. The hysteresis is set internally and is typically set at 9 mV. The delay from the comparator input
to the driver output is typically 1.2 µs.
low-side driver
The low-side driver is designed to drive low rds(on) N-channel MOSFETs. The maximum drive voltage is 5 V from
VREF5. The current rating of the driver is typically 1.5 A at source and sink.
high-side driver
The high-side driver is designed to drive low rds(on) N-channel MOSFETs. The current rating of the driver is 1.2 A
at source and sink. When configured as a floating driver, the bias voltage to the driver is developed from VREF5,
limiting the maximum drive voltage between OUTx_u and LLx to 5 V. The maximum voltage that can be applied
between LHx and OUTGND is 33 V.
deadtime
Deadtime prevents shoot through current from flowing through the main power FETs during switching transitions
by actively controlling the turnon time of the MOSFETs drivers.
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detailed description (continued)
current protection
Overcurrent protection is achieved by comparing the drain-to-source voltage of the high-side and low-side
MOSFET devices to a set-point voltage. This voltage is set using an external resistor between VCC and the
TRIP1 or TRIP2 terminals. If the drain-to-source voltage up exceeds the set-point voltage during high-side
conduction, the current limit circuit terminates the high-side driver pulse. If the set-point voltage is exceeded
during low-side conduction, the low-side pulse is extended through the next cycle. Together this action has the
effect of decreasing the output voltage until the undervoltage protection circuit is activated and the fault latch
is set and both the high and low-side MOSFET drivers are shut off.
overvoltage protection
For overvoltage protection (OVP), the TPS5120 monitors INV pin voltage. When the INV voltage is higher than
0.95 V (+12%), the OVP comparator output goes high and the FLT timer starts to charge an external capacitor
connected to FLT. After a set time, the FLT circuit latches the MOSFET drivers off.
undervoltage protection
For undervoltage protection (UVP), the TPS5120 monitors INV pin voltage. When the INV voltage is lower than
0.68 V ( –19.4%), the OVP comparator output goes high, and the FLT timer starts to charge an external capacitor
connected to FLT. Also, when the current comparator triggers the OCP, the UVP comparator detects the under
voltage output and starts the FLT capacitor charge. After a set time, the FLT circuit latches off all of the MOSFET
drivers.
FLT
When an OVP or UVP comparator output goes high, the FLT circuit starts to charge the FLT capacitor. If the
FLT pin voltage goes beyond a constant level, the TPS5120 latches the MOSFET drivers. At this time, the state
of MOSFET is different depending on the OVP alert and the UVP alert. Also, the enable time used to latch the
MOSFET driver is decided by the capacity of the FLT capacitor. The charging constant current value is also
different depending on whether it is an OVP alert or a UVP alert. The difference is shown in the following
equation:
FLT source current (OVP) = FLT source current (UVP) × 5
shutdown
The TPS5120 can be shut down by grounding STBY1, STBY2, and 5V_STBY. The shutdown current is as l o w
as 1 µA.
UVLO
When the input voltage goes up to about 4 V, the TPS5120 is operational. When the input voltage is lower than
the turnon value, the device is turned off. The typical hysteresis voltage is 40 mV.
phase Inverter
Phase inverter controls the phase of SMPS1 and SMPS 2. SMPS1 operates in phase with the OSC. SMPS2
operates 180° out of phase from SMPS1. This allows smaller input capacitors to be used.
oscillator
TPS5120 has a triangle oscillator generator internal to the IC. The oscillation frequency is set by the size of the
capacitor connected to the CT pin. The voltage amplitude is 0.43 V ~ 1.17 V.
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Table 1. Logic Chart
5V_STBY STBY1 STBY2 SMPS1 SMPS2 5 V REGULATOR POWERGOOD
L L L Disable Disable Disable Disable
L L H Disable Enable Enable Active†
L H L Enable Disable Enable Active†
L H H Enable Enable Enable Active
H L L Disable Disable Enable L
H L H Disable Enable Enable Active†
H H L Enable Disable Enable Active†
H H H Enable Enable Enable Active
†PG is set high during a softstart.
POWERGOOD timing sequence
POWERGOOD
STBY1
STBY2
INV1
INV2
H
L
H
L
H
L
0.91 V
0.85 V
0.78 V
0 V
0.91 V
0.85 V
0.78 V
0 V
TSS
During a softstart, this channel’s powergood comparator output is fixed low (POWERGOOD output is high).
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage: INV1, INV2, CT, PWM/SKIP, REG5V_IN, SOFTSTART1, SOFTSTART2, –0.3 V to 7 V. . . . .
FLT, POWERGOOD –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STBY1, STBY2, 5V_STBY, TRIP1, TRIP2 –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage: LL1, LL2 –1.0 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT1_u, OUT2_u –1.0 V to 35 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH1, LH2 –0.3 V to 35 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT1_d, OUT2_d, 5V_OUT, FB1, FB2 –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REF –0.3 V to 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT1_u, LH1 to LL1 –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUT2_u, LH2 to LL2 –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation (TA ≤ 25°C), PD 874 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal unless otherwise noted.
2. This rating is specified at duty = 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should
not exceed 2 µs.
3. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CPOWER DISSIPATION
TA = 85°C
DBT 874 mW 6.993 mW/°C454 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 28 V
INV1, INV2, CT, PWM/SKIP, SOFTSTART1, SOFTSTART2, FLT 6
REG5V_IN, POWERGOOD –0.1 5.5
Input voltage, VISTBY1, STBY2, 5V_STBY 28 V
In ut
voltage,
VI
OUT1_u, OUT2_u, LH1, LH2 33
V
TRIP1, TRIP2 –0.1 28
Oscillator frequency, fosc 300 500 kHz
Operating free-air temperature range, TA–40 85 °C
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
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electrical characteristics over recommended free-air temperature range, VCC = 7 V (unless
otherwise noted)
reference voltage
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref Reference voltage 0.85 V
TA = 25°C, I = 50 µA–1% 1%
Vref
(
tol
)
Reference voltage tolerance TA = –20°C to 85°C, I = 50 µA–1.5% 1.5%
Vref(tol)
Reference
voltage
tolerance
TA = –40°C to 85°C, I = 50 µA–2% 2%
R(egin) Line regulation VCC = 4.5 V to 28 V, I = 50 µA 0.05 3 mV
R(egl) Load regulation I = 0.1 µA to 1 mA 0.15 5 mV
oscillator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Frequency PWM mode, CT = 44 pF, TA = 25 °C 300 kHz
V
High le el o tp t oltage
DC 1 1.1 1.2
V
VOH High level output voltage fosc = 300 kHz 1.17 V
V
Lo le el o tp t oltage
DC 0.4 0.5 0.6
V
VOL Low level output voltage fosc = 300 kHz 0.43 V
error amplifier
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage TA = 25°C 2 10 mV
Open-loop voltage gain 50 dB
Unity-gain bandwidth 2.5 MHz
I(snk) Output sink current VO = 1 V 0.3 0.7 mA
I(src) Output source current VO = 1 V 0.2 0.9 mA
skip comparator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vhys Hysteresis window SKIP mode 9 mV
duty control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DUTY Maximum duty cycle 300 kHz, VI = 0 V 83%
control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
High le el inp t oltage
STBY1, STBY2 2.2
V
VIH High-level input voltage PWM/SKIP, 5V_STBY 2.2 V
V
Lo le el inp t oltage
STBY1, STBY2 0.3
V
VIL Low-level input voltage PWM/SKIP, 5V_STBY 0.3 V
5-V internal switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(TO_H)
Threshold
4.2 4.8
V
V(TO_L) Threshold 4.1 4.7 V
Vhys Hysteresis 30 200 mV
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended free-air temperature range, VCC = 7 V (unless
otherwise noted) (continued)
5-V regulator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput voltage IO = 0 mA to 50 mA,
TA = 25°CVCC = 5.5 V to 28 V, 4.8 5.2 V
R(egin) Line regulation VCC = 5.5 V to 28 V, I =10 mA 20 mV
R(egl) Load regulation I = 1 mA to 10 mA, VCC = 5.5 V 40 mV
IOS Short circuit output current 5VREG = 0 V, TA = 25°C 65 mA
V(TO_H)
UVLO threshold voltage
5V OUT voltage
3.6 4.2
V
V(TO_L) UVLO threshold voltage 5V_OUT voltage 3.5 4.1 V
Vhys Hysteresis 5V_OUT voltage 30 150 mV
output drivers
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT_u sink current VO = 3 V 1.2 A
OUT_u source current VO = 2 V –1.5 A
OUT_d sink current VO = 3 V 1.5 A
OUT_d source current VO = 2 V –1.5 A
I(TRIP) TRIP pin current TA = 25°C 11.5 13 14.5 µA
soft start
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SOFT) Soft start current 1.6 2.3 2.9 µA
V(TO_H)
Threshold voltage (SKIP mode)
3.7
V
V(TO_L) Threshold voltage (SKIP mode) 2.5 V
output voltage monitor
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVP comparator threshold 0.91 0.95 0.99 V
UVP comparator threshold 0.64 0.68 0.72 V
PG comparator 1, 2 threshold 0.75 0.78 0.81 V
PG comparator 3, 4 threshold 0.88 0.91 0.94 V
PG propagation dela from INV to POWERGOOD
Turnon 13
s
PG propagation delay from INV to POWERGOOD Turnoff 1.2 µs
Timer latch current source
UVP protection 1.5 2.3 3.1
A
Timer latch current source OVP protection 8 11.5 15 µA
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Supply current TA = 25°C, CT = 0 V, INV = 0 V 1.1 1.5 mA
ICC(S) Shutdown current STBY 1, STBY2, 5V_STBY = 0 V 0.001 10 µA
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
TJ – Junction Temperature – °C
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
1.05
1.10
1.15
1.20
1.25
1.30
–50 0 50 100 150
Icc – Quiescent Current – mA
VCC = 28 V
VCC = 7 V VCC = 4.5 V
QUIESCENT CURRENT (SHUTDOWN)
vs
JUNCTION TEMPERATURE
0
200
400
600
800
1000
1200
–50 0 50 100 150
Icc(s) – Quiescent Current – nA
VCC = 28 V
VCC = 7 V
VCC = 4.5 V
TJ – Junction Temperature – °C
Figure 3
Figure 4
DRIVE OUTPUT CURRENT (OUT_u)
vs
DRIVE OUTPUT VOLTAGE
–1.80
–1.70
–1.60
–1.50
–1.40
–1.30
–1.20
–1.10
–1.00
–0.90
–0.80
0.5 11.5 22.5 33.5
IO(SOURCE)
– Drive Output Current (OUT_u) – A
TJ = –40 °C
TJ = –20 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
VO – Drive Output Voltage (OUT_u) – V Figure 5
vs
DRIVE OUTPUT VOLTAGE
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.5 22.5 33.5 44.5
IO(SINK)
TJ = –40 °C
TJ = 25 °CTJ = –20 °C
TJ = 85 °C
TJ = 125 °C
VO – Drive Output Voltage (OUT_u) – V
DRIVE OUTPUT CURRENT (OUT_u)
– Drive Output Current (OUT_u) – A
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
DRIVE OUTPUT CURRENT (OUT_d)
vs
DRIVE OUTPUT VOLTAGE
–2.00
–1.80
–1.60
–1.40
–1.20
–1.00
–0.80
0.5 11.5 22.5 33.5
VO – Drive Output Voltage (OUT_d) – V
IO(SOURCE)– Drive Output Current (OUT_d) – A
TJ = –40 °C TJ = –20 °C
TJ = 25 °C
TJ = 85 °CTJ = 125 °C
Figure 7
vs
DRIVE OUTPUT VOLTAGE
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.5 22.5 33.5 44.5
TJ = –40 °C TJ = –20 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
IO(SINK)
DRIVE OUTPUT CURRENT (OUT_d)
– Drive Output Current (OUT_d) – A
VO – Drive Output Voltage (OUT_d) – V
Figure 8
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
–50 0 50 100 150
V
(OSCH) – Oscillator Output Voltage – V
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
TJ – Junction Temperature – °C
Figure 9
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
480
485
490
495
500
–50 0 50 100 150
V(OSCL) – Oscillator Output Voltage – mV
TJ – Junction Temperature – °C
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
vs
JUNCTION TEMPERATURE
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
–50 0 50 100 150
VIO– Error Amplifier Input Offset Voltage – mV
VCC = 28 V
TJ – Junction Temperature – °C
VCC = 4.5 V,
VCC = 7 V
Figure 11
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
1.50
1.75
2.00
2.25
2.50
2.75
3.00
–50 0 50 100 150
VO+ – Positive Error Amplifier Output Voltage – V
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
TJ – Junction Temperature – °C
Figure 12
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
–50 0 50 100 150
VO–– Negative Error Amplifier Output Voltage – mV
TJ – Junction Temperature – °C
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
Figure 13
SKIP COMPARATOR HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
–50 0 50 100 150
Vhys – Skip Comparator Hysteresis Voltage – mV
VCC = 4.5 V
VCC = 7 V
VCC = 28 V
TJ – Junction Temperature – °C
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
VREF5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
–60–50–40–30–20–10
0IO – Output Current – mA
TJ = –40 °CTJ = –20 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
VO – VREF5 Output Voltage – V
Figure 15
VREF5 SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
–120
–100
–80
–60
–40
–20
0
–50 0 50 100 150
IOS– VREF5 Short–Circuit Output Current – mA
VCC = 4.5 V
VCC = 7 V
VCC = 28 V
TJ – Junction Temperature – °C
Figure 16
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
3.50
3.60
3.70
3.80
3.90
4.00
–50 0 50 100 150
V(TO) – UVLO Threshold Voltage – V
V(TO_H)
V(TO_L)
TJ – Junction Temperature – °CFigure 17
UVLO
HYSTERESIS
VOLTAGE
vs
JUNCTION TEMPERATURE
0
20
40
60
80
100
120
140
–50 0 50 100 150
Vhys – UVLO Hysteresis Voltage – mV
TJ – Junction Temperature – °C
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
REG5V_IN THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
4.4
4.5
4.5
4.6
4.6
4.7
4.7
–50 0 50 100 150
V
(TO)– REG5V_IN Threshold Voltage – V
V(TO_L)
V(TO_H)
TJ – Junction Temperature – °C
Figure 19
REG5V_IN HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
0
20
40
60
80
100
120
140
–50 0 50 100 150
Vhys – REG5V_IN Hysteresis Voltage – mV
TJ – Junction Temperature – °C
Figure 20
–50 0 50 100 150
SOFTSTART
CURRENT
vs
JUNCTION TEMPERATURE
–2.30
–2.28
–2.26
–2.24
–2.22
–2.20
–2.18
–2.16
–2.14
–2.12
–2.10
Softstart Current – A
VCC = 4.5 V
µ
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
Figure 21
OVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
944
946
948
950
952
954
956
–50 0 50 100 150
V(TO) – OVP Threshold Voltage – mV
VCC = 4.5 V
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
POWERGOOD THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
750
775
800
825
850
875
900
925
950
–50 0 50 100 150
V(TO) – Powergood Threshold Voltage – mV
V(TO_H)
V(TO_L)
TJ – Junction Temperature – °C
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
VCC = 4.5 V,
VCC = 7 V,
VCC = 28 V
Figure 23
SCP
(OVP)
SOURCE
CURRENT
vs
JUNCTION TEMPERATURE
–12.0
–11.9
–11.8
–11.7
–11.6
–11.5
–11.4
–11.3
–11.2
–11.1
–11.0–50 0 50 100 150
SCP (OVP) Source Current –
VCC = 4.5 V
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
Aµ
Figure 24
SCP (OVP) SOURCE CURRENT
vs
JUNCTION TEMPERATURE
–2.40
–2.38
–2.35
–2.33
–2.30
–2.28
–2.25
–2.23
–2.20
–50 0 50 100 150
I(SOURCE) –
VCC = 4.5 V
SCP (OVP) Source Current –
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
Aµ
Figure 25
TRIP
SINK
CURRENT
vs
TRIP INPUT VOLTAGE
12.0
12.2
12.4
12.6
12.8
13.0
13.2
13.4
13.6
13.8
14.0
0 4 8 121620242832
VI – TRIP Input Voltage – V
I(SINK)– TRIP Sink Current – A
TJ = –40 °C
TJ = –20 °C
TJ = 25 °C
TJ = 85 °CTJ = 125 °C
µ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 26
OSCILLATOR FREQUENCY
vs
CAPACITANCE
10
100
1000
0 50 100 150 200 250
CT – Capacitance – pF
fOSC – Oscillator Frequency – kHz
VCC = 7 V,
TJ = 25 °C
Figure 27
OUTPUT MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
81.0
81.5
82.0
82.5
83.0
83.5
84.0
84.5
85.0
–50 0 50 100 150
Output Maximum Duty Cycle – %
VCC = 7 V,
VCC = 28 V
VCC = 4.5 V
TJ – Junction Temperature – °C
fosc = 300 kHz
Figure 28
SCP DELAY TIME
vs
CAPACITANCE
1
10
100
1 k
10 k
100 k
10 100 1 k 10 k 100 k
SCP – Capacitance – pF
– SCP Delay Time (OVP) – s
td(SCP) µ
Figure 29
SOFTSTART TIME
vs
SOFTSTART CAPACITANCE
10
100
1 k
10 k
100 k
100 1 k 10 k 100 k
Softstart Capacitance – pF
t – Softstart Time – s
µ
SLVS278E – AUGUST 2000 – REVISED MARCH 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 30
DRIVER DEAD TIME (OUT_u FALL)
vs
JUNCTION TEMPERATURE
162.5
165.0
167.5
170.0
172.5
175.0
–50 0 50 100 150
Driver Dead Time – ns
VCC = 4.5 V
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
Figure 31
DRIVER DEAD RISE TIME (OUT_u RISE)
vs
JUNCTION TEMPERATURE
70
75
80
85
90
95
100
–50 0 50 100
Driver and Dead Rise Time (OUT_u RISE)
VCC = 4.5 V
TJ – Junction Temperature – °C
VCC = 7 V,
VCC = 28 V
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS5120DBT ACTIVE TSSOP DBT 30 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5120DBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5120DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5120DBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS5120 :
•Automotive: TPS5120-Q1
•Enhanced Product: TPS5120-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS5120DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5120DBTR TSSOP DBT 30 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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