ee FAIRCHILD ree SEMICONDUCTOR 74VHC74 Dual D-Type Flip-Flop with Preset and Clear General Description The VHG74 is an advanced high speed CMOS Dual D- Type Flip-Flop fabricated with silicon gate CMOS technol- ogy. It achieves the high speed operation similar to equiva- lent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transi- tion of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit ensures that OV to 7V can be applied to the input pins without regard to the supply volt- October 1992 Revised March 1999 age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features Mf High Speed: fyax = 170 MHz (typ) at Ta = 25C W High noise immunity: Vain = Vnit = 28% Voc (min) li Power down protection is provided on all inputs H Low power dissipation: log = 2 MA (max) at Ta = 25C Mf Pin and function compatible with 74HC74 Ordering Code: Order Number | Package Number Package Description 74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74VHC748J M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.8mm Wide 74VHC74MTG MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram 1 Logic Symbol IEEE/IEC PR, Sys Q i CK, > dD 4 0. = J 1 Q, CLR, YR PR, be Q, CK) o ~ _2 Q CLR, Pin Descriptions Pin Names Description Dy, Dp Data Inputs CK, CKp Clock Pulse Inputs CLR, CLRe Direct Clear Inputs PRy, PR Direct Preset Inputs Qy, a, Qo, Q, Output cLR, 2 Dy 3 CK, 4 PR, ; Q a 6 Q 7 GND Truth Table Inputs Outputs = Function CLR} PR| D | CK Q Q L H X X L H Clear H L x x H L Preset L L X X |H (Note 1) |] H (Note 1) H H L Js L H H H H}w7 H L H H xX | Qa Qn No Change Note 1: This configuration is nonstable; that is, it will not persist when pre- set and clear inputs return to their inactive (HIGH) state. 1999 Fairchild Semiconductor Corporation DSO11505.prf www.fairchildsemi.com Jea|D pue jesalg YUM doj4-dij4 edAL-q lend PLOHAPL74VHC74 Absolute Maximum Ratingsinote 2) Supply Voltage (Vcc) 0.5V to +7.0V DC Input Voltage (Vin) 0.5V to +7.0V DC Output Voltage (Vout) 0.5V to Veco + 0.5V Input Diode Current (I}) -20 mA Output Diode Current (lox) +20 mA DC Output Current (Igy) +25 mA DC Vec/GND Current (loc) +50 mA Storage Temperature (Tst@) 65C to +150C Lead Temperature (T_) Soldering (10 seconds) 260C DC Electrical Characteristics Recommended Operating Conditions (note 3) Supply Voltage (Vcc) 2.0V to 5.5V Input Voltage (Vin) OV to +5.5V Output Voltage (Voy) OV to Voc Operating Temperature (Topr) 40C to +85C Input Rise and Fall Time (t,, t) Voc =3.3V + 0.3V 0 ~ 100 ns/V Voc =5.0V 40.5V 0~ 20 ns/V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varai- bles. Fairchild does not recommend operation outside databook specifica- tions. Note 3: Unused inputs must be held HIGH or LOW. They may not float. Voc Ta = 25C Ta =40C to +85C | - Symbol Parameter Units Conditions (Vv) Min Typ Max Min Max Vin HIGH Level Input 2.0 1.50 1.50 V Voltage 3.0-5.5] 0.7 Voc 0.7 Voc VIL LOW Level Input 2.0 0.50 0.50 Vv Voltage 3.0-5.5 0.3 Veg 0.3 Veg Vou HIGH Level Output 2.0 1.9 2.0 1.9 Vin = Vin | lon =-80 pA Voltage 3.0 2.9 3.0 2.9 v or Vit 45 44 45 44 3.0 2.58 2.48 V lon =4 mA 45 3.94 3.80 loy=8 mA Vo. LOW Level Output 2.0 0.0 0.1 0.1 Vin = Vin | lot = 50 pA Voltage 3.0 0.0 0.1 0.1 v or Vit 45 0.0 0.1 0.1 3.0 0.36 0.44 V loc =4 mA 45 0.36 0.44 loL=8 mA In Input Leakage Current 0-55 +0.1 +1.0 pA Vin = 5.5V or GND loc Quiescent Supply Current 5.5 2.0 20.0 pA Vin =Vec or GND www.fairchildsemi.com 2AC Electrical Characteristics Voc Ta = 25C Ta =40C to +85C | - Symbol Parameter Units Conditions (v) Min Typ Max Min Max fax Maximum Clock 3.3403 80 125 70 MHz C_=15 pF Frequency 50 75 45 C_=50 pF 5.0+0.5 130 170 110 C_=15 pF MHz 90 415 75 C_=50 pF teLy Propagation Delay 3.3+0.3 6.7 11.9 1.0 14.0 ns C_=15 pF teu Time (CK-Q, Q) 9.2 15.4 1.0 17.5 C, =50 pF 5.0+0.5 4.6 7.3 1.0 8.5 CL =15 pF 6.1 9.3 1.0 10.5 ns C_=50 pF tpLy Propagation Delay Time |3.3+0.3 7.6 12.3 1.0 14.5 ns CL =15 pF teu (CLR, PR -Q, Q) 10.1 15.8 1.0 18.0 C_=50 pF 5.0+0.5 48 7.7 1.0 9.0 CL =15 pF 6.3 9.7 1.0 11.0 ns C_=50 pF Cn Input Capacitance 4 10 10 pF Veco = Open Cpp Power Dissipation 25 pF (Note 4) Capacitance Note 4: Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: I (opr.) = Cpp * Vec * fin+ lee/2 (per F/F). AC Operating Requirements Vee Ta= 25C Ta = 40C to +85C Symbol Parameter w A 5) Typ Guaranteed Minimum Units tw) Minimum Pulse Width (CK) 3.3 6.0 7.0 tw(H) 5.0 5.0 5.0 ns tw(L) Minimum Pulse Width (CLR, PR) 3.3 6.0 7.0 ne 5.0 5.0 5.0 ts Minimum Setup Time 3.3 6.0 7.0 5.0 5.0 5.0 ns ty Minimum Hold Time 3.3 0.5 0.5 5.0 0.5 0.5 ns trec Minimum Recovery Time (CLR, PR) 3.3 5.0 5.0 ns 5.0 3.0 3.0 Note 5: Veg is 3.3 + 0.3V or 5.0 + 0.5V 3 www.fairchildsemi.com DLOHAPL74VHC74 Physical DimensiON$ inches (millimeters) unless otherwise noted 0.010 -0.020 (0.254 0.508) 1 es 0,008 0.040 (0-203-0.254) TYP ALL LEADS O]0.006 (0.15) \ 45 | + | H 0.228 0.335 -0,344 (8.509 8.738) SEATING PLANE 0.244 0: (5.791 6.198) Oo) re LEAD NO. 1 --"[ , IDENT 0.010 max (0.254) 0.1500.157 (3.810 3.988) 0.053 ~0.089 (1.346 1.753) Be MAX TYP 0.0040.010 ALL LEADS 1 (0.102 0.258) SEATING a Yi i tr fs ain PLANE ' | 4 014 = 0.050 | | 0.044~0.020 yyp 0.016 0.050 (0.356) 279) < -~ (0.356 0.508) 0.004 (0.406 1.270) TYP 0.008 54, (0.102) TYP ALL LEADS 0.203) ALL LEAD TIPS Mea HEV bn 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14 8 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) 1 7 0.394-0.402 0.71 _ Dseeb oe . 0.006-0.010 (0.0- 10.2) (ray) (o.15-0.25) 'YP [ \ 0.067-0.083 rT Ga-niy (02788 TYP Ct 0.049 ~ |. = nel | I 9.000-0.010 (oy gsy TYP) (0-90.25) 0.016-0.031 9.014-0.020 1, >| ~(o.4-0.8) "YP (0.35-0.50)_ M14D (REV B) 14-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M14D www.fairchildsemi.com 4Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) as Ti Py ALL LEAD TIP: PIN #1 IDENT, io Ma at ea i a nis = MAS PS yer [c] poeeaae : imine i" La Loen,usS aT - MOTE Ss A CONFORM: TO JEUEC FEGISTRATION MO-1S3 VARIATION AB_ FEF NOTE 6, DATED 7/93 B. DIMENSION: APE IN MILLIMETERS C, DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS _ | a 1 4.18 | 1.78 ] 0.654 | | ee | C J SEE DETAIL & aI Oe mog-o20 / \ JAS tot ~ a cn TOP EOQTTOM Finle Pu, 3l- a s i SEATING PLANE [1 DETAIL & 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com DLOHAPLPhysical DimensiONS inches (millimeters) unless otherwise noted (Continued) 74VHC74 Dual D-Type Flip-Flop with Preset and Clear 0,7400.770 (18.80 19.56) 0.090 (2.286) (ia) [3] [rz] [ry] fro) Ts) fe] INDEX AREA aA 0.250+0.010 bo M7 (6.350 +0.254) PINNG. 1% PINNO. 1 IDENT De Be ENs IDENT LT ITs 0.092 0.030 MAX (2.337) (0.762) DEPTH OPTION 1 OPTION 02 9-138 50.008 0.300 -0.320 1148_0.200 (3.428 20.127) 6a (7.620 8.128) 0.065 te Te >| ~<_ TP 1 ew 4 TYP a (9.683 5.080) | | (1.524) \ optional (1.651) A A rT Yy [on 4 S>== 0.008D.016 syp 0.020 ' go +4 TYP (0.203 0.406) (0.508) ~ le MIN a | a 0.075 +0.015 (8.175 3.810) 11.905 40.381] nia \ . |_| 0.014--0.023 typ ye || o100+0.010 MIN (0.356 0.584) > .1000.010 typ 0.050 +0.010 (2.540=0-254) | ~e________ TYP +0.040 (1.270 0.254) 0.325 015 +1016 B.2 ( 38 0) NIA IREY FD 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.