FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2007-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
Memory FRAM
CMOS
2 M Bit (256 K × 8)
MB85R2001
■DESCRIPTIONS
The MB85R2001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words × 8 bits
of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.
The MB85R2001 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R2001 can be used for 1010 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
The MB85R2001 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
■FEATURES
• Bit configuration : 262,144 words × 8 bits
• Read/write endurance : 1010 times/bit
• Operating power supply voltage : 3.0 V to 3.6 V
• Operating temperature range : − 40 °C to + 85 °C
• Data retention : 10 years ( + 55 °C)
• Package : 48-pin plastic TSOP (1)
DS05-13107-5E
MB85R2001
2 DS05-13107-5E
■PIN ASSIGNMENTS
■PIN DESCRIPTIONS
Pin name Function
A0 to A17 Address Input
I/O1 to I/O8 Data Input/Output
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
GND Ground
NC No Connection
A11
A9
NC
A8
A13
WE
CE2
A15
NC
VCC
NC
NC
GND
NC
NC
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
NC
GND
A10
CE1
NC
I/O8
I/O7
I/O6
I/O5
I/O4
VCC
NC
I/O3
I/O2
I/O1
NC
NC
NC
A0
A1
GND
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(FPT-48P-M25)
(TOP VIEW)
MB85R2001
DS05-13107-5E 3
■BLOCK DIAGRAM
A0
A17
to
Address Latch.
Row Dec. Ferro Capacitor Cell
Column Dec.
S/A
I/O1 to I/O8
I/O8
I/O1
to
intCEB
intCE2
intWE
intOE
intCE2
intCEB
CE2
intCE2
·
·
·
·
·
WE
OE
CE1
MB85R2001
4 DS05-13107-5E
■FUNCTION TRUTH TABLE
L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
: Latch address and latch data at falling edge, : Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
Operation Mode CE1CE2 WE OE I/O1 to I/O8 Supply Current
Standby Pre-charge
HXXX
High-Z Standby
(ISB)
XLXX
XXHH
Read L
HHL
Dout
Operation
(ICC)
Read
(Pseudo-SRAM, OE control*1)LHH
Write
L
HLH
Din
Write
(Pseudo-SRAM, WE control*2)LH H
MB85R2001
DS05-13107-5E 5
■ABSOLUTE MAXIMUM RATINGS
* : All voltages are referenced to GND = 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
* : All voltages are referenced to GND = 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Rating Unit
Min Max
Supply Voltage* VCC −0.5 +4.0 V
Input Voltage* VIN −0.5 VCC + 0.5 V
Output Voltage* VOUT −0.5 VCC + 0.5 V
Ambient Operating Temperature TA−40 +85 °C
Storage Temperature Tstg −40 +125 °C
Parameter Symbol Value Unit
Min Typ Max
Supply Voltage* VCC 3.0 3.3 3.6 V
Input Voltage (high)* VIH VCC x 0.8 ⎯VCC + 0.5 V
Input Voltage (low)* VIL −0.5 ⎯+0.8 V
Operating Temperature TA−40 ⎯+85 °C
MB85R2001
6 DS05-13107-5E
■ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
(within recommended operating conditions)
*1 : During the measurement of ICC, the Address, Data In were taken to only change once per active cycle.
IOUT: output current
*2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V.
Parameter Symbol Condition Value Unit
Min Typ Max
Input Leakage Current |ILI|VIN = 0 V to VCC ⎯⎯10 μA
Output Leakage Current |ILO|VOUT = 0 V to VCC,
CE1 = VIH or OE = VIH ⎯⎯10 μA
Supply Current ICC CE1 = 0.2 V, CE2 = VCC − 0.2 V,
IOUT = 0 mA*1⎯10 15 mA
Standby Current ISB
CE1 ≥ VCC − 0.2 V
⎯10 50 μACE2 ≤ 0.2 V*2
OE ≥ VCC − 0.2 V, WE ≥ VCC − 0.2 V*2
Output Voltage (high) VOH IOH = − 2.0 mA VCC x 0.8 ⎯⎯V
Output Voltage (low) VOL IOL = 2.0 mA ⎯⎯0.4 V
MB85R2001
DS05-13107-5E 7
2. AC CHARACTERISTICS
• AC TEST CONDITIONS
Supply Voltage : 3.0 V to 3.6 V
Operating Temperature : −40 °C to +85 °C
Input Voltage Amplitude : 0.3 V to 2.7 V
Input Rising Time : 5 ns
Input Falling Time : 5 ns
Input Evaluation Level : 2.0 V / 0.8 V
Output Evaluation Level : 2.0 V / 0.8 V
Output Impedance : 50 pF
(1) Read Operation
(within recommended operating conditions)
(2) Write Operation
(within recommended operating conditions)
Parameter Symbol Value Unit
Min Max
Read Cycle Time tRC 150 ⎯ns
CE1 Active Time tCA1 120 ⎯ns
CE2 Active Time tCA2 120 ⎯ns
OE Active Time tRP 120 ⎯ns
Pre-charge Time tPC 20 ⎯ns
Address Setup Time tAS 5⎯ns
Address Hold Time tAH 50 ⎯ns
OE Setup Time tES 5⎯ns
Output Hold Time tOH 0⎯ns
Output Set Time tLZ 30 ⎯ns
CE1 Access Time tCE1 ⎯100 ns
CE2 Access Time tCE2 ⎯100 ns
OE Access Time tOE ⎯100 ns
Output Floating Time tOHZ ⎯20 ns
Parameter Symbol Value Unit
Min Max
Write Cycle Time tWC 150 ⎯ns
CE1 Active Time tCA1 120 ⎯ns
CE2 Active Time tCA2 120 ⎯ns
Pre-charge Time tPC 20 ⎯ns
Address Setup Time tAS 5⎯ns
Address Hold Time tAH 50 ⎯ns
Write Pulse Width tWP 120 ⎯ns
Data Setup Time tDS 0⎯ns
Data Hold Time tDH 50 ⎯ns
Write Setup Time tWS 5⎯ns
MB85R2001
8 DS05-13107-5E
3. Pin Capacitance
Parameter Symbol Condition Value Unit
Min Typ Max
Input Capacitance CIN VIN = VOUT = GND
f = 1 MHz, TA = +25 °C
⎯⎯10 pF
Output Capacitance COUT ⎯⎯10 pF
MB85R2001
DS05-13107-5E 9
■TIMING DIAGRAMS
1. Read Cycle Timing (CE1, CE2 Control)
2. Read Cycle Timing (OE Control)
tAS tAH
tES
Valid
tRP
H or L
CE1
CE2
tRC
tPC
A0 to A17
OE
I/O1 to I/O8
tOHZ
High-Z
Valid
tOH
tLZ
Invalid Invalid
tCA1
tCA2
tCE1,
tCE2
A0 to A17
OE
I/O1 to I/O8
t
AS
t
AH
t
RC
t
OE
t
OHZ
High-Z
Valid
t
OH
t
LZ
Valid H or L
t
RP
Invalid Invalid
t
PC
CE1
CE2
t
CA1
t
CA2
MB85R2001
10 DS05-13107-5E
3. Write Cycle Timing (CE1, CE2 Control)
4. Write Cycle Timing (WE Control)
CE1
CE2 tCA2
tCA1
tWC
tPC
A0 to A17
WE
Data In
tWP
tDH
High-Z
tAH
tAS
tDS
Valid H or L
Valid H or L
tWS
A0 to A17
tWP
tWC
tDH
High-Z
tAH
tAS
tDS
Valid H or L
Valid H or L
tPC
WE
Data In
CE1
CE2
tCA1
tCA2
MB85R2001
DS05-13107-5E 11
■POWER ON/OFF SEQUENCE
(within recommended operating conditions)
■NOTES ON USE
After the IR reflow completed, it is not guaranteed to save the data written prior to the IR reflow.
Parameter Sym-
bol
Value Unit
Min Typ Max
CE1 level hold time for Power OFF tpd 85 ⎯⎯ns
CE1 level hold time for Power ON tpu 85 ⎯⎯ns
Power supply rising time tr0.05 ⎯200 ms
CE1 > VCC × 0.8*CE1 : Don't Care CE1 > VCC × 0.8*
tputrtpd
VCC
CE2
3.0 V
1.0 V
V
IH
(Min)
V
IL
(Max)
GND
CE1 CE1
VCC
CE2
3.0 V
1.0 V
V
IH
(Min)
V
IL
(Max)
GND
* : CE1 (Max) < VCC + 0.5 V
Notes: • Use either of CE1 or CE2, or both for disenable control of the device.
• Because turning the power-on from an intermediate level cause malfunction, when the power
is turned on, VCC is required to be started from 0 V.
• If the device does not operate within the specified conditions of read cycle, write cycle, power
on/off sequence, memory data can not be guaranteed.
• When turning the power on or off, it is recommended that CE2 is connected to GND to prevent
unexpected writing.
CE2 ≤ 0.2 V
MB85R2001
12 DS05-13107-5E
■ORDERING INFOMATION
Part number Package
MB85R2001PFTN-GE1 48-pin plastic TSOP(1)
(FPT-48P-M25)
MB85R2001
DS05-13107-5E 13
■PACKAGE DIMENSIONS
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
48-pin plastic TSOP(1) Lead pitch 0.50 mm
Package width ×
package length 12.00 × 12.40 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.20 mm MAX
Weight 0.37 g
Code
(Reference) P-TSOP(1)48-12×12.4-0.50
48-pin plastic TSOP(1)
(FPT-48P-M25)
(FPT-48P-M25)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F48043S-c-2-4
24
1 48
25
LEAD No.
12.40±0.10(.488±.004)
14.00±0.20(.551±.008)
0.08(.003) .006
–.001
+.002
–0.03
+0.05
0.145
"A"
INDEX
12.00±0.10
(.472±.004)
1.13±0.07
0.10±0.05
0.50(.020)
.009
–.002
+.002
–0.04
+0.05
0.22
M
0.10(.004)
0.25(.010) 0.60±0.15
(.024±.006)
0°~8°
Details of "A" part
(.044±.003) (Mounting height)
(Stand off)
(.004±.002)
*2
*1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB85R2001
14 DS05-13107-5E
MEMO
MB85R2001
DS05-13107-5E 15
MEMO
MB85R2001
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
