1
®
FN6274.0
ISL9209
Charging System Safety Circ uit
The ISL9209 is an integrated circuit (IC) optimized to provide
a redundant safety protection to a Li-ion battery from failures
of a charging system. The IC monitors the input voltage, the
battery voltage, and the charge current. When any of the
three parameters exceeds its limit, the IC turns off an internal
P-channel MOSFET to remove the power fro m the chargi ng
system. In addition to the above protected parameters, the
IC also monitors its own internal temperature and turns off
the P-channel MOSFET when the temperature exceeds
140°C. Together with the battery charger IC and the
protection module in a battery pack, the charging system
using the ISL9209 has triple-level protection and is two-fault
tolerant.
The IC is designed to turn on the interna l PFET slowly to
avoid inrush current at power up but will turn off the PFET
quickly when the input is overvoltage in order to remove the
power before any damage occurs. The ISL9209 has a logic
warning output to indicate the fault and an enable input to
allow the system to remove the input power.
Typical Application Circuit
Features
• Fully Integrated Protection Circuit for Three Protected
Variables
• High Accuracy Protection Thresholds
• User Programmable Over-Current Protection Threshold
• Input Over-Voltage Protection in Less Than 1μs
• High Immunity of False Triggering Under Transients
• Warning Output to Indicate the Occurrence of Faults
• Enable Input
• Easy to Use
• Thermal Enhanced TDFN Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Cell Phones
• Digital Still Cameras
• PDAs and Smart Phones
• Portable Instruments
• Desktop Chargers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mo unt Devices
(SMDs)”
• Technical Brief TB379 “Thermal Characterizatio n of
Packaged Semiconductor Devices”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
Ordering Information
PART NUMBER
(NOTE) PART
MARKING TEMP.
RANGE (°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL9209IRZ 09Z -40 to 85
12 Ld 4x3 TDFN
L12.4x3A
ISL9209IRZ-T 09Z 12 Ld 4x3 TDFN Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
INPUT ISL6292
Battery
Charger
RVB
ISL9209
C1
ILIM
RILIM WRN
VIN
GND
VB
OUT
Battery
Pack
EN
Pinout ISL9209
(4x3 TDFN)
TOP VIEW
VIN
VIN
GND
WRN
NC
NC
OUT
OUT
ILIM
VB
NC
2
3
4
1
5
11
10
9
12
8
67EN
EPAD
Data Sheet April 25, 2006
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2FN6274.0
April 25, 2006
Absolute Maximum Ratings (Reference to GND) Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30V
Output and VB Pin (OUT, VB) (Note 1) . . . . . . . . . . . . . . . -0.3 to 7V
Other Pins (ILIM, WRN, EN) . . . . . . . . . . . . . . . . . . . . . -0.3 to 5.5V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . .3500V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .350V
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Supply Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 5.5V
Operating Current Range. . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.0A
Thermal Resistance (Typical, Note 2, 3) θJA (°C/W) θJC (°C/W)
4X3 TDFN Package. . . . . . . . . . . . . . . 41 3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . .150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The maximum voltage rating for the VB pin under continuous operating conditions is 5.5V. All other pins are allowed to operate continuously at
the absolute maximum ratings.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Typical values are tested at VIN = 5V and 25°C Ambient Temperature, maximum and minimum values are
guaranteed over the recommended operating conditions, unless otherwise noted.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
POWER-ON RESET
Rising VIN Threshold VPOR 2.45 - 3.0 V
POR Hysteresis - 125 - mV
VIN Bias Current IVIN When enabled 0.75 0.9 1.05 mA
VIN Bias Current When disabled 30 60 100 μA
PROTECTIONS
Input Overvoltage Protection (OVP) VOVP 5.65 5.85 6.0 V
Input OVP Hysteresis - 50 100 mV
Input OVP Falling Threshold 5.55 - - V
Input OVP Propagation Delay --1μs
Overcurrent Protection IOCP VVB = 3V, RILIM = 25kΩ0.93 1.0 1.07 A
Overcurrent Protection Blanking Time BTOCP - 170 - μs
Battery Overvoltage Protection Threshold VBOVP 4.325 4.4 4.475 V
Battery OVP Threshold Hysteresis -75-mV
Battery OVP Falling Threshold 4.225 - - V
Battery OVP Blanking Time BTBOVP - 180 - μs
VB Pin Leakage Current VVB = 4.4V - - 20 nA
Over Temperature Protection Rising Threshold - 140 - °C
Over Temperature Protection Falling Threshold - 90 - °C
LOGIC
EN Input Logic HIGH 1.5 - - V
EN Input Logic LOW --0.4V
EN Internal Pull Down Resistor 100 200 400 kΩ
WRN Output Logic Low Sink 5mA current - 0.35 0.8 V
WRN Output Logic High Leaka ge Current - - 1 μA
POWER MOSFET
On Resistance RDS(ON) Measured at 500mA, 4.3V < VIN < 5.5V - 250 450 mΩ
ISL9209
3FN6274.0
April 25, 2006
Pin Descriptions
VIN (Pin1, 2)
The input power source. The VIN can withstand 30V input.
GND (Pin 3)
System ground reference.
WRN (Pin 4)
WRN is an open-drain logic output that turns LOW when any
protection event occurs.
NC (Pin 5, 6, 12)
No connection and must be left floating.
EN (Pin 8)
Enable input. Pull this pin to low or leave it floating to enable
the IC and force it to high to disable the IC.
VB (Pin 8)
Battery voltage monitoring input. This pin is connected to the
battery pack positive terminal via an isolation resistor.
ILIM (Pin 9)
Overcurrent protection threshold setting pin. Conn ect a
resistor between this pin and GND to set the OCP threshold.
OUT (Pin 10, 11)
Output pin.
EPAD
The exposed pad at the bottom of the TDFN package for
enhancing thermal performance. Must be electrically
connected to the GND pin.
Typical Applications
Block Diagram
INPUT ISL6292
Battery
Charger
RVB
ISL9209
C1
ILIM
RILIM WRN
VIN
GND
VB
OUT
Battery
Pack
EN
PART DESCRIPTION
RILIM 25kΩ
RVB 200kΩ to 1MΩ
C11µF/16V X5R ceramic capacitor
FIGURE 1. BLOCK DIAGRAM
POR
Pre-reg
Ref
VIN
VB
GND
1.2V
0.8V
R1
R2
Q1
INPUT
CP1
ISL6292
Battery
Charger
CP2
OUT
RILIM
ILIM
FET
Driver EA
R3
R4
RVB
CP3
Q2Q3
BUF
WRN
Q4
Logic
EN
Q5R5
ISL9209
4FN6274.0
April 25, 2006
Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted.
FIGURE 2. CAPTURED W AVEFORMS FOR POWER-UP. THE
OUTPUT IS LOADED WITH A 10Ω RESISTOR FIGURE 3. CAPTURED W AVEFORMS WHEN THE INPUT
VOLTAGE STEPS FROM 5.5V TO 9.5V
FIGURE 4. CAPTURED W AVEFORMS WHEN THE INPUT
GRADUALLY RISES TO THE INPUT
OVERVOLTAGE THRESHOLD
FIGURE 5. TRANSIENT WHEN THE INPUT VOLTAGE STEPS
FROM 6.5V TO 5.5V
FIGURE 6. TRANSIENT W AVEFORMS WHEN INPUT STEPS
FROM ZERO TO 9V FIGURE 7. BATTER Y OVERVOLT AGE PROTECTION. THE IC
IS LATCHED OFF AFTER 16 COUNTS OF
PROTECTION. VB VOLTAGE VARIES BETWEEN
4.3V TO 4.5V
VIN (1V/div)
OUT (1V/div)
Load Current
(200mA/div)
Time: 5ms/div
VIN (2V/div)
OUT (2V/div)
WRN (5V/div)
Time: 5μs/div
VIN (2V/div)
Time: 500ms/d iv
OUT (2V/div)
WRN (5V/div)
VIN (2V/div)
Time: 5ms/div
OUT (2V/div)
WRN (5V/div)
VIN (2V/div)
OUT (2V/div)
Time: 500μs/div
WRN (5V/div)
ILIM (1V/div)
VIN (1V/div)
Time: 20s/div
OUT (1V/div)
WRN (5V/div)
VB (1V/div)
ISL9209
5FN6274.0
April 25, 2006
FIGURE 8. POWER-UP W AVEFORMS WHEN OUTPUT IS
SHORT-CIRCUITED FIGURE 9. ZOOMED-IN VIEW OF FIGURE 8 (BLUE: LOAD
CURRENT; PINK: OUT PIN VOLTAGE)
FIGURE 10. INPUT BIAS CURRENT vs INPUT VOL TAGE
WHEN ENABLED AND DISABLED FIGURE 1 1. INPUT BIAS CURRENT AT DIFFERENT INPUT
VOLTAGES WHEN ENABLED AND DISABLED
FIGURE 12. VPOR vs TEMPERA TURE FIGURE 13. INPUT OVERVOL T AGE PROTECTION
THRESHOLDS vs TEMPERATURE
Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued)
VIN (1V/div)
OUT (1V/div)
Load Current
(500mA/div)
WRN (5V/div)
Time: 200ms/div VIN (1V/div)
OUT (1V/div)
Load Current
(500mA/div)
WRN (5V/div)
Time: 10ms/div
0
100
200
300
400
500
600
700
800
900
1000
0 5 10 15 20 25 30 35
INPUT VOLTAGE (V)
INPUT BIAS CURRENT (µA)
ENABLED
DISABLED
0
100
200
300
400
500
600
700
800
900
1000
-50 -20 10 40 70 100 130
TEMPERATURE (°C)
CURRENT (µA)
5V/ENABLED 4.3V/ENABLED
30V/ENABLED
30V/DISABLED
4.3V/DISABLED
5V/DISABLED
2.62
2.64
2.66
2.68
2.7
2.72
2.74
2.76
2.78
2.8
2.82
-50 -20 10 40 70 100 130
VPOR (V)
RISING THRESHOLD
FALLING THRESHOLD
TEMPERATURE (°C)
5.72
5.74
5.76
5.78
5.8
5.82
5.84
5.86
-50 -20 10 40 70 100 130
VOVP (V)
TEMPERATURE (°C)
RISING THRESHOLD
FALLING THRESHOLD
ISL9209
6FN6274.0
April 25, 2006
FIGURE 14. OVERCURRENT PROTECTION THRESHOLDS vs
TEMPERATURE AT VARIOUS INPUT VOLTAGES FIGURE 15. OVERCURRENT PROTECTION BLANKING TIME
vs TEMPERATURE
FIGURE 16. OVERCURRENT PROTECTION THRESHOLDS vs
TEMPERATURE AT VARIOUS INPUT VOLTAGES FIGURE 17. BATTER Y VOLT AG E OVP THRESHOLDS vs
TEMPERATURE AT VARIOUS INPUT VOLTAGES
FIGURE 18. BATTERY OVP BLANKING TIME FIGURE 19. VB PIN LEAKAGE CURRENT vs TEMPERATURE
Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued)
970
980
990
1000
1010
1020
1030
1040
-50 -20 10 40 70 100 130
TEMPERATURE (°C)
IOCP (mA)
3V
5V
4.3V
5.5V
CURRENT
LIMIT = 1A
150
155
160
165
170
175
180
185
190
195
200
-50 -20 10 40 70 100 130
BTOCP (µs)
TEMPERATURE (°C)
475
480
485
490
495
500
505
510
515
520
-50 -20 10 40 70 100 130
TEMPERATURE (°C)
IOCP (mA)
4.3V
3V
5V
5.5V
CURRENT
LIMIT = 0.5A
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.4
4.41
4.42
-50 -20 10 40 70 100 130
VBOVP (V)
RISING THRESHOLDS FOR
4.5V, 5V AND 5.5V INPUT
FALLING THRESHOLDS FOR
4.5V, 5V AND 5.5V INPUT
TEMPERATURE (°C)
150
155
160
165
170
175
180
185
190
195
200
-50 -20 10 40 70 100 130
BTBOVP (µs)
TEMPERATURE (°C)
0
0.5
1
1.5
2
2.5
3
-50 -20 10 40 70 100 130
TEMPERATURE (°C)
VB PIN LEAKAGE CURRENT (nA)
TESTED AT 5V
ISL9209
7FN6274.0
April 25, 2006
Theory of Operation
The ISL9209 is an integrated circuit (IC) optimized to provide
a redundant safety protection to a Li-ion battery from
charging system failures. The IC monitors the input voltage,
the battery voltage, and the charge current. When any of the
above three parameters exceeds its limit, the IC turns off an
internal P-channel MOSFET to remove the power from the
charging system. In addition to the above protected
parameters, the IC also monitors its own internal
temperature and turns off the P-channel MOSFET when the
temperature exceeds 140°C. Together with the battery
charger IC and the protection module in a battery pack, the
charging system has triple-level protection from
overcharging the Li-ion battery and is two-fault tolerant. The
ISL9209 protects up to 30V input voltage.
Power-Up
The ISL9209 has a power-on reset (POR) threshold of 2.6V
with a built-in hysteresis of 125mV. Before the input voltage
reaches the POR threshold, the internal power PFET is off.
Approximately 10ms after the input voltage exceeds the
POR threshold, the IC resets itself and begins the soft-start.
The 10ms delay allows any transients at the input during a
hot insertion of the power supply to settle down before the IC
starts to operate. The soft-start slowly turns on the power
PFET to reduce the inrush current as well as the input
voltage drop during the transition. The power-up behavior is
illustrated in Figure 2.
Input Overvoltage Protection (OVP)
The input voltage is monitored by the comparator CP1 in the
Block Diagram (Figure 1). CP1 has an accurate reference of
1.2V from the bandgap reference. The OVP threshold is set
by the resistive divider consisting of R1 and R2. The
FIGURE 20. EN INPUT THRESHOLD vs TEMPERATURE FIGURE 21. EN PIN INTERNAL PULL-DOWN RESISTANCE
FIGURE 22. ON RESISTANCE vs TEMPERATURE AT DIFFERENT INPUT VOLTAGES
Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = 25°C,
RILIM = 25.5kΩ, RVB = 200kΩ, Unless Otherwise Noted. (Continued)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-50 -20 10 40 70 100 130
EN THRESHOLD (V)
TEMPERATURE (°C)
150
160
170
180
190
200
210
220
230
240
250
-50 -20 10 40 70 100 130
EN PIN INTERNAL PULL-DOWN (kΩ)
TEMPERATURE (°C)
0
0.1
0.2
0.3
0.4
0.5
-50 -20 10 40 70 100 130
TEMPERATURE (°C)
3V 4.3V
5V
5.5V
RDS(ON) (Ω)
ISL9209
8FN6274.0
April 25, 2006
protection threshold is set to 5.85V. When the input voltage
exceeds the threshold, the CP1 outputs a logic signal to turn
off the power PFET within 1µs (see Figure 3) to prevent the
high input voltage from damaging the electronics in the
handheld system. The hysteresis for the input OVP
threshold is given in the Electrical Specification. When the
input overvoltage condition is removed, the ISL9209
re-enables the output by running through th e soft-start, as
shown in Figure 5. Because of the 10ms second delay
before the soft-start, the output is never enabled if the input
rises above the OVP threshold quickly, as shown in Figure 6.
Battery Overvolta ge Protection
The battery voltage OVP is realized with the VB pin. The
comparator CP3, as shown in Figure 1, monitors the VB pin
and issues an overvoltage signal when the battery voltage
exceeds the 4.4V battery OVP threshold. The threshold has
75mV built-in hysteresis. The comparator CP3 has a built-in
180µs blanking time to prevent any transient voltage from
triggering the OVP. If the OVP situation still exists after the
blanking time, the power PFET is turned off. The control
logic contains a 4-bit binary counter that if the battery
overvoltage event occurs 16 times, the power PFET is
turned off permanently, as shown in Figure 7. Recycling the
input power or toggling the enable (EN) input will reset the
counter and restart the ISL9209.
The resistor between the VB pin and the battery, RVB, as
shown in the Typical Applications circuit, is an important
component. This resistor provides a current limit in case the
VB pin is shorted to the input voltage under a failure mode.
The VB pin leakage current under norma l operation is
negligible to allow a resistance of 200kΩ to 1MΩ be used.
Overcurrent Protection (OCP)
The current in the power PFET is limited to prevent charging
the battery with an excessive current. The current is sensed
using the voltage drop across the power FET after the FET is
turned on. The reference of the OCP is gene rated using a
sensing FET Q2, as shown in Figure 1. The current in the
sensing FET is forced to the value programmed by the ILIM
pin. The size of the power FET Q1 is 31,250 times the size
of the sensing FET. Therefore, when the current in the power
FET is 31,250 times the current in the sensing FET, the drain
voltage of the power FET falls below that of the sensing FET.
The comparator CP2 then outputs a signal to turn off the
power FET.
The OCP threshold can be calculated using the following
equation:
where the 0.8V is the regulated voltage at the ILIM pin. The
OCP comparator CP2 has a built-in 170µs delay to prevent
false triggering by transient signals. The OCP function also
has a 4-bit binary counter that accumulates during an OCP
event. When the total count reaches 16, the power PFET is
turned off permanently unless the input power is recycled or
the enable pin is toggled. Figure 8 and Figure 9 illustrate the
waveforms during the power-up when the output is
short-circuited to ground.
Internal Over Temperature Protection
The ISL9209 monitors its own internal temperature to
prevent thermal failures. When the internal temperature
reaches 140°C, the IC turns off the P-channel power
MOSFET. The IC does not resume operation until the
internal temperature drops below 90°C.
External Enable Control
The ISL9209 offers an enable (EN) input. When the EN pin
is pulled to logic HIGH, the protection IC is shut down. The
internal control circuit as well as the power PFET are turned
off. Both 4-bit binary counters for the battery OVP and the
OCP are reset to zero when the IC is re-enabled. The EN pin
has an internal 200kΩ pull-down resistor . Leaving the EN pin
floating or driving it to below 0.4V enables the IC.
Warning Indicat io n Out pu t
The WRN pin is an open-drain output that ind icates a LOW
signal when any of the three protection events happens. This
allows the microprocessor to give an indication to the user to
further enhance the safety of the chargin g system.
Applications Information
The ISL9209 is designed to meet the “Lithium-Safe” criteria
when operating together with the ISL6292 family Li-ion
battery chargers. The “Lithium-Safe” criteria requires the
charger output to fall within the green region shown in
Figure 23 under normal operating conditions and NOT to fall
in the red region when there is a single fault in the charging
system. Taking into account the safety circuit in a Li-ion
battery pack, the charging system is allowed to have two
faults without creating hazardous conditions for the battery
cell. The output of any ISL6292 family chargers, such as the
ISL6292C, has a typical I-V curve shown with the blue lines
under normal operation, which is within the green region.
The function of the ISL9209 is to add a redundant protection
layer such that, under any single fault condition, the charging
system output does not exceed the I-V limits shown with the
red lines. As a result, the charging system adopting the
ISL9209 and the ISL6292C chip set can easily pass the
“Lithium-Safe” criteria test procedures.
The ISL9209 is a simple device that requires only three
external components, in addition to the ISL6292 charger
circuit, to meet the “Lithium-Safe” criteria, as shown in the
Typical Application Circuit. The selection of the current limit
resistor RILIM is given in the Overcurrent Protection section.
ILIM 0.8V
RILIM
--------------- 31250 25000
RILIM
----------------
=⋅=
ISL9209
9FN6274.0
April 25, 2006
RVB Selection
The RVB prevents a large current from the VB pin to the
battery terminal, in case the ISL9209 fails. The
recommended value should be between 200kΩ to 1MΩ.
With 200kΩ resistance, the worst case current flowing from
the VB pin to the charger output is,
(30V - 4.2V)/200kΩ = 130μA,
assuming the VB pin voltage is 30V under a failure mode
and the battery voltage is 4.2V. Such a small current can be
easily absorbed by the bias current of other components in
the handheld system. Increasing the RVB value reduce s the
worst case current, but at the same time increases the error
for the 4.4V battery OVP threshold.
The error of the battery OVP threshold is the original
accuracy at the VB pin given in the Electrical Specifica tio ns
plus the voltage built across the RVB by the VB pin leakage
current. The VB pin leakage current is less than 20nA, as
given in the Electrical Specification. With the 200kΩ resistor ,
the worst-case additional error is 4mV and with a 1MΩ
resistor, the worst-case addi tional error is 20mV.
Interfacin g to MCU
The ISL9209 has the enable (EN) and the warning (WRN)
digital signals that can be interfaced to a microcontroller unit
(MCU). Both signals can be left floating if not used. When
interfacing to an MCU, it is highly recommended to insert a
resistor between the ISL9209 signal pin and the MCU GPIO
pin, as shown in Figure 24. The resistor creates an isolation
to limit the current, in case a high voltage shows up at the
ISL9209 pins under a failure mode. The recommended
resistance ranges from 10kΩ to 100kΩ. The selection of the
REN is dependent on the IO voltage (VIO) of the MCU. REN
should be selected so that the ISL9209 EN pi n voltage is
above the disable threshold when the GPIO output of the
MCU is high.
Capacitor Selection
The input capacitor (C1 in the Typical Application Circuit) is
for decoupling. Higher value reduces the voltage drop or the
over shoot during transien ts.
Two scenarios can cause the input voltage over shoot. The
first one is when the AC adapter is inserted live (hot
insertion) and the second one is when the curre nt in the
power PFET of the ISL9209 has a step-down change.
Figure 25 shows an equivalent circuit for the ISL9209 input.
The cable between the AC/DC converter output and the
handheld system input has a parasitic inductor . The parasitic
resistor is the lumped sum of various components, such as
the cable, the adapter output capacitor ESR, the connector
contact resistance, and so on.
During the load current step-down transient, the energy
stored in the parasitic inductor is used to charge the input
decoupling capacitor C2. The ISL9209 is designed to turn off
the power PFET slowly during the OCP, the battery OVP
event, and when the device is disabled via the EN pin.
Because of such design, the input over shoo t during those
events is not significant. During an input OVP, however, the
PFET is turned in less than 1µs and can lead to significant
over shoot. Higher capacitance reduces this type of over
shoot.
FIGURE 23. LITHIUM-SAFE OPERATING REGIONS
50
1000
BATTERY VOLTAGE (V)
CHARGE CURRENT (mA)
1234
ISL9209
LIMITS
ISL6292C
LIMITS
6
FIGURE 24. DIGITAL SIGNAL INTERFACE BETWEEN ISL9209
AND MCU
WRN
R5
Q4
Q5
EN
ISL9209 MCU
RPU
RWRN
REN
VIO
FIGURE 25. EQUIVALENT CIRCUIT FOR TH E ISL9209 INPUT
AC/DC ISL9209
ADAPTER CABLE HANDHELD SYSTEM
C1 L R C2
ISL9209
10 FN6274.0
April 25, 2006
The over shoot caused by a hot insertio n is not very
dependent on the decoupling capacitance value. Especially
when ceramic type capacitors are used for de co u pli n g. In
theory, the over shoot can rise up to twice of the DC output
voltage of the AC adapter. The actual peak voltage is
dependent on the damping factor that is mainly determine d
by the parasitic resistance (R in Figure 25).
In practice, the input decoupling capacitor is recommended
to use a 16V X5R dielectric ceramic capacitor with a value
between 0.1µF to 1µF.
The output of the ISL9209 and the input of the charging
circuit typically share one decoupling capacitor. The
selection of that capacitor is mainly determined by the
requirement of the charging circuit. When using the ISL6292
family chargers, a 1µF, 6.3V, X5R capacitor is
recommended.
Layout Recommendation
The ISL9209 uses a thermally enhanced DFN package. The
exposed pad under the package should be connected to the
ground plane electrically as well as thermally. A grid of
1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5
vias per row is recommended (refer to the ISL9200EVAL1
evaluation board layout). The vias should be about 0.3mm to
0.33mm in diameter. Use some copper on the component
layer if possible to further improve the thermal performanc e
but it is not mandatory.
Since the ISL9209 is a protection device, the layout sho uld
also pay attention to the spacing between tracks. When the
distance between the edges of two tracks is less than
0.76mm, an FMEA (failure mechanism an d effect analysis)
should be performed to ensure that a short between those
two tracks does not lead to the charger output exceeding the
“Lithium-Safe” region limits. Intersil will have the FMEA
document for the solution using the ISL9209 and the
ISL6292C chip set but the layout FMEA should be added as
part of the analysis.
ISL9209
11
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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FN6274.0
April 25, 2006
ISL9209
Thin Dual Flat No-Lead Plastic Package (TDFN)
C
//
L
C
e
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
NX (b)
SECTION "C-C"
5
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BA
MC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
L
L12.4x3A
12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.70 0.75 0.80 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.23 0.30 5,8
D 4.00 BSC -
D2 3.15 3.30 3.40 7,8
E 3.00 BSC -
E2 1.55 1.70 1.80 7,8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N122
Nd 6 3
Rev. 0 1/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
