Nt AR | | LTC1064-1 TECHNOLOGY FEATURES mw 8th Order Filter in a 14-Pin Package = No External Components w 100:1 Clock to Center Ratio w 150uVpms Total Wideband Noise a 0.03% THD or Better w 50kHz Maximum Corner Frequency w Operates from +2.37V to +8V Power Supplies ws Passband Ripple Guaranteed Over Full Military Temperature Range APPLICATIONS = Antialiasing Filters w Telecom PCM Filters Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter DESCRIPTION The LTC1064-1 is an 8th order, clock sweepable elliptic (Cauer) lowpass switched capacitor filter. The passband ripple is typically + 0.15dB, and the stopband attenuation at 1.5 times the cutoff frequency is 68dB or more. An external TTL or CMOS clock programs the value of the filter's cutoff frequency. The clock to cutoff frequency ra- tio is 100:1. No external components are needed for cutoff frequen- cies up to 20kHz. For cutoff frequencies over 20kHz two low value capacitors are required to maintain passband flatness. The LTC1064-1 features low wideband noise and low harmonic distortion even for input voltages up to 3Veams. In fact the LTC1064-1 overall performance com- petes with equivalent multi op amp RC active realizations. The LTC1064-1 is available in a 14-pin DIP or 16-pin surface mounted SOL package. The LTC 1064-1 is pin compatible with the LTC 1064-2. TYPICAL APPLICATION 8th Order Clock Sweepable Lowpass Elliptic Antialiasing Filter ip 14 Rib.) Vw= COMP2* ANALOG _av Gno | v= pom CLOCK (TTL, ANALOG ss5MHz) GND = comP1* 4 INV Ay Po Vout NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0. 1pF CAPACITOR CLOSE TO THE PACKAGE. FOR SERVO OFFSET NULLING APPLICATIONS, PIN 1 1S THE 2ND STAGE SUMMING JUNCTION. FOR CUTOFF FREQUENCY ABOVE 20kHz, USE COMPENSATION CAPACITORS (5pF-56pF) BETWEEN PINS 13 AND 1 ANO 6 AND 7. Frequency Response Vour/Vin L & ao 0 65 10 15 20 2 30 35 40 FREQUENCY (kHz) 8TH ORDER CLOCK SWEEPABLE LOWPASS ELLIPTIC ANTIALIASING FILTER MAINTAINS, FOR 0.1Hz 350 z -45 S @ 300 60 2 S 250 Vg= +5V = & 200 _75 --Ta=25C 150. fork = 1MHz 99 | fc= 10kKHz + 0.108 f _agp = 10.7kHz ~ 105 1 10 100 01 23 4 5 6 7 8 9 10 11 100 50 0 0 123 4 56 7 8 10 11 12 FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) Lee 7.91LTC1064-1 Graph 4. Gain vs Frequency Graph 5. Gain vs Frequency Graph 6. Gain vs Frequency ! A : Mill: Mil nN -15 \ 15 \ ~5 Vg= 7.5V 30 -1S= 254 30 |-YS= 37 0V 10 fei =5MHz HH ry am s Ae S f=50kHz S45 2 _ 45 _145 |. COMP1 =339F 2 B z Ny = COMP2 =56pF oS i oS A S 1 oid - 60 20 = 80 a Teue= 2MH? fo = 20kH2 J 80 Terk =3MHz f=30kKHz I x oO Can PEAK 1 one AT sbkiia _75 |. COMP1 NOT USED COMP2 = 20F han) ay N _75 L_ COMPI = t0pF COMP2 = 15pF N 95 rn B.f. x =3MHz f=30kHz LPN B. folk =4MHz fp =40kHz COMP1 = 24pF COMP2 = 36pF COMP1.=20pF COMP2 =30pF 40 A ~90 Fe for, =4MHz fe =40kHz ~90 FC. for, =5MHz te =50kHz B COMP1 =36pF COMP? =47pF COMP1 =30pF COMP2 = 47pF | 105 4 revue 4 ~105 1 ae Greer. i -35 { 10 100 1 1 10 100 FREQUENCY (kHz) 10 100 FREQUENCY (kHz) : FREQUENCY (kHz) Graph 8. Total Harmonic Distortion (0.025%) Vs = +7.5V Ta = 25C fo = 1MHz fc = 10kHz Input = 1kHz at 3Vams Graph 7. Typical Wideband Noise (151p:Vams) Vs= +5V Ta =25C feik = 1MHz fo = 10kHz Input Grounded CLAS eee) Le La aS tn) Wa PLreet Bear ra Fs Lee eked PIN DESCRIPTION Power Supply Pins (4, 12) The V+ (pin 4) and V (pin 12} should be bypassed with a 0.1F capacitor to an adequate analog ground. Low noise, non-switching power supplies are recommended. To avoid latch up when the power supplies exhibit high turn-on transients, a 1N5817 schottky diode should be added from the V+ and V~ pins to ground, Figure 1. Clock Pin (11) For +5V supplies the logic threshold level is 1.4V. For + 8V and OV to 5V supplies the logic threshold levels are Graph 9. Power Supply Current vs Power Supply Voltage 44 }totk = 1MHz POWER SUPPLY CURRENT (mA) _ 0 2 4 6 8 10 12 14 16 18 20 22 24 TOTAL POWER SUPPLY VOLTAGE (V) 2.2V and 3V respectively. The logic threshold levels vary +100mV over the full military temperature range. The recommended duty cycle of the input clock is 50% al- though for clock frequencies below 500kHz the clock on time can be as low as 200ns. The maximum clock fre- quency for +5V supplies is 4MHz. For +7V supplies and above, the maximum clock frequency is 5MHz. Do not al- low the clock levels to exceed the power supplies. For clock level shifting, see Figure 3. Analog Ground Pins (3, 5) For dual supply operation these pins should be connected to a ground plane. For single supply operation both pins 1-92 owerLTC1064-1 a PIN DESCRIPTION should be tied to one half supply, Figure 2. Also pins 8 and 10, although they are not internally connected should be tied to analog ground or system ground. This improves the clock feedthrough performance. Connection Pins (7, 14) A very short connection between pins 14 and 7 is recom- mended. This connection should be preferably done under the IC package. In a breadboard, use a one inch, or less, shielded coaxial cable; the shield should be grounded. Ina PC board, use a one inch trace or less; surround the trace by a ground plane. Compensation Pins (13 and 1, 6 and 7) For filter cutoff frequencies higher than 20kHz, in order to minimize the passband ripple, compensation capacitors should be added between pins 6 and 7 (comp1) and pins 1 and 13 (comp2). For comp1 (comp2), add ipF (1.5pF) mica 14 13 12 1 10 edg 18 Fos v- 1N5817 Vin yr 1N5817 fork T sm fo ie fo fr [= Vout Figure 1. Using Schottky Diodes to Protect the IC capacitor for each kHz increase in cutoff frequency above 20kHz. For more details refer to graphs 4, 5, and 6. Input, Output Pins (2, 9) The input pin 2 is connected to an 18k resistor tied to the inverting input of an op amp. Pin 2 is protected against static discharge. The devices output, pin 9, is the output of an op amp which can typicatly source/sink 3/1mA. Al- though the internal op amps are unity gain stable, driving long coax cables is not recommended. When testing the device for noise and distortion, the out- put, pin 9, should be buffered, Figure 4. The op amp power supply wire (or trace) should be connected directly to the power source. NC Pins (8, 9) The no connection pins preferably should be grounded. Figure 2. Single Supply Operation. if Fast Power Up or Down Transients are Expected, Use a 1N5817 Schottky Diode Between Pins 4 and 5. from Power Supply Spikes. ip A +a 5k LL 0.1 pF 5k tI v + $e ' ] TAL | LEVEL k Figure 3. Level Shifting the Input TL Clock for Single Supply Operation, V+ >6V LI TUR 7-93LTC1064-1 PIN DESCRIPTION POWER SOURCE V+ V~- RECOMMENDED OP AMPS: (71022, LT318, LT1056 = Figure 4. Buffering the Filter Output. The Buffer Op Amp Should Not Share the LTC 1064-1 Power Lines. TYPICAL APPLICATIONS Transitional Elliptic-Bessel 10th Order Lowpass Filter c 0. Vout yv- foik=250 xf _3ap 3 et= _ (uF) Vin OUTPUT WIDEBAND NOISE: 110,Vaus Transient Response to a 2V Step Input Amplitude Response Horizontal: 0.1ms/Div Vertical: 1V/Div 1 10 100 fiw (kHz) 7-94 LI leeLTC1064-1 TYPICAL APPLICATIONS Transitional Elliptic-Bessel Dual Sth Order Lowpass Filter C Vw Voutt v- v+ toi = 200 xt 308 0.1 "TF Vourte 5 47.5k , eC tap (pF) QUTPUT1 WIDEBAND NOISE: 50xV pus Ving OUTPUT2 WIDEBAND NOISE: 110V ams Transient Reponse to a 2V Step Input Horizontal: 0.ims/Div Vertical: 1V/Div woe Amplitude Response 10 100 fin (KHz) Adding an Output Buffer-Filter to Eliminate Any Clock Feedthrough Over a 10:1 Clock Range, for f = 2kHz to 20kHz LY Wee 7-95LTC1064-1 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. _ J Package 14-Lead Ceramic DIP 0.785 0.005 ara (0.13) 9.025 IN (6.635), fa] [13] fre} fi} fro] [9] fa RAD TYP ) 0.220 0.310 15.588 7.674) 0.2900,320 = 0.200 van ae (HOO a a a MAX 2.490) MAX 0.015 - 0.080 Hy (0.381 1.524) o-15 i ] 0.008-0.0:8 } (0203 0.460) 0.385 0.025 0.014-0.026 010020010 15.779 0.635) (0.36 0.66) + Soh an 0.038 0.068 - 19.965 1.727) MIN 0.300 -0.320 (7.620 8. 128) 0.0090.015 (0.229 -0.381) +0.025 ~0.015 +0835) 0.381 0.325 6.255 NOTE: N Package 14-Lead Plastic DIP 0.770 414388 (19.558) RAPA 0,250 +0.010 (6.350 2.0.254) D Ly Ly Gy Let Ls] 0.125 (0.508) (3.175) 0.130. 0.005 (3.302 0,127) Package 16-Lead Plastic SOL a | 0.045 ~0.065 (1143-1657) N14108 PIN 1 IDENT. NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGE ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. ms SEE NOTE - 0.398 0.413 (10.109 10.490} 16 15 14 13 12 11:10 9 PHAR HAAA 0.394-0.419 (10.007 10.643) is GOOOgodUU t 0.291 0.299 1234567 8 = oar=P a} Mee 2682) 0.037 -0.045 0.010-0.029 42, (0.2540.737) {0.940 1.143) 0 -B TYP fy Linon ova | 0.004 0.012 {0.102 -0.305) 0.0090.013 (0229-0330) SEE NOTE 0.016 -0.050 0.014-0.019 (0.406 1.270) (0.356 - 0.482) simwues 7-96 Owe