MAX5168MCCM+T - Maxim Integrated Products, Inc.

General Description

The MAX5168 contains 32 sample/hold amplifiers and

four 1-of-8 multiplexers. The logic controlling the muxes

and sample/hold amplifiers combines the four muxes into

a unified 1-of-32 multiplexer with a sample/hold at each

output. Additional logic allows two devices to function as

a single 64-channel unit. The MAX5168 is available with

an output impedance of 50Ω, 500Ω, or 1kΩ.

The MAX5168 operates with +10V and -5V supplies, and

a separate +5V digital logic supply. Manufactured with a

proprietary BiCMOS process, it provides high accuracy,

fast acquisition time, a low droop rate, and a low hold

step. The MAX5168 has a typical linearity error of less

than 0.01% and can accurately acquire 8V step input sig-

nals to 0.01% accuracy in 2.5µs within the +7V to -4V

input signal range. Transitions from sample mode to hold

mode result in only a 0.5mV error. While in hold mode, the

output voltage slowly droops at a rate of 1mV/s.

The MAX5168 is available in a 48-pin TQFP package and

is specified for both the commercial (0°C to +70°C) and

extended industrial (-40°C to +85°C) temperature ranges.

________________________Applications

Automatic Test Systems (ATE)

Industrial Process Controls

Arbitrary Function Generators

Avionics Equipment

Features

♦32-Channel Sample/Hold

♦0.01% Accuracy of Acquired Signal

♦0.01% Linearity Error

♦Fast Acquisition Time: 2.5µs

♦Low Droop Rate: 1mV/s

♦Low Hold Step: 0.25mV

♦Wide Output Voltage Range: +7V to -4V

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

________________________________________________________________ Maxim Integrated Products 1

OUT21

OUT20

OUT19

OUT18

OUT17

OUT16

VDD

OUT15

OUT14

OUT13

OUT12

OUT11

ADDR2

ADDR3

ADDR4

SELECT

S/H

CONFIG

DGND

VSS

AGND

N.C.

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

ADDR1

ADDR0

OUT31

OUT30

OUT29

OUT28

OUT27

OUT26

OUT25

OUT24

OUT23

OUT22

TQFP

MAX5168

TOP VIEW

Pin Configuration

19-1674; Rev 0; 4/00

Ordering Information

48 TQFP

PIN-

PACKAGE

TEMP. RANGE

0°C to +70°CMAX5168LCCM

PART

48 TQFP0°C to +70°CMAX5168MCCM

48 TQFP0°C to +70°CMAX5168NCCM

48 TQFP-40°C to +85°CMAX5168LECM

48 TQFP-40°C to +85°CMAX5168MECM

48 TQFP-40°C to +85°CMAX5168NECM

ROUT

(Ω)

500

For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

IN = AGND, TA=

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +10.0V, VSS = -5.0V, VL= +5.0V ±5%, AGND = DGND = 0, RL= 5kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to AGND.......................................................-0.3V to +11.0V

VSS to AGND .........................................................-6.0V to +0.3V

VDD to VSS ......................................................................+15.75V

VLto DGND ...........................................................-0.3V to +6.0V

VLto AGND ...........................................................-0.3V to +6.0V

DGND to AGND.....................................................-0.3V to +2.0V

IN, OUT_ .....................................................................VSS to VDD

Logic Inputs to DGND ...........................................-0.3V to +6.0V

Maximum Current into OUT_ ............................................±10mA

Maximum Current into Logic Inputs .................................±20mA

Continuous Power Dissipation (TA= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C)......1000mW

Operating Temperature Ranges

MAX5168_CCM ................................................0°C to +70°C

MAX5168_ECM..............................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Figure 2 (Note 1)

IN = AGND

To ±1mV of final value, Figure 2 (Note 1)

-4.0V < VIN < +7V, RL= ∞

TA= +25°C,

RL= ∞, Figure 2

RL= ∞,

CL= 250pF

(Note 1)

VIN = 0, sample mode

8V step with 500ns

rising edge (Note 1)

MAX5168N

+15°C ≤TA≤+65°C (Note 1)

8V step to 0.08%

RL= ∞

100mV step to ±1mV

CONDITIONS

200

tAP

Aperture Delay

µs

Hold-Mode Settling Time

1µs

2.5 4

tAQ

Acquisition Time

VSS VDD

VCH

Output Clamp High

ISINK

Output Sink Current

ISOURCE

Output Source Current

700 1000 1300

350 500 650

ROUT_

0.25 1.00

VHS

Hold Step

0.01 0.08

Linearity Error

Ω

35 50 65

DC Output Impedance

10 20

CIN

Input Capacitance

MAX5168M

-72 -76

MAX5168L

-72 -76

Analog Crosstalk

mV/s

140

Droop Rate

-30 -5 +30

VOS

Offset Voltage µV/°C

20 40

CL= 250pF for

MAX5168L

CL= 10nF for

MAX5168M/N

VSS +V

DD -

0.75 2.4

VOUT_

Output Voltage Range

UNITSMIN TYP MAXSYMBOLPARAMETER

IN = AGND, TA= +25°C

ANALOG SECTION

TIMING PERFORMANCE

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +10.0V, VSS = -5.0V, VL= +5.0V ±5%, AGND = DGND = 0, RL= 5kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at TA= +25°C.)

Note 1: Guaranteed by design.

Note 2: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).

Figure 2 (Note 1)

CONDITIONS

tSET

Data Setup Time

200

tPW

S/H Pulse Width

ADDR_ = 0.8V or 2.0V,

S/H = 0.8V or 2.0V mA

UNITSMIN TYP MAXSYMBOLPARAMETER

RL= ∞

(Note 2)

IN = DGND or VCC

Figure 2 (Note 1)

ISS

Negative Analog Supply Current

IDD

Positive Analog Supply Current

4.75 5 5.25

Digital Logic Supply

-4.75 -5 -5.45

VSS

Negative Analog Supply

9.5 10 10.5

VDD

Positive Analog Supply

µA

-1 +1

Input Current

0.8

VIL

Input Voltage Low

2.0

VIH

Input Voltage High

150

tDH

Data Hold Time

For VDD and VSS, sample mode,

IN = AGND

ADDR_ = DGND or VL,

S/H = DGND or VL

-60 -75

PSRRPower-Supply Rejection Ratio

0.5

Digital Logic Supply Current

POWER SUPPLIES

DIGITAL INPUTS

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

4 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD = +10V, VSS = -5V, VL= +5V, VIN = +5V, RL= ∞, CL= 0, AGND = DGND = 0, VCH = VDD, VCL = VSS, TA= +25°C, unless

otherwise noted.)

0.4

0.2

1.0

0.8

0.6

1.2

1.4

1.8

1.6

2.0

-4 -2 -1-3 01234567

DROOP RATE vs. INPUT VOLTAGE

MAX5168 TOC 01

INPUT VOLTAGE (V)

DROOP RATE (mV/s)

-40 10-15 35 60 85

DROOP RATE vs. TEMPERATURE

MAX5168 TOC 02

TEMPERATURE (°C)

DROOP RATE (mV/s)

-40

-20

-80

-60

-100

-120

0.1 101 100 1000 10,000

POWER-SUPPLY REJECTION RATIO

SAMPLE MODE

MAX5168 TOC 03

FREQUENCY (kHz)

PSRR (dB)

NEGATIVE SUPPLY (VSS)

POSITIVE SUPPLY (VDD)

-40

-20

-80

-60

-100

-120

0.1 101 100 1000 10,000

POWER-SUPPLY REJECTION RATIO

HOLD MODE

MAX5168 TOC 04

FREQUENCY (kHz)

PSRR (dB)

NEGATIVE SUPPLY (VSS)

POSITIVE SUPPLY (VDD)

-20

-140

-60

-40

-80

-100

-120

-160

-4 -2 -1 0-3 1 2 54637

HOLD STEP vs. INPUT VOLTAGE

MAX5168 TOC 05

INPUT VOLTAGE (V)

HOLD STEP (µV)

100

115

110

105

120

-55 -15-35 5 25 45 65 85

HOLD STEP vs. TEMPERATURE

MAX5168 TOC 06

TEMPERATURE (°C)

HOLD STEP (µV)

-5.0

-4.6

-4.8

-4.0

-4.2

-4.4

-3.8

-3.6

-3.2

-3.4

-3.0

-4 -2 -1-3 01234567

OFFSET VOLTAGE vs. INPUT VOLTAGE

MAX5168 TOC 07

INPUT VOLTAGE (V)

OFFSET VOLTAGE (mV)

-7

-5

-6

-3

-4

-1

-2

-40 10-15 356085

OFFSET VOLTAGE vs. TEMPERATURE

MAX5168 TOC 08

TEMPERATURE (°C)

OFFSET VOLTAGE (mV)

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

_______________________________________________________________________________________ 5

NAME FUNCTION

1ADDR2 Bit 2 of the Address Decoder

2ADDR3 Bit 3 of the Address Decoder

3ADDR4 Bit 4 of the Address Decoder

4SELECT

Enables the S/H pin. The polarity of SELECT is determined by the state of the CONFIG pin. If CONFIG

is low, then SELECT is active-high. If CONFIG is high, then SELECT is active-low. When SELECT is not

in its active state, all 32 channels are in hold mode independent of the S/H pin.

8DGND Digital GND

7 VL+5V Logic Supply

6CONFIG Sets the polarity of the SELECT pin.

5S/H Puts the selected channel into sample mode when low. Places all channels into hold mode when high.

12, 13 N.C. No connection. Not internally connected.

11 IN Input Pin

10 AGND Analog GND

9 VSS -5V Analog Supply

Pin Description

47 ADDR0 Bit 0 of the Address Decoder

31–46 OUT16–OUT31 Outputs 16–31 Pins

30 VDD +10V Analog Supply

14–29 OUT0–OUT15 Outputs 0–15 Pins

48 ADDR1 Bit 1 of the Address Decoder

MAX5168

Detailed Description

Digital Interface

The MAX5168 has three logic control inputs and five

address lines. The address lines are inputs to a demul-

tiplexer that selects one of the 32 outputs in a standard

addressing scheme (Table 1). The analog input is con-

nected to the addressed sample/hold when directed by

the control logic (Table 2).

The three logic control lines determine the state of the

addressed sample/hold. The normal circuit connection

for this device is to hardwire CONFIG and SELECT to

opposing logic voltages. When SELECT and CONFIG

are in opposite states (one high and the other low), the

five address lines select one of the sample/holds. Use

the S/H line to place the selected channel into sample

or hold mode. The other 31 channels will remain in hold

mode.

If an active-high sampling mode is desired, tie S/H and

CONFIG low. In this case, SELECT controls the

addressed channel with a high state putting that chan-

nel into sample mode.

The SELECT and CONFIG pins allow the design of a

virtual 64-channel device using two of the MAX5168s.

See the Applications Information section for more infor-

mation about 64-plus output addressing schemes.

Sample/Hold

The MAX5168 contains 32 buffered sample/hold circuits

with internal hold capacitors. Internal hold capacitors

minimize leakage current, dielectric absorption,

feedthrough, and required board space. The value of

the hold capacitor affects acquisition time and droop

rate. Smaller capacitance allows faster acquisition

times but increases the droop rate. Larger values

increase hold acquisition time. The hold capacitor used

in the MAX5168 provides fast 2.5µs (typ) acquisition

time while maintaining a relatively low 1mV/s (typ)

droop rate, making the sample/hold ideal for high-

speed sampling.

Sample Mode

When SELECT and CONFIG are in opposing logic states,

the S/H line controls the mode of operation. Sample mode

is entered when S/H is low. During sample mode, the

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

6 _______________________________________________________________________________________

MAX5168

SW1

SW2 SW30 SW31

ADDR0–ADDR4

S/H

SELECT

CONFIG

OUT0

OUT1

OUT30

OUT31

Figure 1. Functional Diagram

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

_______________________________________________________________________________________ 7

Table 1. Channel/Output Selection

Table 2. Logic Table for CONFIG, SELECT, and S/H

SELECT

Sampling10

Sampling0

Hold00

Hold10

HoldX1

CHANNEL FUNCTIONCONFIG

S/H (SAMPLE/HOLD)

VOUT2000

VOUT110

VOUT0000

VOUT9110

VOUT8010

VOUT7100

VOUT3100

VOUT4000

VOUT5100

VOUT6000

ADDR0ADDR3ADDR4 ADDR2 ADDR1

VOUT12010

VOUT1111

VOUT10010

VOUT19101

VOUT18001

VOUT17101

VOUT13110

VOUT14010

VOUT15110

VOUT16001

VOUT26011

VOUT2511

VOUT24011

VOUT31111

VOUT27111

VOUT28011

VOUT29111

VOUT3001

VOUT23101

VOUT22001

VOUT21101

VOUT20001

X = Don’t care.

SELECTED

OUTPUT

SELECTED

MAX5168

selected multiplexer channel connects to IN, allowing the

hold capacitor to acquire the input signal. To guarantee

an accurate sample, maintain sample mode for at least

4µs. The output of the sample/hold amplifier tracks the

input after 4µs. Only the addressed channel on the

selected multiplexer samples the input; all other channels

remain in hold mode.

Hold Mode

No matter what the condition of the other control lines,

S/H = high places the MAX5168 into an all-channel

hold mode. Hold mode disables the multiplexer and

disconnects all 32 sample/holds from the input. When a

channel is disconnected, the hold capacitor maintains

the sampled voltage at the output with a 1mV/s typical

droop rate (towards VDD).

Hold Step

When switching between sample mode and hold mode,

the voltage of the hold capacitor changes due to

charge injection from stray capacitance. This voltage

change, called a hold step, is minimized by limiting the

amount of stray capacitance seen by the hold capacitor.

The MAX5168 limits the hold step to 0.25mV (typ). An

output capacitor to ground can be used to filter out this

small hold-step error.

Output

The MAX5168 contains an output buffer for each multi-

plexer channel (32 total), so the hold capacitor sees a

high-impedance input that reduces the droop rate. The

capacitor droops at 1mV/s (typ) while in hold mode. The

buffer also provides a low output impedance; however,

the device contains output resistors in series with the

buffer output (Figure 1) for selected output filtering. To

provide greater design flexibility, the MAX5168 is avail-

able with an output impedance of 50Ω, 500Ω, or 1kΩ.

Output loads increase the analog supply current (IDD

and ISS). Excessive loading of the output(s) drastically

increases power dissipation. Do not exceed the maximum

power dissipation specified in the Absolute Maximum

Ratings.

The resistor-divider formed by the output resistor (RO) and

load impedance (RL) scales the sampled voltage

(VSAMP). Determine the output voltage (VOUT_) as follows:

Voltage Gain = AV= RL/ (RL+ RO)

VOUT_ = VSAMP ✕AV

The maximum output voltage range depends on the ana-

log supply voltages available and the scaling factor used:

(VSS + 0.75V) ✕AV≤VOUT_ ≤(VDD - 2.4V) ✕AV

when RL= ∞, then AV= 1, and this equation becomes

(VSS + 0.75V) ≤VOUT ≤(VDD - 2.4V)

Timing Definitions

Acquisition time (tAQ) is the time the MAX5168 must

remain in sample mode for the hold capacitor to

acquire an accurate sample. The hold-mode settling

time (tH) is the time necessary for the output voltage to

settle to its final value. Aperture delay (tAP) is the time

interval required to disconnect the input from the hold

capacitor. The hold pulse width (tPW) is the time the

MAX5168 must remain in hold mode while the address

is changed. Data setup time (tDS) is the time an

address must be maintained at the digital input pins

before the address becomes valid. Data hold time (tDH)

is the time an address must be maintained after the

device is placed in hold mode (Figure 2).

Applications Information

Multiplexing a DAC

Figure 3 shows a typical demultiplexer application.

Different digital codes are converted by the digital-to-

analog converter (DAC) and then stored on 32 different

channels of the MAX5168. The 40mV/s (max) droop

rate requires refreshing the hold capacitors every

250ms before the voltage droops by 1/2LSB for an 8-bit

DAC with a 5V full-scale voltage.

Virtual 64 Output Sample/Hold

Two MAX5168s can be configured to operate as a single

64 output sample/hold. The upper and lower addressed

devices are identified by CONFIG’s logic level. Connect

the CONFIG pin of the upper device low, making its

SELECT pin active high. Connect the CONFIG pin of the

lower device high to make the SELECT pin active low.

Figure 4 shows how to configure the devices.

The devices now use only six address lines and a sin-

gle S/H control to decode 64 outputs. Address lines

A0–A4 from the control logic connect to ADDR0–

ADDR4 on both of the 32-channel devices. The A5 line

toggles the SELECT pins of both devices to select the

active one. The device that has CONFIG tied high

responds to the lower 32 addresses (000000 through

011111). The device that has CONFIG grounded

responds to the upper 32 addresses (100000 through

111111).

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

8 _______________________________________________________________________________________

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

_______________________________________________________________________________________ 9

S/H

ADDR_

SELECT, CONFIG

OUT_

tPW

tDH

tDS

tAQ tAP

HOLD STEP

(CHANNEL x FROM HOLD TO SAMPLE) (CHANNEL x FROM SAMPLE TO HOLD)

Figure 2. Timing Diagram

S/H

SELECT

OUT0

OUT1

OUT30

OUT31

SWITCHES 0–31

ADDRESS BUS

ADDR0–ADDR4

DATA BUS

CONFIG

DAC

MAX5168

ADDRESS DECODER

Figure 3. Multiplexing a DAC

MAX5168

Input Drive Requirements

The input of the MAX5168 feeds the inputs of 32 high-

impedance buffers. These buffers are what charge the

sample/hold capacitor through the multiplexer switch

resistance. The bias current of a selected buffer is

10µA, and this feeds into the 10pF input capacitance.

Figure 5 shows an equivalent input circuit. The bias cur-

rents of the other 31 sample and holds are very small in

comparison to the bias current of the selected channel.

Powering the MAX5168

The MAX5168 does not require a special power-up

sequence to avoid latchup. The device requires three

separate supply voltages for operation. However, when

one or two of the voltages are not available, DC-DC

charge-pump (switched-capacitor) converters provide

a simple, efficient solution. The MAX860 provides volt-

age doubling or inversion, ideal for conversions from

+5V to +10V or from +5V to -5V.

Chip Information

TRANSISTOR COUNT: 6961

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

10 ______________________________________________________________________________________

OUT0

OUT1

OUT30

OUT31

OUT32

OUT33

OUT62

OUT63

MAX5168

CONFIG

ADDR0–ADDR4

SELECT

S/H

CONFIG

ADDR0–ADDR4

SELECT

S/H

A0–A4

INPUT

Figure 4. 64-Output Sample/Hold Circuit

IBIAS

10µA, INH = LOW

CIN

10pF

Figure 5. Input Equivalent Circuit

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

______________________________________________________________________________________ 11

Package Information

32L/48L,TQFP.EPS

MAX5168

32-Channel Sample/Hold Amplifier

with a Single Multiplexed Input

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

NOTES