SG2525A
SG3525A
REGULATING PULSE WIDTH MO DULATORS
.8 TO 35 V OPERATION
.5.1 V REFEREN CE TRIMM ED TO ± 1 %
.100 Hz T O 500 KHz OS CILLAT OR RANGE
.SEPARATE OSCILLATOR SYNC TERMINAL
.ADJUSTABLE DEADTIME CONTROL
.INTERN AL SOFT- STA RT
.PULSE-BY-PULSE SHUTDO WN
.INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
.LATCHING PWM TO PREVENT MULTIPLE
PULSES
.DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION
The SG 3525 A s eries of puls e width m odulat or i nte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in des igning all t y pes of s witching power su p-
plies . The on- chip + 5 .1 V r eferenc e is trim med to ±
1 % and the input commo n-mode range of the error
amplif ier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to b e slaved or a singl e unit to be
synchronized to an external system clock. A single
resistor between the CT and the discharge terminals
provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdow n te rminal cont rols bo th the sof t-star t circ u-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as s of t-s tar t r ec y cl e w it h longer s hu t-
down com mands . Th ese fu nctions are also contr ol-
led by an undervoltage lockout which keeps the out-
puts off and the soft-start capacitor discharged for
sub -n or ma l input voltag es . Th is loc k out c irc u it ry in-
clu des approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated f or any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG 3525A ou tput stage features NOR logic, giving a
LOW o utput for an OFF state.
DIP16 16(Narrow)
Type Plastic DIP SO16
SG2525A SG2525AN SG2525AP
SG3525A SG3525AN SG3525AP
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
®
June 20 00 1/12
ABSOLU TE M AXIMUM RA TINGS
Symbol Parameter Value Unit
ViSupply Voltage 40 V
VCC ollector Supply Voltage 40 V
IOSC Oscillator Charging Current 5 mA
IoOutput Current, Source or Sink 500 mA
IRR eference Output Current 50 mA
ITC urrent through CT Terminal
Logic Inputs
Analog Inputs
5
– 0.3 to + 5.5
– 0.3 to Vi
mA
V
V
Ptot Total Power Dissipation at Tamb = 70 °C 1000 mW
TjJunction Temperature Range – 55 to 150 °C
Tstg Storage Temperature Range – 65 to 150 °C
Top Operating Ambient Temperature : SG2525A
SG3525A – 25 to 85
0 to 70 °C
°C
THERMAL DATA
Symbol Parameter SO16 DIP16 Unit
Rth j-pi ns
Rth j-amb
Rth j-al umina
Thermal Resistance Junction-pins Max
Thermal Resistance Junction-am bient Max
Thermal Resistance Junction-alumina (*) Max 50
50
80 °C/W
°C/W
°C/W
*Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
SG2525A-SG3525A
2/12
ELECTRICAL CHARACTERISTICS
(V# i = 20 V , and ov er ope ra ti ng tem pe rature, unles s ot her wi se spe c if ied )
Symbol Parameter Test Conditions SG2525A SG3525A Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj = 25 °C 5.05 5.1 5.15 5 5.1 5.2 V
∆VREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV
∆VREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV
∆VREF/∆T* Temp. Stability Over Operating Range 20 50 20 50 mV
* Total Output Variation Line, Load and
Temperature 5 5.2 4.95 5.25 V
Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA
* Output Noise Voltage 10 Hz ≤f ≤ 10 kHz,
Tj = 25 °C40 200 40 200 µVrms
∆VREF* Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV
OSCILLATOR SECTION * *
*, •Initial Accuracy Tj = 25 °C± 2 ± 6 ± 2 ± 6%
*, •Voltage Stability Vi = 8 to 35 V ± 0.3 ± 1 ± 1 ± 2%
∆f/∆T* Temperature Stability Over Operating Range ± 3 ± 6 ± 3 ± 6%
f
MIN Minimum F requency RT = 200 KΩ CT = 0. 1 µF 120 120 Hz
fMAX Maximum Frequency RT = 2 KΩ CT = 470 pF 400 400 KHz
Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA
*, •Clock Amplitude 3 3.5 3 3.5 V
*, •Clock Width Tj = 25 °C 0.3 0.5 1 0.3 0.5 1 µs
Sync Threshold 1.2 2 2.8 1.2 2 2.8 V
Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
VOS Input Offset Voltage 0.5 5 2 10 mV
IbInput Bias Current 1 10 1 10 µA
Ios Input Offset Current 1 1 µA
DC Open Loop Gain RL ≥ 10 MΩ60 75 60 75 dB
* Gain Bandwidth
Product Gv = 0 dB Tj = 25 °C 1 2 1 2 MHz
*, ❚DC Transconduct. 30 KΩ ≤ RL ≤ 1 MΩ
Tj = 25 °C1.1 1.5 1.1 1.5 ms
Output Low Level 0.2 0.5 0.2 0.5 V
Output High Level 3.8 5.6 3.8 5.6 V
CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB
PSR Supply Voltage
Rejection Vi = 8 to 35 V 50 60 50 60 dB
SG2525A-SG3525A
3/12
ELE CTRIC AL CH ARACT E RIS T ICS ( co nt inu ed)
Symbol Parameter Test Conditions SG2525A SG3525A
Unit
Min. Typ. Max. Min. Typ. Max.
PWM COMPARATOR
Minimum Duty-cycle 0 0 %
•Maximum Duty-cycle 45 49 45 49 %
•Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V
Maximum Duty -cycle 3.3 3.6 3.3 3.6 V
* Input Bias Current 0.05 1 0.05 1 µA
SHUTDOWN SECTION
Soft Start Current VSD = 0 V, VSS = 0 V 255080255080 µA
Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V
Shutdown T hreshold To outputs, VSS = 5.1 V
Tj = 25 °C0.6 0.8 1 0.6 0.8 1 V
Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 m A
* Shutdown D elay VSD = 2.5 V Tj = 25 °C 0.2 0.5 0.2 0.5 µs
OUTPUT DRIVERS (each output) (VC = 20 V)
Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V
Isink = 100 mA 1 2 1 2 V
Output H igh Level Isource = 20 mA 18 19 18 19 V
Isource = 100 mA 17 18 17 18 V
Under-Voltage Loc kout Vcomp and Vss = High 678678 V
I
CCollector Leakage VC = 35 V 200 200 µA
tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns
tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns
TOTAL STANDBY CURRENT
IsSupply Current Vi = 35 V 14 20 14 20 m A
*These parame t ers, a lthou gh guaranteed o ver th e recomm end ed operating con diti ons, are not 10 0 % tes ted in p roduc tio n.
•Tested at fosc = 40 KHz (RT = 3.6 KΩ, CT = 10 nF, RD = 0 Ω). Approximate o sci llat or frequency is define d by :
1
f = CT (0.7 RT + 3 RD)
.DC transconductance (gM) rel ates to DC ope n-loop vol tage gain (Gv) according t o t he foll owing equation : Gv = gM RL where RL is the resis tance
from pin 9 to ground. The minimum gM s pecifi c ation is used t o calcul at e m inimum Gv when the error ampl ifi er out put i s loaded.
SG2525A-SG3525A
4/12
TEST CIRCUI T
SG2525A-SG3525A
5/12
Figur e 1 : Oscillat or Charge Time vs. RT
and CT.Figu re 2 : Oscillator Discharge Time vs. RD
and CT.
RECOMM END ED OPE R ATING CON DITIONS (•)
Parameter Value
Input Voltage (Vi) 8 to 35 V
Collector Supply Voltage (VC) 4.5 to 35 V
Sink/Source Load C urrent (steady state) 0 to 100 mA
Sink/Source Load C urrent (peak) 0 to 400 mA
Reference Load Current 0 to 20 mA
Oscillator Frequency Range 100 Hz to 400 KHz
Oscillator Timing Resistor 2 KΩ to 150 K Ω
Oscillator Timing Capacitor 0.001 µF to 0.1 µF
Dead Time Resistor Range 0 to 500 Ω
•(⋅) Range over which t he dev ice is funct i onal and parameter limits are guarante ed.
Figure 3 : Output Saturation
Characteristics. Figure 4 : Erro r Am plifier V olt ag e G ain and
Phase vs. Frequency.
SG2525A-SG3525A
6/12
SHUTDOW N OPTION S (see Block Diagram)
Since both the compensation and soft-start termi-
nals (Pins 9 and 8) have current source pull-ups,
either can readily accept a pull-down signal which
only has to sink a maximum of 1 00 µA to turn off the
outputs. This is subject to the added requiremen t of
disc har gi ng whatever exter na l c apacitanc e m ay be
attached to these pins.
An alternate approach is the use of the shutdown cir-
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating
this circuit by applying a positive signal on Pin 10
performs two functions : the PWM latch is immedi-
ately set pr oviding the f ast es t turn-off signal to the
outputs ; and a 150 µA current sink begins to dis-
charge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is termi-
nated without signific ant discharge of the soft-start
capa citor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting.
Holding Pin 10 high f or a l onger du ration, h owe v er,
will ultimately discharge this external capacitor, re-
cycling slo w t ur n- on upo n r elease.
Pin 10 should not be left floating as noise pickup
coul d co nc eiv ably inter r upt nor m al op er at ion .
Figure 5 : Err or Am plifier.
PRINCIPLES OF OPERATION
SG2525A-SG3525A
7/12
Figur e 7 : Output Circuit (1/2 cir cu it shown).
Figure 6 : Os c illa t or Sc hematic .
SG2525A-SG3525A
8/12
Figure 1 0. Figure 11.
For single-ended supplies, the driver outputs are
gro unded. The VC terminal is switched to ground by
the totem-pole source transistors on alternate oscil-
lator cycle s.
In conventional push-pull bipolar designs, forward
base drive is controlled by R1 - R3. Rapid turn-off
times for the power devices are achieved with
spee d- up c apacitors C1 and C2.
The low source impedance of the output drivers pro-
vides rapid charging of Power Mos input capaci-
tan c e whi le m inimiz ing e xter nal com pone nt s .
Low power transformers can be driven directly.
Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
Figure 8. Figure 9.
SG2525A-SG3525A
9/12
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
SG2525A-SG3525A
10/12
SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0 .386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8˚(max.)
SG2525A-SG3525A
11/12
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SG2525A-SG3525A
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