AT89C51CC02UA-TISUM - ATMEL - Datasheet.Directory

Rev. 4126L –CA N–0 1/0 8

Features

•80C51 Core Architecture

•256 Bytes of On-chip RAM

•256 Bytes of On-chip XRAM

•16K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Erase/Write Cycle: 100K

•Boot Code Section with Independent Lock Bits

•2K Bytes of On-chip Flash for Bootloader

•In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability

•2K Bytes of On-chip EEPROM

– Erase/Write Cycle: 100K

•14-sources 4-level Interrupts

•Three 16-b it T ime rs /Coun ter s

•Full Duplex UART Compatible 80C51

•Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)

•Three or Four Ports: 16 or 20 Digital I/O Lines

•Two-channel 16-bit PCA

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

•Double Data Pointer

•21-bit Watchdog Timer (7 Programmable bits)

•A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs

•Full CAN Controller

– Fully Compliant with CAN rev.# 2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 4 Independent Message Objects

-Each Message Object Programmable on Transmission or Reception

-Individual Tag and Mask Filters up to 29-bit Identifier/Channel

-8-byte Cyc lic Data Register (FIFO)/Me ssa ge Object

-16-bit Status and Control Register/Message Object

-16-bit Time-Stamping Register/Message Object

-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

-Acces s to Messa ge Ob ject C ontrol and D ata Regist ers V i a SFR

-Programmable Reception Buffer Length up to 4 Message Objects

-Priority Management of Reception of Hits on Several Message Objects

Simultan eously (Basic CAN Feature)

-Priority Management for Transmi ssion

-Message Object Overrun Interrupt

– Supports

-Time Triggered Communication

-Autobaud and Listening Mode

-Programmable Automatic Reply Mode

•1-Mbit/s Maximum Transfer Rate at 8 MHz(1) Crystal Frequency In X2 Mode

•Readable Error Counters

•Programmable Link to On-chip Timer for Time Stamping and Network Synchronization

•Independent Baud Rate Prescaler

•Data, Remote, Error and Overload Frame Handling

•Power -sav ing Modes

–Idle Mode

– Power-down Mode

•Power Supply: 3 Volts to 5.5 Volts

•Temperature Range: Industrial (-40° to +85°C)

•Packages: SOIC28, SOIC24, PLCC28, VQFP32

Note: 1. At BRP = 1 sampling point will be fixed.

Enhanced 8-bit

Microcontroller

with CAN

Controller and

Flash

T89C51CC02

AT89C51CC02

AT/T89C51CC02

4126L–CAN–01/08

Description Part of the CANaryTM fami ly of 8-bi t mi croc on tr oll ers dedi ca ted to CAN ne twor k appl ic a-

tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller.

In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CA N controller T89C51CC02 p rovides 16K Byte s of Flash m emory

including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes

EEPROM and 512 Bytes RAM.

Special attention is payed to the reduction of the electro-magnetic emission of

T89C51CC02.

Block Diagram

Note: 1. 8 analog Inputs/8 Digital I/O.

2. 2-bit I/O Port.

Timer 0 INT

RAM

256x8

T1 RxD

TxD

XTAL2

XTAL1

UART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

P2(2)

Port 1Port 2 Port 3

Parallel I/O Ports

P1(1)

XRAM

256 x 8

IB-bus

PCA

RESET

Watch

Dog

PCA

ECI

Vss

Vcc

Timer 2

T2EX

Port 4

P4(2)

10-bit

ADC

Flash

16K x

Boot

loader

2K x 8

PROM

2K x 8 CAN

CONTROLLER

TxDC

RxDC

VAVCC

VAREF

VAGND

AT/T89C51CC02

4126L–CAN–01/08

Pin Configurations

P3.4/T0

P3.3/INT1

P4.1/RxDC

P3.7

P3.2/INT0

P1.5/AN5

P1.7/AN7

P1.6/AN6

P2.0

VAREF

VAVCC

VAGND

P1.0/

AN0/T2

P1.1/AN1/T2EX

P1.2/AN2/ECI

P1.3/AN3/CEX0

P1.4/AN4/CEX1

RESE

VCC

VSS

P4.0/TxDC

P2.1

P3.6

P3.5/T1

P3.1/TxD 13

P3.0/RxD 14 16 XTAL1

15 XTAL2

SO28

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7

P4.0/TxDC

P4.1/RxDC

P2.1

P3.6

P2.0

P1.4/AN4/CEX1

P1.5/AN5

P1.6/AN6

P1.7/AN7

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

VAVCC

PLCC-28

P3.1/TxD

P3.0/RxD

P4.1/RxDC

P3.4/T0

XTAL2

P1.5/AN5

P1.7/AN7

P1.6/AN6

RESE

VAREF

VAVCC

VAGND

P1.0/

AN0/T2

P1.1/AN1/T2EX

P1.2/AN2/ECI

P1.3/AN3/CEX0

P1.4/AN4/CEX1

VSS

XTAL1

VCC

P4.0/TxDC

P3.5/T1

P3.3/INT1

P3.2/INT0

SO24

AT/T89C51CC02

4126L–CAN–01/08

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7

P4.0/TxDC

P4.1/RxDC

P2.1

P3.6

P2.0

P1.4/AN4/CEX1

P1.5/AN5

P1.6/AN6

P1.7/AN7

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

VAVCC

QFP-32

AT/T89C51CC02

4126L–CAN–01/08

Pin Description

Pin Name Type Description

VSS GND Circuit ground

VCC Supply Voltage

VAREF Reference Voltage for ADC (input)

VAVCC Supply Voltage for ADC

VAGND Reference Ground for ADC (internaly connected with the VSS)

P1.0:7 I/O Po rt 1:

Is an 8-bit bi-d irectional I/O port with internal pull-ups. Port 1 pi ns can be used for dig ital input/o utput or as

analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled

high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that

are being pulled low externally will be the source of current (I IL, See se ction ’Electrical Characteristic’)

because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF

As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA

external clock input and the PCA module I/O.

P1.0/AN0/T2

Analog input channel 0,

External clock input for Timer/counter2.

P1.1/AN1/T2EX

Analog input channel 1,

Trigger input for Timer/counter2.

P1.2/AN2/ECI

Analog input channel 2,

PCA exter nal clock input.

P1.3/AN3/CEX0

Analog input channel 3,

PCA module 0 Entry of input/PWM output.

P1.4/AN4/CEX1

Analog input channel 4,

PCA module 1 Entry of input/PWM output.

P1.5/AN5

Analog input channel 5,

P1.6/AN6

Analog input channel 6,

P1.7/AN7

Analog input channel 7,

It can drive CMOS inputs without external pull-ups.

P2.0:1 I/O Po rt 2:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled

high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being

pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups.

In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

AT/T89C51CC02

4126L–CAN–01/08

P3.0:7 I/O Po rt 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled

high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that

are being pulled lo w ext ernal ly will be a source of current (IIL, See section ’Electrical Characteristic’)

because of the internal pull-ups.

The output latch corresponding to a secondary function must be programmed to one for that function to

operate (e xcept for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2/INT0: External interrupt 0 input/timer 0 gate control input

P3.3/INT1: External interrupt 1 input/timer 1 gate control input

P3.4/T0: Timer 0 counter input

P3.5/T1: Timer 1 counter input

P3.6: Regular I/O port pin

P3.7: Regular I/O port pin

P4.0:1 I/O Po rt 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled

high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being

pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up

transistor.

The output latch corresponding to a secondary function RxDC must be programmed to one for that

function to operate. The secondary functions are assigned to the two pins of port 4 as follows:

P4.0/TxDC:

Tran smitter output of CAN controller

P4.1/RxDC:

Receiver input of CAN controller.

It can drive CMOS inputs without external pull-ups.

RESET I/O Reset:

A high level on this pin during two machine cycles while the oscillator is running resets the device. An

internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.

XTAL1 I XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the

device fr om an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To

operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

XTAL2 O XTAL2:

Output from the inverting oscillator amplifier.

Pin Name Type Description

AT/T89C51CC02

4126L–CAN–01/08

I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A

CPU ’read lat ch’ signal transf ers the latch ed Q output onto the inte rnal bus. Similar ly, a

’read pin’ signal transfers the logi cal level of the Port pin. Some Port data instructions

activate the ’read latch’ signal while others activate the ’read pin’ signal. Latch instruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Port Structure Figure 1 shows the structure of Ports, which have internal pull-ups. An external source

can pull the pin low. Each Port pin can be configured either for general-purpose I/O or

for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register.

This turns off the output FET drive.

To configur e a pin for its al ternate functi on, set t he bit in the P x reg is ter . When t he latc h

is set, the ’al ternate o utpu t function ’ sig nal contr ols the out put level (See Figure 1). T he

operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’

paragraph.

Figure 1. Ports Structure

Note: 1. The internal pull-up can be disabled on P1 when analog function is selected.

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

BUS

P2.x

P3.x

P4.x

P1.x(1)

AT/T89C51CC02

4126L–CAN–01/08

Read-Modify-Write

Instructions Some in structi ons rea d the l atch data r ather th an t he pin data. The latc h bas ed in stru c-

tions read the dat a, modi fy the data an d then r ewrite the latc h. Thes e are c alled ’Read-

Modify-Write’ instructions. Below is a complete list of these special instructions (See

Table 1). When the destination operand is a Port or a Port bit, these instructions read

the latch rather than the pin:

It is not o bv iou s that the l as t thr ee in str uc ti ons in thi s list are Rea d- Mod ify -Wr it e instru c-

tions. These instructions read the port (all 8 bits), modify the specifically addressed bit

and write the new byte back to the latch. These Read- Modify-Write instr uctions are

directe d to the l atch rather than th e pin in order to avoid po ssible misinterpret ation of

voltage (and theref ore, log ic) l evels at th e pin. For e xampl e, a P ort bit used to driv e the

base of an external bipolar transistor cannot rise above the transistor’s base-emitter

junctio n v ol tage (a v al ue lowe r than VI L) . W ith a l ogi c one writt en to the bi t, a ttem pts by

the CPU to read the P ort at the p in are misinter pret ed as lo gic zero . A read of the latc h

rather than the pins returns the correct logic one value.

Quasi Bi-direc tiona l Por t

Operation Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as ’quasi-bidi-

rectional’ Ports. When configured as an input, the pin impedance appears as logic one

and sources current in response to an external logic zero condition. Resets write logic

one to all Port l atches. If logical zero is s ubsequently w ritten to a Port la tch, it c an be

returned to input conditions by a logic one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write insruction cycles. Output

buffe rs (and therefore the pin state) are updated early in the instruction after Read-Mod-

ify-Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1)

to aid this log ic tran sition See Fi gure 2. Th is incr eas es s witc h s peed. This ext ra p ull-u p

sources 100 times normal internal circuit current during 2 oscillator clock periods. The

internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist

of three p-chan nel FET (pF ET) devi ces. A pFE T is on when th e gate sen ses log ic zero

and off wh en the gate senses logic one. p FET # 1 is turne d o n for two oscil lator pe riods

immedia tely after a zer o-to-one transition in the Port latch. A log ic one at the Por t pin

turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form

a latch to drive logic one. pFET #2 is a very weak pull-up switched on whenever the

Table 1. Read/Modify/Write Instructions

Instruction Description Example

ANL Logical AND ANL P1, A

ORL Logical OR ORL P2, A

XRL Logical EX-OR XRL P3, A

JBC Jum p if bit = 1 and clear bit JBC P1.1, LABEL

CPL Complement bit CPL P3.0

INC Increment INC P2

DEC Decrement DE C P2

DJNZ Decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C Move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y Clear bit y of Port x CLR P2.4

SET Px.y Set bit y of Port x SET P3.3

AT/T89C51CC02

4126L–CAN–01/08

associated nFET is switch ed off. This is traditional CMOS switch con ventio n. Current

strengths are 1/10 that of pFET #3.

Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the

pin.

Figure 2. Internal Pull-up Configurations

READ PI N

INPU T D ATA

P1.x

OUTPUT DATA

2 Osc. PERIODS

p1(1) p2 p3

VCCVCCVCC

P2.x

P3.x

P4.x

AT/T89C51CC02

4126L–CAN–01/08

SFR Mapping Tables 3 through Table 11 show the Special Function Registers (SFRs) of the

T89C51CC02.

Table 2. C51 Core SFRs

MnemonicAddName 76543210

ACC E0h Accumulator

B F0h B Register

PSW D0h Program St atus Word CY AC F0 RS1 RS0 OV F1 P

SP 81h Stack Pointer

DPL 82h Data Pointer Low

byte

LSB of DPTR

DPH 83h Data Pointer High

byte

MSB of DPTR

Table 3. I/O Port SFRs

MnemonicAddName 76543210

P1 90h Port 1

P2 A0h Port 2 (x2)

P3 B0h Port 3

P4 C0h Port 4 (x2)

Table 4. Timers SFRs

MnemonicAddName 76543210

TH0 8Ch Timer/Counter 0 High

byte

TL0 8Ah Timer/Counter 0 Low

byte

TH1 8Dh Timer/Counter 1 High

byte

TL1 8Bh Timer/Counter 1 Low

byte

TH2 CDh Timer/Counter 2 High

byte

TL2 CCh Timer/Counter 2 Low

byte

TCON 88h Timer/Counter 0 and

1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h Timer/Counter 0 and

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

AT/T89C51CC02

4126L–CAN–01/08

T2CON C8h Timer/Counter 2

control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h T imer/Counter 2

Mode T2OE DCEN

RCAP2H CBh Timer/Counter 2

Reload/Capture High

byte

RCAP2L CAh Timer/Counter 2

Reload/Capture Low

byte

WDTRST A6h WatchDog Timer

Reset

WDTPRG A7h WatchDog Timer

Program S2 S1 S0

Table 4. Timers SFRs (Continued)

MnemonicAddName 76543210

Table 5. Serial I/O Port SFRs

MnemonicAddName 76543210

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Addres s Mask

SADDR A9h Slave Address

Table 6. PCA SFRs

MnemonicAddName 76543210

CCON D8h PCA Timer/Counter

Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter

Mode CIDL CPS1 CPS0 ECF

CL E9h PCA Timer/Counter

Low byt e

CH F9h PCA Timer/Counter

High byte

CCAPM0

CCAPM1 DAh

DBh

PCA Timer/Counter

Mode 0

PCA Timer/Counter

Mode 1

ECOM0

ECOM1 CAPP0

CAPP1 CAPN0

CAPN1 MAT0

MAT1 TOG0

TOG1 PWM0

PWM1 ECCF0

ECCF1

CCAP0H

CCAP1H FAh

FBh

PCA Compare

Capture Module 0 H

PCA Compare

Capture Module 1 H

CCAP0H7

CCAP1H7 CCAP0H6

CCAP1H6 CCAP0H5

CCAP1H5 CCAP0H4

CCAP1H4 CCAP0H3

CCAP1H3 CCAP0H2

CCAP1H2 CCAP0H1

CCAP1H1 CCAP0H0

CCAP1H0

AT/T89C51CC02

4126L–CAN–01/08

CCAP0L

CCAP1L EAh

EBh

PCA Compare

Capture Module 0 L

PCA Compare

Capture Module 1 L

CCAP0L7

CCAP1L7 CCAP0L6

CCAP1L6 CCAP0L5

CCAP1L5 CCAP0L4

CCAP1L4 CCAP0L3

CCAP1L3 CCAP0L2

CCAP1L2 CCAP0L1

CCAP1L1 CCAP0L0

CCAP1L0

Table 6. PCA SFRs (Continued)

MnemonicAddName 76543210

Table 7. Interrupt SFRs

MnemonicAddName 76543210

IEN0 A8h Interrupt Enable

Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 E8h Interrupt Enable

Control 1 ETIM EADC ECAN

IPL0 B8h Interrupt Priority

Control Low 0 PPC PT2 PS PT1 PX1 PT0 PX0

IPH0 B7h Interru p t Priorit y

Control High 0 PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 F8h Interru p t Priorit y

Control Low 1 POVRL PADCL PCANL

IPH1 F7h Interrupt Priorit y

Control High1 POVRH PADCH PCANH

Table 8. ADC SFRs

MnemonicAddName 76543210

ADCON F3h A DC Control PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

ADCF F6h ADC Configuration CH7 CH6 CH5 C H4 CH3 CH2 CH1 CH0

ADCLK F2h A D C C lo ck PRS4 PRS3 PRS 2 PRS1 PRS0

ADDH F5h A DC Data High byte A DAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 A DAT3 ADAT2

ADDL F4h ADC Data Low byte ADAT1 ADAT0

Table 9. CAN SFRs

MnemonicAddName 76543210

CANGCON ABh CAN General

Control ABRQ OVRQ TTC SYNCTTC AUT-BAUD TEST ENA GRES

CANGSTA AAh CAN General

Status OVFG TBSY RBSY ENFG BOFF ERRP

CANGIT 9Bh CAN General

Interrupt CANIT OVRTIM OVRBUF SERG CERG FERG AERG

CANBT1 B4h CAN bit Timing 1 BRP5 BRP4 B RP 3 BRP2 BRP1 BRP0

CANBT2 B5h CAN bit Timing 2 SJW1 SJW0 PRS2 PRS1 PRS0

CANBT3 B6h CAN bit Timing 3 PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

AT/T89C51CC02

4126L–CAN–01/08

CANEN CFh CAN Enable

Channel byte ENCH3 ENCH2 ENCH1 ENCH0

CANGIE C1h CAN General

Interrupt Enable ENRX ENTX ENERCH ENBUF ENERG

CANIE C3h CAN Interrupt

Enable C han ne l

byte IECH3 IECH2 IECH1 IECH0

CANSIT BBh CAN Status Interrupt

Channel byte SIT3 SIT2 SIT1 SIT0

CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14 CANTIM 13 CANTIM 12 CANTIM 11 CANTIM 10 CANTIM 9 CANTIM 8

CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0

CANSTMPH AFh CAN Timer Stamp

high TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP 11 TIMSTMP

10 TIMSTMP 9 TIMSTMP 8

CANSTMPL AEh CAN Timer Stamp

low TIMSTMP7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

CANTTCH A5h CAN Tim er TTC

high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC

9TIMTTC

CANTTCL A4h CAN Ti mer TTC low TIMTTC

7TIMTTC

6TIMTTC

5TIMTTC

4TIMTTC

3TIMTTC

2TIMTTC

1TIMTTC

CANTEC 9Ch CAN Transmit Error

Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

CANREC 9Dh CAN Receive Error

Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

CANPAGE B1h CAN Page - - CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h CAN Status Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR

CANCONCH B3h CAN Control

Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

CANMSG A3h CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

CANIDT1 BCh

CAN Identifier Tag

byte 1(Part A)

CAN Identifier Tag

byte 1(PartB)

IDT10

IDT28 IDT9

IDT27 IDT8

IDT26 IDT7

IDT25 IDT6

IDT24 IDT5

IDT23 IDT4

IDT22 IDT3

IDT21

CANIDT2 BDh

CAN Identifier Tag

byte 2 (PartA)

CAN Identifier Tag

byte 2 (PartB)

IDT2

IDT20 IDT1

IDT19 IDT0

IDT18 -

IDT17 -

IDT16 -

IDT15 -

IDT14 -

IDT13

CANIDT3 BEh

CAN Identifier

Tag byte 3(PartA)

CAN Identifier

Tag byte 3(PartB)

IDT12

IDT11

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

CANIDT4 BFh

CAN Identifier

Tag byte 4(PartA)

CAN Identifier

Tag byte 4(PartB)

IDT4

IDT3

IDT2

IDT1

IDT0 RTRTAG -

RB1TAG RB0TAG

CANIDM1 C4h

CAN Identifier Mask

byte 1(PartA)

CAN Identifier Mask

byte 1(PartB)

IDMSK10

IDMSK28

IDMSK9

IDMSK27

IDMSK8

IDMSK26

IDMSK7

IDMSK25

IDMSK6

IDMSK24

IDMSK5

IDMSK23

IDMSK4

IDMSK22

IDMSK3

IDMSK21

Table 9. CAN SFRs (Continued)

MnemonicAddName 76543210

AT/T89C51CC02

4126L–CAN–01/08

CANIDM2 C5h

CAN Identifier Mask

byte 2(PartA)

CAN Identifier Mask

byte 2(PartB)

IDMSK2

IDMSK20

IDMSK1

IDMSK19

IDMSK0

IDMSK18

IDMSK17

IDMSK16

IDMSK15

IDMSK14

IDMSK13

CANIDM3 C6h

CAN Identifier Mask

byte 3(PartA)

CAN Identifier Mask

byte 3(PartB)

IDMSK12

IDMSK11

IDMSK10

IDMSK9

IDMSK8

IDMSK7

IDMSK6

IDMSK5

CANIDM4 C7h

CAN Identifier Mask

byte 4(PartA)

CAN Identifier Mask

byte 4(PartB)

IDMSK4

IDMSK3

IDMSK2

IDMSK1

IDMSK0 RTRMSK - IDEMSK

Table 9. CAN SFRs (Continued)

MnemonicAddName 76543210

Table 10. Other SFRs

MnemonicAddName 76543210

PCON 87h Power Cont rol SMOD1 SMOD0 POF GF1 GF0 PD IDL

AUXR1 A2h Auxiliary Register 1 ENBOOT GF3 0 DPS

CKCON 8Fh C lock Control CAN X2 W DX 2 PCAX 2 SIX2 T2X2 T1X2 T0X2 X2

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 EEE EEBUSY

AT/T89C51CC02

4126L–CAN–01/08

Reserved

Notes: 1. These registe rs are bit- addr essable.

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFRs are those

whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

2. AUXR1 bit ENBOOT is initialized with the content of the BLJB bit inverted.

Table 11. SFR Map ping

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

0xxx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN

xxxx 0000 CFh

C0h P4

xxxx xx11 CANGIE

1100 0000 CANIE

1111 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT

xxxx 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

1100 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

1010 0000 CANGCON

0000 0000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

xxxx xxxx CANSTMPH

xxxx xxxx AFh

A0h P2

xxxx xx11 CANTCON

0000 0000 AUXR1(2)

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 CKCON

0000 0000 8Fh

80h SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT/T89C51CC02

4126L–CAN–01/08

Clock The T 89C51CC02 core needs only 6 clock periods per machine cycl e. This feature,

called “X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU

power.

• Saves power consumption while keeping the same CPU power (oscillator power

saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in

operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to ke ep the origin al C51 compat ibility, a div ider-by-2 is inserted be tween the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by the software.

An extra feature is available to start after Reset in the X2 Mode. This feature can be

enabled by a bit X2B in the Hardwar e Security Byte. T his bit is descri bed in the sectio n

’In-System Programming’.

Description The X 2 bit in th e CKCO N regist er (See Table 12 ) allows switchi ng fro m 12 cloc k cyc les

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Setting this bit activates the X2 feature (X2 Mode) for the CPU Clock only (See Figure

3).

The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 Mode only if the corre-

sponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1

input. In X2 Mod e, as thi s div id er is by pas s ed, t he s ignal s o n XT A L1 m us t hav e a cycl ic

ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2

bit is valid ated on the XTA L1 ÷ 2 rising edge to avoid glitches when switching from the

X2 to the STD mode. Figure 4 shows the mode switching waveforms.

AT/T89C51CC02

4126L–CAN–01/08

Figure 3. Clock CPU Generation Diagram

TAL1

TAL2

PCON.1

CPU Core

÷ 2

PERIPH

CLOCK

Clock

Peripher al Cloc k Sym bol

CPU

CLOCK

CPU Core Clock Symbol

CKCON.0

X2B

Hardware Byte

CANX2

CKCON.7 WDX2

CKCON.6 PCAX2

CKCON.5 SIX2

CKCON.4 T2X2

CKCON.3 T1X2

CKCON.2 T0X2

CKCON.1

IDL

PCON.0

÷ 2

CKCON.0

FCan Clock

FWd Clock

FPc a Clock

FUart Clock

FT2 Clock

FT1 Clock

FT0 Clock

and ADC

On RESET

AT/T89C51CC02

4126L–CAN–01/08

Figure 4. Mode Switching Waveforms(1)

Note: 1. In order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using

the clock freque ncy a s a time ref erence (UART, timers...) will hav e their time re ference divided b y 2. Fo r exam ple, a fre e run-

ning timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate

will have a 9600 baud rate.

XTAL2

XTAL1

CPU

clock

X2 bit

Mode

STD

Mode STD

Mode

AT/T89C51CC02

4126L–CAN–01/08

CKCON (S:8Fh)

Clock Control Register

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

76543210

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number Bit

Mnemonic Description

7CANX2

CAN Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

6WDX2

Wa tchdog Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

5PCAX2

Program ma ble Counter Array Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

4SIX2

Enhanced UART clock (MODE 0 and 2) (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3T2X2

Timer 2 Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

2T1X2

Timer 1 Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

1T0X2

Timer 0 Clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

0X2

CPU Clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

the peripherals.

Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the

individual peripherals ’X2’ bits.

AT/T89C51CC02

4126L–CAN–01/08

Power Management Two power reduction modes are implemented in the A/T89C51CC02: the Idle mode and

the Po wer-do wn mode . These modes are det ailed in the fol lowing s ecti ons. In additio n

to these pow er r edu cti on mo des , t he cl oc ks o f the core and peripherals c an be dy nam i-

cally divided by 2 using the X2 Mode detailed in Section “Clock”.

Reset Pin In order to s tart-up (col d rese t) or to restar t (war m re set) p roperl y the micr ocont roller , a

high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of

the intern al regis ters like S F Rs, PC , etc. and to unpre dictable beha vi or of the microc on-

trolle r. A warm res et can be ap plied eith er direct ly on the RS T pin or in directl y by an

internal reset source such as a watchdog, PCA, timer, etc.

At Power-up (cold reset) Two conditions are required before enabling a CPU start-up:

• VDD must reach the specified VDD range,

• The level on xtal1 input must be outside the specification (VIH, VIL).

If one of these two conditio ns are not met, the microcontrolle r does not start correctly

and can exe cute an instr uction fe tch from an ywhere in the progr am space. A n active

level applie d on the RS T pin must be mainta ined un til both of the abov e conditi ons ar e

met. A re set is activ e when the level VIH1 i s reache d and when th e pulse w idth covers

the period of time where VDD and the oscillator are not stabilized. Two parameters have

to be taken into account to determine the reset pulse width:

• VDD rise time (vddrst),

• Oscillator startup time (oscrst).

To determine the capacitor the highest value of these two parameters has to be chosen.

The reset circuitry is shown in Figure 5.

Figure 5. Reset Circuitry

Table 13 and Table 14 give some typical examples for three values of VDD rise times,

two values of oscillator start-up time and two pull-down resistor values.

Table 13. Minimum Reset Capacitor for a 50K Pull-down Resistor

oscrst/vddrst 1ms 10ms 100ms

5ms 820nF 1.2µF 12µF

20ms 2.7µF 3.9µF 12µF

VDD

Rrst

Crst

RST pin

Internal reset

Reset input circuitry

AT/T89C51CC02

4126L–CAN–01/08

Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor

Note: These values assume VDD starts from 0v to the nominal value. If the time between two

on/off sequences is too fast, the power-supply decoupling capacitors may not be fully

discharged, leading to a bad reset sequence.

During a Normal

Operation (Warm Reset) Reset pi n m us t b e m ain tai ned for at l ea st 2 m achi ne cy cl es (24 os c il lator c lock pe r iod s)

to apply a reset s equence duri ng normal oper ation. The num ber of clock periods is

mode independent (X2 or X1).

Watchdog Reset A 1K resistor must be added i n series with the capacitor to allow the use of watchdog

reset pulse output on the RST pin or when an external power-supply supervisor is used.

Figure 6 shows the reset circuitry when a capacitor is used.

Figure 6. Reset Circuitry for a Watchdog Configuration

Figure 7 shows the reset circuitry when an external reset circuit is used.

Figure 7. Reset Circuitry Example Using an External Reset Circuit

oscrst/vddrst 1ms 10ms 100ms

5ms 2.7µF 4.7µF 47µF

20ms 10µF 15µF 47µF

VDD

Rrst

Crst

1k RST pin

Internal reset

watchdog

To other on-board cir cuitry

Reset input circuitry

VDD

Rrst

1k RST pin

Internal reset

watchdog

To other on-board cir c uitry

Reset input circuitry

RST

External reset

circuit

AT/T89C51CC02

4126L–CAN–01/08

Reset Re commendation

to Prevent Flash

Corruption

When a Flash program memory is embedded on-chip, it is strongly recommended to

use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys-

tem malfunction during periods of insufficient power-supply voltage (power-supply

failure, power supply switched off, etc.).

Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,

progra m execution halts . Idle mode freezes the clock to the CPU at kn own states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

preserved, i.e., the program counter and program status word register retain their data

for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The

status of the Port pins during Idle mode is detailed in Table 15.

Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (See Table 16). The

A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The

instruction that sets IDL bit is the last instruction executed.

Note: If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down

mode. Then it does not go in Idle mode when exiting Power-down mode.

Exiting Idle Mode There are two ways to exit Idle mode:

1. Generate an enabled interrupt.

Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-

cution resumes with the interrupt service routine. Upon completion of the interrupt

service r out ine , pr o gram ex ec uti on re sumes wi th the in struc ti on im med iat ely f oll ow-

ing the instruction that activated Idle mode. The general purpose flags (GF1 and

GF0 in PCON register) may be used to indicate whether an interrupt occurred dur-

ing no rmal op er ation or duri ng I dle mo de. When Idle mo de i s ex ite d b y a n i nte rrup t,

the interrupt service routine may examine GF1 and GF0.

2. Generate a reset.

A logic high on the RST pin clears IDL bit in PCON register directly and asynchro-

nously. This restores the clock to the CPU. Program execution momentarily

resum es with the in structio n immed iately foll owing t he instruc tion that ac tivated the

Idle mode and may continue for a number of clock cycles before the internal reset

algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to

address C:0000h.

Note s : 1. D ur i ng the t im e th at ex ec uti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated Idle

mode should not write to a Port pin or to the external RAM.

2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.

Power-down Mode The Power-dow n mode pla ces the A/T 89C51CC02 in a very lo w power state. Power-

down m ode st ops t he oscill ator , freez es a ll c lock at k nown s tate s. The CPU st atus p rior

to entering Power-down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-down mode. In addition, the

SFRs a nd RAM c on tents are pres er ved. T h e s tatu s o f the Po rt pins dur in g P ower -do w n

mode is detailed in Table 15.

Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters

the Power-down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

AT/T89C51CC02

4126L–CAN–01/08

Exiting Power-down Mode Note: If VDD was reduced during the Power-down mode, do not exit Power-down mode until

VDD is restored to t he nor mal operating level.

There are two ways to exit the Power-down mode:

1. Generate an enabled external interrupt.

– The A/T89C51CC02 provides capability to exit from Power-down using

INT0#, INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# input,

execution resumes when the input is released (See Figure 8). Execution

resumes with the interrupt service routine. Upon completion of the interrupt

service routine, program execution resumes with the instruction immediately

following the instruction that activated Power-down mode.

Notes: 1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,

the duration of the interrupt must be long enough to allow the oscillator to stabilize.

The execution will only resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal

RAM content.

Figure 8. Power-down Exit Waveform Using INT1:0#

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the A/T89C51CC02 and

vectors the CPU to address 0000h.

Note s : 1. D ur i ng the t im e th at ex ec uti o n re su me s, th e i nte r na l R AM ca n no t be ac ce ss ed ; ho w -

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from po w er-do wn by res et r edefines a ll t he SF R s, but does not af f ec t the inte rna l

RAM content.

INT1:0#

OSC

Power-down phase Oscillator restart phase Ac tive phaseActive phase

AT/T89C51CC02

4126L–CAN–01/08

Table 15. Pin Conditions in Special Operating Modes

Mode Port 1 Port 2 Port 3 Port 4

Reset High High High High

Idle

(internal

code) Data Data Data Data

Idle

(external

code) Data Data Data Data

Power-

Down(inter

nal code) Data Data Data Data

Power-

Down

(external

code)

Data Data Data Data

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 16. PCON Register

PCON (S:87h)

Power Control Register

Reset Value = 00X1 0000b

Not bit address ab le

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Seria l por t Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Seria l por t Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-off F lag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by

software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle Mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT/T89C51CC02

4126L–CAN–01/08

Data Memory The T89C51CC02 provides data memory access in two different spaces:

The internal space mapped in three separate segments:

• The lower 128 Bytes RAM segment.

• The upper 128 Bytes RAM segment.

• The expanded 256 Bytes RAM segment (XRAM).

A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 9 shows the internal data memory spaces organization.

Figure 9. Internal memory - RAM

Internal Space

Lower 128 Bytes RAM The lower 128 Bytes of RAM (See Figure 10) are accessible from address 00h to 7Fh

using direct or indire ct addressing modes. The lowest 32 Bytes are grouped into 4

banks of 8 r egister s (R0 to R7 ). Two bits RS0 and RS1 in P SW regis ter (Se e Table 18)

select which bank is in use according to Table 17. This allows more efficient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt service routines.

Table 17. Register Bank Selection

The next 16 Bytes above the register banks form a block of bit-addressable memory

space . The C51 ins truction s et include s a wide s election o f singlebit instruct ions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

256 Bytes

Upper

128 Bytes

Internal RAM

Lower

128 Bytes

Internal RAM

Special

Function

Registers

80h 80h

00h

FFh FFh

00h

FFh

Direct Addressing

Addressing

7Fh

Internal XRAM

Direct or Indirect

Indirect Addressing

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

0 1 Register bank 0 from 08h to 0Fh

1 0 Register bank 0 from 10h to 17h

1 1 Register bank 0 from 18h to 1Fh

AT/T89C51CC02

4126L–CAN–01/08

Figure 10. Lower 128 Bytes Internal RAM Organization

Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

Expanded RAM The on-chip 256 Bytes of expanded RAM (XRAM) are accessible from address 0000h to

00FFh using indirect addressing mode through MOVX instructions. In this add ress

range.

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

bit-Addressable Space

4 Banks of

8 Registers

R0-R7

30h

7Fh

(bit Addresses 0-7Fh)

20h

2Fh

18h 1Fh

10h 17h

08h 0Fh

00h 07h

AT/T89C51CC02

4126L–CAN–01/08

Dual Data Pointer

Description The T89C51CC02 imp lements a second data pointer for speeding up code exe cution

and reducing code size in case of intensive usage of external memory accesses.

DPTR0 and DPTR1 are Seen by the CPU as DPTR and are accessed us ing the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

pointer 1 (See Figure 11).

Figure 11 . Dual Data Pointe r Implem enta tio n

Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded

in asse mbler. The latest C compiler takes a lso advantag e of thi s feature b y providin g

enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the

DPS bit in the AUXR 1 reg ister. H owever, note that th e INC i nstruc tion do es not d irectly

force the DPS bit to a particular state, but simply toggles it . In simple routines, such as

the bloc k mov e exa mple, onl y the f act tha t DPS i s tog gled i n the pro per s equence m at-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is 0 or 1 on entry.

; ASCII block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is

added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers

movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE

incDPTR; increment SOURCE address

incAUXR1; switch data pointers

movx@DPTR,A; write the byte to DEST

incDPTR; increment DEST address

jnzmv_loop; check for NULL terminator

end_move:

DPH0

DPH1

DPL0

DPS AUXR1.0

DPH

DPL

DPL1

DPTR

DPTR0

DPTR1

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 18. PSW Register

PSW (S:D0h)

Program Status Word Register

Reset Value = 0000 0000b

76543210

CY AC F0 RS1 RS0 OV F1 P

Bit

Number Bit

Mnemonic Description

7CY

Carry Flag

Carry out from bit 1 of ALU operands.

6AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5F0User Definable Flag 0

4 - 3 RS1:0 Register Bank Select bits

Refer to Table 17 for bits description.

2OV

Overflow Flag

Overflow set by arithmetic operations.

1F1User Definable Flag 1

Parity bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

AT/T89C51CC02

4126L–CAN–01/08

Table 19. AUXR1 Register

AUXR1 (S:A2h)

Auxiliary Control Register 1

Reset Val ue = XXXX 00X0b

Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming

section.

76543210

- - ENBOOT - GF3 0 - DPS

Bit

Number Bit

Mnemonic Description

7 - 6 - Reserved

The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT(1) Enable Boot Flash

Set this bit to map the boot Flash between F800h -FFFFh

Clear this bit to disable boot Flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3GF3General Purpose Flag 3

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

1-Reserved for Data Pointer Extension

0DPS

Data Pointer Select bit

Set to select second dual data pointer: DPTR1.

Clear to select first dual data pointer: DPTR0.

AT/T89C51CC02

4126L–CAN–01/08

EEPROM Data

Memory The 2K bytes on-c hip E EPROM m emory block is loc ated at address es 00 00h to 0 7FFh

of the XRAM/XRAM memory space and is selected by setting control bits in the EECON

A physi cal w rite i n the E EPROM m emo ry is d one in two step s: wr ite data in the colum n

latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 up to 128 Bytes (the page

size). Wh en prog ramming , only th e dat a written in the col umn latch i s progr ammed an d

a ninth bit is used to obtain this feature. This provides the capabil ity to program the

whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth

bit is se t when the writing th e correspondi ng byte in a ro w and all these n inth bits are

reset after the writing of the complete EEPROM row.

W rite Dat a in the Colu mn

Latches Data is written by byte to the column latches as for an external RAM memory. Out of the

11 addre ss bi ts of the data poi nter , t he 4 MS Bs ar e us ed fo r pag e selection ( row ) and 7

are used for byte selection. Between two EEPROM programming sessions, all the

addres ses in the c olumn latch es mus t stay on the sa me page, mea ning tha t the 4 MSB

must no be changed.

The following procedure is used to write to the column latches:

• S av e and dis ab le int er rupt

• Set bit EEE of EECON register

• Load DPTR with the address to write

• Store A register with the data to be written

• Execute a M OVX @DPTR, A

• If needed loop the three last instructions until the end of a 128 Bytes page

• Restore interrupt

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

Programming The EEPROM programming consists of the following actions:

• Write one or more Bytes of one page in the column latches. Normally , all Bytes must

belong to the same page; if not, the last page address will be latched and the others

discarded.

• Launch programming by writing the control sequence (50h followed by A0h) to the

EECON register.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

• The end of programming is indicated by a hardware clear of the EEBUSY flag.

Note: The sequence 5xh and Axh must be executed without instructions between then other-

wise the program mi ng is aborted .

Read Data The following procedure is used to read the data stored in the EEPROM memory:

• S av e and dis ab le int er rupt

• Set bit EEE of EECON register

• Load DPTR with the address to read

• Execute a M OVX A, @DPTR

• Restore interrupt

AT/T89C51CC02

4126L–CAN–01/08

Examples ;*F*************************************************************************

;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

; Save and clear EA

MOV EECON, #02h; map EEPROM in XRAM space

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

; Restore EA

ret

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 Bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

; Save and clear EA

MOV EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEECON, #00h; unmap EEPROM

; Restore EA

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

; Save and clear EA

MOV EECON, #050h

MOV EECON, #0A0h

; Restore EA

ret

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 20. EECON Register

EECON (S:0D2h)

EEPROM Control Register

Reset Val ue = XXXX XX00 b

Not bit address ab le

76543210

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Bit Number Bit

Mnemonic Description

7 - 4 EEP L3-0 Progr amming Launch Command bits

Write 5Xh followed by AXh to EEPL to launch the programming.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1EEE

Enable EEPROM Space b it

Set to map the EEPROM space during MOVX instructions (Write in the column

latches)

Clear to map the XRAM space during MOVX.

0EEBUSY

Progr amm ing Busy Flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

AT/T89C51CC02

4126L–CAN–01/08

Program/Code

Memory The T89C51CC02 implement 16K Bytes of on-chip program/code memory.

The Flash mem ory incr ease s EPRO M and ROM functio nality by in-cir cuit elec trical era-

sure and programming. Thanks to the internal charge pump, the high voltage needed for

programming or erasing Flas h cells is gene rated on-chip using the stan dard VDD volt-

age. Thus, the Flash memory can be programmed using only one voltage and allows In-

Syst em Pro gram ming (IS P). Hardwa re prog rammi ng mode is also avail able usi ng sp e-

cific programming tool.

Figure 12. Program/Code Memory Organization

Flash Memory

Architecture T89C51CC02 features two on-chip Flash memories:

•Flash memory FM0:

containing 16K Bytes of program memory (user space) organized into 128 bytes

pages,

•Flash memory FM1:

2K Bytes for boot loader and Application Programming Interfaces (API).

The FM0 can be program by both par allel programming and Seri al ISP whereas FM1

supports only par allel programming b y programmers. The ISP mod e is detailed in the

’In-System Programming’ section.

All Read/Write access operations on Flash memory by user application are managed by

a set of API described in the ’In-System Programming’ section.

Figure 13. Flash Memory Architecture

0000h

16K Bytes

3FFFh

Internal

Flash

3FFFh

16K Bytes

Flash Memory

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 Bytes)

User Space

Extra Row (128 Bytes)

2K Bytes

Flash Memory

FM1

Boot Space

FFFFh

F800h

FM1 mapped between F800h and

FFFFh when bit ENBOOT is set in

AUXR1 register

AT/T89C51CC02

4126L–CAN–01/08

FM0 Memory Architect ure The Flash memory is made up of 4 blocks (See Figure 13):

1. The memory array (user space) 16K Bytes

2. The Extra Row

3. The Hardware security bits

4. The column latch registers

User Space This space is composed of a 16K Bytes Flash memory organized in 128 pages of 128

Bytes. It contains the user’s application code.

Extra Row (XRow) This ro w is a part of FM0 and has a s ize o f 12 8 B yt es . The ex tra r ow may c on tain i nfo r-

mation for boot loader usage.

Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software, the 4 LSB can only be read by software and

written by hardware in parallel mode.

Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes).

The column latches are the entrance buffers of the three previous memory locations

(user array, XROW and Hardware security byte).

Cross Flash Memory Access

Description The FM0 memory can be programmed as describe on Table 21. Programming FM0

from FM0 is impos si bl e.

The FM1 memory can be program only by parallel programming.

Table 21 show all software Flash access allowed.

Table 21. Cross Flash Memory Access

Code executing from

Action FM0

(user Flash) FM1

(boot Fl ash)

FM0

(user Flash)

Read ok -

Load column latch ok -

Write - -

FM1

(boot Flash)

Read ok ok

Load column latch ok -

Write ok -

AT/T89C51CC02

4126L–CAN–01/08

Overview of FM0

Operations The CPU interfaces the Flash memory through the FCON register and AUXR1 register.

These regis ters are use d to:

• Map the memory spaces in the adressable space

• Launch the programming of the memory spaces

• Get the status of the Flash memory (busy/not busy)

Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column

latches space is made accessible by setting the FPS bit in FCON register. Writing is

possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a

page while bits 14 to 7 are used to select the programming address of the page.

Setting FPS bit takes precedence on the EEE bit in EECON register.

The other memory spaces (user, extra row, hardware security) are made accessible in

the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-

dance with Table 22. A MOVC instruction is then used for reading these spaces.

Table 22. FM0 blocks Select bits

Launching Programming FPL 3:0 b its in FCO N regist er ar e used to s ecure the launc h of pr ogra mming. A s peci fic

sequence must be written in these bits to unlock the write protection and to launch the

programming. This sequence is 5xh followed by Axh. Table 23 summarizes the memory

spaces to program according to FMOD1:0 bits.

Table 23. Programming Spaces

Note: The sequence 5xh and Axh must be executing without instructions between them other-

wise the program mi ng is aborted .

Interrupts that may occur during programming time must be disabled to avoid any spuri-

ous exit of the programming mode.

FMOD1 FMOD0 FM0 Adressable Space

0 0 User (0000h-3FFFh)

0 1 Extra Row(FF80h-FFFFh)

1 0 Hardware Security Byte (0000h)

11Reserved

Wr ite to FCON

OperationFPL3:0 FPS FMOD1 FMOD0

User

5 x 0 0 No act ion

Ax00

Write the column latches in user

space

Extr a Row

5 x 0 1 No act ion

Ax01

Write the column latches in extra row

space

Hardware

Security

Byte

5 x 1 0 No act ion

A x 1 0 Write the fuse bits space

Reserved 5 x 1 1 No act ion

A x 1 1 No act ion

AT/T89C51CC02

4126L–CAN–01/08

Status of the Flash Memory The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.

Loading the Column Latches An y num ber of data fr om 1 by te to 1 28 B yt es ca n be lo ade d i n the c olu mn latc he s. T his

provides the capability to program the whole memory by byte, by page or by any number

of Bytes in a page.

When progra mmin g is laun ched , an aut omati c eras e of the l ocatio ns lo aded in the co l-

umn latches is first performed, then programming is effectively done. Thus no page or

block erase is needed and only the loaded data are programmed in the corresponding

page.

The following procedure is used to load the column latches and is summarized in

Figure 14:

• Save then disable interrupt and map the column latch space by setting FPS bit.

• Load the DPTR with the address to load.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• If needed loop the three last instructions until the page is completely loaded.

• unmap the column latch and Restore Interrupt

AT/T89C51CC02

4126L–CAN–01/08

Figure 14. Column Latches Loading Procedure(1)

Note: 1. The last page address used when loading the column latch is the one used to select

the page programming address.

Programming the Flash Spaces

User The following procedure is used to program the User space and is summarized in

Figure 15:

• Load up to one page of data in the column latches from address 0000h to 3FFFh.

• Save then disable the interrupts.

• Launch the programming by writing the data sequence 50h followed by A0h in

FCON register.This step must be executed from FM1.

The end of the programming indicated by the FBUSY flag cleared.

• Restore the interrupts.

Extra Row The foll owing proc edure is used to pr ogram the E xtra Row spa ce and i s summar ized in

Figure 15:

• Load data in the column latches from address FF80h to FFFFh.

• Save then disable the interrupts.

• Launch the programming by writing the data sequence 52h followed by A2h in

FCON register. This step of the procedure must be executed from FM1.

The end of the programming indicated by the FBUSY flag cleared.

• Restore the interrupts.

Column Latches

Data Load

DPTR = Address

ACC = Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Column Latches Mapping

FCON = 08h (FPS = 1)

Data Memory Mapping

FCON = 00h (FPS = 0)

Save & Disable IT

EA = 0

Restore IT

AT/T89C51CC02

4126L–CAN–01/08

Figure 15. Flash and Extra row Programming Procedure

Hardware Security Byte The following procedure is used to program the Hardware Security Byte space

and is summarized in Figure 16:

• Set FPS and map Hardware byte (FCON = 0x0C)

• Save then disable the interrupts.

• Load DPTR at address 0000h.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• Launch the programming by writing the data sequence 54h followed by A4h in

FCON register. This step of the procedure must be executed from FM1.

The end of the programming indicated by the FBusy flag cleared.

• Restore the interrupts

Flash Spaces

Programming

Save & Disable IT

EA = 0

Launch Programmi ng

FCON = 5xh

FCON = Axh

End Programming

Restore IT

Colum n La tch es Load i n g

See Figure 14

FBusy

Cleared?

Clear Mode

FCON = 00h

AT/T89C51CC02

4126L–CAN–01/08

Figure 16. Hardware Programming Procedure

Reading the Flash Spaces

User The following procedure is used to read the User space:

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR is

the address of the code byte to read.

Note: FCON must be cleared (00h) when not used.

Extra Row The following procedure is used to read the Extra Row space and i s summarized in

Figure 17:

• Map the Extra Row space by writing 02h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= FF80h to FFFFh.

• Clear FCON to unmap the Extra Row.

Hardware Security Byte The following procedure is used to read the Hardware Security Byte and is sum-

marized in Figure 17:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= 0000 h.

• Clear FCON to unmap the Hardware Security Byte.

Flash Spaces

Programming

Save & Disable IT

EA = 0

Launch Programming

FCON = 54h

FCON = A4h

End Programming

RestoreIT

FBusy

Cleared?

Clear Mode

FCON = 00h

Data Load

DPTR = 00h

ACC = Data

Exec: MOVX @DPTR, A

FCON = 0Ch

Save & Disable IT

EA = 0

End Loading

Restore IT

AT/T89C51CC02

4126L–CAN–01/08

Figure 17. Reading Procedure

Note: aa = 10 for the Hardware Security Byte.

Flash Protection from Parallel

Programming The three lock bits in Hardware S ecurity Byte (See ’In-System Programmi ng’ section)

are programmed according to Table 24 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 3.

Table 24. Program Lock bit

Note: 1. Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core

verification.

Preventing Flash Corruption See Section “Power Management”.

Flash Spaces Reading

Flash Spaces Mapping

FCON = 00000aa0b

Data Read

DPTR = Addr ess

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

Program Lock bits

Protection Description

Security

Level LB0 LB1 LB2

1 U U U No program lock features enabled.

2 P U U Parallel programming of the Flash is disabled.

3UPU

Same as 2, also verify through parallel programming interface is

disabled. This is the factory defaul programming.

4UUPSame as 3

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 25. FC ON Regis ter

FCON Register FCON (S:D1h)

Flash Control Register

Reset Value = 0000 0000b

76543210

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

Bit

Number Bit

Mnemonic Description

7 - 4 FPL3:0 Programming Launch Command bits

Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(See Table 23.)

3FPS

Flash Map Program Space

Set to map the column latch space in the data memory space.

Clear to re-map the data memory space.

2 - 1 FMO D1:0 Flash Mode

See Table 22 or Table 23.

0FBUSY

Flash Busy

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be changed by software.

AT/T89C51CC02

4126L–CAN–01/08

AT/T89C51CC02

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Operation Cross

Memory Access Space addressable in read and write are:

•RAM

• ERAM (Expanded RAM access by movx)

• EEPROM DATA

• FM0 ( user flash )

• Hardware by te

•XROW

•Boot Flash

• Flash Column latch

The tab le below prov ides the differen t kind o f m emory wh ich can be acces sed f rom dif-

ferent code location.

Note: 1. RWW: Read While Write

Table 26. Cros s Memory Access

Action RAM ERAM Boot FLASH FM0 E² Data Hardware

Byte XROW

boot FLASH Read OK OK OK OK -

Write - OK(1) OK(1) OK(1) OK(1)

FM0 Read OK OK OK -OK -

Write - OK (idle) OK(1) --OK

AT/T89C51CC02

4126L–CAN–01/08

Sharing Instructions Table 27. Instructions sha r ed

Note: by cl : usin g Column Latch

Table 28. Read MOVX A, @DPTR

Table 29. Write MOVX @DPTR,A

Action RAM ERAM EEPROM

DATA Boot

FLASH FM0 Hardware

Byte XROW

Read MOV MOVX MOVX MOVC MOVC MOVC MOVC

Write MOV MOVX MOVX - by cl by cl by cl

EEE bit in

EECON

FCON Register ENBOOT ERAM EEPROM

DATA

Flash

Column

Latch

00XOK

01XOK

10X OK

11XOK

EEE bi t in

EECON

FCON Register ENBOOT ERAM EEPROM

Data

Flash

Column

Latch

00XOK

01X OK

10X OK

11X OK

AT/T89C51CC02

4126L–CAN–01/08

Table 30. Read MOVC A, @DPTR

Code Execution

FCON Register

ENBOOT DPTR FM1 FM0 XROW Hardware

ByteFMOD1 FMOD0 FPS

From FM0

00X

0 0000h to 3FFFh OK

10000h to 3FFFh OK

F800h to FFFFh Do not use this configuration

01X X

0000 to 007Fh

See (1) OK

10X X X OK

11X

0 000h to 3FFFh OK

10000h to 3FFFh OK

F800h to FFFFh Do not use this configuration

From FM1

(ENBOOT =1

010000h to 3FFF OK

F800h to FFFFh OK

0X NA

11X OK

0X NA

01X 10000h to 007h

See (2)

0NA

10X 1XOK

0NA

11X 1000h to 3FFFh OK

0NA

1. For DP TR h igher th an 007 Fh only lo wes t 7 bit s are decod ed, thus the be havior is the sa me as for addre sses from

0000h to 007Fh

2. For DP TR h igher th an 007 Fh only lo wes t 7 bit s are decod ed, thus the be havior is the sa me as for addre sses from

0000h to 007Fh

AT/T89C51CC02

4126L–CAN–01/08

In-System

Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash

technology the T89C51CC02 allows the system engineer the development of applica-

tions wi th a very high l evel of f lexib ility . Th is flexi bilit y is bas ed on t he p ossibi lity t o alter

the customer program at any stages of a product’s life:

• Before mounting the chip on the PCB, FM0 flash can be programmed with the

application code. FM1 is always preprogrammed by Atmel with a bootloader (chip

can be ordered with CAN bootloader or UART bootloader).(1)

• Once the chip is mounted on the PCB, it can be programmed by serial mode via the

CAN bus or UART.

Note: 1. The user can also program his own bootloader in FM1.

This ISP allows code modification over the total lifetime of the product.

Besides the default Bootloa ders Atmel prov ide customers all the nee ded Application-

Progr amm ing -Inter fa ce s (A PI) wh ic h are nee ded for the ISP . T he AP I a re loc at ed i n th e

Boot memory.

This allow the customer to have a full use of the 16-Kbyte user memory.

Flash Programming and

Erasure There are three methods for programming the Flash memory:

• The Atmel bootloader located in FM1 is activated by the application. Low level API

routines (located in FM1)will be used to program FM0. The interface used for serial

downloading to FM0 is the UART or the CAN. API can be called also by user’s

bootloader located in FM0 at [SBV]00h.

• A further method exist in activating the Atmel boot loader by hardware activation.

See the Section “Hardware Security Byte”.

• The FM0 can be programmed also by the parallel mode using a programmer.

Figure 18. Flash Memory Mapping

F800h

3FFFh

16K Bytes

Flash Memo ry

2K Bytes IAP

Bootloader

FM0

FM1

Custom

Bootloader

[SBV]00h

FFFFh

FM1 Mapped between F800h and FFFF

when API Called

0000h

AT/T89C51CC02

4126L–CAN–01/08

Boot Process

Software Boot Process

Example Many algorithms can be used for the software boot process. Below are descriptions of

the different flags and Bytes.

Boot Loader Jump bit (BLJB):

- This bi t indicates if on RES ET the user wa nts to jump to this applicat ion at ad dress

@0000h on FM0 or execute the boot loader at address @F800h on FM1.

- BLJB = 0 (i.e. boo tloader FM1 e xecut ed after a res et) is t he defau lt Atm el fac tory pro-

gramming.

-To read or modify this bit, the APIs are used.

Boot Vector Address (SBV):

- This byte contains the MSB of the user boot loader address in FM0.

- The default value of SBV is FCh (no user boot loader in FM0).

- To read or modify this byte, the APIs are used.

Extra Byte (EB) & Boot Status Byte (BSB):

- These Bytes are reserved for customer use.

- To read or modify these Bytes, the APIs are used.

Figure 19. Hardware Boot Process Algorithm

Application-

Programming-Interface Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

by functions.

All these APIs are described in detail in the following documents on the Atmel web site.

– Datasheet Bootloader CAN T89C51CC02.

– Datasheet Bootloader UART T89C51CC02.

RESET

BLJB == 0

Hardware

Software

Bootloader

in FM1

Application

in FM0

bit ENBOOT in AUXR1 Register

Is Initialized with BLJB Inverted.

ENBOOT = 0

PC = 0000h

ENBOOT = 1

PC = F800h

Example, if BLJB=0, ENBOOT

is set (=1) during reset, thus the

bootloader is executed after the

reset.

AT/T89C51CC02

4126L–CAN–01/08

XROW Bytes The EXTRA ROW (XRO W) incl udes 128 bytes. Some of these bytes are us ed for spe-

cific purpose in conjonction with the bootloader.

Table 31. XROW Mapping

Hardware Conditions It is poss ible to force th e controller to ex ecute the bootl oader after a Res et with hard-

ware conditions.

During the first programming, the user can define a configuration on Port1 that will be

recognized by the chip as the hardware conditions during a Reset. If this condition is

met, the chip will start executing the bootloader at the end of the Reset.

See a detailed description in the applicable Document.

– Datasheet Bootloader CAN T89C51CC02.

– Datasheet Bootloader UART T89C51CC02.

Description Default Value Address

Copy of the Manufacturer Code 58h 30h

Copy of the Device ID#1: Family code D7h 31h

Copy of the Device ID#2: Memories size and type BBh 60h

Copy of the Device ID#3: Name and Revision FFh 61h

AT/T89C51CC02

4126L–CAN–01/08

Hardware Security Byte Table 32. Hardware Security byte

After erasing the chip in parallel mode, the default value is : FFh

The erasing in ISP mode (from bootloader) does not modify this byte.

Notes: 1. Only the 4 MSB bits can be accessed by software .

2. The 4 LSB bits can only be accessed by parallel mode.

76543210

X2B BLJB - - - LB2 LB1 LB0

Bit

Number Bit

Mnemonic Description

7X2B

X2 bit

Set this bit to start in standard mode

Clear this bit to start in X2 Mode.

6BLJB

Boot Loader Jum p bit

- 1: To start the user ’s application on next RESET (@0000h) located in FM0,

- 0: To start the boot loader(@F800h) located in FM1.

5 - 3 - Reserved

The value read from these bits are indeterminate.

2 - 0 L B 2:0 Lock bits (see Table 22)

AT/T89C51CC02

4126L–CAN–01/08

Seria l I/ O P o rt The T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Async hronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Figure 20. Serial I/O Port Block Diagram

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 21. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON registe r bit is set.

The software m ay examine the FE bit after each reception to check for data errors.

Once set, on ly s oftwa re o r a r eset c lea rs t he FE b it. Su bs equ entl y r ec eived fr am es wi th

valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the

stop bit instead of the last data bit (See Figure 22 and Figure 23).

Write SBUF

RI TI

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode 0 Transmit

Receive

Shift register

Load SBUF

Read SBUF

SCON reg

Interrupt Request

Serial Port

TXD

RXD

RITIRB8TB8RENSM2SM1

SM0/FE

IDLPDGF0GF1POF-SMOD0

SMOD1

To UART Framing Error Control

SM0 to UART Mode Control

Set FE bit if Stop bit is 0 (Framing Error)

AT/T89C51CC02

4126L–CAN–01/08

Figure 22. UART Timing in Mode 1

Figure 23. UART Timing in Mod es 2 and 3

Automatic Addres s

Recognition The aut oma tic a ddr es s r ec ogn iti on feat ure i s en abl ed when th e m ul tiproce ssor c om mu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in the hardware, automatic address recognition enhances the multiproces-

sor communication feature by allowi ng the serial port to examine the addr ess of each

incoming command frame. Only when the serial port recognizes its own address will the

receiver set the RI bit in the SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If necessar y, the user can enab le the automati c addres s recogniti on feature in mode 1.

In this configuration, the stop bit takes the place of the ninth data bit. bit RI is set only

when the rece iv ed co mmand frame addres s ma tch e s the de vic e’s addre ss and is term i-

nated by a valid stop bit.

To supp ort automatic a ddr ess re co gni tio n, a dev ic e i s ide nti fie d by a given addre ss an d

a broadcast address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

Given Address Each device has an individual address that is specified in the SADDR register; the

SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form

the device’s given address. The don’t-care bits provide the flexibility to address one or

more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

Data Byte

SMOD0 = x

Stop

bit

Start

bit

RXD D7D6D5D4D3D2D1D0

SMOD0 = 1

SMOD0 = 0

Data Byte Ninth

bit Stop

bit

Start

bit

RXD D8D7D6D5D4D3D2D1D0

SMOD0 = 1

AT/T89C51CC02

4126L–CAN–01/08

Here is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0011b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

munic ate with slave A o nly, the ma ster must send an addre ss wher e bit 0 is clea r (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Given1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the s lave s, the ma ster mus t send a n add ress F Fh. To com mun icate with slav es A

and B, but not slave C, the master can send and address FBh.

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 33. SCON Register

SCON (S:98h)

Serial Control Register

Reset Value = 0000 0000b

bit addressable

76543210

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number Bit

Mnemonic Description

FE Framing Error bit (SMOD0 = 1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SM0 Serial port Mode bit 0 (SMOD0 = 0)

Refer to SM1 for serial port mode selection.

6SM1

Seria l por t Mode bit 1

SM0 SM1 Mode Baud Rate

0 0 Shift Register FXTAL/12 (or FXTAL/ 6 in mode X2)

0 1 8-bit UART Variable

1 0 9bit UART FXTAL/64 or FXTAL/32

1 1 9bit UART Variable

5SM2

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

4REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

3TB8

Tran smitter bit 8/Ninth bit to Transmit in Modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

2RB8

Receiver bit 8/Ninth bit Received in Modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

1TI

Transmit Interrupt Flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

0RI

Receive Interrupt Flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and

Figure 23. in the other modes.

AT/T89C51CC02

4126L–CAN–01/08

Table 34. SADEN Register

SADEN (S:B9h)

Slave Address Mask Register

Reset Value = 0000 0000b

Not bit address ab le

Table 35. SADDR Register

SADDR (S:A9h)

Slave Address Register

Reset Value = 0000 0000b

Not bit address ab le

Table 36. SBUF Register

SBUF (S:99h)

Serial Data Buffer

Reset Value = 0000 0000b

Not bit address ab le

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Mask Data for Slave Individual Address

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Slave Individual Address

76543210

Bit

Number Bit

Mnemonic Description

7 - 0 Data sent/received by Serial I/O Port

AT/T89C51CC02

4126L–CAN–01/08

Table 37. PCON Register

PCON (S:87h)

Power Control Register

Reset Value = 00X1 0000b

Not bit address ab le

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Seria l por t Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Seria l por t Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-off F lag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by

software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle Mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT/T89C51CC02

4126L–CAN–01/08

Timers/Counters The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are

identi fied as Tim er 0 and Timer 1, an d can be in depende ntly confi gured to oper ate in a

variety of modes as a Timer or an event Counter. When operating as a Timer, the

Timer/Counter runs for a programmed length of time, then issues an interrupt request.

When oper ating as a Coun ter, the Timer /Counter counts n egative transit ions on an

external pin. After a preset number of counts, the Counter issues an interrupt request.

The v arious o perating m odes of each Time r/Counter are des cribed in the foll owing

sections.

Timer/Counter

Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to

form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (See Figure 38)

turns the Timer on by allowing the selected input to increment TLx. When TLx overflows

it incre ments THx; when THx overflows it sets th e Timer overfl ow flag (TFx) i n TCON

ters can be acc essed to obtai n the cur rent count or to enter pres et value s. They ca n be

read at any time but TRx bit must be cleared to preset their values, otherwise the behav-

ior of the Timer/Counter is unpredictable.

The C/Tx# control bit selects Timer oper ation or Counter operation by selecting the

divided-down peripher al clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when changing the mode of operation, otherwise the behavior

of the Timer/Counter is unpredictable.

For T imer oper atio n ( C/Tx# = 0 ), t he Ti mer regi ster co unts the divid ed-d own periph era l

clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock

periods). The Timer clock rate is fPER/6, i.e. f OSC/12 in standa rd mode or fOSC/6 i n X2

Mode.

For Count er oper ati on (C/T x # = 1), the T imer reg ister cou nts t he neg ative tran si tions on

the Tx external input pin. The external input is sampled every peripheral cycles. When

the sample is high in one cycle and low in the next one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,

the maximum count rate is fPER/12, i.e. fOSC/24 in standard mode or fOSC/12 in X2 Mode.

There are no restrictions on the duty cycle of the external input signal, but to ensure that

a given l evel is s ampled at leas t once before it changes , it should be held for at l east

one full peripheral cycle.

Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 24 through Figure 27 show the logical configuration of each mode.

Timer 0 is contr ol led by the four l ower bi ts of TMO D regi s ter (S ee Figu re 39) an d bi ts 0,

1, 4 and 5 of TCON register (See Figure 38). TMOD register selects the method of

Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10

and M00) . TCON register provides Timer 0 c ontrol functions: o verflow fla g (TF0), run

control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For norm al Tim er ope ration ( GATE 0 = 0), settin g TR0 allows TL0 to be inc reme nted by

the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-

rupt reque st.

It is important to stop Timer/Counter before changing mode.

AT/T89C51CC02

4126L–CAN–01/08

Mode 0 (13-bit Timer) Mode 0 co nfigures Timer 0 as an 13-bit Tim er which is set up a s an 8-bit Ti mer (TH0

(See Figure 24). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register.

Figure 24. Timer/Counter x (x= 0 or 1) in Mode 0

Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (See Figure 25). The selected input increments TL0 register.

Figure 25. Timer/Counter x (x= 0 or 1) in Mode 1

Mode 2 (8-bit Timer with Auto-

Reload) Mode 2 con figures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (See Figure 26). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

reques t is ser viced , hard ware clears TF0. The re load l eaves T H0 un chang ed. The nex t

reload value may be changed at any time by writing it to TH0 register.

FTx

CLOCK

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

÷ 6 Overflow Timer x

Interrupt

Request

C/Tx#

TMOD Reg

TLx

(5 bits)

THx

(8 bits)

INTx#

See section “Clock”

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow Timer x

Interrupt

Request

C/Tx#

TMOD R eg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See se ctio n “Clock”

AT/T89C51CC02

4126L–CAN–01/08

Figure 26. Timer/Counter x (x= 0 or 1) in Mode 2

Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (See Figure 27). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer func tion (counti ng FPER /6) and takes over use of the Timer 1 in terrupt (TF1 ) and

run contro l (TR1) bits. T hus, operation of T imer 1 is restric ted when Timer 0 is in mode

Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit Counters

Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-

ing comments help to understand the differences:

• Timer 1 functions as either a Timer or event Counter in three m odes of operati on.

Figure 24 to Figure 26 show the logical configuration for modes 0, 1, and 2. Timer

1’s mode 3 is a hold-count mode.

• Timer 1 is controlled by the four high-order bits of TMOD register (See Figure 39)

and bits 2, 3, 6 and 7 of TCON register (See Figure 38). TMOD register selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

TRx

TCON Reg

TFx

TCON Reg

GATEx

TMOD Reg

Overflow Timer x

Interrup

Reques

C/Tx#

TMOD Reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

See section “Clock”

TR0

TCON.4

TF0

TCON.5

INT0#

GATE0

TMOD.3

Overflow Timer 0

Interrup

Reques

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits) TF1

TCON.7

Overflow Timer 1

Interrup

Reques

FTx

CLOCK ÷ 6

FTx

CLOCK ÷ 6

See section “Clock”

AT/T89C51CC02

4126L–CAN–01/08

• For normal Ti mer operation (GATE1= 0), setting TR1 allows TL1 to be incremented

by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control

Timer operation.

• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

• When Timer 0 is in mode 3, it uses T imer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

• It is important to stop Timer/Counter before changing mode.

Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(See Fi gure 24). The upper 3 bits of T L1 regi ster are i gnore d. Pres cale r over flow in cre-

ments TH1 register.

Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (See Figure 25). The selected input increments TL1 register.

Mode 2 (8-bit Timer with Auto-

Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

TH1 r egi ster on ove rflow (Se e F igure 26). T L1 overfl ow s ets TF1 flag in TCO N r egist er

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

Mode 3 (Halt) Placi ng Timer 1 in mode 3 c auses it to ha lt and hold i ts count. Thi s can be used to hal t

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is se t eve ry tim e an ov erfl ow oc cur s. Fla gs are cl eared when v ec torin g to the Ti mer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes

interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 28. Timer Interrupt System

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 38. TC ON Regis ter

TCON (S:88h)

Timer/Counter Control Register

Reset Value = 0000 0000b

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6TR1

Timer 1 Run Control bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer /Counter 1.

5TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4TR0

Timer 0 Run Control bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer /Counter 0.

3IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (See IT1).

Set by hardware when external interrupt is detected on INT1# pin.

2IT1

Interrupt 1 Type Control bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (See IT0).

Set by hardware when external interrupt is detected on INT0# pin.

0IT0

Interrupt 0 Type Control bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

AT/T89C51CC02

4126L–CAN–01/08

Table 39. TMOD Register

TMOD (S:89h)

Timer/Counter Mode Control Register

Reset Value = 0000 0000b

Notes: 1. Reload ed from TH1 at overflo w.

2. Reload ed from TH0 at overflo w.

Table 40. TH0 Register

TH0 (S:8Ch)

Timer 0 High Byte Register

Reset Value = 0000 0000b

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit

Number Bit

Mnemonic Description

7GATE1

Timer 1 Gating Control bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer Select bit

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: T imer 1 counts negative transitions on external pin T1.

5M11Timer 1 Mode Select bits

M11 M01 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5bit prescaler (TL1).

0 1 Mode 1: 16-bit Timer/Counter.

1 1 Mode 3: Timer 1 halted. Retains count.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1)

4M01

3GATE0

Timer 0 Gating Control bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2C/T0#

Timer 0 Counter/Timer Select bit

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: T imer 0 counts negative transitions on external pin T0.

1M10

Timer 0 Mode Select bit

M10 M00 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5bit prescaler (TL0).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)

1 1 Mode 3: TL0 is an 8-bit Timer/Counter.

TH0 is an 8-bit Timer using Ti m er 1’s TR0 and TF0 bits.

0M00

76543210

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 0

AT/T89C51CC02

4126L–CAN–01/08

Table 41. TL0 Register

TL0 (S:8Ah)

Timer 0 Low Byte Register

Reset Value = 0000 0000b

Table 42. TH1 Register

TH1 (S:8Dh)

Timer 1 High Byte Register

Reset Value = 0000 0000b

Table 43. TL1 Register

TL1 (S:8Bh)

Timer 1 Low Byte Register

Reset Value = 0000 0000b

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 0

76543210

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 1

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 1

AT/T89C51CC02

4126L–CAN–01/08

Timer 2 The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eightbit timer registers, TH2

and TL2 that ar e cascad e-co nnecte d. It is contr olled by T2 CON regis ter (See Table 45)

and T2MOD register (See Table 46). Timer 2 operation is similar to Timer 0 and Timer

1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

• Auto-reload mode (up or down counter)

• Programmable clock-output

Auto-Reload Mode The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-

matic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table

45). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 29. In

this mode the T2EX pin controls the counting direction.

When T2EX is high, Timer 2 counts up. Time r overflow occurs at FFFFh which sets the

TF2 fl ag a nd g ener ates an interr upt reques t. T he overfl ow a lso c ause s th e 16 -bit v alu e

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflow or underflow, depending on the direction of

the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit

resolution.

Figure 29. Auto-Reload Mode Up/Down Counter

(DOWN COUNTING RELOAD VALUE)

TF2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(8-bit)

FFh

(8-bit) FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

TIMER 2

INTERRUPT

T2CON Reg

T2EX:

1=UP

2=DOWN

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

See section “Clock”

AT/T89C51CC02

4126L–CAN–01/08

Programmable Clock-

Output In cloc k-ou t mode, Tim er 2 ope ra tes as a 50 %-d uty- cycl e, progr am ma ble c lock ge nera-

tor (Figure 30). The input clock increments TL2 at frequency fOSC/2. The timer

repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H

and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do

not generate interrupts. The formula gives the clock-out frequency depending on the

system oscill ato r freque nc y and the value in the RCAP2H and RCAP2L registe rs:

For a 16 MHz system clock in x1 mode, Timer 2 has a programmable frequency range

of 61 Hz (fOSC/216) to 4 MHz (fOSC/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

•Clear C/T2

bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or different depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 30. Clock-Out Mode

Clock OutFrequency–FT2clock

4 65536 RCAP2H–RCAP2L⁄()×

-----------------------------------------------------------------------------------------

EXEN2

EXF2

OVERFLOW

T2EX

TH2

(8-bit)

TL2

(8-bit)

TIMER 2

RCAP2H

(8-bit)

RCAP2L

(8-bit)

T2OE

T2C ON re g

T2CON reg

T2MOD reg

INTERRUPT

TR2

T2CON.2

FT2

CLOCK

Q D

Toggle

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 44. T2CON Register

T2CON (S:C8h)

Timer 2 Control Register

Reset Value = 0000 0000b

bit addressable

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number Bit

Mnemonic Description

7TF2

Timer 2 Overflow Flag

TF2 is not set if RCLK=1 or TCLK = 1.

Must be cleared by software.

Set by hardware on Timer 2 overflow.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2

interrupt is enabled.

Must be cleared by software.

5 RCLK Receive Clock bit

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run Control bit

Clea r to turn off Timer 2.

Set to tu rn on Timer 2.

1C/T2#

Timer/Counter 2 Select bit

Clear for timer operation (input from internal clock system: fOSC).

Set for counter operation (input from T2 input pin).

0 CP/RL2#

Timer 2 C a pture / R e load b it

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

Timer 2 overflow.

Clear to auto-reload on T imer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

AT/T89C51CC02

4126L–CAN–01/08

Table 45. T2MOD Register

T2MOD (S:C9h)

Timer 2 Mode Control Register

Reset Val ue = XXXX XX00 b

Not bit address ab le

Table 46. TH2 Register

TH2 (S:CDh)

Timer 2 High Byte Register

Reset Value = 0000 0000b

Not bit address ab le

76543210

------T2OEDCEN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1T2OE

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

0 DCEN Down Counter Enable bit

Clear to disable Ti mer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 High Byte of Timer 2

AT/T89C51CC02

4126L–CAN–01/08

Table 47. TL2 Register

TL2 (S:CC h)

Timer 2 Low Byte Register

Reset Value = 0000 0000b

Not bit address ab le

Table 48. RCAP2H Register

RCAP2H (S:CBh)

Timer 2 Reload/Capture High Byte Register

Reset Value = 0000 0000b

Not bit address ab le

Table 49. RCAP2L Register

RCAP2L (S:CAh) Timer 2 Reload/Capture Low Byte Register

Reset Value = 0000 0000b

Not bit address ab le

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Low Byte of Timer 2

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 High Byte of Timer 2 Reload/Capture.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - 0 Low Byte of Timer 2 Reload/Capture.

AT/T89C51CC02

4126L–CAN–01/08

Watchdog Timer T89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that

automatically resets the chip if it software fails to reset the WDT before the selected time

interval has elapsed. It permits large Timeout ranging from 16ms to 2s @fOSC = 12 MHz

in X1 mode.

This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog

Timer re se t r egister (WDT RST ) a nd a Wa tch dog T ime r pr ogram ming (WD TPRG ) regi s-

ter. When exiting reset, the WDT is -by default- disable.

To enabl e the WDT, the user has to wr ite the sequence 1E H and E 1H into WDTRST

enabled, it will increment every machine cycle while the oscillator is running and there is

no way to disable the WDT except through reset (either hardware reset or W DT over-

flow reset). When W DT overflows, it will generate an output RESET puls e at the RST

pin. The RESET pulse duration is 96xTOSC, where TOSC=1/fOSC. To make the best use of

the WDT, i t should be serviced i n those sec tions of c ode that will periodicall y be exe-

cuted within the time required to prevent a WDT reset

Note: When the watchdog is enable it is impossible to change its period.

Figure 31. Watchdog Timer

WDTPRG

RESET Decoder

Control

WDTRST

Enable

14-bit Counter 7-bit Counter

Outputs

Fwd Clock

RESET

- - -

- - 2 1 0

AT/T89C51CC02

4126L–CAN–01/08

Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.

Table 50. Machine Cycle Count

To compute WD Timeout, the following formula is applied:

Note: Svalue represents the decimal value of (S2 S1 S0)

Find Hereafter computed Timeout values for fOSCXTAL = 12 MH z in X1 mode

Table 51. Timeout Computat ion

S2 S1 S0 Machine Cycle Count

000 2

14 - 1

001 2

15 - 1

010 2

16 - 1

011 2

17 - 1

100 2

18 - 1

101 2

19 - 1

110 2

20 - 1

111 2

21 - 1

S2 S1 S0 fOSC=12 MHz fOSC=16MHz fOSC=20 M Hz

0 0 0 16.38 ms 12.28 ms 9.82 ms

0 0 1 32.77 ms 24.57 ms 19.66 ms

0 1 0 65.54 ms 49.14 ms 39.32 ms

0 1 1 131.07 ms 98.28 ms 78.64 ms

1 0 0 262.14 ms 196.56 ms 157.28 ms

1 0 1 524.29 ms 393.12 ms 314.56 ms

1 1 0 1.05 s 786.24 ms 629.12 ms

1 1 1 2.10 s 1.57 s 1.25 s

FTime Out Fosc

62×WDX2X2∧214 2Svalue

×()

-----------------------------------------------------------------------------

=–

AT/T89C51CC02

4126L–CAN–01/08

Watchdog Timer

During Power-down

Mode and Idle

In Power-down m ode the osc illator stops, whi ch means th e WDT also s tops. While i n

Power-down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enabl ed p rior to e nterin g Po wer-do wn mo de. W hen Powe r-down is e xited wit h

hardware reset, the watchdog is disabled. Exiting Power-down with an interrupt is signif-

icantly different. The interrupt shall be held low long enough for the oscillator to stabilize.

When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from

resetting the device while the interrupt pin is held low, the WDT is not started until the

interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service

for the interrupt used to exit Power-down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting

T89C51CC02 while in Idle mode, the user should always set up a timer that will periodi-

cally exit Idle, service the WDT, and re-enter Idle mode.

WDTPRG (S:A7h) – Watchdog Timer Duration Programming register

Reset Val ue = XXXX X000b

76543210

-----S2S1S0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2S2

Wa tchdog T imer Duratio n selection bit 2

Work in conjunction with bit 1 and bit 0.

1S1

Wa tchdog T imer Duratio n selection bit 1

Work in conjunction with bit 2 and bit 0.

0S0

Wa tchdog T imer Duratio n selection bit 0

Work in conjunction with bit 1 and bit 2.

AT/T89C51CC02

4126L–CAN–01/08

Table 53. WDTRST Register

WDTRST (S:A6h Write Only) – Watchdog Timer Enable register

Reset Value = 1111 1111b

Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in

sequence without instruction between these two sequences.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - Watchdog Control Value

AT/T89C51CC02

4126L–CAN–01/08

CAN Controller The CAN Cont ro ller pr ovid es al l th e fe atu re s re qui re d to im pl eme nt th e s eria l c om mun i-

cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to

by ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed. The CAN

Controll er is ab le to ha ndle al l typ es of fram es (D ata, Remo te, Erro r and Ov erload) and

achieves a bitrate of 1-Mbit/s at 8 MHz1 Crystal frequency in X2 Mode.

Note: 1. At BRP = 1 sampling point will be fixed.

CAN Protocol The CAN pr otocol is an interna tiona l stand ard define d in the ISO 11898 for high sp eed

and ISO 11519-2 for low speed.

Principles CAN is based on a broadcast communication mechanism. This broadcast communica-

tion is achieved by using a message oriented transmission protocol. These messages

are identified by using a message identifier. Such a message identifier has to be unique

within the whole network and it defines not only the content but also the priority of the

message.

The priority at which a message is transmi tted compared to another less urgent mes-

sage is spe cifie d by th e iden tifier of ea ch message. The priorities are laid down during

system design in the form of corresponding binary values and cannot be changed

dynamically. The identifier with the lowest binary number has the highest priority.

Bus acc ess co nflicts ar e resolved by bit-wis e arbitrati on on the i dentifier s involved by

each node observing the bus level bit for bit. This happens in accordance with the "wired

and" m echanism, b y w hic h t he d omi nan t state ove rw rit es the r ece ss i ve sta te. T h e c om-

petit ion for bus alloc ation is l ost by a ll node s wi th r ecessiv e tr ansmis sion a nd do minan t

obser vation. All t he "los ers" a utomati cally become rece ivers of the mess age wi th the

highest priority and do not re-attempt transmission until the bus is available again.

Message Formats The CAN protocol supports two messa ge frame formats, the o nly essential difference

being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A,

suppor ts a l ength of 11 bit s for the i denti fier, a nd the C AN exte nded frame , also know n

as CAN 2.0 B, supports a length of 29 bits for the identifier.

Can Standard Frame

Figure 32. CAN Standard Fra mes

A message in the CAN standard frame format begins with the "Start Of Frame (SOF)",

this is followed by the "Arbitration field" which consist of the identifier and the "Remote

Transmission Reque st (RTR)" bit u sed to distinguish between the data fram e and the

data request frame called remote frame. The following "Control field" contains the "IDen-

tifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the

11-bit identifier

ID10..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

0 - 8 bytes

SOF

SOF RTR IDE r0 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Arbitration

Field Data

Field

Data Frame

Control

Field End of

Frame

CRC

Field ACK

Field Interframe

Space

11-bit identifier

ID10..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

SOF

SOF RTR IDE r0 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Arbitration

Field

Remote Frame

Control

Field End of

Frame

CRC

Field ACK

Field Interframe

Space

AT/T89C51CC02

4126L–CAN–01/08

number of follow ing data by tes in the "D ata field ". In a remote frame, the DLC contai ns

the numbe r of reque sted data byt es. The "Data field" that fol lows can hol d up to 8 data

bytes . The fra me integrity is guar anteed by the follo wing "Cyc lic Redund ant Check

(CRC) " sum . The "A CKno wledg e (ACK ) field " comp romis es the ACK sl ot and the ACK

delimiter. The b it in t he A C K slot i s se nt as a re ce ss iv e bit and is ov erwr itt en a s a dom i-

nant bit by the receivers which have at this time received the data correctly. Correct

messages are acknowledged by the receivers regardless of the result of the acceptance

test. T he end of the mess age is in dicat ed by "E nd Of Fram e (EOF )". The " Inter missio n

Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If

there is no following bus access by any node, the bus remains idle.

CAN Extended Frame

Figure 33. CAN Extended F rames

A mess age i n the C AN ex tended frame format i s li kely t he sa me as a mes sage in CA N

standard frame format. The difference is the length of the identifier used. The identifier is

made up of the exi sting 11-bit id entifier (base id entifier ) and an 18-bit ext ension (iden ti-

fier exten si on). Th e d istin ct ion be tween CA N s tan dar d frame for ma t an d CA N e xtende d

frame for ma t is mad e by us ing the IDE bit whi ch is tr ansmi tted as dominan t in cas e o f a

frame in CAN standard frame format, and transmitted as recessive in the other case.

Format Co-existence As the two form ats have to co-exist on o ne bus, it is lai d down which message has

higher priority on the bus in the case of bus access collision with different formats and

the same identifier / base identifier: The message in CAN standard frame format always

has priority over the message in extended format.

There are three different types of CAN modules available:

– 2.0A - Considers 29 bit ID as an error

– 2.0B Passive - Ignores 29 bit ID messages

– 2.0B Active - Handles both 11 and 29 bit ID Messages

Bit Timing To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize

throughout the entire frame. This is done at the beginning of each message with the fall-

ing edge SOF and on each recessive to dominant edge.

Bit Construction One CAN bit tim e is specifi ed as four non-ov erlapp ing time segments . Each s egment is

construc ted f ro m an in tege r m ul tip le o f the T im e Quan tum. The Ti me Q u antu m or T Q is

the smallest discrete timing resolution used by a CAN node.

11-bit base identifier

IDT28..18

Interframe

Space

CRC

del. ACK

del.

15-bit CRC

0 - 8 bytes

SOF

SOF SRR IDE ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite

)

Arbitration

Field

Arbitration

Field Data

Field

Data Frame

Control

Field

Control

Field

End of

Frame

CRC

Field ACK

Field Interframe

Space

11-bit base identifier

IDT28..18

18-bit identifier extension

ID17..0

18-bit identifier extension

ID17..0

Interframe

Space

4-bit DLC

DLC4..0 CRC

del. ACK

del.

15-bit CRC

SOF

SOF SRR IDE r0

4-bit DLC

DLC4..0

RTR

r0r1

r1 ACK 7 bits Intermission

3 bits

Bus Idle Bus Idle

(Indefinite)

Remote Frame

End of

Frame

CRC

Field ACK

Field Interframe

Space

AT/T89C51CC02

4126L–CAN–01/08

Figure 34. CAN Bit Construction

Synchronization Segment The first segment is used to synchronize the various bus nodes.

On transm ission , at the start of thi s segme nt, the curren t bit leve l is output. If th ere is a

bit state c ha nge b etwe en th e pr ev io us bit and t he c urr ent b it, th en t he bu s s tat e ch ang e

is expected to occur within this segment by the receiving nodes.

Propagation Time Segment This segment is used to compensate for signal delays across the network.

This i s necessa ry to c ompensate for signa l propag ation del ays on the bus li ne and

through the transceivers of the bus nodes.

Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors.

This segment may be lengthened during resynchronization.

Sample Point The sample point is the point of time at which the bus level is read and interpreted as the

value of the respective bit. Its location is at the end of Phase Segment 1 (between the

two Phase Segme nts ).

Phase Segment 2 This segment is also used to compensate for edge phase errors.

This segm ent may be shortened during resynchroniza tion, but the length has to be at

least as long as the information processing time and may not be more than the length of

Phase Segment 1.

Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit.

The Info rmation processin g Time begin s at the sam ple point , is measur ed in TQ and is

fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample

point and is the l ast se gment i n the bit tim e, Pha se Segme nt 2 minimum shall not b e

less than the Information processing Time.

Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Seg-

ment 2 may be s hortened to compensa te for oscillator tolerances. If, for example, the

transmitte r oscil lator is slower tha n the recei ver osci llator , the next fal ling edge used for

resynchronization may be delayed. So Phase Segment 1 is lengthened in order to

adjust the sample point and the end of the bit time.

Time Quantum

(producer)

Nominal CAN Bit Time

Segments

(producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2

propagation

delay

Segments

(consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2

Sample Point

Transmission Point

(producer)

CAN Frame

(producer)

AT/T89C51CC02

4126L–CAN–01/08

Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next

fallin g edge use d for resy nchroni zation may be too ear ly. So Pha se Segm ent 2 in bit N

is shortened in order to adjust the sample point for bit N+1 and the end of the bit time

Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the

Resynchronization Jump Width.

This segment may not be longer than Phase Segment 2.

Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus.

Early sa mpling al lows more T ime Quanta in the Phase Se gment 2 so the Synchron iza-

tion Jump Width can be programmed to its maximum. This maximum capacity to

shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,

so that lower cost oscillators such as ceramic resonators may be used.

Late sampling allows more Time Quanta in the Propagation Time Segment which allows

a poorer bus topology and maximum bus length.

Arbitration

Figure 35. Bus Arbitration

The CAN protocol handles bus accesses according to the concept called “Carrier Sense

Multiple Access with Arbitration on Message Priority”.

During trans mission, arbitra tion on the CAN bus can be lost to a com peting device with

a higher priority CAN Identifier. This arbitration concept avoids collisions of messages

whose transmission was started by more than one node simultaneously and makes sure

the most important message is sent first without time loss.

The bu s acces s confl ict is res olved du ring th e arbitr ation fi eld mos tly ove r the iden tifier

value . If a dat a frame and a remo te frame with the sa me identifier ar e initiated at th e

same time, the data frame prevails over the remote frame (c.f. RTR bit).

Errors The CAN protocol signals any errors immediately as they occur. Three error detection

mechanisms are implemented at the message level and two at the bit level:

Error at Message Level • Cyclic Redundancy Check (CRC)

The CRC safeguards the information in the frame by adding redundant check bits at

the transmission end. At the receiver these bits are re-computed and tested against

the received bits. If they do not agree there has been a CRC error.

•Frame Check

This mechanism verifies the structure of the transmitted frame by checking the bit

node A

TXCAN

node B

TXCAN

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

SOF

SOF RTR IDE

CAN bus

- - - - - - - -

Arbitration lost

Node A loses the bus

Node B wins the bus

AT/T89C51CC02

4126L–CAN–01/08

fields against the fixed format and the frame size. Errors detected by frame checks

are designated "format errors".

• ACK Errors

As already mentioned frames received are acknowledged by all receivers through

positive acknowledgement. If no acknowledgement is received by the transmitter of

the message an ACK error is indicated.

Error at Bit Level • Monitoring

The ability of the transmitter to detect errors is based on the monitoring of bus

signals. Each node which transmits also observes the bus level and thus detects

differences between the bit sent and the bit received. This permits reliable detection

of global errors and errors local to the transmitter.

• Bit Stuffing

The coding of the individual bits is tested at bit level. The bit representation used by

CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency

in bit coding. The synchronization edges are generated by means of bit stuffing.

Error Signalling If one or more errors are discovered by at least one node using the above mechanisms,

the current transmission is aborted by sending an "error flag". This prevents other nodes

acceptin g the mes sage and thus ensur es the c onsistency of data th roughout the net-

work. After transmi ssion of an erroneou s message th at has been aborted, the sender

automatically re-attempts transmission.

CAN Controller

Description The CAN controller accesses are made through SFR.

Several operations are possible by SFR:

• arithmetic and logic operations, transfers and program control (SFR is accessible by

direct addressing).

• 4 independent message objects are implemented, a pagination system manages

their ac ce ss es .

Any me ssage obj ec t c an be pro gr amm ed in a r ec ept ion b u ffe r bl oc k ( ev en non -con sec-

utive buffer s). For th e recepti on of def ined me ssages one or sev eral re ceiver me ssag e

objects can be masked without participating in the buffer feature. An IT is generated

when the buffer is full. The fr am es followi ng the buffe r-ful l i nterr upt will not be take n in to

account until at least one of the buffer message objects is re-enabled in reception.

Higher priori ty of a message object for rec eption or transmi ssion is given to the lower

message object number.

The progr amma ble 16 -bit Time r (CANT IMER ) is u sed to stam p each rec eive d and sent

message in the CANSTMP register. This timer starts counting as soon as the CAN con-

troller is enabled by the ENA bit in the CANGCON register.

The Time Trigger Communication (TTC) protocol is supported by the T89C51CC02.

AT/T89C51CC02

4126L–CAN–01/08

Figure 36. CAN Controll er Block Diag r am

CAN Controller Mailbox

and Registers

Organization

The pagination allows management of the 91 registers including 80(4 x 20) Bytes of

mailbox via 32 SFRs.

All actions on the message object window S FRs apply to the corresponding message

object registers pointed by the message object number find in the Page message object

bit

Stuffing /Destuffing

Cyclic

Redundanc y Chec k

Receive Transmit

Error

Counter

Rec/Tec

bit

Timing

Logic

Page

Encoder

µC-Core Interface

Core

Control

Interface

Bus

TxDC

RxDC

AT/T89C51CC02

4126L–CAN–01/08

Figure 37. CAN Controll er Mem ory Orga ni za tio n

Ch.3 - ID Tag - 1

Ch.3 - ID Tag - 2

Ch.3 - ID Tag - 4

Ch.3 - ID Tag - 3

Ch.3 - ID Mask - 1

Ch.3 - ID Mask - 2

Ch.3 - ID Mask - 4

Ch.3 - ID Mask - 3

Ch.3 - Message Data - byte 0

General Control

General Status

bit Timing - 1

bit Timing - 2

bit Timing - 3

Enable Interr upt

Enable Interrupt message object

Page message object

message object Status

message object Control & DLC

Message Data

ID T ag - 1

ID T ag - 2

ID T ag - 4

ID T ag - 3

ID Mask - 1

ID Mask - 2

ID Mask - 4

ID Mask - 3

message ob ject 0 - Status

message object 0 - Control & DLC

Ch.0 - ID Tag - 1

Ch.0 - ID Tag - 2

Ch.0 - ID Tag - 4

Ch.0 - ID Tag - 3

Ch.0 - Message Data - byte 0

message object 3 - Status

message object 3 - Control & DLC

Status Interrupt message object

(message object number)(Data offset)

SFRs On-chip CAN Controller Registers

4 Message Objects

8 Bytes

TimStmp High

TimStmp Low

Ch.0 - ID Mask- 1

Ch.0 - ID Mask- 2

Ch.0 - ID Mask - 4

Ch.0 - ID Mask- 3

CANTimer High

CANTimer Low

TimTT C High

TimTTC Low

TEC counter

REC counter

Timer Control

Enable message object

message object Window SFRs

Ch.0 TimStmp High

Ch.0 TimStmp Low

Ch.3 TimStmp High

Ch.3 TimStmp Low

General Interrupt

AT/T89C51CC02

4126L–CAN–01/08

Working on Message Obje cts The P age me ssag e object r egist er (CANP AGE) is used t o sele ct one o f the 4 mess age

objects. Then, message object Control (CANCONCH) and message object Status

(CANSTCH) are available for this selected message object number in the corresponding

SFRs. A single register (CANMSG ) is used for the message. The mail box pointer is

managed by the Page message object register with an auto-incrementation at the end of

each access. The range of this counter is 8.

Note that the mai box is a pure RA M, ded ic ate d to one mes sage ob ject, witho ut ov erla p.

In most cases , it is not nec essary to transfe r the rec eived messag e into t he stand ard

memory. The message to be transmitted can be built di rectly in the maibox. Most calcu-

lations or tests can be executed in the mailbox area which provide quicker access.

CAN Controller

Management In order to enable the CAN Controller correctly the following registers have to be

initialized:

• General Control (CANGCON),

• bit Timing (CANBT 1, 2 & 3),

• And for each page of 15 message objects:

– Messa ge objec t Control (CANCONCH),

– Message object Status (CANSTCH).

During operation, the CAN Enable message object registers (CANEN) gives a fast over-

view of the message objects availability.

The CAN messages can be handled by interrupt or polling modes.

A message object can be configured as follows:

• Transmit message object

• Receive message object

• Receive buffer message object

• Disable

This configuration is made in the CONCH field of the CANCONCH register (See

Table 54).

When a message object is configured, the corresponding ENCH bit of CANEN register

is set.

Table 54. Configuration for CONCH1:2

When a Trans mitter or Receiv er actio n of a mes sage obj ect is c omplet ed, the co rre-

sponding ENCH bit of the CANEN register is cleared. In order to re-enable the message

object, it is necessary to re-write the configuration in CANCONCH register.

Non-consecutive message objects can be used for all three types of message objects

(Transmitter, Receiver and Receiver buffer).

CONCH 1 CONCH 2 Type of Message Object

0 0 Disable

0 1 Transmitter

10Receiver

1 1 Receiver buffer

AT/T89C51CC02

4126L–CAN–01/08

Buffer Mode A ny mess age obje ct can be used t o define one buff er, incl uding non-con secut ive mes-

sage objects, and with no limitation in number of message objects used up to 4.

Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1;

Figure 38. Buffer Mode

The same acceptance filter must be defined for each message objects of the buffer.

When there is no mask on the identifier or the IDE, all messages are accepted.

A received frame will always be stored in the lowest free message object.

When the flag RxOk is set on one of the buffer message objects, this message object

can then be r ea d b y t he a ppl icati on . T hi s flag mu st then be cl eared by th e s oftw ar e an d

the message object re-enabled in buffer reception in order to free the message object.

The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can

generate an interrupt.

The frames following the buffer-full interrupt will not be stored and no status will be over-

written in the CANSTCH registers invo lved in the buffer until at least one of the buffer

message objects is re-enabled in reception.

This flag must be cleared by the software in order to acknowledge the interrupt.

IT CAN Management The differ ent int erru pts are:

• Transmission interrupt

• Recepti on int erru pt

• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error)

• Interrupt when Buffer receive is full

• Interrupt on overrun of CAN Timer

message object 0

message object 1

message object 2

message object 3

Block buffer

buffer 0

buffer 1

AT/T89C51CC02

4126L–CAN–01/08

Figure 39. CAN Controller Interrupt Structure

To enable a transmission interrupt:

• Enable General CAN IT in the interrupt system register

• Enable interrupt by message object, EICHi

• Enable transmission interrupt, ENTX

To enable a reception interrupt:

• Enable General CAN IT in the interrupt system register

• Enable interrupt by message object, EICHi

• Enable reception interrupt, ENRX

To enable an interrupt on message object error:

• Enable General CAN IT in the interrupt system register

• Enable interrupt by message object, EICHi

• Enable interrupt on error, ENERCH

To enable an interrupt on general error:

• Enable General CAN IT in the interrupt system register

• Enable interrupt on error, ENERG

SIT i

i=0

i=4

OVRIT

ENRX

CANGIE.5 ENTX

CANGIE.4 ENERCH

CANGIE.3

ENBUF

CANGIE.2 ECAN

IEN1.0

RXOK i

CANSTCH.5

TXOK i

CANSTCH.6

BERR i

CANSTCH.4

SERR i

CANSTCH.3

FERR i

CANSTCH.1

CERR i

CANSTCH.2

AERR i

CANSTCH.0

EICH i

CANIE

OVRTIM

CANGIT.5

OVRBUF

CANGIT.4

FERG

CANGIT.1

AERG

CANGIT.0

SERG

CANGIT.3

CERG

CANGIT.2

ENERG

CANGIE.1

ETIM

IEN1.2

SIT i

CANSIT

CANIT

CANGIT.7

CAN

AT/T89C51CC02

4126L–CAN–01/08

To enable an interrupt on Buffer-full condition:

• Enable General CAN IT in the interrupt system register

• Enable interrupt on Buffer full, ENBUF

To enable an interrupt when Timer overruns:

• Enable Overrun IT in the interrupt system register

When an interrupt occurs, the corresponding message object bit is set in the SIT

To acknowled ge an interrupt, the corres ponding CANSTCH bits (RX OK, TXOK,...) or

CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.

When the C AN no de is in tr an sm is si on an d dete ct s a For m Err or in its fr ame , a bit Err or

will al so be r ai sed . Conseq uently, two co nse cu tiv e in ter rupts c an oc cur , b oth due to th e

same error.

When a mess age object error occu rs and is set in CANSTCH r egister, no gener al error

are set in CANGIE register.

AT/T89C51CC02

4126L–CAN–01/08

Bit Timing and Baud

Rate FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time

quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.

Field and se gme nt abbrev ia tions:

• BRP: Baud Rate Prescaler.

• TQ: T ime Quantum (output of Baud Rate Prescaler).

• SYNS: SYNchronization Segment is 1 TQ long.

• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.

• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.

• PHS2: PHase Segment 2 is programmable to be superior or eual to the Information

Processing Time and inferior or equal to TPHS1

• INFORMATION PROCESSING TIME is 2 TQ.

• SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1

and 4.

The total number of TQ in a bit time has to be programmed at least from 8 to 25.

Figure 40. Sample and Transmission Point

The baud rate selection is made by Tbit calculation:

Tbit = Tsyns + Tprs + Tphs1 + Tphs2

1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ

2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl

3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl

4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl

Tphs2 = Max of (Tphs1 and 2 TQ)

5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl

The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to

25.

FCAN

CLOCK Prescal er BRP

PRS 3bit length

PHS1 3bit length

PHS2 3bit length

SJW 2-bit length

bit Timing

System Cl ock Tscl

Time Quantum

Sample Point

Transmission Poin

AT/T89C51CC02

4126L–CAN–01/08

Figure 41. General Structure of a bit Period

example of bit timing determination for CAN baudrate of 500 kbit/s:

FOSC = 12 MHz in X1 mode => FCAN = 6MHz

Verify that the CAN baud rate you want is an integer division of FCAN clock.

FCAN/CANbaudrate = 6 MHz/500 kHz = 12

The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0

Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 =

12TQ

Tsyns = 1TQ and Tsjw =1TQ => SJW = 0

If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3

Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4

PHS1 = 3 and PRS = 2

BRP = 0 so CANBT1 = 00h

SJW = 0 and PRS = 2 so CANBT2 = 04h

PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h

bit Rate Prescaler

Oscillator

1/ Fcan

Tscl

System Clock

One Nominal bit

Tsyns (*) Tprs

Sample Point

(*) Synchronization Segment: SYNS

Tbit

Tsyns = 1xTscl (fixed)

Data

Tbit Tsyns Tprs Tphs1Tphs2++ +=

Tbit calculation:

Transmission Poi

Tphs1 + Tsjw (3) Tphs2 - Tsjw (4)

(

1) Phase error ≤ 0

(

2) Phase error ≥ 0

(

3) Phase error > 0

(

4) Phase error < 0

Tphs2 (2)

Tphs1 (1)

AT/T89C51CC02

4126L–CAN–01/08

Fault Confinement With respect to fault confinement, a unit may be in one of the three following status:

• Error active

• Error passive

• Bus off

An error active unit takes part in bus communication and can send an active error frame

when the CAN macro detects an error.

An error passive unit cannot send an active error frame. It takes part in bus communica-

tion, but when an error is detected, a passive error frame is sent. Also, after a

transmission, an error passive unit will wait before initiating further transmission.

A bus off unit is not allowed to have any influence on the bus.

For fault confinement, two error counters (TEC and REC) are implemented.

See CAN Specification for details on Fault confinement.

Figure 42. Line Error Mode

TEC>255

Error

Active

Error

Passive Bus

Off

Init.

TEC<127

and

REC<127

TEC>127

REC>127 128 Occurrences

11 Consecutive

Recessive

bit

TEC: Transmit Error Counter

REC: Receive Error Counter

ERRP = 0

BOFF = 0

ERRP = 1

BOFF = 0

ERRP = 0

BOFF = 1

AT/T89C51CC02

4126L–CAN–01/08

Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received

and an ID+RT R+RB+IDE specified while takin g the comparis on mask into ac count) the

ID+RTR+RB+IDE received are written over the ID TAG Registers.

ID => IDT0-29

RTR => RTRTAG

RB => RB0-1TAG

IDE => IDE in CANCONCH register

Figure 43. Acceptance Filter Block Diagram

example:

To accept only ID = 318h in part A.

ID MSK = 111 1111 1111 b

ID TAG = 011 0001 1000 b

13/32

RxDC

13/32

Write

13/32

Hit

13/32

ID MSK Registers (Ch i)

ID & RB RTR IDE

Rx Shift Register (internal)

ID & RB RTR IDE

Enable (Ch i)

ID TAG Registers (Ch i) & CanConch

ID & RB RTR

IDE

AT/T89C51CC02

4126L–CAN–01/08

Data and Remote Frame Description of the different steps for:

• Data frame

• Remote frame, with automatic reply

• Remote frame

u uu uu

0 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

0 1 x 0 0

c uc uu

0 0 x 1 0 u cc uu

0 0 x 0 1

DATA FRAME

Node A Node B

ENCH

RTR

RPLV

TXOK

RXOK

message object in reception

message object disabled

messa ge object in tr an smission

message object disabled

u uu uu

1 1 x 0 0

c uu uc

0 1 x 1 0

c uu

0 0 x 0 1

REMOTE FRAME

DATA FRAME

u uu uu

1 1 1 0 0

u uu cc

0 1 0 0 0

c uc cu

0 0 0 1 0

ENCH

RTR

RPLV

TXOK

RXOK

ENCH

RTR

RPLV

TXOK

RXOK

(immediate)

message object in reception

message object in transmission

message object disabled

message object in transmission

message object in reception

message object disabled

by CAN controller by CAN controller

u uu uu

1 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

1 1 0 0 0

c uu uc

0 1 x 1 0 u cc uu

1 0 0 0 1

REMOTE FRAME

ENCH

RTR

RPLV

TXOK

RXOK

u uu uu

0 1 x 0 0

c uc uu

0 0 x 1 0

u cc uc

0 0 x 0 1

DATA FRAME

(deferred)

u: modified by user

ic: modified by CAN

message ob ject in reception

message object in transmission by use

mess age object disabled

message object in transmission

mess age object in reception

mess age object disabled

by user

AT/T89C51CC02

4126L–CAN–01/08

Time Trigger

Communication (TTC)

and Me ss age Sta mping

The T89C51CC0 2 has a pr ogrammable 1 6-bit Timer (CANTIMH&CA NTIML) for m es-

sage stamp and T TC.

This CAN Timer starts after th e CAN control ler is enabled by th e ENA bit in t he CANG -

CON register.

Two modes in the timer are implemented:

• Time Trigger Communica tio n:

– Capture of this timer value in the CANTTCH & CANTTCL registers on Start

Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in

the CANGCON register, when the network is configured in TTC by the TTC

bit in the CANGCON register.

Note: In this mode, CAN only sends the frame once, even if an error occurs.

• Messa ge Stamping

– Capture of this timer value in the CANSTMPH & CANSTMPL registers of the

message object which received or sent the frame.

– All messages can be stamps.

– The stamping of a received frame occurs when the RxOk flag is set.

– The stamping of a sent frame occurs when the TxOk flag is set.

The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.

When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit

in the interrupt enable register IEN1 is set.

Figure 44. Block Diagram of CAN Timer

EOF on CAN frame

ENA

CANGCON.1

CANTCON

RXOK i

CANSTCH.5

TXOK i

CANSTCH.4

÷ 6

Fcan

CLOCK

SOF on CAN frame

TTC

CANGCON.5 SYNCTTC

CANGCON.4

CANTTCH & CANTTCL

CANSTMPH & CANSTMPL

CANTIMH & CANTIML

OVRTIM

CANGIT.5

When 0xF FFF to 0x00 00

AT/T89C51CC02

4126L–CAN–01/08

CAN Autobaud and

Listening Mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must

be set. In this mode , the CAN cont roll er is only list ening to the line withou t ackno wledg-

ing the received messages. It cannot send any message. The error flags are updated.

The bit timing can be adjusted until no error occurs (good configuration find).

In this mode, the error counters are frozen.

To go back to the standard mode, the AUTOBAUD bit must be cleared.

Figure 45. Autobaud Mode

Routine Examples 1. Init of CAN macro

// Reset the CAN macro

CANGCON = 01h;

// Disable CAN interrupts

ECAN = 0;

ETIM = 0;

// Init the Mailbox

for num_page =0; num_page <4; num_page++

{

CANPAGE = num_channel << 4;

CANCONCH = 00h

CANSTCH = 00h;

CANIDT1 = 00h;

CANIDT2 = 00h;

CANIDT3 = 00h;

CANIDT4 = 00h;

CANIDM1 = 00h;

CANIDM2 = 00h;

CANIDM3 = 00h;

CANIDM4 = 00h;

for num_data =0; num_data <8; num_data++)

{

CANMSG = 00h;

}

// Configure the bit timing

CANBT1 = xxh

CANBT2 = xxh

CANBT3 = xxh

TxDC

RxDC

AUTOBAUD

CANGCON.3 RxDC

TxDC

AT/T89C51CC02

4126L–CAN–01/08

// Enable the CAN macro

CANGCON = 02h

2. Configure message object 3 in reception to receive only standard (11bit

identifier) message 100h

// Select the message object 3

CANPAGE = 30h

// Enable the interrupt on this message object

CANIE = 08h

// Clear the status and control register

CANSTCH = 00h

CANCONCH= 00h

// Init the acceptance filter to accept only message 100h in standard mode

CANIDT1 = 20h

CANIDT2 = 00h

CANIDT3 = 00h

CANIDT4 = 00h

CANIDM1 = FFh

CANIDM2 = FFh

CANIDM3 = FFh

CANIDM4 = FFh

// Enable channel in reception

CANCONCH = 88h // enable reception

Note: to enable the CAN interrupt in reception:

EA = 1

ECAN = 1

CANGIE = 20h

3. Send a message on the message object 0

// Select the message object 0

CANPAGE = 00h

// Enable the interrupt on this message object

CANIE = 01h

// Clear the Status register

CANSTCH = 00h;

// load the identifier to send (ex: 555h)

CANIDT1 = AAh;

CANIDT2 = A0h;

// load data to send

CANMSG = 00h

CANMSG = 01h

CANMSG = 02h

CANMSG = 03h

CANMSG = 04h

CANMSG = 05h

CANMSG = 06h

CANMSG = 07h

// configure the control register

CANCONCH = 18h

4. Interrupt routine

// Save the current CANPAGE

AT/T89C51CC02

4126L–CAN–01/08

// Find the first message object which generate an interrupt in CANSIT

// Select the corresponding message object

// Analyse the CANSTCH register to identify which kind of interrupt is

generated

// Manage the interrupt

// Clear the status register CANSTCH = 00h;

// if it is not a channel interrupt but a general interrupt

// Manage the general interrupt and clear CANGIT register

// restore the old CANPAGE

AT/T89C51CC02

4126L–CAN–01/08

CAN SFRs

Table 55. SFR Mapping

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

0xxx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN

xxxx 0000 CFh

C0h P4

xxxx xx11 CANGIE

1100 0000 CANIE

1111 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT

xxxx 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

1100 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

1010 0000 CANGCON

0000 0000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

xxxx xxxx CANSTMPH

xxxx xxxx AFh

A0h P2

xxxx xx11 CANTCON

0000 0000 AUXR1(2)

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 CKCON

0000 0000 8Fh

80h SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

AT/T89C51CC02

4126L–CAN–01/08

Registers Table 56. CANGCON Register

CANGCON (S:ABh)

CAN General Control Register

Reset Val ue = 0000 0000b

7654 3210

ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES

Bit Number Bit Mnemonic Description

7ABRQ

Abort Request

Not an auto-resetable bit. A reset of the ENCH bit (message object

control & DLC register) is done for each message object. The

pending transmission communications are immediately aborted but

the on-going communication will be terminated normally, setting

the appropriate status flags, TxOk or RxOk.

6OVRQ

Overload Frame Request (Initiator).

Auto-resetable bit.

Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the

overload frame.

5TTC

Network in Timer Trigger Communication

set to select node in TTC.

clear to disable TTC features.

4 SYNCTTC

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the

End Of Frame.

When this bit is clear the TTC timer is caught on the Start Of

Frame.

This bit is only used in the TTC mode.

3AUTOBAUD

AUTOBAUD

set to active listening mode.

Clear to disable listening mode

2TEST

Test mode. The test mode is intended for factory testing and not for

customer use.

1ENA/STB

Enable/Standby CAN Controller

When this bit is set, it enables the CAN controller and its input

clock.

When this bit is clear, the on-going communication is terminated

normally and the CAN controller state of the machine is frozen (the

ENCH bit of each message object does not change).

In the standby mode, the transmitter constantly provides a

recessive level; the receiver is not activated and the input clock is

stopped in the CAN controller. During the disable mode, the

registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller

state of the machine.

0GRES

General Reset (Software Reset).

Auto-resetable bit. This reset command is ‘ORed’ with the

hardware reset in order to reset the controller. After a reset, the

controller is disabled.

AT/T89C51CC02

4126L–CAN–01/08

Table 57. CANGSTA Register

CANGSTA (S:AAh Read Only)

CAN General Status Register

Reset Value = x0x0 0000b

76543210

- OVFG - TBSY RBSY ENFG BOFF ERRP

Bit Number Bit Mnemonic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6OVFG

Overload frame flag

This status bit is set by the hardware as long as the produced

overload frame is sent.

This flag does not generate an interrupt

Reserved

The values read from this bit is indeterminate. Do not set this bit.

4TBSY

Transmitter busy

This status bit is set by the hardware as long as the CAN

transmitter generates a frame (remote, data, overload or error

frame) or an ack field. This bit is also active during an InterFrame

Spacing if a frame must be sent.

This flag does not generate an interrupt.

3RBSY

Receiver busy

This status bit is set by the hardware as long as the CAN receiver

acquires or monitors a frame.

This flag does not generate an interrupt.

2ENFG

Enable on-chip CAN controller flag

Because an enable/disable command is not effective immediately,

this status bit gives the true state of a chosen mode.

This flag does not generate an interrupt.

1BOFF

Bus off mode

See Figure 42

0 ERRP Error passive mode

See Figure 42

AT/T89C51CC02

4126L–CAN–01/08

Table 58. CANGIT Register

CANGIT (S:9Bh)

CAN General Interrupt

Note: 1. This field is Read Only.

Reset Val ue = 0x0 0 0000b

76543210

CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

Bit Number Bit Mnemonic Description

7CANIT

General interrupt flag(1)

This status bit is the image of all the CAN controller interrupts sent

to the interrupt controller.

It can be used in the case of the polling method.

Reserved

The values read from this bit is indeterminate. Do not set this bit.

5OVRTIM

Overrun CAN Timer

This status bit is set when the CAN timer switches 0xFFFF to

0x0000.

If the bit ETIM in the IE1 register is set, an interrupt is generated.

Clear this bit in order to reset the interrupt.

4OVRBUF

Ove r r u n B U FFER

0 - no interrupt.

1 - IT turned on

This bit is set when the buffer is full.

bit resetable by user.

See Figure 39.

3SERG

Stuff Error General

Detection of more than five consecutive bits with the same polarity.

This flag can generate an interrupt. resetable by user.

2CERG

CRC Error General

The receiver performs a CRC check on each destuffed received

message from the start of frame up to the data field.

If this checking does not match with the destuffed CRC field, a

CRC error is set.

This flag can generate an interrupt. resetable by user.

1FERG

Form Error General

The form error results from one or more violations of the fixed form

in the following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt. resetable by user.

0AERG

Acknowle dgment Error General

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt. resetable by user.

AT/T89C51CC02

4126L–CAN–01/08

Table 59. CANTEC Register

CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter

Reset Val ue = 00h

Table 60. CANREC Register

CANREC (S:9Dh Read Only) – CAN Reception Error Counter

Reset Val ue = 00h

76543210

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

Bit Number Bit Mnemonic Description

7 - 0 TEC7:0 T ransmit Error Counter

See Figure 42

76543210

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

Bit Number Bit Mnemonic Description

7 - 0 REC7:0 Recep tion Erro r Counter

See Figure 42

AT/T89C51CC02

4126L–CAN–01/08

Table 61. CANGIE Register

CANGIE (S:C1h) – CAN

Reset Val ue = xx 00 000xb

76543210

- - ENRX ENTX ENERCH ENBUF ENERG -

Bit Number Bit Mnemonic Description

7 - 6 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

5 ENRX Enable Receive Interrupt

0 - Disable

1 - Enable

4ENTX

Enable T ransmit Interrupt

0 - Disable

1 - Enable

3 ENERCH Enable Message Object Error Interrupt

0 - Disable

1 - Enable

2 ENBUF Enable BUF Interrupt

0 - Disable

1 - Enable

1 ENERG Enable General Error Interrupt

0 - Disable

1 - Enable

Reserved

The value read from this bit is indeterminate. Do not set this bit.

See Figure 39.

AT/T89C51CC02

4126L–CAN–01/08

Table 62. CANEN Register

CANEN (S:CFh Read Only)

CAN Enable Message Object Registers

Reset Val ue = xx xx 0000b

Table 63. CANSIT Register

CANSIT (S:BBh Read Only) – CAN Status Interrupt Message Object Registers

Reset Value = xxxx0000b

76543210

----ENCH3 ENCH2 ENCH1 ENCH0

Bit Number Bit Mnemonic Description

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 ENCH3:0

Enable Message Object

0 - message object is disabled => the message object is free for a

new emission or reception.

1 - message object is enabled.

This bit is resetable by re-writing the CANCONCH of the

corresponding message object.

76543210

----SIT3SIT2SIT1SIT0

Bit Number Bit Mnemonic Description

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 SIT3:0

Status of Interrupt by Message Object

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT3:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0.

See Figure 39.

100

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4126L–CAN–01/08

Table 64. CANIE Register

CANIE (S:C3h) – CAN Enable Interrupt message object Registers

Reset Val ue = xx xx 0000b

Table 65. CANBT1 Register

CANBT1 (S:B 4h) – CAN bit Timing Regist ers 1

Note: 1. The CAN c ontr oll er bi t tim ing r egi ste rs m us t be ac ce ss ed only if th e C AN con trol ler is

disabled with the ENA bit of the CANGCON register set to 0.

See Figure 41.

No default value after reset.

76543210

----IECH 3IECH 2IECH 1IECH 0

Bit Number Bit Mnemonic Description

7 - 4 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

3 - 0 IECH3:0

Enable Interrupt by Message Object

0 - disable IT.

1 - enable IT.

IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.

76543210

- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -

Bit Number Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 1 BRP 5:0

Baud Rate Prescaler

The period of the CAN controller system clock Tscl is

programmable and determines the individual bit timing.(1)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tscl = BRP[5..0] + 1

FCAN

101

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Table 66. CANBT2 Register

CANBT2 (S:B 5h) – CAN bit Timing Regist ers 2

Note: 1. The CAN c ontr oll er bi t tim ing r egi ste rs m us t be ac ce ss ed only if th e C AN con trol ler is

disabled with the ENA bit of the CANGCON register set to 0.

See Figure 41.

No default value after reset.

76543210

- SJW 1 SJW 0 - PRS 2 PRS 1 PR S 0 -

Bit Number Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 5 SJW1:0

Re-synchronization Jump Width

To compensate for phase shifts between clock oscillators of

different bus controllers, the controller must re-synchronize on any

relevant signal edge of the current transmission.

The synchronization jump width defines the maximum number of

clock cycles. A bit period may be shortened or lengthened by a re-

synchronization.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 - 1 PRS 2:0

Programming Time Segment

This part of the bit time is used to compensate for the physical

delay times within the network. It is twice the sum of the signal

propagation time on the bus line, the input comparator delay and

the output driver delay.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tsjw = Tscl x (SJW [1..0] +1)

Tprs = Tscl x (PRS [2. .0] + 1)

102

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Table 67. CANBT3 Register

CANBT3 (S:B6h)

CAN bit Timing Registers 3

Note: 1. The CAN c ontr oll er bi t tim ing r egi ste rs m us t be ac ce ss ed only if th e C AN con trol ler is

disabled with the ENA bit of the CANGCON register set to 0.

See Figure 41.

No default value after reset.

76543210

- PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP

Bit Number Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 - 4 PHS2 2:0

Phase Segment 2

This phase is used to compensate for phase edge errors. This

segment can be shortened by the re-synchronization jump width.

Phasse segment 2 is the maximum of Phase segment1 and the

Information Processing Time (= 2TQ).

3 - 1 PHS1 2:0

Phase Segment 1

This phase is used to compensate for phase edge errors. This

segment can be lengthened by the re-synchronization jump width.

0SMP

Sample Type

0 - once, at the sample point.

1 - three times, the threefold sampling of the bus is the sample

point and twice over a distance of a 1/2 period of the Tscl. The

result corresponds to the majority decision of the three values.

Tphs2 = Tscl x (PHS2[2..0] + 1)

Tphs1 = Tscl x (PHS1[2..0] + 1)

103

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Table 68. CANPAGE Register

CANPAGE (S:B1h) – CAN Message Object Page Register

Reset Val ue = xx 00 0000 b

Table 69. CANCONCH Register

CANCONCH (S:B3h) – CAN Message Object Control and DLC Register

No default value after reset

76543210

- - CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX 0

Bit Number Bit Mnemonic Description

7 - 6 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

5 - 4 CHNB3:0 Selection of Message Object Number

The available numbers are: 0 to 3(See Figure 37).

3AINC

Auto Increment of the Index (Active Low)

0 - auto-increment of the index (default value).

1 - non-auto-increment of the index.

2 - 0 INDX2:0 Index

Byte location of the data field for the defined message object (See

Figure 37).

76543210

CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 D LC 1 DLC 0

Bit Number Bit Mnemonic Description

7 - 6 CO NCH1:0

Configuration of Message Object

CONCH1 CONCH0

0 0: disable

0 1: Launch transmission

1 0: Enable Reception

1 1: Enable Reception Buffer

NOTE: The user must re-write the configuration to enable the

corresponding bit in the CANEN1:2 registers.

5RPLV

Reply valid

Used in the automatic reply mode after receiving a remote frame

0 - reply not ready.

1 - reply ready & valid.

4IDE

Identifier Extension

0 - CAN standard rev 2.0 A (ident = 11 bits).

1 - CAN standard rev 2.0 B (ident = 29 bits).

3 - 0 DLC3:0

Data Le ngth Code

Number of Bytes in the data field of the message.

The range of DLC is from 0 up to 8.

This value is updated when a frame is received (data or remote

frame).

If the expected DLC differs from the incoming DLC, a warning

appears in the CANSTCH register.

104

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Table 70. CANSTCH Register

CANSTCH (S:B 2h) – CAN Message Ob je ct Stat us Regis ter

Note: See Figu re 39.

No default value after reset.

76543210

DLCW TXOK RXOK BERR SERR CERR FERR AERR

Bit Number Bit Mnemonic Description

7DLCW

Data Length Code Warning

The incoming message does not have the DLC expected.

Whatever the frame type, the DLC field of the CANCONCH register

is updated by the received DLC.

6TXOK

Transmit OK

The communication enabled by transmission is completed.

When the controller is ready to send a frame, if two or more

message objects are enabled as producers, the lower index

message object (0 to 13) is supplied first. Must be cleared by

software.

This flag can generate an interrupt.

5RXOK

Receive OK

The communication enabled by reception is completed.

In the case of two or more message object reception hits, the lower

index message object (0 to 13) is updated first. Must be cleared by

software.

This flag can generate an interrupt.

4BERR

bit Error (only in transmission)

The bit value monitored is different from the bit value sent.

Exceptions:

the monitored recessive bit sent as a dominant bit during the

arbitration field and the acknowledge slot detecting a dominant bit

during the sending of an error frame. Must be cleared by software.

This flag can generate an interrupt.

3SERR

Stuff Error

Detection of more than five consecutive bits with the same polarity.

Must be cleared by software.

This flag can generate an interrupt.

2CERR

CRC Error

The receiver performs a CRC check on each destuffed received

message from the start of frame up to the data field.

If this checking does not match with the destuffed CRC field, a

CRC error is set. Must be cleared by software.

This flag can generate an interrupt.

1FERR

Form Error

The form error results from one or more violations of the fixed form

in the following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

Must be cleared by software.

This flag can generate an interrupt.

0AERR

Acknowle dgment Error

No detection of the dominant bit in the acknowledge slot. Must be

cleared by software.

This flag can generate an interrupt.

105

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Table 71. CANIDT1 Register for V2.0 part A

CANIDT1 for V2.0 part A (S:BCh) – CAN Identifier Tag Registers 1

No default value after reset.

Table 72. CANIDT2 Register for V2.0 part A

CANIDT2 for V2.0 part A (S:BDh) – CAN Identifier Tag Registers 2

No default value after reset.

Table 73. CANIDT3 Register for V2.0 part A

CANIDT3 for V2.0 part A (S:BEh) –CAN Identifier Tag Registers 3

No default value after reset.

76543210

IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3

Bit Number Bit Mnemonic Description

7 - 0 IDT10:3 IDentifier Tag Value

See Figure 43.

76543210

IDT 2IDT 1IDT 0-----

Bit Number Bit Mnemonic Description

7 - 5 IDT2:0 IDentifier Tag Value

See Figure 43.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

76543210

--------

Bit Number Bit Mnemonic Description

7 - 0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

106

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Table 74. CANIDT1 for V2.0 part A

CANIDT4 for V2.0 part A (S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

Table 75. CANIDT2Register for V2.0 part A

CANIDT1 for V2.0 Part B (S:BCh)

CAN Identifier Tag Registers 1

No default value after reset.

Table 76. CANIDT2 Register for V2.0 Part B

CANIDT2 for V2.0 Part B (S:BDh)

CAN Identifier Tag Registers 2

No default value after reset.

76543210

-----RTRTAG-RB0TAG

Bit Number Bit Mnemonic Description

7 - 3 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

2 RTRTAG Remote transmission request tag value.

Reserved

The values read from this bit are indeterminate. Do not set these

bit.

0 RB0TAG Reserved bit 0 tag value.

76543210

IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21

Bit Number Bit Mnemonic Description

7 - 0 IDT28:21 IDentifier Tag Value

See Figure 43.

76543210

IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13

Bit Number Bit Mnemonic Description

7 - 0 IDT20:13 IDentifier Tag Value

See Figure 43.

107

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Table 77. CANIDT3 Register for V2.0 Part B

CANIDT3 for V2.0 Part B (S:BEh)

CAN Identifier Tag Registers 3

No default value after reset.

Table 78. CANIDT4 Register for V2.0 Part B

CANIDT4 for V2.0 Part B (S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

76543210

IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5

Bit Number Bit Mnemonic Description

7 - 0 IDT12:5 IDentifier Tag Value

See Figure 43.

76543210

IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG

Bit Number Bit Mnemonic Description

7 - 3 IDT4:0 IDentifier Tag Value

See Figure 43.

2RTRTAGRemote Transmiss ion Request Tag Value

1 RB1TAG Reserved bit 1 tag value.

0 RB0TAG Reserved bit 0 tag value.

108

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Table 79. CANIDM1 Register for V2.0 part A

CANIDM1 for V2.0 part A (S:C4h)

CAN Identifier Mask Registers 1

No default value after reset.

Table 80. CANIDM2 Register for V2.0 part A

CANIDM2 for V2.0 part A (S:C5h)

CAN Identifier Mask Registers 2

No default value after reset.

Table 81. CANIDM3 Register for V2.0 part A

CANIDM3 for V2.0 part A (S:C6h)

CAN Identifier Mask Registers 3

No default value after reset.

76543210

IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 IDMSK 4 IDMSK 3

Bit Number Bit Mnemonic Description

7 - 0 IDTMSK10:3

IDentifier Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

76543210

IDMSK 2IDMSK 1IDMSK 0-----

Bit Number Bit Mnemonic Description

7 - 5 IDTMSK2:0

IDentifier Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

4 -0 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

76543210

--------

Bit Number Bit Mnemonic Description

7 - 0 - Reserved

The values read from these bits are indeterminate.

109

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4126L–CAN–01/08

Table 82. CANIDM4 Register for V2.0 part A

CANIDM4 for V2.0 part A (S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 83. CANIDM1 Register for V2.0 Part B

CANIDM1 for V2.0 Part B (S:C4h)

CAN Identifier Mask Registers 1

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

-----RTRMSK-IDEMSK

Bit Number Bit Mnemonic Description

7 - 3 - Reserved

The values read from these bits are indeterminate. Do not set these

bits.

2RTRMSK

Remote transmission request Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21

Bit Number Bit Mnemonic Description

7 - 0 IDMSK28:2 1

IDentifier Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

110

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4126L–CAN–01/08

Table 84. CANIDM2 Register for V2.0 Part B

CANIDM2 for V2.0 Part B (S:C5h)

CAN Identifier Mask Registers 2

Note: 1. The ID Mask is only used for reception.

No default value after reset.

Table 85. CANIDM3 Register for V2.0 Part B

CANIDM3 for V2.0 Part B (S:C6h)

CAN Identifier Mask Registers 3

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13

Bit Number Bit Mnemonic Description

7 - 0 IDMSK20:1 3

IDentifier Mask Value(1)

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

76543210

IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5

Bit Number Bit Mnemonic Description

7 - 0 IDMSK12:5

IDentifier Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

111

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4126L–CAN–01/08

Table 86. CANIDM4 Register for V2.0 Part B

CANIDM4 for V2.0 Part B (S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 87. CANMSG Register

CANMSG (S:A3h)

CAN Message Data Register

No default value after reset.

76543210

IDMS K 4 I DMSK 3 IDMSK 2 IDMSK 1 ID MSK 0 RTRMS K - IDEMSK

Bit Number Bit Mnemonic Description

7 - 3 IDMSK4:0

IDentifier Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 43.

2RTRMSK

Remote transmission request Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension Mask Value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

MSG 7MSG 6MSG 5MSG 4MSG 3MSG 2MSG 1MSG 0

Bit Number Bit Mnemonic Description

7 - 0 MSG7:0

Message Data

This register contains the mailbox data byte pointed at the page

message object register.

After writing in the page message object register, this byte is equal

to the specified message location (in the mailbox) of the pre-

defined identifier + index. If auto-incrementation is used, at the end

of the data register writing or reading cycle, the mailbox pointer is

auto-incremented. The range of the counting is 8 with no end loop

(0, 1,..., 7, 0,...)

112

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4126L–CAN–01/08

Table 88. CANTCON Register

CANTCON (S:A1h)

CAN Timer ClockControl

Reset Val ue = 00h

Table 89. CANTIMH Register

CANTIMH (S:ADh)

CAN Timer High

Reset Val ue = 0000 0000b

Table 90. CANTIML Register

CANTIML (S:ACh)

CAN Timer Low

Reset Val ue = 0000 0000b

76543210

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

Bit Number Bit Mnemonic Description

7 - 0 TPRESC7:0

Timer Prescaler of CAN Timer

This register is a prescaler for the main timer upper counter

range = 0 to 255.

See Figure 44.

76543210

CANGTIM

15 CANGTIM

14 CANGTIM

13 CANGTIM

12 CANGTIM

11 CANGTIM

10 CANGTIM

9CANGTIM

Bit Number Bit Mnemonic Description

7 - 0 CANGT I M15:8 High byte of Message Timer

See Figure 44.

76543210

CANGTIM

7CANGTIM

6CANGTIM

5CANGTIM

4CANGTIM

3CANGTIM

2CANGTIM

1CANGTIM

Bit Number Bit Mnemonic Description

7 - 0 CANGTIM 7:0 L ow byte of Message Timer

See Figure 44.

113

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4126L–CAN–01/08

Table 91. CANSTMPH Register

CANSTMPH (S:AFh Read Only)

CAN Stamp Timer High

No default value after reset

Table 92. CANSTMPL Register

CANSTMPL (S:AEh Read Only)

CAN Stamp Timer Low

No default value after reset

Table 93. CANTTCH Register

CANTTCH (S:A5h Read Only)

CAN TTC Timer High

Reset Val ue = 0000 0000b

Table 94. CANTTCL Register

CANTTCL (S:A4h Read Only)

CAN TTC Timer Low

Reset Val ue = 0000 0000b

76543210

TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 TIMSTMP 9 TIMS T M P 8

Bit Number Bit Mnemonic Description

7 - 0 TIMSTMP 15:8 H i gh by te of Time Stamp

See Figure 44.

76543210

TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

Bit Number Bit Mnemonic Description

7 - 0 T I MSTM P7:0 Low byte of Time Stamp

See Figure 44.

76543210

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIM TTC 8

Bit Number Bit Mnemonic Description

7 - 0 TIMTTC15:8 High by te of TTC Time r

See Figure 44.

76543210

TIMTTC 7 TIM TTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0

Bit Number Bit Mnemonic Description

7 - 0 TIM TTC 7 :0 Low Byte of TTC Timer

See Figure 44.

114

AT/T89C51CC02

4126L–CAN–01/08

Programmable

Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. T he PCA co nsists of a dedic ated timer /counte r which se rves as the time ba se for

an arra y of two c ompar e/cap ture mod ules . Its clock input c an be pro gramm ed to co unt

any of the following signals:

• PCA clock frequency/6 (See “clock” section)

• PCA clock frequency/2

• Timer 0 overflow

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

• Rising and/or falling edge capture,

• Software timer

• High-speed output

• Pulse width modulator

When the c ompare /capture m odules are progra mmed in ca pture mo de, software timer,

or high speed output mode, an interrupt can be generated when the module executes its

function. Both modules and the PCA timer overflow share one interrupt vector.

The PCA timer /counter and compa re/captu re mod ules share P ort 1 for external I/Os.

These pi ns are listed below. If the pin is not used for the PCA , it can still be used for

standard I/O.

PCA Timer The PCA timer is a common time base for both modules (See Figure 9). The timer count

source is determine d from the CPS1 and CP S0 bits in the CMOD SFR (S ee Table 8)

and can be programmed to run at:

• 1/6 the PCA clock frequency.

• 1/2 the PCA clock frequency.

• The Timer 0 overflow.

• The input on the ECI pin (P1.2).

PCA Component External I/O Pin

16-bit Counter P1.2/ECI

16-bit Module 0 P1.3/CEX0

16-bit Module 1 P1.4/CEX1

115

AT/T89C51CC02

4126L–CAN–01/08

Figure 46. PCA Timer/Counter

The CMOD register includes three additional bits associated with the PCA.

• The CIDL bit which allows the PCA to stop during idle mode.

• The ECF bit which when set causes an interrupt and the PCA overflow flag CF in

CCON register to be set when the PCA timer overflows.

The CCON registe r contains the run c ontrol bit for the PCA and the fl ags for the PCA

timer and each module.

• The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.

• The CF bit is set when the PCA counter overflows and an interrupt will be generated

if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

• The CCF0:1 bits are the flags for the modules (CCF0 for module0...) and are set by

hardware when either a match or a capture occurs. These flags also can be cleared

by software.

CIDL CPS1 CPS0 ECF

CH CL

16-bit up counter

To PCA

modules

FPca/6

FPca/2

T0 OVF

P1.2

Idle

CMOD

0xD9

CF CR CCON

0xD8

CCF1 CCF0

overflow

116

AT/T89C51CC02

4126L–CAN–01/08

PCA Modules Each one of the two compare/capture modules has six possible functions. It can

perform:

• 16-bit Capture, positive-edge triggered

• 16-bit Capture, negative-edge triggered

• 16-bit Capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High Speed Output

• 8-bit Pulse Width Modulator.

Each module in the PCA has a specia l functi on register asso ciated with it (CCAP M0 for

module 0 ...) . The CCAPM0:1 reg isters contai n the bits that control the mode that each

module will operate in.

• The ECCF bit enables the CCF flag in the CCON register to generate an interrupt

when a match or compare occurs in the associated module.

• The PWM bit enables the pulse width modulation mode.

• The TOG bit when set causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare

• The match bit MAT when set will cause the CCFn bit in the CCON register to be set

when there is a match between the PCA counter and the module’s capture/compare

• The two bits CAPN and CAPP in CCAPMn register determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the

CAPP bit enables the positive edge. If both bits are set both edges will be enabled.

• The bit ECOM in CCAPM register when set enables the comparator function.

117

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4126L–CAN–01/08

PCA Interrupt

Figure 47. PCA Interrupt System

PCA Capture Mode To use one of the PCA modul es in capture mod e either one or both of the CCAP M bits

CAPN and CAPP for that module must be set. The external CEX input for the module

(on port 1) is sa mpl ed fo r a trans i tio n. Wh en a v ali d tr ansi tion occurs the PC A har d war e

loads the value of the PCA counter registers (CH and CL) into the module’s capture reg-

isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

Figure 48. PCA Capture Mode

CF CR CCON

0xD8

CCF1 CCF0

Module 1

Module 0

PCA Timer/Counter

To Interr u p t

IEN0.6 EA

IEN0.7

ECF

CMOD.0 ECCFn

CCAPMn.0

CEXn

n = 0, 1

PCA Counter

(8-bits) CL

(8-bits)

CCAPnH CCAPnL

CCFn

CCON Reg

PCA

Interrup

Reques

- 0CAPPnCAPNn000ECCFn

7 CCAPMn Register (n = 0, 1) 0

118

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4126L–CAN–01/08

16-bit Soft ware Timer

Mode The PCA mod ules can be used as software tim ers by settin g both the ECOM and MAT

bits in th e modu les CC APMn registe r. T he P CA tim er will be c ompar ed to the mod ule’s

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

Figure 49. PCA 16-bit Software Timer and High Speed Output Mode

CCAPnL

(8 bits)

CCAPnH

(8 bits)

-ECOMn0 0MATn TOGn0 ECCFn

70 CCAPMn Register

(n = 0, 1)

(8 bits)

16-bit Comparator Match

Enable CCFn

CCON re g

PCA

Interrupt

Request

CEXn

Compare/Capture Module

PCA Counter

“0”

“1”

Reset

Write to

CCAPnL

Write to CCAPnH

For software Ti mer m ode, set ECOMn and MATn.

For high speed output mode, set ECOMn, MATn and TOGn.

Toggle

(8 bits)

119

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4126L–CAN–01/08

High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activ ate this mode the T OG, MAT, and ECO M bits in the module’ s CCAPMn SFR

must be set.

Figure 50. PCA High Speed Output Mode

Pulse Width Modulator

Mode All the PCA modules can be used as PWM outputs. The output frequency depends on

the source for the PCA timer. All the modules will have the same output frequency

becau se they al l share the PCA ti mer. Th e duty cyc le of eac h modul e is indep endent ly

variable using the module’s c apture register CCAPLn. When the value of the PCA CL

SFR is les s than the v alue in the mo dule’s CC APLn S FR the outp ut will be low, wh en it

is equal to or greater than it, t he output will be hig h. When CL overfl ows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with-

out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

CH CL

CCAPnH CCAPnL

ECOMn CCAPMn, n = 0 to 1

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16 bit comparator Match

CF CR CCON

0xD8

CCF1 CCF0

PCA IT

Enable

CEXn

PCA counter/timer

“1”“0”

Write to

CCAPnL

Reset

Write to

CCAPnH

120

AT/T89C51CC02

4126L–CAN–01/08

Figure 51. PCA PWM Mode

CL rolls over from FFh TO 00h loads

CCAPnH contents into CCAPnL

CCAPnL

CCAPnH

8-bit

Comparator

CL (8 bits)

“0”

“1”

CL < CCAPnL

CL >= CCAPnL CEX

PWMn

CCAPMn.1

ECOMn

CCAPMn.6

121

AT/T89C51CC02

4126L–CAN–01/08

PCA Registers Table 95. CMOD Register

CMOD (S:D9h)

PCA Counter Mode Register

Reset Valu e = 0XX X X0 00b

76543210

CIDL - - - - CPS1 CPS0 ECF

Bit Number Bit

Mnemonic Description

7CIDL

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2-1 CPS1:0

EWC Count Pulse Sele ct bits

CPS1 CPS0 Clock source

0 0 Internal Clock, FPca/6

0 1 Internal Clock, FPca/2

1 0 Timer 0 overflow

1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

0ECF

Enable PCA Count e r Ov e r flow Inter rupt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

122

AT/T89C51CC02

4126L–CAN–01/08

Table 96. CCON Register

CCON (S:D8h)

PCA Counter Control Register

Reset Value = 00xx xx 00b

76543210

CFCR----CCF1 CCF0

Bit Number Bit Mnemonic Descri ptio n

7CF

PCA Timer/Counter Overflow flag

Set by hardware when the PCA T imer/Counter rolls over. This

generates a PCA interrupt request if the ECF bit in CMOD register

is set.

Must be cleared by software.

6CR

PCA Timer / C ounte r Run Co ntrol bit

Clear to turn the PCA Ti mer/Count er off.

Set to turn the PCA Timer/Counter on.

5-2 - Reserved

The value read from these bist are indeterminate. Do not set these

bits.

1CCF1

PCA Module 1 Compare/Capture Flag

Set by hardware when a match or capture occurs. This generates a

PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set.

Must be cleared by software.

0CCF0

PCA Module 0 Compare/Capture Flag

Set by hardware when a match or capture occurs. This generates a

PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set.

Must be cleared by software.

123

AT/T89C51CC02

4126L–CAN–01/08

Table 97. CCAPnH Registers

CCAP0H (S:FAh)

CCAP1H (S:FBh)

PCA High Byte Compare/Capture Module n Register (n=0..1)

Reset Value = 0000 0000b

Table 98. CCAPnL Registers

CCAP0L (S:EAh)

CCAP1L (S:EBh)

PCA Low Byte Compare/Capture Module n Register (n=0..1)

Reset Value = 0000 0000b

76543210

CCAPnH 7 CCAPnH 6 CCAPnH 5 CC APnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0

Bit Number Bit Mnemonic Descri ptio n

7:0 CCAPnH 7:0 High byte of EWC-PCA comparison or capture values

76543210

CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0

Bit Number Bit Mnemonic Descri ptio n

7:0 CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values

124

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Table 99. CCAPMn Registers

CCAPM0 (S:DAh)

CCAPM1 (S:DBh)

PCA Compare/Capture Module n Mode registers (n=0..1)

Reset Value = X000 0000b

76543210

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Bit Number Bit Mnemonic Descri ptio n

Reserved

The Value read from this bit is indeterminate. Do not set this bit.

6ECOMn

Enable Compare Mode Module x bit

Clear to disable the Compare function.

Set to enable the Compare function.

The Compare function is used to implement the software Timer, the

high-speed output, the Pulse Width Modulator (PWM) and the

Watchdog Timer (WDT).

5 CAPPn

Capture Mode (Positive) Module x bit

Clear to disable the Capture function triggered by a positive edge

on CEXx pin.

Set to enable the Capture function triggered by a positive edge on

CEXx pin

4CAPNn

Capture Mode (Negative) Module x bit

Clear to disable the Capture function triggered by a negative edge

on CEXx pin.

Set to enable the Capture function triggered by a negative edge on

CEXx pin.

3MATn

Match Module x bit

Set when a match of the PCA Counter with the Compare/Capture

2TOGn

Toggle Module x bit

The toggle mode is configured by setting ECOMx, MA Tx and TOGx

bits.

Set when a match of the PCA Counter with the Compare/Capture

1PWMn

Pulse W idth Modulati on Module x Mode bit

Set to configure the module x as an 8-bit Pulse Width Modulator

with output waveform on CEXx pin.

0 ECCFn

Enable CCFx Interrupt bit

Clear to disable CCFx bit i n CCON register to generate an interrupt

request.

Set to enable CCFx bit in CCON register to generate an interrupt

request.

125

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4126L–CAN–01/08

Table 100. CH Register

CH (S:F9h)

PCA Counter Register High value

Reset Value = 0000 00000b

Table 101. CL Register

CL (S:E9h)

PCA counte r Register Lo w value

Reset Value = 0000 00000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 C H 1 CH 0

Bit Number Bit Mnemonic Descri ptio n

7:0 CH 7:0 High byte of Timer/Counter

76543210

CL 7CL 6CL 5CL 4CL 3CL 2CL 1CL 0

Bit Number Bit Mnemonic Descri ptio n

7:0 CL0 7:0 Low byte of Timer/Counter

126

AT/T89C51CC02

4126L–CAN–01/08

Analog-to-Digital

Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the

T89C51CC02. Eight ADC channel s are available for s ampling of the external sources

AN0 t o AN7. An analog multiple xer all ows the singl e ADC con verter to s elec t one from

the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit-

cascad ed pote nti ome tric ADC.

Two modes of conversion are available:

- Standard conversion (8 bits).

- Precision conversion (10 bits).

For the precision conversion, set bit PSIDLE in ADCON register and start conversion.

The devic e is in a pseud o-idle mode, the CPU does not run but the peripheral s are

always running . Th is m ode al lows digital nois e to be as low as poss ible , to e nsur e hig h

precision conversion.

For th is mode it is nec essa ry to wo rk w ith end o f conv ersio n inter rupt, wh ich is th e only

way to wake the device up.

If another int errupt occurs during the precisi on conversion, it will be served only after

this conv er sion is compl ete d.

Features • 8 channels with multiplexed inputs

• 10-bit cascaded potentiometric ADC

• Conversion time 16 micro-seconds (typ.)

• Zero Error (offset) ± 2 LSB max

• Positive External Reference Voltage Range (VAREF) 2.4 to 3.0-volt (typ.)

• ADCIN Range 0 to 3-volt

• Integral non-linearity typical 1 LSB, max. 2 LSB

• Differential non-linearity typical 0.5 LSB, max. 1 LSB

• Conversion Complete Flag or Conversion Complete Interrupt

• Selectable ADC Clock

ADC Port1 I/O Functions Port 1 pins are gener al I/O tha t are shar ed wit h the ADC ch annels . The ch annel select

bit in ADCF register de fine which A DC channel/por t1 pin will be used as ADCIN. The

remaini ng ADC ch ann els /p ort1 pi ns can b e use d as gene ral pu rp os e I/O or as the alter-

nate function that is available.

A conversion launched on a channel which are not selected on ADCF register will not

have any effect.

VAREF VAREF should be connected to a low impe dance poin t and must remain i n the range

specified VAREF absolute maximum range (See section “AC-DC”).

. If the ADC is not used, it is recommended to tie VAREF to VAGND.

127

AT/T89C51CC02

4126L–CAN–01/08

Figure 52. ADC Description

Figure 5 3 sh ows th e tim ing diagram of a com ple te conv ersio n. F or sim plicit y, th e figu re

depicts the waveforms in idealized form and do not provide precise timing information.

For ADC c ha racte ris tic s and timi ng par am eters r efe r to t he secti on “AC Char ac teri sti cs”

of this datasheet.

Figure 53. Timing Dia gram

Note: Tsetup min, see the AC Parameter for A/D conversion.

Tconv = 11 clock ADC = 1sample and hold + 10-bit conversion

The user must ensure that Tsetup time between setting ADEN and the start of the first conversion.

ADC Converter

Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set ( See Figure 55 ). Clear this flag for re-

arming the inte rru pt.

Note: Always leave Tsetup time before starting a conversion unless ADEN is permanently

high. In this case one should wait Tsetup only before the first conversion

Rai

AN0/P1.0

AN1/P1.1

AN2/P1.2

AN3/P1.3

AN4/P1.4

AN5/P1.5

AN6/P1.6

AN7/P1.7

000

001

010

011

100

101

110

111

SCH2

ADCON.2 SCH0

ADCON.0

SCH1

ADCON.1

ADC

CLOCK

ADEN

ADCON.5 ADSST

ADCON.3

ADEOC

ADCON.4 ADC

Interrupt

Request

EADC

IEN1.1

CONTROL

AVSS

Sam ple and Ho ld

ADDH

VAREF

R/2R DAC

VAGND

-ADDL

SAR

ADCIN

Cai

ADEN

ADSST

ADEOC

TSETUP

TCONV

CLK

128

AT/T89C51CC02

4126L–CAN–01/08

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 102. Selected Analog input

Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input vol tage equals VAGND, the A DC converts it to 000h. Input v oltage between

VAREF and VAG ND ar e a str ai ght-l ine lin ear c onv er sion . Al l oth er volt ag es w ill r esu lt i n

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN shoul d not exceed VAREF absol ute maximum range (See secti on

“AC-DC”).

Clock Selection The ADC cloc k is the same as CPU.

The maxi mum cl ock freq uency is defined in the D C parme ter for A/D c onverter . A pre s-

caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

if PRS = 0 then FADC = Fperiph / 64

if PRS > 0 then FADC = Fperiph / 2 x PRS

Figure 54. A/D Converte r Clock

ADC Standby Mode When the ADC is not used , it is pos sible to se t it in stand by mode by cl earing bi t ADEN

in ADCON register. In this mode the power dissipation is reduced.

SCH2 SCH1 SCH0 Selected Analog Input

000AN0

001AN1

010AN2

011AN3

100AN4

101AN5

110AN6

111AN7

Prescaler ADCLK A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

129

AT/T89C51CC02

4126L–CAN–01/08

IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 55. ADC interrupt structure

Routine Examples 1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable ’channel’ contains the channel to convert

// The variable ’value_converted’ is an unsigned int

// Clear the field SCH[2:0]

ADCON &= F8h

// Select channel

ADCON |= channel

// Start conversion in standard mode

ADCON |= 08h

// Wait flag End of conversion

while((ADCON & 01h)!= 01h)

// Clear the End of conversion flag

ADCON &= EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable ’channel’ contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON &= F8h

// Select the channel

ADCON |= channel

// Start conversion in precision mode

ADCON |= 48h

Note: To enable the ADC interrupt: EA = 1

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

130

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4126L–CAN–01/08

Registers Table 103. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Val ue = 0000 0000b

Table 104. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Val ue = X00 0 0000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 C H 1 CH 0

Bit

Number Bit

Mnemonic Description

7 - 0 C H 0:7 Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

76543210

- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from these bits are indeterminate. Do not set these bits.

6 PSIDLE Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enable/Standby Mode

Set to enable ADC

Clear for S tandby mode.

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

3 ADSST St art and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0 SCH2:0 Selection of Channel to Convert

See Table 102

131

AT/T89C51CC02

4126L–CAN–01/08

Table 105. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Reset Val ue = XXX 0 0000 b

Table 106. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High Byte Register

Reset Val ue = 00h

Table 107. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low Byte Register

Reset Val ue = 00h

76543210

- - - PRS 4PRS 3PRS 2PRS 1PRS 0

Bit

Number Bit

Mnemonic Description

7 - 5 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

4-0 PRS4:0 Clock Prescaler

Fadc = Fcpuclock/(4*PRS)) in X1 mode

Fadc=Fcpuclock/(2*PRS ) in X2 mode

76543210

ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2

Bit

Number Bit

Mnemonic Description

7 - 0 ADAT9:2 ADC result

bits 9-2

76543210

------ADAT 1ADAT 0

Bit

Number Bit

Mnemonic Description

7 - 2 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

1-0 ADAT1:0 ADC result

bits 1-0

132

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4126L–CAN–01/08

Interrupt System

Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and

INT1), three time r interrupts ( timers 0, 1 an d 2), a se rial port in terrupt, a PCA, a CAN

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below.

Figure 56. Interrupt Control System

ECAN

IEN1.0

EX0

IEN0.0

External

Interrupt 0

INT0#

IEN0.7

EX1

IEN0.2

External

Interrupt 1

INT1#

ET0

IEN0.1

Timer 0

IEN0.6

PCA

ET1

IEN0.3

Timer 1

IEN0.4

UART

EADC

IEN1.1

A to D

Converter

ETIM

IEN1.2

CAN Timer

CAN

Interrupt Enable Lowest Priority Interrupts

Highest

Priority Enable

Priority

Interrup

TxDC

RxDC

AIN1:0

IPH/L

Controller

Timer 2

ET2

IEN0.5

TxD

RxD

CEX0:1

133

AT/T89C51CC02

4126L–CAN–01/08

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each int errupt source can al so be indivi dually programme d to one of fou r priority le vels

by setting or c learing a bit in t he Inter rupt Pr iority regis ters. The Tabl e belo w shows th e

bit values and priority levels associated with each combination.

Table 108. Priority Level bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is servi ced. Thus within ea ch prio rity le vel ther e is a se cond p riority str ucture

determined by the polling sequence, See Table 109.

Table 109. Interrupt Priority Within Level

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowest)

011

102

1 1 3 (Highest)

Interrupt Name Interrupt Address Vector Interrupt Number Polling Priority

External interrupt (INT0) 0003h 1 1

Timer0 (TF0) 000Bh 2 2

External interrupt (INT1) 0013h 3 3

Timer 1 (TF1) 001Bh 4 4

PCA (CF or CCFn) 0033h 7 5

UART (RI or TI) 0023h 5 6

Timer 2 (TF2) 002Bh 6 7

CAN (Txok, Rxok, Err or OvrBuf ) 003Bh 8 8

ADC (ADCI) 0043h 9 9

CAN Timer Overflow (OVRTIM) 004Bh 10 10

134

AT/T89C51CC02

4126L–CAN–01/08

Registers Figure 57. IEN0 Register

IEN0 (S:A8h)

Interrupt Enable Register

Reset Val ue = 0000 0000b

bit addressable

76543210

EA EC ET2 ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All Interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

6EC

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

5ET2

Timer 2 Overflow Interrupt Enable bit

Clear to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

4ES

Serial port En a b le bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

3ET1

Timer 1 Overflow Interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

2EX1

External Interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 Overflow Interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

0EX0

External Interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

135

AT/T89C51CC02

4126L–CAN–01/08

Figure 58. IEN1 Register

IEN1 (S:E8h)

Interrupt Enable Register

Reset Value = xxxx x000b

bit addressable

76543210

---- ETIM EADCECAN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2ETIM

TImer overrun Interrupt Enable bit

Clear to disable the timer overrun interrupt.

Set to enable the timer overrun interrupt.

1 EADC ADC Interrupt Ena ble bit

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

0ECAN

CAN Interrupt Enable bit

Clear to disable the CAN interrupt.

Set to enable the CAN interrupt.

136

AT/T89C51CC02

4126L–CAN–01/08

Table 110. IPL0 Register

IPL0 (S:B8h)

Interrupt Enable Register

Reset Val ue = X00 0 0000b

bit addressable

76543210

- PPC PT2 PS PT1 PX1 PT0 PX0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PPCH for priority level

5PT2

Timer 2 Overflow Interrupt Priority bit

Refer to PT2H for priority level.

4PS

Serial Port Priority bit

Refer to PSH for priority level.

3PT1

Timer 1 Overflow Interrupt Priority bit

Refer to PT1H for priority level.

2PX1

External Interrupt 1 Priority bit

Refer to PX1H for priority level.

1PT0

Timer 0 Overflow Interrupt Priority bit

Refer to PT0H for priority level.

0PX0

External Interrupt 0 Priority bit

Refer to PX0H for priority level.

137

AT/T89C51CC02

4126L–CAN–01/08

Table 111. IPL1 Register

IPL1 (S:F8h)

Interrupt Priority Low Register 1

Reset Value = XXXX X000b

bit addressable

76543210

---- POVRLPADCL PCANL

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRL

Timer Overrun Interrupt Priority Level Less Significant bit

Refer to PI2CH for priority level.

1PADCL

ADC Interrupt Priority Level Less Significant bit

Refer to PSPIH for priority level.

0PCANL

CAN Interrupt Priority Level Less Significant bit

Refer to PKBH for priority level.

138

AT/T89C51CC02

4126L–CAN–01/08

Table 112. IPH0 Regist er

IPH0 (B7h)

Interrupt High Priority Register

Reset Val ue = X00 0 0000b

76543210

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

PCA Interrupt Priority Level Most Significant bit

PPCH PPC Priority level

0 0 Lowest

1 1 Highest priority

5PT2H

Timer 2 Overflow Interrupt High Priority bit

PT2H PT2 Priority Level

0 0 Lowest

1 1 Highest

4 PSH

Serial Port High Priority bit

PSH PS Priority Level

0 0 Lowest

1 1 Highest

3PT1H

Timer 1 Overflow Interrupt High Priority bit

PT1H PT1 Priority Level

0 0 Lowest

1 1 Highest

2PX1H

External Interrupt 1 High Priority bit

PX1H PX1 Priority Level

0 0 Lowest

1 1 Highest

1PT0H

Timer 0 Overflow Interrupt High Priority bit

PT0H PT0 Priority Level

0 0 Lowest

1 1 Highest

0PX0H

External Interrupt 0 High Priority bit

PX0H PX0 Priority Level

0 0 Lowest

1 1 Highest

139

AT/T89C51CC02

4126L–CAN–01/08

Table 113. IPH1 Regist er

IPH1 (S:F7h)

Interrupt high priority Register 1

Reset Val ue = XXXX X000b

76543210

---- POVRHPADCH PCANH

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRH

Timer Overrun Interrupt Priority Level Most Significant bit

POVRH POVRLPriority level

0 0 Lowest

1 1 Highest

1 PADCH

ADC Interrupt Priority Level Most Significant bit

PADCH PADCLPriority level

0 0 Lowest

1 1 Highest

0PCANH

CAN Interrupt Priority Level Most Significant bit

PCANH PCANLPr iority level

0 0 Lowest

1 1 Highest

140

AT/T89C51CC02

4126L–CAN–01/08

Electrical Characteristics

DC Parameters for

Standard Voltage

TA = -40°C to +85°C; VSS = 0 V; VCC = 3 volts to 5.5 volts; F = 0 to 40 MHz

Notes: 1. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.

2. Flash retention is guaranteed with the same formula for VCC min down to 0V.

3. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Absolute Maximum Ratings

I = industrial....................................................... -40°C to 85°C

Storage Temp eratu re ................. ...... ..... ...... . -6 5°C to + 150°C

Volta ge on VCC from VSS .....................................-0.5V to + 6V

Voltage on Any Pin from VSS . ..... ...... ..... ....-0.5V to VCC + 0.2V

Power Dissipation ............................................................. 1 W

Note: Stresses at or above those listed under “Absolute

Maximu m Rati ngs ” may caus e perma nen t damag e to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Power Dissipation value is based on the maximum

allowable die temperature and the thermal resistance

of the package.

Table 114. DC Parameters in Standard Voltage

Symbol Parameter Min Typ(1) Max Unit Test Conditions

VIL Input Low Voltage -0.5 0.2Vcc - 0.1 V

VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V

VIH1(2) Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V

VOL Output Low V oltage, ports 1, 2, 3 and 4(3) 0.3

0.45

1.0

IOL = 100 μA

IOL = 1.6 mA

IOL = 3.5 mA

VOH Output High V oltage, ports 1, 2, 3, 4 and 5 VCC - 0.3

VCC - 0.7

VCC - 1.5

IOH = -10 μA

IOH = -30 μA

IOH = -60 μA

VCC = 5V ± 10%

RRST RST Pulldown Resistor 50 90 200 kΩ

IIL Logical 0 Input Current ports 1, 2, 3 and 4 -50 μA Vin = 0.45V

ILI Input Leakage Current ±10 μA 0.45V < Vin < VCC

ITL Logical 1 to 0 Transition Current, ports 1, 2, 3

and 4 -650 μA Vin = 2.0V

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA = 25°C

IPD Power-down Current 160 400 μA3V < V

CC < 5.5V(4)

ICC

Power Supply Current

ICCOP(6) = 0.7 Freq (MHz) + 3 mA

ICCIDLE (5)= 0.6 Freq (MHz) + 2 mA

141

AT/T89C51CC02

4126L–CAN–01/08

Maximum IOL per 8-bit port:

Ports 1, 2 and 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

4. Power-down ICC is measured with all output pins disconnected; XTAL2 NC.; RST = VSS (See Figure 61.).

5. I dl e ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -

0.5V; XTAL2 N.C; RST = VSS (See Figure 60.).

6. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (Se e Fig ur e 62.) , VIL =

VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; RST = VCC. ICC would be slightly higher if a crystal oscillator used (See Figure

59.).

Figure 59. ICC Test Condition, Active Mode

Figure 60. ICC Test Condition, Idle Mode

VaVcc

VCC

ICC

(NC)

CLOCK

SIGNAL

VCC

All other pins are disconnecte

RST

XTAL2

XTAL1

VSS

VCC

VAGND

RST

XTAL2

XTAL1

VCC

ICC

(NC)

VaVcc

VCC

All other pins are disconnecte

CLOCK

SIGNAL

VSS

VAGND

142

AT/T89C51CC02

4126L–CAN–01/08

Figure 61. ICC Test Condition, Power-down Mode

Figure 62. Clock Signal Waveform for ICC Tests in Active and Idle Modes

DC Parameters for A/D

Converter Table 115. DC Parameters for AD Converter in Precision Conversion

Notes: 1. Typicals are based on a limited number of samples and are not guaranteed.

2. With ADC enabled.

VaVcc

RST

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

VAGND

VCC-0.5V

0.45V 0.7VCC

0.2VCC-0.1

TCLCH

TCHCL

TCLCH = TCHCL = 5ns.

Symbol Parameter Min Typ(1) Max Unit Test Conditions

AVin Analog input voltage Vss- 0.2 Max Vref

+ 0.6 V

VaVcc Analog supply voltage Vref Vcc Vcc +

10% V

Rref(2) Resistance between V aref and Vss 12 16 24 KΩ

Varef Reference voltage 2.40 3.00 V

Cai Analog input Capacitance 60 pF During sampling

Rai Analog input Resistor 400 ΩDuring sampling

INL Integral non linearity 1 2 lsb

DNL Differential non linearity 0.5 1 lsb

OE Offset error -2 2 lsb

143

AT/T89C51CC02

4126L–CAN–01/08

AC Parameters

Serial Port Timing - Shift

Table 118. AC Parameters for a Variable Clock

Symbol Parameter

TXLXL Serial port clock cycl e time

TQVHX Output data set-up to clock rising edge

TXHQX Output data hold after clock rising edge

TXHDX Input data hold after clock rising edge

TXHDV Clock rising edge to input data valid

Table 117. AC Parameters for a Fix Clock (F = 40 MHz)

Symbol Min Max Units

TXLXL 300 ns

TQVHX 200 ns

TXHQX 30 ns

TXHDX 0ns

TXHDV 117 ns

Symbol Type Standard

Clock X2 Clock x parameter

for -M range Units

TXLXL Min 12 T 6 T ns

TQVHX Min 10 T - x 5 T - x 50 ns

TXHQX Min 2 T - x T - x 20 ns

TXHDX Min x x 0 ns

TXHDV Max 10 T - x 5 T- x 133 ns

144

AT/T89C51CC02

4126L–CAN–01/08

Shift Register Timing Waveforms

External Clo ck Driv e

Characteristics (XTAL1) Table 119. AC Parameters

External Clo ck Driv e

Waveforms

AC Testing Input/Output Waveforms

AC in pu ts dur ing tes ting are dri ven a t VCC - 0.5 for a logic “1” and 0.45V for a logic “0” .

Timing measu rement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Float Waveforms

VALID VALID VALIDVALID VALID

VALID

INPUT DATA VALID

0123456 87

CLOCK

OUTPUT DATA

WRITE to SBUF

CLEAR RI

TXLXL

TQVXH TXHQX

TXHDV TXHDX SET TI

SET RI

INSTRUCTION

01234567

VALID

Symbol Parameter Min Max Units

TCLCL Osc illator Period 25 ns

TCHCX High Time 5 ns

TCLCX Low Time 5 ns

TCLCH Rise Time 5 n s

TCHCL Fall Time 5 ns

TCHCX/TCLCX Cyclic ratio in X2 Mode 40 60 %

VCC-0.5V

0.45V

0.7VCC

0.2VCC-0.1

TCHCL TCLCX TCLCL

TCLCH

TCHCX

INPUT/OUTPUT 0.2 VCC + 0.9

0.2 VCC - 0.1

VCC -0.5V

0.45 V

FLOAT

VOH - 0.1V

VOL + 0.1V

VLOAD VLOAD + 0.1V

VLOAD - 0.1V

145

AT/T89C51CC02

4126L–CAN–01/08

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level

occurs. IOL/IOH ≥ ± 20mA.

Clock Waveforms Valid in normal clock mode. In X2 Mode XTAL2 must be changed to XTAL2/2.

Flash/EEPROM Memory Table 120. Memory AC Timing

Vcc = 3.0V to 5.5V, TA = -40°C to +85°C

Figure 63. Flash Memory - Internal Busy Waveforms

A/D Converter Table 121. AC Parameters for A/D Conversion

Symbol Parameter Min Typ Max Unit

TBHBL Flash/EEPROM Internal Busy

(Programming) Time 13 17 ms

NFCY Number of Flash/EEPROM Erase/Write

Cycles 100 000 cycles

TFDR Flash/EEPROM Data Retention Time 10 years

FBUSY bit TBHBL

Symbol Parameter Min Typ Max Unit

TSETUP 4µs

ADC Clock Frequency 700 KHz

146

AT/T89C51CC02

4126L–CAN–01/08

Ordering Information

Factory default programming for T89C51CC02CA-xxxx is Bootloader CAN and

HSB = BBh:

•X1 mode

• BLJB = 0 : jump to Bootloader

• LB2 = 0 : Security Level 3.(1)

Factory default programming for T89C51CC02UA-xxxx is Bootloader UART and

HSB = BBh:

•X1 mode

• BLJB = 0 : jump to Bootloader

• LB2 = 0 : Security Level 3.(1)

Notes: 1. LB2 = 0 is not described in Table 22 Program load bit. LB2 = 0 is equivalent to LB1 =

0: Security Level 3.

2. Customer can change these modes by re-programming with a parallel programmer,

this can be done by an Atmel distributor.

Part Number Bootloader Temperature

Range Pa ckage Packing Product Marking

T89C51CC02CA-RATIM

OBSOLETE

T89C51CC02CA-SISIM

T89C51CC02CA-TDSIM

T89C51CC02CA-TISIM

T89C51CC02UA-RATIM

T89C51CC02UA-SISIM

T89C51CC02UA-TDSIM

T89C51CC02UA-TISIM

AT89C51CC02CA-RATUM CAN(2) Industrial & Green VQFP32 Tray 89C51CC02CA-UM

AT89C51CC02CA-SISUM CAN(2) Industrial & Green PLCC28 Stick 89C51CC02CA-UM

AT89C51CC02CA-TDSUM CAN(2) Industrial & Green SOIC24 Stick 89C51CC02CA-UM

AT89C51CC02CA-TISUM CAN(2) Industrial & Green SOIC28 St ick 89C51CC02CA-UM

AT89C51CC02UA-RATUM UART(2) Industrial & Green VQFP32 Tray 89C51CC02UA-UM

AT89C51CC02UA-SISUM UART(2) Industrial & Green PLCC28 Stick 89C51CC02UA-UM

AT89C51CC02UA-TDSUM UART(2) Industrial & Green SOIC24 Stick 89C51CC02UA-UM

AT89C51CC02UA-TISUM UART(2) Industrial & Green SOIC28 Stick 89C51CC02UA-UM

147

AT/T89C51CC02

4126L–CAN–01/08

Package Drawings

VQFP32

148

AT/T89C51CC02

4126L–CAN–01/08

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP

1/ CONTROLLING DIMENSIONS : INCHES

2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -

1982.

3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.

MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).

THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM

PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.

4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND

COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT

BOTTOM OF PARTING LINE.

5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.

6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE

" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .

DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

149

AT/T89C51CC02

4126L–CAN–01/08

PLCC28

150

AT/T89C51CC02

4126L–CAN–01/08

STANDARD NOTES FOR PLCC

1/ CONTROLLING DIMENSIONS : INCHES

2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982.

3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSION

MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER

SIDE.

151

AT/T89C51CC02

4126L–CAN–01/08

SOIC24

152

AT/T89C51CC02

4126L–CAN–01/08

SOIC28

153

AT/T89C51CC02

4126L–CAN–01/08

154

AT/T89C51CC02

4126L–CAN–01/08

Datasheet Revision

History

Changes from 4126C-

10/02 to 4126D - 04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.

2. Added note on Flash retention formula for VIH1, in Section "DC Parameters for

Standard Voltage", page 141.Changes from 4129F-11/02 to 4129G-04/03

1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.

2. Added note on Flash retention formula for VIH1, in Section "DC Parameters for

Standard Voltage", page 141.

Changes from 4126D -

05/03 to 4126E - 10/03 1. Updated “Electrical Characteristics” on page 140.

2. Corrected Figure 39 on page 82.

Changes from 4126E -

10/03 to 4126F - 12/03 1. Changed value of IPDMAX to 400, Section "Absolute Maximum Ratings",

page 140.

2. PCA , CPS0, register correction, Section "PCA Registers", page 121.

3. Cross Memory section added. Section "Operation Cross Memory Access",

page 44.

Changes from 4126F -

12/03 4126G - 08/04 1. Figure clock-out mode modified see, Figure 30 on page 65.

2. Corrected error in Table 51 on page 70, (1.25ms to 1.25s) for Time-out

Computation.

3. Added explanation on the CAN protocol, see Section “CAN Controller”, page 73.

Changes from 4126G -

08/04 to 4126H - 01/05 1. Various minor corrections throughout the document.

Changes from 4126H -

01/05 to 4126I 11/05 1. Added Green product ordering information.

Changes from 4126I to

4126J 05/06 1. Minor corrections throughout the document.

Changes from 4126J to

4126K 11/07 1. Updated Package drawings.

Changes from 4126K

11/07 to 4126L 02/08 1. Removed non-green part numbers from ordering information.

Table of Contents

Table of

Contents Features .................................................................................................1

Description ............................................................................................2

Block Diagram .......................................................................................2

Pin Configurations ................................................................................3

Pin Description...................................................................................... 5

I/O Configurations .................................................................................................7

Port Structure ....................................................................................................... 7

Read-Modify-Write Instructions............................................................................ 8

Quasi Bi-directional Port Operation...................................................................... 8

SFR Mapping .......................................................................................10

Clock .................................................................................................... 16

Description ......................................................................................................... 16

Register.............................................................................................................. 19

Power Management ............................................................................20

Reset Pin ..............................................................................................20

At Power-up (cold reset)..................................................................................... 20

During a Normal Operation (Warm Reset)......................................................... 21

Watchdog Reset................................................................................................. 21

Reset Recommendation to Prevent Flash Corruption.........................................22

Idle Mode............................................................................................................ 22

Power-down Mode ............................................................................................. 22

Registers .............................................................................................................25

Data Memory .......................................................................................26

Internal Space .................................................................................................... 26

Dual Data Pointer............................................................................................... 28

Registers ............................................................................................................ 29

EEPROM Data Memory .......................................................................31

Write Data in the Column Latches...................................................................... 31

Programming...................................................................................................... 31

Read Data .......................................................................................................... 31

Examples............................................................................................................ 32

Registers ............................................................................................................ 33

Program/Code Memory .............. ..... .............. ..... .... ..... .............. ..... ....34

Flash Memory Architecture ................................................................................ 34

Overview of FM0 Operations.............................................................................. 36

Registers ............................................................................................................ 42

Operation Cross Memory Access .....................................................44

Sharing Instructions........................................................................... 45

In-System Programming (ISP) ................. ..... .............. ..... .... ..... .........47

Flash Programming and Erasure ....................................................................... 47

Boot Process...................................................................................................... 48

Application-Programming-Interface.................................................................... 48

XROW Bytes ...................................................................................................... 49

Hardware Conditions.......................................................................................... 49

Hardware Security Byte...................................................................................... 50

Serial I/O Port ......................................................................................51

Framing Error Detection.................................................................................... 51

Automatic Address Recognition ......................................................................... 52

Given Addr ess................. ...... ................... ....... ...... ....... ...... .................... ...... ...... 52

Broadcast Address............................................................................................. 53

Registers .............................................................................................................54

Timers/Counters .................................................................................57

Timer/Counter Operations.................................................................................. 57

Timer 0 ............................................................................................................... 57

Timer 1 ............................................................................................................... 59

Interrupt.............................................................................................................. 60

Registers ............................................................................................................ 61

Timer 2 .................................................................................................64

Auto-Reload Mode ............................................................................................. 64

Programmable Clock-Output.............................................................................. 65

Registers ............................................................................................................ 66

Watchdog Timer ..................................................................................69

Watchdog Programming......................................................................................70

Watchdog Timer During Power-down Mode and Idle ......................71

Register.............................................................................................................. 71

CAN Controller ....................................................................................73

Table of Contents

iii

CAN Protocol...................................................................................................... 73

CAN Controller Description ................................................................................ 77

CAN Controller Mailbox and Registers Organization ......................................... 78

CAN Controller Management .............................................................80

IT CAN Management.......................................................................................... 81

Bit Timing and Baud Rate .................................................................................. 84

Fault Confinement.............................................................................................. 86

Acceptance Filter................................................................................................ 87

Data and Remote Frame.................................................................................... 88

Time Trigger Communication (TTC) and Message Stamping............................ 89

CAN Autobaud and Listening Mode................................................................... 90

Routine Examples .............................................................................................. 90

CAN SFRs.......................................................................................................... 93

Registers ............................................................................................................ 94

Programmable Counter Array (PCA) ...............................................114

PCA Timer........................................................................................................ 114

PCA Modules ................................................................................................... 116

PCA Interrupt.................................................................................................... 117

PCA Capture Mode .......................................................................................... 117

16-bit Software Timer Mode............................................................................. 118

High Speed Output Mode................................................................................. 119

Pulse Width Modulator Mode ........................................................................... 119

PCA Registers.................................................................................................. 121

Analog-to-Digital Converter (ADC) ..................................................126

Features ........................................................................................................... 126

ADC Port1 I/O Functions.................................................................................. 126

VAREF ............................................................................................................. 126

ADC Converter Operation ................................................................................ 127

Voltage Conversion.......................................................................................... 128

Clock Selection................................................................................................. 128

ADC Standby Mode.......................................................................................... 128

IT ADC Management.........................................................................................129

Routine Examples ............................................................................................ 129

Registers ...........................................................................................................130

Interrupt System ...............................................................................132

Introduction....................................................................................................... 132

Registers .......................................................................................................... 134

Electrical Characteristics .................................................................140

Absolute Maximum Ratings.............................................................................. 140

DC Parameters for Standard Voltage............................................................... 140

DC Parameters for A/D Converter.................................................................... 142

AC Parameters................................................................................................. 143

Ordering Information........................................................................ 146

Package Drawings............................................................................ 147

VQFP32............................................................................................................ 147

PLCC28............................................................................................................ 149

......................................................................................................................... 150

SOIC24............................................................................................................. 151

SOIC28............................................................................................................. 152

Datasheet Revi sion Hist ory ...................... ..... ..... .............. .... ..... ..... . 154

Changes from 4126C-10/02 to 4126D - 04/03 ................................................. 154

Changes from 4126D -05/03 to 4126E - 10/03 ................................................ 154

Changes from 4126E - 10/03 to 4126F - 12/03................................................ 154

Changes from 4126F - 12/03 4126G - 08/04 ................................................... 154

Changes from 4126G - 08/04 to 4126H - 01/05............................................... 154

Changes from 4126H - 01/05 to 4126I 11/05................................................... 154

Changes from 4126I to 4126J 05/06................................................................ 154

Changes from 4126J to 4126K 11/07............................................................... 154

Changes from 4126K 11/07 to 4126L 02/08 .................................................... 154

Table of Contents ...................................................................................i

Printed on recycled paper.

4126L–CAN–01/08

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