MC100EP35DTR2G - ON Semiconductor

August, 2008 − Rev. 6

1Publication Order Number:

MC10EP35/D

MC10EP35, MC100EP35

3.3V / 5V ECL JK Flip-Flop

Description

The MC10/100EP35 is a higher speed/low voltage version of the

EL35 JK flip−flop. The J/K data enters the master portion of the

flip−flop when the clock is LOW and is transferred to the slave, and

thus the outputs, upon a positive transition of the clock. The reset pin is

asynchronous and is activated with a logic HIGH.

The 100 Series contains temperature compensation.

Features

•410 ps Propagation Delay

•Maximum Frequency > 3 GHz Typical

•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −5.5 V

•Open Input Default State

•Q Output Will Default LOW with Inputs Open or at VEE

•Pb−Free Packages are Available

*For additional marking information, refer to

Application Note AND8002/D.

H = MC10 A = Assembly Location

K = MC100 L = Wafer Lot

5R = MC10 Y = Year

3M = MC100 W = Work Week

M = Date Code

G= Pb−Free Package

ALYWG

HP35

ALYWG

KP35

MARKING

DIAGRAMS*

SOIC−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

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8HEP35

ALYW

KEP35

ALYW

DFN8

MN SUFFIX

CASE 506AA

5R MG

3M MG

(Note: Microdot may be in either location)

MC10EP35, MC100EP35

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VEE

VCC

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

QCLK

RESET

Flip Flop

Table 1. PIN DESCRIPTION

CLK*

J*, K* ECL Signal Inputs

FUNCTION

ECL Clock Inputs

RESET* ECL Asynchronous Reset

Q, Q ECL Data Outputs

Table 2. TRUTH TABLE

L-

RESET

CLK

Qn+1

Z = LOW to HIGH Transition

VCC Positive Supply

VEE Negative Supply

* Pins will default LOW when left open.

EP (DFN8 only) Thermal exposed pad must be

connected to a sufficient thermal conduit.

Electrically connect to the most negative

supply (GND) or leave unconnected, float-

ing open.

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

SOIC−8

TSSOP−8

DFN8

Level 1

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in

Transistor Count 77 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MC10EP35, MC100EP35

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V −6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

−6

Iout Output Current Continuous

Surge

100

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

MC10EP35, MC100EP35

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Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

4. All loading with 50 W to VCC − 2.0 V.

Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 6) 3865 3940 4115 3930 4055 4180 3990 4115 4240 mV

VOL Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. All loading with 50 W to VCC − 2.0 V.

Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 7)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 8) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

VOL Output LOW Voltage (Note 8) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

7. Input and output parameters vary 1:1 with VCC.

8. All loading with 50 W to VCC − 2.0 V.

MC10EP35, MC100EP35

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Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 10) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 10) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

10.All loading with 50 W to VCC − 2.0 V.

Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 12) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

VOL Output LOW Voltage (Note 12) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV

VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

12.All loading with 50 W to VCC − 2.0 V.

Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 13)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 30 40 50 30 40 50 30 40 50 mA

VOH Output HIGH Voltage (Note 14) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 14) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

13.Input and output parameters vary 1:1 with VCC.

14.All loading with 50 W to VCC − 2.0 V.

MC10EP35, MC100EP35

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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

fmax Maximum Frequency

(See Figure 2. Fmax/JITTER)

> 3 > 3 > 3 GHz

tPLH,

tPHL

Propagation Delay to

Output Differential R, CLK to Q, Q 200 400 480 200 410 490 200 420 575

tRR Reset Recovery 150 80 150 90 150 100 ps

Setup Time

Hold Time

150

tPW Minimum Pulse width

RESET 550 400 550 400 550 400

tJITTER Cycle−to−Cycle Jitter

(See Figure 2. Fmax/JITTER)

0.2 < 1 0.2 < 1 0.2 < 1 ps

Output Rise/Fall Times Q, Q

(20% − 80%)

70 120 170 80 130 180 100 150 200 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

100

200

300

400

500

600

700

800

900

0 1000 2000 3000 4000 5000

Figure 2. Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

MC10EP35, MC100EP35

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Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

ORDERING INFORMATION

Device Package Shipping†

MC10EP35D SOIC−898 Units / Rail

MC10EP35DG SOIC−8

(Pb−Free)

98 Units / Rail

MC10EP35DR2 SOIC−82500 / Tape & Reel

MC10EP35DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC10EP35DT TSSOP−8 100 Units / Rail

MC10EP35DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC10EP35DTR2 TSSOP−82500 / Tape & Reel

MC10EP35DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC10EP35MNR4 DFN8 1000 / Tape & Reel

MC10EP35MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

MC100EP35D SOIC−898 Units / Rail

MC100EP35DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100EP35DR2 SOIC−82500 / Tape & Reel

MC100EP35DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC3100EP35DT TSSOP−8 100 Units / Rail

MC3100EP35DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100EP35DTR2 TSSOP−82500 / Tape & Reel

MC100EP35DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100EP35MNR4 DFN8 1000 / Tape & Reel

MC100EP35MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC10EP35, MC100EP35

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Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC10EP35, MC100EP35

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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PACKAGE DIMENSIONS

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC10EP35, MC100EP35

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

A BB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC10EP35/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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