CY7C037AV-20AXC - Cypress Semiconductor

CY7C027V/027AV/028V

CY7C037AV/038V

3.3 V 32K/64K x 16/18 Dual-Port Static

RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-06078 Rev. *E Revised October 14, 201 1

Features

■True dual-ported memory cells which allow

simultaneous access of the same memory location

■32K x 16 organizati on (CY7C027V/027AV [1])

■64K x 16 organizati on (CY7C028V)

■32K x 18 organizati on (CY7C037AV)

■64K x 18 organizati on (CY7C038V)

■0.35 micron Complementary metal oxide semiconductor

(CMOS) for optimum speed and power

■High speed access: 15, 20, and 25 ns

■Low operating power

■Active: ICC = 115 mA (typical)

■Standby: I SB3 = 10 A (typical)

■Fully asynchronous operation

■Automatic power-down

■Expandable data bus to 32/36 bits or more using Master/Slave

chip select when using more than one device

■On-chip arbitration logic

■Semaphores included to permit software handshaking

between ports

■INT flag for port-to-port communication

■Separate upper-byte and lower-byte control

■Dual chip enables

■Pin select for Master or Slave

■Commercial and Industrial temperature ranges

■100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin

TQFP

Notes

1. CY7C027V, and CY7C027AV are functiona lly i dentical.

2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.

3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 device s.

4. A0–A14 for 32K; A0–A15 for 64K devices.

5. BUSY is an output in master mode and an inpu t in slave mode.

R/W

I/O

8/9L

–I/O

15/17L

I/O

Control

Address

Decode

–A

14/15L

R/W

BUSY

I/O

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

I/O

–I/O

7/8L

R/W

I/O

8/9L

–I/O

15/17R

I/O

–I/O

7/8R

Logic Block Diagram

–A

14/15L

True Dual-Ported

RAM Array

–A

14/15R

R/W

BUSY

SEM

INT

Address

Decode A

–A

14/15R

[2] [2]

[3] [3]

[4] [4]

[5] [5]

[4] [4]

15/16

8/9

15/16

8/9

15/16 15/16

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 2 of 22

Contents

Pin Configurations ...........................................................3

Pin Configurations (continued) ........................................4

Selection Guide ................................................................4

Pin Definitions ..................................................................5

Architecture ......................................................................5

Functional Description ................... ... .............. ... .. ............5

Write Operation ......................... ... .............. ... ..............5

Read Operation ...........................................................5

Interrupts .....................................................................5

Busy ............................................................................6

Master/Slave ...............................................................6

Semaphore Operation .................................................6

Maximum Ratings .............................................................7

Operating Range ..................... .. .............. ... .............. ... ......7

Electrical Characteristics..................................................7

Capacitance ......................................................................7

Switching Characteristics ...................... ... .............. ... ......8

Data Retention Mode ........................................................9

Timing ................................................................................9

Switching Waveforms ....................................................10

Ordering Information ......................................................17

32K x16 3.3 V Asynchronous Dual-Port SRAM ........17

64K x16 3.3 V Asynchronous Dual-Port SRAM ........17

32K x18 3.3 V Asynchronous Dual-Port SRAM ........17

64K x18 3.3 V Asynchronous Dual-Port SRAM ........17

Ordering Code Definition ...........................................18

Package Diagram ............................................................19

Acronyms ........................................................................ 20

Document Conventions . ... .............. ... .............. ... ... ........20

Units of Measure .......... ... .............. ... ... .............. ... .....20

Document History Page ....... ... .............. ... ... .............. .. ...21

Sales, Solutions, and Legal Information ......................22

Worldwide Sales and Design Support .......................22

Products .................................................................... 22

PSoC Solutions ......... .............. ... ... .............. ... ... ........22

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 3 of 22

Pin Configurations

Figure 1. 100-Pin TQFP (Top View)

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A9R

A10R

A11R

A12R

A13R

A14R

UBR

LBR

CE1R

SEMR

OER

GND

A15R

GND

R/WR

GND

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

CE0R

CY7C027V/027AV (32K x 16)

A9L

A10L

A11L

A12L

A13L

A14L

UBL

LBL

CE1L

SEML

OEL

GND

A15L

VCC

R/WL

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

CE0L

A8L

A7L

A6L

A5L

A4L

A3L

INTL

A1L

GND

M/S

A0R

A1R

A0L

A2L

BUSYR

INTR

A2R

A3R

A4R

A5R

A6R

A7R

A8R

BUSYL

34 35 36 424139 403837 43 44 45 5048 494746

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C028V (64K x 16)

[6] [6]

Note

6. This pin is NC for CY7C027V/027AV.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 4 of 22

Pin Configurations (continued)

Figure 2. 100-Pin TQFP (Top View)

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

A8R

A9R

A10R

A11R

A12R

A13R

CE0R

A15R

UBR

SEMR

R/WR

GND

I/O17R

LBR

A14R

GND

OER

GND

I/O16R

I/O15R

I/O14R

I/O13R

I/O12R

I/O11R

CE1R

CY7C037AV (32K x 18)

A9L

A10L

A11L

A12L

A13L

A14L

CE1L

LBL

CE0L

R/WL

OEL

I/O17L

I/O16L

UBL

A15L

VCC

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

SEML

A8L

A7L

A6L

A5L

A4L

A3L

BUSYL

A1L

INTL

GND

VCC

INTR

A0R

A0L

A2L

M/S

BUSYR

A1R

A2R

A3R

A4R

A5R

A6R

A7R

GND

34 35 36 424139 403837 43 44 45 5048 494746

I/O10R

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C038V (64K x 18)

[7]

Selection Guide

Parameter -15 -20 -25 Unit

Maximum access time 15 20 25 ns

Typical operating current 125 120 115 mA

Typical standby current for ISB1 (Both ports TTL level) 35 35 30 mA

Typical standby current for ISB3 (Both ports CMOS level) 10 A 10 A10 AA

Note

7. This pin is NC for CY7C037AV.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 5 of 22

Architecture

The CY7C027V/027A V/028V and CY7037A V/038V consist of an

array of 32K and 64K words of 16 a nd 18 bits each of dual-port

RAM cells, I/O and address lines, and control signals (CE, OE,

R/W). These control pins permit independent access for reads or writes

to any location in memory. To handle simultaneo us write s/reads to the

same location, a BUSY pin is provided on each port. T wo interrupt (INT)

pins can be utilized for port-to-port communication. Two semaphore

(SEM) control pins are used for allocating shared resources. With the

M/S pin, the devices can function as a master (BUSY pins are outpu ts)

or as a slave (BUSY pins are inputs). The devices also have an

automatic power down feature controll ed by CE. Each port is provid ed

with its own output enable control (OE), which allows data to be read

from the device.

Functional Description

The CY7C027V/027AV/028V and CY7037AV/038V are low

power CMOS 32K, 64K x 16/18 du al-port static RAMs. Various

arbitration schemes are included on the devices to handle

situations when multiple processors access the same piece of

data. Two ports are provided, permitting independent,

asynchronous access for reads and writes to any location in

memory. The devices can be utilized as stand-alone 16/18-bit

dual-port static RAMs or multiple devices can be combined to

function as a 32/36-bit or wider master/slave dual-port static

RAM. An M/S pin is provided for implementing 32/36-bit or wider

memory applications with out the need for separate master and

slave devices or additional discrete logic. Application areas

include interprocessor/multiprocessor designs, communications

status buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE), Read

or Write Enable (R/W), and Output Enable (OE). Two flags are

provided on ea ch port (B USY an d INT ). BUSY signals that the port is

trying to access the same location currently being accessed by the other

port. The interru pt flag (INT ) permits commu nica ti on b etwee n por ts or

systems by means of a mail box. The semaphores are used to p ass a

flag, or token, from one port to the other to indicate that a shared

resource is in use. The sema ph ore l ogic i s co mprised of eig ht shar ed

latches. Onl y one si de can control the la tch ( semaphor e) at any time.

Control of a semaph ore indicates that a share d re sou rce i s in use . An

automatic power down feature is controlled independently on each port

by a chip select ( CE) pin.

The CY7C027V/027AV/028V and CY7037AV/038V are

available in 100-pin Thi n Quad Plastic Flatpacks (TQFP).

Write Operation

Data must be set up for a duration of tSD before the ri sing edge of

R/W to gu arantee a valid write. A write ope ration is contro lled by either

the R/W pin (see Figure 7) or the CE pin (see Figure 8). Required inputs

for non-contention op erations are summarized in Table 1.

If a location is being written to by one port and the opposite port

attempts to read that location, a port-to-port flowthrough delay

must occur before the da ta is read on the output; o therwise the

data read is not deterministic. D ata is valid on the port tDDD after

the data i s presented on the other p ort.

Read Operation

When reading the device, the user must assert both the OE and

CE pins. Data is available tACE after CE or tDOE after OE is asserted. If

the user wishes to access a semaphore flag, then the SEM pin must be

asserted instead of the CE pin, and OE must also be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (7FFF for the

CY7C027V/037AV/027AV, FFFF for the CY7C028V/38V) is the

mailbox for the right port and the second-highest memory

location (7FFE for the CY7C027V/027AV/037AV, FFFE for the

CY7C028V/38V) is the mailbox for the left port. When one port

writes to the other port’s mailbox, an interrupt is generated to the

owner. The interrupt is reset when the owner reads the contents

of the mailbox. The message is user defined.

Pin Definitions

Lef t Port Right Port Description

CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0  VIL and CE1 VIH)

R/WLR/WRRead/Write Enable

OELOEROutput Enable

A0L–A15L A0R–A15R Address (A0–A14 for 32K; A0–A15 for 64K devices)

I/O0L–I/O17L I/O0R–I/O17R Data bus input/output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)

SEML SEMRSemaphore En ab l e

UBLUBRUpper byte select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)

LBLLBRLower byte select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)

INTLINTRInterrupt flag

BUSYLBUSYRBusy flag

M/S Master or Slave select

VCC Power

GND Ground

NC No connect

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 6 of 22

Each port can read the other port’s mailbox without resetting the

interrupt. The active state of the busy signal (to a port) prevent s

the port from setting the interrupt to the winning port. Also, an

active busy to a port prevents that port from reading its own

mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin.

The operation of the interrupts and their interaction with Busy are

summarized in Table 2.

Busy

The CY7C027V/027AV/028V and CY7037AV/038V provide

on-chip arbitration to resolve simultaneous memory location

access (contention). If both ports’ C Es are asserted and an address

match occurs within tPS of each o ther , the busy logi c determines which

port has access. If tPS is violated, one port definitely gains permission to

the location, but it is not predictable which port gets that permission.

BUSY is asserted tBLA after an address match or tBLC after CE is taken

LOW.

Master/Slave

A M/S pin is provided to expand the word width by configuring the

device as ei ther a master or a sl ave. The BUSY output o f the master is

connected to the BUSY input of the slave. This allows the device to

interface to a master device with no external components. Writing to

slave devices must be delayed until after the BUSY input has settled

(tBLC or tBLA), otherwise, the slave chip may begin a write cycle during

a contention situat ion . When tied HIGH, the M/S pin allows the device

to be used as a master and, therefore, the BUSY line is an output. BUSY

can then be used to send the arbitration outcome to a slave.

Semaphore Operation

The CY7C027V/027AV/028V and CY7037AV/038V provide

eight semaphore latche s, which are separate from the dual-port

memory locations. Semaphores are used to reserve resources

that are shared between the two ports.The state of the

semaphore indicates that a resource is in use. For example, if

the left port wants to request a given resource, it sets a latch by

writing a zero to a semaphore location. The left port then verifies

its success in setting the latch by reading it. After writing to the

semaphore, SEM or OE must be deasserted for tSOP before

attempting to read the semaphore. The semaphore value is available

tSWRD + tDOE after the rising edge of the semaphore write. If the left port

was successful (reads a zero), it assumes control of the shared

resource, otherwise (rea ds a one) it assumes the right port h as control

and continues to poll the semaphore. When the right side has relin-

quished control of the semaphore (by writing a one), the left side

succeeds in gaining control of the semaphore. If the left side no longer

requires the semaphore, a one is written to cancel its request.

Semaphores are accessed by asserti ng SEM LOW. The SEM pi n

functions as a chip select for the semaphore latches (CE must remain

HIGH during SEM LOW). A0–2 represents the semaphore address. OE

and R/W are used in the same manner as a normal memory access.

When writing or reading a semaphore, the other address pins have no

effect.

When writing to the semaphore, only I/O0 is used. If a zero is written

to the left port of an available semaphore, a one appears at the same

semaphore address on the right port. That semaphore can now only be

modified by the side showing zero (the left port in this case). If the left

port now relinquishes control by writing a one to the semaphore, the

semaphore is set to one for both sides. However, if the right port had

requested the semaphore (written a zero) while the left port had control,

the right port would immediately own the semaphore as soon as the left

port released it. Table 3 shows sample semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines

output the semaphore value. The read value is latched in an

output register to prevent the semaphore from changing state

during a write from the other port. If both ports attempt to access

the semaphore within tSPS of each other , the semaphore is definitely

obtained by one side or the other, but there is no guarantee which side

controls the semaphore .

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 7 of 22

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User gui d el i ne s are not tested.

Storage temperature ................... .............–65 C to +150 C

Ambient temperature with

power applied...........................................–55 C to +125 C

Supply voltage to ground potential ...............–0.5 V to +4.6 V

DC voltage applied to

outputs in High-Z st ate... ... .....................–0.5 V to VCC+0.5 V

DC input voltage[8]......................... .. ......–0.5 V to VCC+0.5 V

Output current into outputs (LOW) ..............................20 mA

Static discharge voltage.......................................... > 1100 V

Latch-up current ................ ... ... ... ........................... > 200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0 C to +70 C 3.3 V  300 mV

Industrial[9] –40 C to +85 C 3.3 V  300 mV

Electrical Characteristics Over the Operating Range

Parameter Description CY7C027V/027AV/028V/CY7C037AV/CY7C038V Unit-15 -20 -25

Min Typ Max Min Typ Max Min Typ Max

VOH Output HIGH vol tage

(VCC=Min., IOH= –4.0 mA) 2.4 – 2.4 – – 2.4 – – V

VOL Output LOW voltage (VCC=Min., I OH= +4.0 mA) – 0.4 – 0.4 – 0.4 V

VIH Input HIGH voltage 2.2 – 2.2 – 2.2 – V

VIL Input LOW voltage – 0.8 – 0.8 – 0.8 V

IIX Input leakage current 555555A

IOZ Output leakage current –10 10 –10 10 –10 10 A

ICC Operating current (VCC=Max. IOUT=0

mA) outputs disabled Com’l. 125 185 – 120 175 – 115 165 mA

Ind.[9] – 140 195 – mA

ISB1 Standby current (Both ports TTL

level) CEL & CER  VIH, f=fMAX Com’l. 35 50 35 45 30 40 mA

Ind.[9] –4555 –mA

ISB2 Standby current (One port TTL level)

CEL | CER  VIH, f=fMAX Com’l. 80 120 75 110 65 95 mA

Ind.[9] –85120 –mA

ISB3 Standby current (Both ports CMOS

level) CEL & CER  VCC0.2 V, f=0 Com’l. 10 250 10 250 10 250 A

Ind.[9] –10250 –A

ISB4 Standby current (One port CMOS

level) CEL | CER  VIH, f=fMAX[10] Com’l. 75 105 70 95 60 80 mA

Ind.[9] –80105 –mA

Capacitance[11]

Parameter Description Test Conditions Max Unit

CIN Input capacitance TA = 25 C, f = 1 MHz,

VCC = 3.3 V 10 pF

COUT Output capacitance 10 pF

Notes

8. Pulse width < 20 ns.

9. Industrial parts are available in CY7C028V and CY7C038V, CY7C027V/027AV only.

10.fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except ou tput enable). f = 0 m eans no address or con trol lines change. This applies only to inputs at CM OS level stan dby ISB3.

11. Tested initially and after any design or process changes that may affect these parameters.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 8 of 22

Figure 3. AC Test Loads and Waveforms

3.0V

GND 90% 90%

10%

3ns 3ns

10%

ALL INPUTPULSES

(a) Normal Load (Load 1)

R1 = 590 

3.3 V

OUTPUT

R2 = 435 

C= 30pF

VTH = 1.4 V

OUTPUT

C= 30 pF

(b) Thévenin Equivalent (Load 1) (c)Three-State Delay(Load 2)

R1 = 590 

R2 = 435 

3.3 V

OUTPUT

C= 5pF

RTH = 250 



including scope and jig)

(Used for tLZ, tHZ, tHZWE, & tLZWE

Switching Characteristics Over the Operating Range[12]

Parameter Description

CY7C027V/027AV/028V/

CY7C037AV/CY7C038V Unit

-15 -20 -25

Min Max Min Max Min Max

Read Cycle

tRC Read cycle time 15 – 20 – 25 – ns

tAA Address to data valid – 15 – 20 – 25 ns

tOHA Output hold from address change 3 – 3 – 3 – ns

tACE[13] CE LOW to data valid – 15 – 20 – 25 ns

tDOE OE LOW to data valid –10–12–13ns

tLZOE[14, 15, 16] OE LOW to Low Z 3–3–3–ns

tHZOE[14, 15, 16] OE HIGH to High Z – 10 – 12 – 15 ns

tLZCE[14, 15, 16] CE LOW to Low Z 3 – 3 – 3 – ns

tHZCE[14, 15, 16] CE HIGH to High Z –10–12–15ns

tPU[16] CE LOW to power-up 0 – 0 – 0 – ns

tPD[16] CE HIGH to power-down – 15 – 20 – 25 ns

tABE[13] Byte enable access time – 15 – 20 – 25 ns

Wr ite Cycle

tWC Write cycle time 15 – 20 – 25 – ns

tSCE[13] CE LOW to write end 12 – 16 – 20 – ns

tAW Address valid to write end 12 – 16 – 20 – ns

tHA Address hold from write end 0 – 0 – 0 – ns

tSA[13] Address setup to write start 0 – 0 – 0 – ns

tPWE Write pulse width 12–17–22–ns

tSD Data setup to write end 10–12–15–ns

Notes

12.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3. 0 V, and output loading of the specified

IOI/IOH and 30 pF load cap acitance .

13.To access RAM, CE=L, UB=L, SEM=H. To access sem aphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.

14.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

15.Test conditions used are Load 2.

16.This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells fr om wri ting port to reading port,

refer to Figure 11.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 9 of 22

Data Retention Mode

The CY7C027V/027AV/028V and CY7037AV/038V are de-

signed with battery backup in mind. Data retention voltage and

supply current are guaranteed over temperature. The following

rules ensure data retention:

1. Chip Enable (CE) must be held HIGH during data retention, within

VCC to VCC – 0.2 V

2. CE must be kept between VCC – 0.2 V and 70% of VCC during

the power up and power down transitions

3. The RAM can begin operation >tRC after VCC reaches the

minimum operating vol tage (3.0 V)

tHD Data hold from write end 0 – 0 – 0 – ns

tHZWE[17, 18] R/W LOW to High Z – 10 – 12 – 15 ns

tLZWE[17, 18] R/W HIGH to Low Z 3 – 3 – 3 – ns

tWDD[21] Wr it e pulse to data delay – 30 – 40 – 50 ns

tDDD[21] Write data valid to read data valid – 25 – 30 – 35 ns

Busy Timing[19]

tBLA BUSY LOW from address match – 15 – 20 – 20 ns

tBHA BUSY HIGH from address mismatch – 15 – 20 – 20 ns

tBLC BUSY LOW from CE LOW –15–20–20ns

tBHC BUSY HIGH from CE HIGH –15–16–17ns

tPS Port setup for priority 5 – 5 – 5 – ns

tWB R/W HIGH after BUSY (Slave) 0–0–0–ns

tWH R/W HIGH after BUSY HIGH (Slave) 13–15–17–ns

tBDD[21] BUSY HIGH to data valid – 15 – 20 – 25 ns

Interrupt Timing[19]

tINS INT set time – 15 – 20 – 20 ns

tINR INT reset time – 15 – 20 – 20 ns

Semaphore Timing

tSOP SEM flag update pulse (OE or SEM) 10–10–12–ns

tSWRD SEM flag write to read time 5 – 5 – 5 – ns

tSPS SEM flag contention window 5 – 5 – 5 – ns

tSAA SEM address access time – 15 – 20 – 25 ns

Switching Characteristics Over the Operating Range[12](continued)

Parameter Description

CY7C027V/027AV/028V/

CY7C037AV/CY7C038V Unit

-15 -20 -25

Min Max Min Max Min Max

Timing

Parameter Test Conditions[22] Max Unit

ICCDR1 At VCCDR = 2 V 50 A

Data Retention Mode

3.0 V 3.0 V

VCC 2.0 V

VCC to VCC –0.2 V

VCC

tRC

VIH

Notes

17.Test conditions used are Load 2

18.This parameter is guarant eed by design, b ut it is not production t ested. For inf ormation on port-to-port delay through RAM cells from writing port to read ing port, refer

to Figure 11.

19.For information on port-to-port delay th rough RAM cells from writing port to reading port, refer to Figure 11 waveform.

20.Test conditions used are Load 1.

21.tBDD is a calculated p arameter and is the great er of tWDD–tPWE (actual) or tDDD–tSD (actual).

22.CE = VCC, Vin = GND to VCC, TA = 25 C. This parameter is guaranteed but not tested.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 10 of 22

Switching Waveforms

Notes

23.R/W is HIGH for read cycles.

24.Device is continuously selected CE = VIL and UB or LB = VIL. This wavefo rm cannot be used for semaphore reads.

25.OE = VIL.

26.Address valid prior to or coincident with CE transition LOW.

27.To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

tOHA

Figure 4. Read Cycle No. 1 (Either Port Address Access)[23, 24, 25]

tACE

tLZOE

tDOE

tHZOE

tHZCE

DATA VALID

tLZCE

tPU tPD

ISB

ICC

DATA OUT

CE and

LB or UB

CURRENT

Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]

UB or LB

DATAOUT

tRC

ADDRESS

tAA tOHA

tLZCEtABE

tHZCE

tACE

tLZCE

Figure 6. Read Cycle No. 3 (Either Port)[23, 25, 26, 27]

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 11 of 22

Notes

28.R/W must be HIGH d uring all address t ransitions.

29.A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

30.tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

31.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on

the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.

32.To access RAM, CE = VIL, SEM = VIH.

33.To access upper byte, CE = VIL, UB = VIL, SEM = VIH.

To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

34.Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.

35.During this period, the I/O pins are in the output state, and input signals must not be applied.

36.If the CE or SEM LOW transition occurs simult aneously with or after t he R/W LOW transition, the outputs remain in the high impedance state.

Switching Waveforms(continued)

tAW

tWC

tPWE

tHD

tSD

tHA

R/W

DATAOUT

DATA IN

ADDRESS

tHZOE

tSA

tHZWE tLZWE

Figure 7. Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31]

[34]

[31]

[32,33]

NOTE 35 NOTE 35

tAW

tWC

tSCE

tHD

tSD

tHA

R/W

DATA IN

ADDRESS

tSA

Figure 8. Write Cycle No. 2: CE Controlled Ti ming[28, 29, 30, 36]

[32,33]

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 12 of 22

Notes

37.CE = HIGH for the duration of the above timing (both write and read cycle).

38.I/O0R = I/O0L = LOW (request semaphor e); CER = CEL = HIGH.

39.Semaphores are reset (available to both ports) at cycle start.

40.If tSPS is violated, the sema phore is definite ly obtained by one side or the o ther , but whic h side gets the semaphore is unpre dictable .

Switching Waveforms(continued)

tSOP

tSAA

VALID ADRESS VALID ADRESS

tHD

DATAIN VALID DATAOUT VALID

tOHA

tAW tHA tACE

tSOP

tSCE

tSD

tSA tPWE

tSWRD tDOE

WRITE CYCLE READ CYCLE

R/W

I/O0

SEM

0–A2

Figure 9. Semaphore Read After Write Timing, Either Side[37]

MATCH

tSPS

A0L–A2L

MATCH

R/WL

SEML

A0R–A2R

R/WR

SEMR

Figure 10. Timing Diagra m of Semaphore Contention[38, 39, 40]

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 13 of 22

Note

41.CEL = CER = LOW.

Switching Waveforms(continued)

VALID

tDDD

tWDD

MATCH

R/WR

DATA INR

DATAOUTL

tWC

ADDRESSR

tPWE

VALID

tSD tHD

ADDRESSL

tPS

tBLA tBHA

tBDD

BUSYL

Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)[41]

tPWE

R/W

BUSY tWB tWH

Figure 12. Write Timing with Busy Input (M/S=LOW)

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 14 of 22

Note

42.If tPS is violated, the b usy signal is asserted on one side or the ot her , but t here is no guarant ee to which side BUSY is asserted.

Switching Waveforms(continued)

ADDRESS MATCH

tPS

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CERValidFirst:

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESSL,R

Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[42]

CELValid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MISMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH ADDRESS MISMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right AddressValid First:

Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[42]

Left Address Valid First:

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 15 of 22

Figure 15. Interrupt Timing Diagrams

Notes

43.tHA depends on which enable pin (CEL or R/WL) i s deasserted first.

44.tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Switching Waveforms(continued)

WRITE 7FFF (FFFF for CY7C028V/38V)

tWC

Right SideClears INTR:

tHA

READ 7FFF

tRC

tINR

WRITE 7FFE (FFFE for CY7C028V/38V)

tWC

Right SideSets INTL:

Left Side Sets INTR:

Left SideClears INTL:

READ 7FFE

tINR

tRC

ADDRESSR

CE L

R/WL

INTL

OEL

ADDRESSR

R/WR

CER

INTL

ADDRESSR

CER

R/WR

INTR

OER

ADDRESSL

R/WL

CEL

INTR

tINS

tHA

tINS

(FFFF for CY7C028V/38V)

(FFFE for CY7C028V/38V)

[43]

[44]

[43]

[44]

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 16 of 22

Table 1. Non-Contending Read/Write

Inputs Outputs

CE R/W OE UB LB SEM I/O9–I/O17 I/O0–I/O8Operation

H X X X X H High Z High Z Deselected: Power-down

X X X H H H High Z High Z Deselected: Power-down

L L X L H H Data in High Z Write to upper byte only

L L X H L H High Z Data in Write to lower byte only

L L X L L H Data in Data in Write to both bytes

L H L L H H Data out High Z Read upper byte only

L H L H L H High Z Data out Read lower byte only

L H L L L H Data out Data out Read both bytes

X X H X X X High Z High Z Outputs disabled

H H L X X L Data out Data out Read data in semaphore flag

X H L H H L Data out Data out Read data in semaphore flag

H X X X L Data in Data in Write DIN0 into semaphore flag

X X H H L Data in Data in Write DIN0 into semaphore flag

L X X L X L Not allowed

L X X X L L Not allowed

Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[45]

Left Port Right Port

Function R/WLCELOELA0L–14LINTLR/WRCEROERA0R–14R INTR

Set right INTR flag L L X 7FFF X X X X X L[47]

Reset right INTR flagXXXXXXLL7FFFH

[46]

Set left INTL flag X X X X L[46] LLX 7FFE X

Reset left INTL flag X L L 7FFE H[47] XXX X X

Table 3. Semaphore Operation Example

Function I/O0–I/O17 Left I/O0–I/O17 Right Status

No action 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore

Left port writes 1 to semaphore 1 0 Right port ob tains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphore token

Left port writes 1 to semaphore 1 1 Semaphore free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore free

Notes

45.A0L–15L and A0R–15R,FFFF/FFFE for the CY7C028V/038V.

46.If BUSYR=L, then no chan ge.

47.If BUSYL=L, then no change.

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 17 of 22

Ordering Information

32K x16 3.3 V Asynchronous Dual-Port SRAM

Speed

(ns) Orderin g Code Package

Name Package Type Operating

Range

15 CY7C027V-15AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

CY7C027V-15 AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial

20 CY7C027V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C027V-20AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

25 CY7C027V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C027V-25AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

CY7C027AV-25AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial

64K x16 3.3 V Asynchronous Dual-Port SRAM

Speed

(ns) Orderin g Code Package

Name Package Type Operating

Range

15 CY7C028V-15AXC A100 100-Pin Pb-fr ee Thin Quad Flat Pack Commercial

CY7C028V-15 AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial

20 CY7C028V-20AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C028V-20AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

CY7C028V-20AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C028V-20AXI A100 100-Pin Pb-free Th in Quad Flat Pack Industrial

25 CY7C028V-25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C028V-25AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

32K x18 3.3 V Asynchronous Dual-Port SRAM

Speed

(ns) Orderin g Code Package

Name Package Type Operating

Range

20 CY7C037AV-20AXC A100 100-Pin Pb-free Thin Quad Flat Pack Commercial

64K x18 3.3 V Asynchronous Dual-Port SRAM

Speed

(ns) Orderin g Code Package

Name Package Type Operating

Range

20 CY7C038V-20AXI A100 100-Pin Pb-free Thin Quad Flat Pack Industrial

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 18 of 22

Ordering Code Definition

CY 7C 0X XX

Com pany ID: CY = C ypress

7C = Dual Port SRAM

W idth: 02=x16 or 03=x18

Operating R ange

C = Comm ercial I = Industrial

Depth: 7=32K or 8=64K

Package: A=TQFP

Speed G rade : 15ns/20ns/25ns

X : Pb free (RoHS Compliant)

X = V/AV : 3.3 V

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 19 of 22

Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (T QFP) A100

51-85048 *E

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 20 of 22

Acronyms Document Conventions

Units of Measure

Acronym Description

CMOS complementary metal oxide semiconductor

I/O input/output

SRAM static random access memory

TQFP thin quad plastic flatpack

Symbol Unit of Measure

°C degree Celsius

MHz mega hertz

µA microamperes

mA milliamperes

mV millivolts

ns nanoseconds

ohms

pF picofarad

Vvolts

Wwatts

CY7C027V/027AV/028V

CY7C037AV/038V

Document #: 38-06078 Rev. *E Page 21 of 22

Document History Page

Document Title: CY7C027V/027AV/CY7C028V/037AV/038V 3.3 V 32K/6 4K X 16/18 DUAL PORT STATIC RAM

Document Number: 38-06078

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** 237626 YDT 6/30/04 Converted data sheet from old spec 38-00670 to conform with new data

sheet. Removed cross information from features section

*A 259110 JHX See ECN Added Pb-Free packaging information.

*B 2623540 VKN/PYRS 12/17/08 Added CY7C027VN, CY7C027AV and CY7C037AV parts

Updated Ordering information table

*C 2897217 RAME 03/22/2010 Updated Ordering Information

Updated Package Diagram

*D 3093542 ADMU 11/25/2010 Removed information on CY7C027VN and CY7C037V

Updated as per new template

Added Acronyms and Units of Measure table

Added Ordering Code Definition

Updated all footnotes

*E 3403652 ADMU 10/14/2011 removed pruned parts CY7C027V-25AI, CY7C038V-20AI from Ordering

Information

Updated Package Diagram .

Document #: 38-06078 Rev. *E Revised October 14, 2011 Page 22 of 22

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY7C027V/027AV/028V

CY7C037AV/038V

© Cypress Semico nducto r Co rpor ation , 20 09-2 011. The infor mation cont ai ned he rein is subj ect to chang e wi thou t notice. Cy press Semiconductor Corporation assumes no responsibility for the use of

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypr ess products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of ,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypres s

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except as specified above is prohibited wi thout

the express written permission of Cypres s.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTA BILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cy press does n ot

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypr ess does n ot author ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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