25LC040XT-I/ST - Microchip Technology

25AA040/25LC040/25C040

Device Selection Table

Features:

• Low-power CMOS technology:

- Write current: 3 mA, typical

- Read current: 500 μA, typical

- S tandby curre nt: 500 nA, typic al

• 512 x 8-bit organization

• 16 byte page

• Write cycle time: 5 ms max.

• Self-timed Erase and Write cycles

• Block write protection:

- Protect none, 1/4, 1/2 or all of array

• Built -in wri te prot ection:

- Power on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Seque nti al read

• High reliability:

- Endurance: 1M c y cles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP, SOIC and TSSOP packages

• Temperature ranges supported:

Description:

The Microchip Technology Inc. 25AA040/25LC040/

25C040 (25XX040*) is a 4 Kbit serial Electrically

Erasable PROM. The m emory is acce ssed via a simple

Serial Peripheral Interface (SPI) compatible serial bus.

The bus signals required are a clock input (SCK) plus

sep arate dat a in (SI) and dat a out (SO) lines . Access to

the device is controlled through a Chip Select (CS)

input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts. Also, write operations to the device can be

disabled via the write-protect pin (WP).

Package Types

Block Diagram

Part

Number VCC

Range Max. Clock

Frequency Temp.

Ranges

25AA040 1.8-5.5V 1 MHz I

25LC040 2.5-5.5V 2 MHz I

25C040 4.5-5.5V 3 MHz I,E

- Industrial (I): -40°Cto +85°C

- Automotive (E) (25C040): -40°C to +125°C

VSS

VCC

HOLD

SCK

25XX040

VSS

VCC

HOLD

SCK

25XX040

HOLD

VCC

SCK

VSS

25XX040

PDIP

SOIC

TSSOP

SCK

HOLD

STATUS

I/O Control Memory

Control

Logic

HV Genera to r

EEPROM

Array

Page

Y Decoder

Sense Amp.

R/W Control

Logic

VCC

VSS

XDEC

Latches

4K SPI Bus Serial EEPROM

*25XX040 is used in t his doc ument as a generic part number

for the 25AA040/25LC040/25C040 devices.

Not recommended for new designs –

Please use 25AA040A or 25LC040A.

25AA040/25LC040/25C040

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ................ ..... ...... ..... ...... ................. ...... ..... ................. ...... ..... ............ -0.6V to VCC+1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-65°C to 125°C

ESD protection on all pins.........................................................................................................................................4 KV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal ope ration of the device at thos e or any other co nditio ns abov e those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability

DC CHARACTERISTICS Industri al (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V

Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

D001 VIH1High-level input

voltage 2.0 VCC+1 V VCC ≥ 2.7V (Note)

D002 VIH20.7 VCC VCC+1 V VCC< 2.7V (Note)

D003 VIL1Low-level input

voltage -0.3 0.8 V VCC ≥ 2.7V (Note)

D004 VIL2-0.3 0.3 VCC VVCC < 2.7V (Note)

D005 VOL Low-level output

voltage —0.4VIOL = 2.1 mA

D006 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V

D007 VOH High-level output

voltage VCC -0.5 — V IOH =-400 μA

D008 ILI Input leakage current — ±1 μACS = VCC, VIN = VSS TO VCC

D009 ILO Output leakage

current —±1μACS = VCC, VOUT = VSS TO VCC

D010 CINT Intern al Cap acit ance

(all inputs and

outputs)

—7pFT

A = 25°C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

D011 ICC Read Operating Current —

—1

500 mA

μAVCC = 5.5V; FCLK = 3.0 MHz; SO = Open

VCC = 2.5V; FCLK = 2.0 MHz; SO = Open

D012 ICC Write —

—5

3mA

mA VCC = 5.5V

VCC = 2.5V

D013 ICCS Standby Current —

—5

1μA

μACS = VCC = 5.5V, Inputs tied to VCC or

VSS

CS = VCC = 2.5V, Inputs tied to VCC or

VSS

Note: This parameter is periodically sampled and not 100% tested.

© 2006 Microchip Technology Inc. DS21204E-page 3
25AA040/25LC040/25C040
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C  VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C  VCC = 4.5V to 5.5V (25C040 only)
Param 
No. Sym. Characteristic Min. Max. Units Test Conditions
1FCLK Clock Frequency —
—
—
3
2
1
MHz
MHz
MHz
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
2T
CSS CS Setup T ime 100
250
500
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
3T
CSH CS Hold Time 150
250
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
4T
CSD CS Disable Time 500 — ns —
5T
SU Data Setup Time 30
50
50
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
6T
HD Data Hold T ime 50
100
100
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
7T
RCLK Rise Time — 2 μs(Note 1)
8T
FCLK Fall T ime — 2 μs(Note 1)
9T
HI Clock High Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
10 TLO Clock Low Time 150
230
475
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
11 TCLD Clock Delay Time 50 — ns —
12 TCLE Clock Enable Time 50 — ns —
13 TVOutput Valid from Clock Low —
—
—
150
230
475
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
14 THO Output Hold Time 0 — ns (Note 1)
15 TDIS Output Disable Time —
—
—
200
250
500
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
16 THS HOLD Setup Time 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
17 THH HOLD Hold Tim e 100
100
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
18 THZ HOLD Low to Output High-Z 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)
19 THV HOLD High to Output Valid 100
150
200
—
—
—
ns
ns
ns
VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V
20 TWC Internal Write Cycle Time — 5 ms —
21 — Endurance 1M — E/W 
Cycles (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

25AA040/25LC040/25C040

FIGURE 1-1: HOLD TIMING

FIGURE 1-2: SERIAL INPUT TIMING

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

HOLD

16 16 17

Don’t Care 5

High-impedance

n + 2 n + 1 n n - 1

n + 2 n + 1 n nn - 1

SCK

711

LSB in

MSB in

High-impedance

Mode 1,1

Mode 0,0

SCK

MSB out ISB out

Don’t Care

Mode 1,1

Mode 0,0

25AA040/25LC040/25C040

TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT AC

AC Waveform:

VLO = 0.2V —

VHI = VCC - 0.2V (Note 1)

VHI = 4.0V (Note 2)

Timing Measurement Refere nce Lev el

Input 0.5 VCC

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

VCC

100 pF

1.8 KΩ

2.25 KΩ

25AA040/25LC040/25C040

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in p r ogre ss w il l be co mpl ete d, re gard less of

the CS input signal. If CS is brought high during a

program cycle, the device will go in Standby mode as

soon as the programming cycle is complete. When the

device is deselec ted, SO goes into the high-i mpedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low lev el on CS is required p r ior to any se qu enc e

being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX040.

During a read cycle, data is shifted out on this pin after

the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is a hardware write-protect input pin. When

WP is low, all writes to the array or STATUS register

are disabled, but any other operation functions

normally. When WP is high, all functions, including

nonvolatile writes operate normally. WP going low at

any time will reset the write enable latch and inhibit

programming, except when an internal write has

already begun. If an internal write cycle has already

begun, WP going low will have no effect on the write.

See Table 3-3 for Write-Protect Funct i onality Matrix.

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25XX040. Instructions,

address es or data presen t on the SI pin are la tc hed on

the risin g e dge of the c lo ck in put, while dat a on t he SO

pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25XX040 while in the middle of a serial sequence

without having to retransmit the entire sequence again

at a later time. It must be held high any time this func-

tion is no t being us ed . O nc e t he dev ic e i s se lec ted and

a serial sequence is underway, the HOLD pin may be

pulled low to pause further serial communication

without resetting the serial sequence. The HOLD pin

must be brought low while SCK is low, otherwise the

HOLD function will not be invoked until the next SCK

high-to-low transition. The 25XX040 must remain

selected during this sequence. The SI, SCK and SO

pins are in a high-impedance state during the time the

part is paused and transitions on these pins will be

ignored. To resume serial communication, HOLD must

be brought high while the SCK pin is low, otherwise

serial communication will not resume. Lowering the

HOLD line at any time will tri-state the SO line.

Name PDIP SOIC TSSOP Description

CS 1 1 3 Chip Select Input

SO 2 2 4 Serial Data Output

WP 3 3 5 Write-Protect Pin

VSS 4 4 6 Ground

SI 5 5 7 Serial Data Input

SCK 6 6 8 Serial Clock Input

HOLD 7 7 1 Hold Input

VCC 8 8 2 Supply Voltage

25AA040/25LC040/25C040

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX040 is a 512 byte Serial EEPROM designed

to interface directly with the Serial Peripheral Interface

(SPI) port of many of today’s popular microcontroller

families, including Microchip’s PIC16C6X/7X micro-

controllers. It may also interface with microcontrollers

that do not have a built-in SPI port by using discrete

I/O lines programmed properly with the software.

The 25XX04 0 contain s an 8-bit instr uction regist er . The

part is acc ess ed v ia the SI pi n, w ith da t a being c loc ke d

in on the rising edge of SCK. The CS pin must be lo w

and the HOLD pin must be high for the entire operatio n.

The WP pin must be held high to allow writing to the

memory array.

Table 3-1 contains a list of the possible instruction

bytes and format for device operation. The Most

Significant address bit (A8) is located in the instruction

byte. All instructions, addresses, and data are

transferred MSB first, LSB last.

Data is sampled on the first rising edge of SCK after CS

goes low. If the clock line is shared with other periph-

eral devices on the SPI bus, the user can assert the

HOLD input and place the 25XX040 in ‘HOLD’ mode.

After releasing the HOLD pin, operation will resume

from the point when the HOLD was asserted.

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit READ

instruction with the A8 address bit is transmitted to the

25XX040 followed by the lower 8-bit address (A7

through A0). After the correct READ instruction and

address are sent, the data stored in the memory at the

select ed address is shifted out on the SO pi n. The data

stored in the memory at the next address can be read

sequen tially by co nti nui ng to p r ov ide cl oc k p uls es . Th e

internal Address Pointer is automatically incremented

to the next higher address after each byte of data is

shifted out. When the highest address is reached

(01FFh), the address counter rolls over to address

0000h allowing the read cycle to be continued

indefin itely. The read ope ration is t ermina ted by raisin g

the CS pin (Figure 3-1).

3.3 Write Sequence

Prior to any attempt to write data to the 25XX040, the

write enable latch must be set by issuing the WREN

instruction (Figure 3-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX040. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array bec ause the w rite enable l atch will not h ave been

properly set.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITE

instruction, followed by the address, and then the data

to be written. Keep in mind that the Most Significant

address bit (A8) is included in the instruction byte. Up

to 16 bytes of data can be sent to the 25XX040 before

a write cy cle is necess ary . The onl y restrictio n is that all

of the bytes must reside in the same page. A page

address beg ins wit h XXXX 0000 and ends w it h XXXX

1111. If the internal address counter reaches XXXX

1111 and the clock co ntinues, the counter wil l roll back

to the first address of the page and overwrite any data

in the page that may have been written.

For the data to be actually written to the array, the CS

must be brought high after the least significant bit (D0)

of the nth data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 3-2 and Figure 3-3

for more detailed illustrations on the byte write

sequence and the page write sequence respectively.

While the write is in pro gress, the ST ATUS register may

be read to check the status of the WIP, WEL, BP1 and

BP0 bits (Figure 3-6). A read attempt of a memory

array location will not be possible during a write cycle.

When the write cycle is completed, the write enable

latch is reset.

TABLE 3-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 A8011 Read data from memory array beginning at selected address

WRITE 0000 A8010 Write data to memory array beginning at selected address

WRDI 0000 0100 Reset the write enable latch (disable write operations)

WREN 0000 0110 Set the write enable latch (enable write operations)

RDSR 0000 0101 Read STATUS register

WRSR 0000 0001 Write S TATUS regi ster

Note: A8 is the 9th address bit necessary to fully address 512 bytes.

25AA040/25LC040/25C040

FIGURE 3-1: READ SEQUENCE

FIGURE 3-2: BYTE WRITE SEQUENCE

FIGURE 3-3: PAGE WRITE SEQUENCE

SCK

0 23456789101112131415161718192021221

01A800001A7 6 5 4 1A0

76543210

Instruction Lower Address Byte

Data Out

High-impedance

32 Don’t Care

SCK

0 23456789101112131415161718192021221

00A80000 A7 6 5 4 1A076543210

Instruction Lower Address Byte Data Byte

High-impedance

TWC

91011 1415161718192021222324

00A800001A7 6 5 4 21076543210

Instruction Lower Address Byte Data Byte 1

SCK

0 23456718

34 35 36 39 40

76543210

Data Byte n (16 max)

SCK

25 27 28 29 30 31 3226 33

76543210

Data Byte 3

76543210

Data Byte 2

37 38

25AA040/25LC040/25C040

3.4 Wr it e En able (WREN) and Write

Disable (WRDI)

The 25XX040 contains a write enable latch. See

Table 3-3 for the Write-Protect Functionality Matrix.

This latch must be set before any writ e operati on will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enab le latc h wi ll be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

•WP

line is low

FIGURE 3-4: WRITE ENABLE SEQUENCE

FIGURE 3-5: WRITE DISABLE SEQUENCE

SCK 0 2345671

High-impedance

010000 01

SCK 0 2345671

High-impedance

010000 010

25AA040/25LC040/25C040

3.5 Read Status Register (RDSR)

The RDSR instruction provides access to the STATUS

even during a write cycle. The STATUS register is

formatted as follows:

The Write-In-Process (WIP) bit indicates whether the

25XX040 is busy with a write operation. When set to a

‘1’, a write is in progress, when set to a ‘0’, no write is

in progress. This bit is read-only.

The Write Enable La tch (WEL) bit indi cates the st atu s

of the write enable latch. When set to a ‘1’, the latch

allows writes to the array, when set to a ‘0’, the latch

prohibits writes to the array. The state of this bit can

always be updated vi a the WREN or WR DI comm ands

regardless of the state of write protection on the

STATUS register. This bit is read-only.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by t he us er iss uing the WRSR in str u ct ion. Thes e

bits are non volatil e.

See Figure 3-6 for RDSR timing sequence.

3.6 Write Status Register (WRSR)

The WRSR instruction allows the user to select one of

four levels of protection for the array by writing to the

appropriate bits in the STATUS register. The array is

divided up into four segments. The user has the ability

to write-protect none, one, two, or all four of the

segments of the array. The partitioning is controlled as

illustrated in Table 3-2.

See Figure 3-7 for WRSR timing se quence.

TABLE 3-2: ARRAY PROTECTION

FIGURE 3-6: READ STATUS REGISTER SEQUENCE

FIGURE 3-7: WRITE S TATUS REGISTER SEQUENCE

7654 3 2 1 0

XXXXBP1 BP0 WEL WIP

BP1 BP0 Array Addresses

Write-Protected

00 none

01 upper 1/4

(0180h-01FFh)

10 upper 1/2

(0100h-01FFh)

11 all

(0000h-01FFh)

9101112131415

11000000

7654 210

Instruction

Data from STATUS register

High-impedance

SCK

0 23456718

9101112131415

01000000

7654 210

Instruction Data to STATUS register

High-impedance

SCK

0 23456718

25AA040/25LC040/25C040

3.7 Data Protection

The following protection has been implemented to

prevent ina dv erte nt wri tes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

•CS

must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an in ternal write cycle

is ignored and programming is continued

• The w rite e nable latc h is rese t when the WP pi n is

low

3.8 Power-On State

The 25XX040 powers on in the following state:

• The device is in low-power Standby mode

(CS=1)

• The write enable latch is reset

• SO is in high-impedance state

• A low level on CS is required to enter active state

TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX

WP WEL Protected Blocks Unprotected Blocks STATUS Register

Low XProtected Protected Protected

High 0Protected Protected Protected

High 1Protected Writable Writable

25AA040/25LC040/25C040

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil ) Example:

8-Lead TSSOP Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

XXXX

YYWW

NNN

25AA040

I/P 1 L7

0601

25AA040I/

SN 0601

1L7

5A4X

0601

1L7

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu meric tracea bil ity code

Pb-free JEDEC designator for Matte Ti n (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

25AA040/25LC040/25C040

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES*MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E . 300 .313 .325 7.62 7.94 8. 26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing §eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing N o. C04- 018

§ Significant Characteristic

Note: For the most current package drawings, please

see the Mi cro ch ip Pac ka gin g Spec ificatio n loc ate d

at http://www.microchip.com/packaging

25AA040/25LC040/25C040

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Fo ot Angle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFo ot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Packa ge Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff §1.551.421.32.061.056.052A2Molded Packa ge Thickness 1.751.551.35.069.061.053AOverall Height 1.27

.050

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

Note: For the most current package drawings, please

see the Mi cro ch ip Pac ka gi ng Spe ci fic ati on lo cated

at http://www.microchip.com/packaging

25AA040/25LC040/25C040

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

A1 A2

MILLIMETERS*

MIN NOM MAX

1.20

1.05

0.15

4.50

3.10

0.75

8°

0.20

0.30

–

1.00

–

4.40

3.00

0.60

–

0.80

0.05

4.30

2.90

0.45

0°

0.09

0.19

INCHES

MIN NOM MAX

–

.039

–

.173

.118

.024

–

.047

.041

.006

.177

.122

.030

8°

.008

.012

–

.031

.002

.169

.114

.018

0°

.004

.007

.026 BSC 0.65 BSC

.252 BSC 6.40 BSC

12° REF

Units

Dimension Limits

Number of Pins

Pitch

Overall Height

Molded Package Thickness

Standoff

Overall Width

Molded Package Width

Molded Package Length

Foot Length

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005" (0.127mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

Drawing No. C04-086 Revised 7-25-06

Note: For the most current package drawings, please

see the Mi cro ch ip Pac ka gi ng Spe ci fic ati on lo cated

at http://www.microchip.com/packaging

25AA040/25LC040/25C040

APPENDIX A: REVISION HIST ORY

Revision D

Corrections to Section 1.0, Electrical Characteristics.

Revision E (8/2006)

Added note to page 1 header (Not recommended for

new designs). Added note to package drawings.

Updated document format

25AA040/25LC040/25C040

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Microc hip pro vides onl ine s upport v ia our W WW site at

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Technical s upport is a vailable through the web site

at: http://support.microchip.com

25AA040/25LC040/25C040

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

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Questions:

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DS21204E25AA040/25LC040/25C040

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

25AA040/25LC040/25C040

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: 25AA040: 4096-bit 1.8V SPI Serial EEPROM

25AA040T: 4096-bit 1.8V SPI Serial EEPROM

(Tape and Reel)

25XX040X: 4096-bit 1.8V SPI Serial EEPROM

in alternate pinout (ST only)

25AA040XT:4096-bit 1.8V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)

25LC040: 4096-bit 2.5V SPI Serial EEPROM

25LC040T: 4096-bit 2.5V SPI Serial EEPROM

(Tape and Reel)

25LC040X: 4096-bit 2.5V SPI Serial EEPROM

in alternate pinout (ST only)

25LC040XT:4096-bit 2.5V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)

25C040: 4096-bit 5.0V SPI Serial EEPROM

25C040T: 4096-bit 5.0V SPI Ser ial EEPROM

(Tape and Reel)

25C040X: 4096-bit 5.0V SPI Serial EEPROM

in alternate pinout (ST only)

25C040XT: 4096-bit 5.0V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)

Temperature

Range: I = -40 °C to+85 °C

E = -40 °C to+125 °C

Package: P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm body), 8-lead

Examples:

a) 25AA040-I/P: Industrial Temp.,

PDIP package

b) 25AA040-I/SN: Industrial Te mp.,

SOIC package

c) 25AA040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

d) 25AA040X-I/ST: Alternate Pinout,

Industrial Temp., TSSOP package

e) 25AA040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP

package

f) 25LC040-I/P : Industrial Temp.,

PDIP package

g) 25LC040-I/SN: Industrial Temp.,

SOIC package

h) 25LC040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

i) 25LC040X-I/ST: Alternate Pinout,

Industrial Temp., TSSOP package

j) 25LC040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP

package

k) 25C040-I/P: Industrial Temp.,

PDIP package

l) 25C040-I/SN: Industrial Temp.,

SOIC package

m) 25C040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

n) 25C040X-I/ST: Alternate Pinout,

Industrial Temp., TSSOP package

o) 25C040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP

package

p) 25C040-E/P: Extended Temp.,

PDIP package

q) 25C040-E/SN: Extended Temp.,

SOIC package

r) 25C040T-E/SN: Tape and Reel,

Extended Te mp ., SOIC package

s) 25C040X-E/ST: Alternate Pinout,

Extended Temp., TSSOP package

t) 25C040XT-E/ST: Alternate Pinout, Tape

and Reel, Extended Tem p., TSS OP pack-

age

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

25AA040/25LC040/25C040

NOTES:

Information contained in this publication regarding device

applications a nd t he like is p rovided only for your convenience

and may be superseded by u pdates. It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MA TE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving t he c ode protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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08/29/06