Features
•8-bit Microcontroller Compatible with MCS®51 Products
•Enhanced 8051 Architecture
– Single-clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256x8 Internal RAM
– 4096x8 Internal Extra RAM
– Up to 4KB Extended Stack in Extra RAM
– Dual Data Pointers
– 4-level Interrupt Priority
•Nonvolatile Program and Data Memory
– 32K/64K Bytes of In-System Programmable (ISP) Flash Program Memory
– 8K Bytes of Flash Data Memory
– Endurance: Minimum 100,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 256-Byte User Signature Array
– 2-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
•Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– 4-Channel 16-bit Compare/Capture/PWM Array
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Master/Slave Two-Wire Serial Interface
– Programmable Watchdog Timer with Software Reset
– Dual Analog Comparators with Selectable Interrupts and Debouncing
– 8-channel 10-bit ADC/DAC
– 8 General-purpose Interrupt Pins
•Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Active-low External Reset Pin
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
•I/O and Packages
– Up to 38 Programmable I/O Lines
– 40-lead PDIP or 44-lead TQFP/PLCC or 44-pad VQFN/MLF
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style)
• Input-Only (Tristate)
• Push-pull CMOS Output
• Open-drain
•Operating Conditions
– 2.4V to 3.6V VDD Voltag e Range
–-40°C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4–3.6V
8-bit
Microcontroller
with 32K/64K
Bytes In-System
Programmable
Flash
AT89LP3240
AT89LP6440
3706C–MICRO–2/11
2
3706C–MICRO–2/11
AT89LP3240/6440
1. Pin Configurations
1.1 40P6: 40-lead PDIP
1.2 44A: 44-lead TQFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2/P1.0
T2EX/P1.1
SDA/P1.2
SCL/P1.3
SS/P1.4
MOSI/P1.5
MISO/P1.6
SCK/P1.7
RST/P4.2
RXD/P3.0
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2/P4.1
XTAL1/P4.0
GND
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.3
P4.4/ALE
P4.5
P2.7/AIN3/A15
P2.6/AIN2/A14
P2.5/AIN1/A13
P2.4/AIN0/A12
P2.3/A11/CCD
P2.2/A10/CCC
P2.1/A9/CCB
P2.0/A8/CCA
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
MOSI/P1.5
MISO/P1.6
SCK/P1.7
RST/P4.2
RXD/P3.0
VDD
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.3
GND
P4.4/ALE
P4.5
P2.7/AIN3/A15
P2.6/AIN2/A14
P2.5/AIN1/A13
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
WR/P3.6
RD/P3.7
XTAL2/P4.1
XTAL1/P4.0
GND
GND
CCA/A8/P2.0
CCB/A9/P2.1
CCC/A10/P2.2
CCD/A11/P2.3
A12/AIN0/P2.4
P1.4/SS
P1.3/SCL
P1.2/SDA
P1.1/T2EX
P1.0/T2
VDD
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
3
3706C–MICRO–2/11
AT89LP3240/6440
1.3 44J: 44-lead PLCC
1.4 44M1: 44-pad VQFN/MLF
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
MOSI/P1.5
MISO/P1.6
SCK/P1.7
RST/P4.2
RXD/P3.0
VDD
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.3
GND
P4.4/ALE
P4.5
P2.7/AIN3/A15
P2.6/AIN2/A14
P2.5/AIN1/A13
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
WR/P3.6
RD/P3.7
XTAL2/P4.1
XTAL1/P4.0
GND
GND
CCA/A8/AIN0/P2.0
CCB/A9/P2.1
CCC/A10/P2.2
CCD/A11/P2.3
A12/AIN0/P2.4
P1.4/SS
P1.3/SCL
P1.2/SDA
P1.1/T2EX
P1.0/T2
VDD
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
Bottom pad
should be
soldered to ground
NOTE:
MOSI/P1.5
MISO/P1.6
SCK/P1.7
RST/P4.2
RXD/P3.0
VDD
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P4.3
GND
P4.4/ALE
P4.5
P2.7/AIN3/A15
P2.6/AIN2/A14
P2.5/AIN1/A13
WR/P3.6
RD/P3.7
XTAL2/P4.1
XTAL1/P4.0
GND
GND
CCA/A8/P2.0
CCB/A9/P2.1
CCC/A10/P2.2
CCD/A11/P2.3
A12/AIN0/P2.4
P1.4/SS
P1.3/SCL
P1.2/SDA
P1.1/T2EX
P1.0/T2
VDD
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
4
3706C–MICRO–2/11
AT89LP3240/6440
1.5 Pin Description
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
Symbol Type DescriptionTQFP PLCC PDIP VQFN
1761P1.5
I/O
I/O
I
P1.5: User-configurable I/O Port 1 bit 5.
MOSI: SPI master-out/slave-in. When configured as master, this pin is an output.
When configured as slave, this pin is an input.
GPI5: General-purpose Interrupt input 5.
2872P1.6
I/O
I/O
I
P1.6: User-configurable I/O Port 1 bit 6.
MISO: SPI master-in/slave-out. When configured as master, this pin is an input. When
configured as slave, this pin is an output.
GPI6: General-purpose Interrupt input 6.
3983P1.7
I/O
I/O
I
P1.7: User-configurable I/O Port 1 bit 7.
SCK: SPI Clock. When configured as master, this pin is an output. When configured
as slave, this pin is an input.
GPI7: General-purpose Interrupt input 7.
4109 4P4.2
I/O
I
I
P4.2: User-configurable I/O Port 4 bit 2 (if Reset Fuse is disabled).
RST: External Active-Low Reset input (if Reset Fuse is enabled. See “External
Reset” on page 35.).
DCL: Serial Clock input for On-Chip Debug Interface when OCD is enabled.
511105P3.0
I/O
I
P3.0: User-configurable I/O Port 3 bit 0.
RXD: Serial Port Receiver Input.
612 6VDD ISupply Voltage
713117P3.1
I/O
O
P3.1: User-configurable I/O Port 3 bit 1.
TXD: Serial Port Transmitter Output.
814 12 8P3.2 I/O
I
P3.2: User-configurable I/O Port 3 bit 2.
INT0: External Interrupt 0 Input or Timer 0 Gate Input.
915139P3.3
I/O
I
P3.3: User-configurable I/O Port 3 bit 3.
INT1: External Interrupt 1 Input or Timer 1 Gate Input
10 16 14 10 P3.4 I/O
I/O
P3.4: User-configurable I/O Port 3 bit 4.
T1: Timer/Counter 0 External input or PWM output.
11 17 15 11 P3.5 I/O
I/O
P3.5: User-configurable I/O Port 3 bit 5.
T1: Timer/Counter 1 External input or PWM output.
12 1816 12 P3.6 I/O
O
P3.6: User-configurable I/O Port 3 bit 6.
WR: External memory interface Write Strobe (active-low).
13 19 17 13 P3.7 I/O
O
P3.7: User-configurable I/O Port 3 bit 7.
RD: External memory interface Read Strobe (active-low).
14 20 1814 P4.1
I/O
O
O
I/O
P4.1: User-configurable I/O Port 4 bit 1.
XTAL2: Output from inverting oscillator amplifier. It may be used as a port pin if the
internal RC oscillator is selected as the clock source.
CLKOUT: When the internal RC oscillator is selected as the clock source, may be
used to output the internal clock divided by 2.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the external clock is selected as the clock source.
15 21 19 15 P4.0
I/O
I
I/O
P4.0: User-configurable I/O Port 4 bit 0.
XTAL1: Input to the inverting oscillator amplifier and internal clock generation circuits.
It may be used as a port pin if the internal RC oscillator is selected as the clock
source.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the internal RC oscillator is selected as the clock source.
16 22 N/A 16 GND I Ground
5
3706C–MICRO–2/11
AT89LP3240/6440
17 23 20 17 GND I Ground
1824 21 18P2.0
I/O
I/O
O
P2.0: User-configurable I/O Port 2 bit 0.
CCA: Timer 2 Channel A Compare Output or Capture Input.
A8: External memory interface Address bit 8.
19 25 22 19 P2.1
I/O
I/O
O
P2.1: User-configurable I/O Port 2 bit 1.
CCB: Timer 2 Channel B Compare Output or Capture Input.
A9: External memory interface Address bit 9.
20 26 23 20 P2.1
I/O
I/O
O
O
P2.2: User-configurable I/O Port 2 bit 2.
CCC: Timer 2 Channel C Compare Output or Capture Input.
A10: External memory interface Address bit 10.
DA-: DAC negative differential output.
21 27 24 21 P2.3
I/O
I/O
O
O
P2.3: User-configurable I/O Port 2 bit 3.
CCD: Timer 2 Channel D Compare Output or Capture Input.
A11: External memory interface Address bit 11.
D+-: DAC positive differential output.
22 2825 22 P2.4
I/O
I
O
P2.4: User-configurable I/O Port 2 bit 5.
AIN0: Analog Comparator Input 0.
A12: External memory interface Address bit 12.
23 29 26 23 P2.5
I/O
I
O
P2.5: User-configurable I/O Port 2 bit 5.
AIN1: Analog Comparator Input 1.
A13: External memory interface Address bit 13.
24 30 27 24 P2.6
I/O
I
O
P2.6: User-configurable I/O Port 2 bit 6.
AIN2: Analog Comparator Input 2.
A14: External memory interface Address bit 14.
25 31 2825 P2.7
I/O
I
O
P2.7: User-configurable I/O Port 2 bit 7.
AIN3: Analog Comparator Input 3.
A15: External memory interface Address bit 15.
26 32 29 26 P4.5 I/O P4.5: User-configurable I/O Port 4 bit 5.
27 33 30 27 P4.4 I/O
O
P4.4: User-configurable I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
2834 28GND I Ground
29 35 31 29 P4.3
I/O
I/O
P4.3: User-configurable I/O Port 4 bit 3.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the Crystal oscillator is selected as the clock source.
30 36 32 30 P0.7
I/O
O
I
P0.7: User-configurable I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
ADC7: ADC analog input 7.
31 37 33 31 P0.6
I/O
O
I
P0.6: User-configurable I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
ADC6: ADC analog input 6.
32 3834 32 P0.5
I/O
O
I
P0.5: User-configurable I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
ADC5: ADC analog input 5.
33 39 35 33 P0.4
I/O
O
I
P0.4: User-configurable I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
ADC4: ADC analog input 4.
34 40 36 34 P0.3
I/O
O
I
P0.3: User-configurable I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
ADC3: ADC analog input 3.
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
Symbol Type DescriptionTQFP PLCC PDIP VQFN
6
3706C–MICRO–2/11
AT89LP3240/6440
2. Overview
The AT89LP3240/6440 is a low-power, high-performance CMOS 8-bit microcontroller with
32K/64K bytes of In-System Programmable Flash program memory and 8K bytes of Flash data
memory. The device is manufactured using Atmel®'s high-density nonvolatile memory technol-
ogy and is compatible with the industry-standard 8051 instruction set. The AT89LP3240/6440 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP3240/6440 CPU, standard instructions need only
1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Seventy
percent of instructions need only as many clock cycles as they have bytes to execute, and most
of the remaining instructions require only one additional clock. The enhanced CPU core is capa-
ble of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same
current consumption. Conversely, at the same throughput as the classic 8051, the new CPU
core runs at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP3240/6440 provides the following standard features: 32K/64K bytes of In-System
Programmable Flash program memory, 8K bytes of Flash data memory, 4352 bytes of RAM, up
to 38 I/O lines, three 16-bit timer/counters, up to six PWM outputs, a programmable watchdog
timer, two analog comparators, a 10-bit ADC/DAC with 8 input channels, a full-duplex serial port,
a serial peripheral interface, a two-wire serial interface, an internal RC oscillator, on-chip crystal
oscillator, and a four-level, twelve-vector interrupt system. A block diagram is shown in Figure 2-
1.
35 41 37 35 P0.2
I/O
O
I
P0.2: User-configurable I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
ADC2: ADC analog input 2.
36 42 3836 P0.1
I/O
O
I
P0.1: User-configurable I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
ADC1: ADC analog input 1.
37 43 39 37 P0.0
I/O
O
I
P0.0: User-configurable I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
ADC0: ADC analog input 0.
3844 40 38VDD I Supply Voltage
39 1 39 VDD I Supply Voltage
40 2 1 40 P1.0
I/O
I/O
I
P1.0: User-configurable I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
GPI0: General-purpose Interrupt input 0.
41 3 2 41 P1.1
I/O
I
I
P1.1: User-configurable I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
GPI1: General-purpose Interrupt input 1
42 4 3 42 P1.2 I/O
I
P1.2: User-configurable I/O Port 1 bit 2.
GPI2: General-purpose Interrupt input 2.
43 5 4 43 P1.3 I/O
I
P1.3: User-configurable I/O Port 1 bit 3.
GPI3: General-purpose Interrupt input 3.
44 6 5 44 P1.4
I/O
I
I
P1.4: User-configurable I/O Port 1 bit 4.
SS: SPI Slave-Select.
GPI6: General-purpose Interrupt input 4.
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
Symbol Type DescriptionTQFP PLCC PDIP VQFN
7
3706C–MICRO–2/11
AT89LP3240/6440
Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit
precision pulse width modulation output.
Timer 2 on the AT89LP3240/6440 serves as a 16-bit time base for a 4-channel Compare/Cap-
ture Array with up to four multi-phasic, variable precision (up to 16-bit) PWM outputs.
The enhanced UART of the AT89LP3240/6440 includes Framing Error Detection and Automatic
Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emula-
tion of half-duplex SPI or Two Wire interfaces.
The I/O ports of the AT89LP3240/6440 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input-only mode,
the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode
provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an inter-
rupt using the general-purpose interrupt interface.
2.1 Block Diagram
Figure 2-1. AT89LP3240/6440 Block Diagram
32K/64K Bytes
Flash Code
P o r t 2
Configu r a b le I/ O
P o r t 1
Configu r a b le I/ O
U A R T
SPI
Timer 0
Timer 1
Dual Analog
Comparators
W atchdo g
Timer
Internal
RC Oscillator
Gene r al-pu r pos e
Inter r up t
Configu r a b l e
Oscillator
C r ystal o r
Resonator
8K Bytes
Flash Data
P o r t 4
Configu r a b le I/ O
P o r t 3
Configu r a b le I/ O
Timer 2
Compare/
Capture Array
P o r t 0
Configu r a b le I/ O
TWI
8-channel 10-bit
ADC/DAC 8
256 Bytes
RAM
4K Bytes
ERAM
XRAM
Interface
8051 Single Cycle CPU
POR
BOD
Dual Data
Pointers
Multiply
Accumulate
(16 x 16)
On-Chip
Debug
8
3706C–MICRO–2/11
AT89LP3240/6440
2.2 System Configuration
The AT89LP3240/6440 supports several system configuration options. Nonvolatile options are
set through user fuses that must be programmed through the flash programming interface. Vola-
tile options are controlled by software through individual bits of special function registers (SFRs).
The AT89LP3240/6440 must be properly configured before correct operation can occur.
2.2.1 Fuse Options
Table 2-1 lists the fusable options for the AT89LP3240/6440. These options maintain their state
even when the device is powered off, but can only be changed with an external device program-
mer. For more information, see Section 25.7 “User Configuration Fuses” on page 164.
2.2.2 Software Options
Table 2-2 lists some important software configuration bits that affect operation at the system
level. These can be changed by the application software but are set to their default values upon
any reset. Most peripherals also have multipe configuration bits that are not listed here.
Table 2-1. User Configuration Fuses
Fuse Name Description
Clock Source
Selects between the High Speed Crystal Oscillator, Low Speed
Crystal Oscillator, External Clock or Internal RC Oscillator for the
source of the system clock.
Start-up Time Selects time-out delay for the POR/BOD/PWD wake-up period.
Reset Pin Enable Configures the RST pin as a reset input or general purpose I/O
Brown-Out Detector Enable Enables or disables the Brown-out Detector
On-Chip Debug Enable Enables or disables On-Chip Debug. OCD must be enabled prior to
using an in-circuit debugger with the device.
In-System Programming Enable Enables or disables In-System Programming.
User Signature Programming Enable Enables or disables programming of User Signature array.
Default Port State Configures the default port state as input-only mode (tristated) or
quasi-bidirectional mode (weakly pulled high).
In-Application Programming Enable Enables or disabled In-Application (self) Programming
Table 2-2. Important Software Configuration Bits
Bit(s) SFR Location Description
PxM0.y
PxM1.y
P0M0, P0M1, P1M0, P1M1,
P2M0, P2M1, P3M0, P3M1,
P4M0, P4M1
Configures the I/O mode of Port x Pin y to be one of input-only, quasi-
bidirectional, push-pull output or open-drain. The default state is
controlled by the Default Port State fuse above
CDV2-0 CLKREG.3-1 Selects the division ratio between the oscillator and the system clock
TPS3-0 CLKREG.7-4 Selects the division ratio between the system clock and the timers
ALESAUXR.0 Enables/disables toggling of ALE
EXRAM AUXR.1 Enables/disables access to on-chip memories that are mapped to the
external data memory address space
WS1-0 AUXR.3-2 Selects the number of wait states when accessing external data
memory
XSTK AUXR.4 Congifures the hardware stack to be in RAM or extra RAM
DMEN MEMCON.3 Enables/disables access to the on-chip flash data memory
IAP MEMCON.7 Enbles/disables the self programming feature when the fuse allows
9
3706C–MICRO–2/11
AT89LP3240/6440
2.3 Comparison to Standard 8051
The AT89LP3240/6440 is part of a family of devices with enhanced features that are fully binary
compatible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and
pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to
the high performance nature of the device, some system behaviors are different from those of
Atmel's standard 8051 products such as AT89S52 or AT89C2051. The major differences from
the standard 8051 are outlined in the following paragraphs and may be useful to users migrating
to the AT89LP3240/6440 from older devices.
2.3.1 System Clock
The maximum CPU clock frequency equals the externally supplied XTAL1 frequency. The oscil-
lator is not divided by 2 to provide the internal clock and X2 mode is not supported. The System
Clock Divider can scale the CPU clock versus the oscillator source (See Section 6.5 on page
32).
2.3.2 Reset
The RST pin of the AT89LP3240/6440 is active-LOW as compared with the active-high reset in
the standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low
for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset.
2.3.3 Instruction Execution with Single-cycle Fetch
The CPU fetches one code byte from memory every clock cycle instead of every six clock
cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer
executes instructions in 12, 24 or 48 clock cycles. Each standard instruction executes in only 1
to 4 clock cycles. See “Instruction Set Summary” on page 143 for more details. Any software
delay loops or instruction-based timing operations may need to be retuned to achieve the
desired results.
2.3.4 Interrupt Handling
The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In
order for an interrupt to be serviced at the end of an instruction, its flag needs to have been
latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of
the previous instruction if the current instruction executes in only a single clock cycle.
The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once
every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response,
this leads to a higher maximum rate of incidence for the external interrupts.
The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The SPI no longer shares
its interrupt with the Serial Port and the ESPI (IE2.2) bit replaces SPIE (SPCR.7).
2.3.5 Timer/Counters
By default Timer0, Timer 1 and Timer 2 are incremented at a rate of once per clock cycle. This
compares to once every 12 clocks in the standard 8051. A common prescaler is available to
divide the time base for all timers and reduce the increment rate. The TPS3-0 bits in the CLKREG
SFR control the prescaler (Table 6-2 on page 33). Setting TPS3-0 = 1011B will cause the timers
to count once every 12 clocks.
The external Timer/Counter pins, T0, T1, T2 and T2EX, are sampled at every clock cycle instead
of once every 12 clock cycles. This increases the maximum rate at which the Counter modules
may function.
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AT89LP3240/6440
There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Baud
Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in Auto-
Reload/Capture mode increments at 12 times the rate of standard 8051s. Setting TPS3-0 =
1101B will force Timer 2 to count every twelve clocks. Timer 2 in Baud Rate or Clock Out mode
increments at twice the rate of standard 8051s. Setting TPS3-0 = 0001B will force Timer 2 to
count every two clocks.
2.3.6 Serial Port
The baud rate of the UART in Mode 0 defaults to 1/4 the clock frequency, compared to 1/12 the
clock frequency in the standard 8051. In should also be noted that when using Timer 1 to gener-
ate the baud rate in UART Modes 1 or 3, the timer counts at the clock frequency and not at 1/12
the clock frequency. To maintain the same baud rate in the AT89LP3240/6440 while running at
the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of
Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud
rates.
Timer 2 generated baud rates are twice as fast in the AT89LP3240/6440 than on standard
8051s when operating at the same frequency. The Timer Prescaler can also scale the baud rate
to match an existing application.
2.3.7 SPI
The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The ESPI (IE2.2) bit
replaces SPIE (SPCR.7). SPCR.7 (TSCK) now enables timer-generated baud rate.
The SPI includes Mode Fault detection. If multiple-master capabilities are not required, SSIG
(SPSR.2) must be set to one for master mode to function correctly when SS (P1.4) is a general
purpose I/O.
2.3.8 Watchdog Timer
The Watchdog Timer in AT89LP3240/6440 counts at a rate of once per clock cycle. This com-
pares to once every 12 clocks in the standard 8051. A common prescaler is available to divide
the time base for all timers and reduce the counting rate.
2.3.9 I/O Ports
The I/O ports of the AT89LP3240/6440 may be configured in four different modes. By default all
the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all
ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must
be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs. The
user can also configure the ports to start in quasi-bidirectional mode by disabling the Tristate-
Port User Fuse. When this fuse is disabled, P1M0, P2M0, P3M0 and P4M0 will reset to 00h
instead of FFh and the ports will be weakly pulled high. Port 0 and the upper nibble of Port 2
always power up tristated regardless of the fuse setting due to their analog functions.
2.3.10 External Memory Interface
The AT89LP3240/6440 does not support external program memory. The PSEN and EA func-
tions are not supported and those pins are replaced with general purpose I/O. The ALE strobe
does not toggle continuously and cannot be used as a board-level clock.
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3. Memory Organization
The AT89LP3240/6440 uses a Harvard Architecture with separate address spaces for program
and data memory. The program memory has a regular linear address space with support for 64K
bytes of directly addressable application code. The data memory has 256 bytes of internal RAM
and 128 bytes of Special Function Register I/O space. The AT89LP3240/6440 supports external
data memory with portions of the external data memory space implemented on chip as Extra
RAM and nonvolatile Flash data memory. External program memory is not supported. The mem-
ory address spaces of the AT89LP3240/6440 are listed in Table 3-1.
3.1 Program Memory
The AT89LP3240/6440 contains 32K/64K bytes of on-chip In-System Programmable Flash
memory for programstorage. The Flash memory has an endurance of at least 100,000
write/erase cycles and a minimum data retention time of 10 years. The reset and interrupt vec-
tors are located within the first 83 bytes of program memory (refer to Table 9-1 on page 41).
Constant tables can be allocated within the entire 32K/64K program memory address space for
access by the MOVC instruction. The AT89LP3240/6440 does not support external program
memory. A map of the AT89LP3240/6440 program memory is shown in Figure 3-1.
3.1.1 SIG
In addition to the 64K code space, the AT89LP3240/6440 also supports a 256-byte User Signa-
ture Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel
Signature Array is initialized with the Device ID in the factory. The second page of the User Sig-
nature Array (0180H–01FFH) is initialized with analog configuration data including the Internal
RC Oscillator calibration byte. The User Signature Array is available for user identification codes
or constant parameter data. Data stored in the signature array is not secure. Security bits will
disable writes to the array; however, reads by an external device programmer are always
allowed.
In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set (See Table 5-5
on page 28). While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The
User Signature Array is mapped from addresses 0100h to 01FFh and the Atmel Signature Array
is mapped from addresses 0000h to 007Fh. SIGEN must be cleared before using MOVC to
access the code memory. The User Signature Array may also be modified by the In-Application
Programming interface. When IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access
the array (See Section 3.5 on page 21).
Table 3-1. AT89LP3240/6440 Memory Address Spaces
Name Description Range
DATA Directly addressable internal RAM 00H–7FH
IDATA Indirectly addressable internal RAM and stack space 00H–FFH
SFR Directly addressable I/O register space 80H–FFH
EDATA On-chip Extra RAM and extended stack space 0000H–0FFFH
FDATA On-chip nonvolatile Flash data memory 1000H–2FFFH
XDATA External data memory 3000H–FFFFH
CODE On-chip nonvolatile Flash program memory (AT89LP3240) 0000H–7FFFH
On-chip nonvolatile Flash program memory (AT89LP6440) 0000H–FFFFH
SIG On-chip nonvolatile Flash signature array 0000H–01FFH
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AT89LP3240/6440
Figure 3-1. Program Memory Map
3.2 Internal Data Memory
The AT89LP3240/6440 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O
memory mapped into a single 8-bit address space. Access to the internal data memory does not
require any configuration. The internal data memory has three address spaces: DATA, IDATA
and SFR; as shown in Figure 3-2. Some portions of external data memory are also implemented
internally. See “External Data Memory” below for more information.
Figure 3-2. Internal Data Memory Map
3.2.1 DATA
The first 128 bytes of RAM are directly addressable by an 8-bit address (00H–7FH) included in
the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers
each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc-
tions using register addressing will only access the currently specified bank. The lower 128 bit
addresses are also mapped into DATA addresses 20H—2FH.
Program Memory
0000
FFFF
0000
007F
User Signature Array
0100
01FF
Atmel Signature Array
SIGEN=0
SIGEN=1
AT89LP6440
Program Memory
0000
7FFF
0000
007F
User Signature Array
0100
01FF
Atmel Signature Array
AT89LP3240
FFH
UPPER
128
80H
7FH
LOWER
128
0
ACCESSIBLE
BY DIRECT
ADDRESSING
FFH
80H
ACCESSIBLE
BY DIRECT
AND INDIRECT
ADDRESSING
SPECIAL
FUNCTION
REGISTERS
PORTS
STATUS AND
CONTROL BITS
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)
TIMERS
ACCESSIBLE
BY INDIRECT
ADDRESSING
ONLY
IDATA SFR
DATA/IDATA
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AT89LP3240/6440
3.2.2 IDATA
The full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1.
The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the
IDATA space when XSTK = 0.
3.2.3 SFR
The upper 128 direct addresses (80H–FFH) access the I/O registers. I/O registers on AT89LP
devices are referred to as Special Function Registers. The SFRs can only be accessed through
direct addressing. All SFR locations are not implemented. See Section 4. for a listed of available
SFRs.
3.3 External Data Memory
AT89LP microcontrollers support a 16-bit external memory address space for up to 64K bytes of
external data memory (XDATA). The external memory space is accessed with the MOVX
instructions. Some internal data memory resources are mapped into portions of the external
address space as shown in Figure 3-3. These memory spaces may require configuration before
the CPU can access them. The AT89LP3240/6440 includes 4K bytes of on-chip Extra RAM
(EDATA) and 8K bytes of nonvolatile Flash data memory (FDATA).
Figure 3-3. External Data Memory Map
3.3.1 XDATA
The external data memory space can accommodate up to 64KB of external memory. The
AT89LP3240/6440 uses the standard 8051 external memory interface with the upper address
byte on Port 2, the lower address byte and data in/out multiplexed on Port 0, and the ALE, RD
and WR strobes. MOVX instructions targeted to XDATA require a minimum of 4 clock cycles.
XDATA can be accessed with both 16-bit (MOVX @DPTR) and 8-bit (MOVX @Ri) addresses.
See Section 3.3.4 on page 17 for more details of the external memory interface.
Extra RAM
(EDATA: 4KB)
0FFF
2FFF
3000
Flash Data
(FDATA: 8KB)
0000
0FFF
1000
FFFF
External Data
(XDATA: 64KB)
External Data
(XDATA: 60KB)
Extra RAM
(EDATA: 4KB)
External Data
(XDATA: 52KB)
FFFF FFFF
1000
EXRAM = 1 EXRAM = 0
DMEN = 0
EXRAM = 0
DMEN = 1
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Some internal data memory spaces are mapped into portions of the XDATA address space. In
this case the lower address ranges will access internal resources instead of external memory.
Addresses above the range implemented internally will default to XDATA. The
AT89LP3240/6440 supports up to 52K or 60K bytes of external memory when using the inter-
nally mapped memories. Setting the EXRAM bit (AUXR.1) to one will force all MOVX
instructions to access the entire 64KB XDATA regardless of their address (See “AUXR – Auxil-
iary Control Register” on page 18).
3.3.2 EDATA
The Extra RAM is a portion of the external memory space implemented as an internal 4K byte
auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external
memory address space, from 0000H to 0FFFH. MOVX instructions to this address range will
access the internal Extra RAM. EDATA can be accessed with both 16-bit (MOVX @DPTR) and
8-bit (MOVX @Ri) addresses. When 8-bit addresses are used, the PAGE register (086H) sup-
plies the upper address bits. The PAGE register breaks EDATA into sixteen 256-byte pages. A
page cannot be specified independently for MOVX @R0 and MOVX @R1. Setting PAGE above
0FH enables XDATA access, but does not change the value of Port 2. When 16-bit addresses
are used (DPTR), the IAP bit (MEMCON.7) must be zero to access EDATA. MOVX instructions
to EDATA require a minimum of 2 clock cycles.
3.3.3 FDATA
The Flash Data Memory is a portion of the external memory space implemented as an internal
nonvolatile data memory. Flash Data Memory is enabled by setting the DMEN bit (MEMCON.3)
to one. When IAP = 0 and DMEN = 1, the Flash Data Memory is mapped into the FDATA space,
directly above the EDATA space near the bottom of the external memory address space, from
1000H to 2FFFH. (See Figure 3-3). MOVX instructions to this address range will access the
internal nonvolatile memory. FDATA is not accessible while DMEN = 0. FDATA can be
accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the FDATA
address range will access external memory. Addresses above the FDATA range are mapped to
XDATA. MOVX instructions to FDATA require a minimum of 4 clock cycles.
3.3.3.1 Write Protocol
The FDATA address space accesses an internal nonvolatile data memory. This address space
can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a
more complex protocol and take several milliseconds to complete. The AT89LP3240/6440 uses
an idle-while-write architecture where the CPU is placed in an idle state while the write occurs.
When the write completes, the CPU will continue executing with the instruction after the
MOVX @DPTR,A instruction that started the write. All peripherals will continue to function during
the write cycle; however, interrupts will not be serviced until the write completes.
Table 3-2. PA G E – EDATA Page Register
PAG E = 86H Reset Value = 0000 0000B
Not Bit Addressable
PAGE.7 PAGE.6 PAGE.5 PAGE.4 PAGE.3 PAGE.2 PAGE.1 PAGE.0
Bit76543210
Symbol Function
PAG E 7-0 Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions when PAGE < 10H. Any PAGE
value between 10H and FFH will selected XDATA; however, this value will not be output on P2.
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AT89LP3240/6440
To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set
to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA.
FDATA uses flash memory with a page-based programming model. Flash data memory differs
from traditional EEPROM data memory in the method of writing data. EEPROM generally can
update a single byte with any value. Flash memory splits programming into write and erase
operations. A Flash write can only program zeroes, i.e change ones into zeroes (). Any
ones in the write data are ignored. A Flash erase sets an entire page of data to ones so that all
bytes become FFH. Therefore after an erase, each byte in the page can be written only once
with any possible value. Bytes can not be overwritten once they are changed from the erased
state without possibility of corrupting the data. Therefore, if even a single byte needs updating;
then the contents of the page must first be saved, the entire page must be erased and the zero
bits in all bytes (old and new data combined) must be written. Avoiding unnecessary page
erases greatly improves the endurance of the memory.
The AT89LP3240/6440 includes 64 data pages of 128 bytes each. One or more bytes in a page
may be written at one time. The AT89LP3240/6440 includes a temporary page buffer of 64
bytes, or half of a page. Because the page buffer is 64 bytes long, the maximum number of
bytes written at one time is 64. Therefore, two write cycles are required to fill the entire 128-byte
page, one for the low half page (00H–3FH) and one for the high half page (40H–7FH) as shown
in Figure 3-4.
Figure 3-4. Page Programming Structure
The LDPG bit (MEMCON.5) allows multiple data bytes to be loaded to the temporary page buf-
fer. While LDPG = 1, MOVX @DPTR,A instructions will load data to the page buffer, but will not
start a write sequence. Note that a previously loaded byte must not be reloaded prior to the write
sequence. To write the half page into the memory, LDPG must first be cleared and then a
MOVX @DPTR,A with the final data byte is issued. The address of the final MOVX determines
which half page will be written. If a MOVX @DPTR,A instruction is issued while LDPG = 0 with-
out loading any previous bytes, only a single byte will be written. The page buffer is reset after
each write operation. Figures 3-5 and Figure 3-6 on page 16 show the difference between byte
writes and page writes.
The auto-erase bit AERS (MEMCON.6) can be set to one to perform a page erase automatically
at the beginning of any write sequence. The page erase will erase the entire page, i.e. both the
low and high half pages. However, the write operation paired with the auto-erase can only pro-
gram one of the half pages. A second write cycle without auto-erase is required to update the
other half page.
10→
Low Half Page
00 3F
Data Memory
High Half Page
40 7F
00 3F
Page Buffer
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AT89LP3240/6440
Figure 3-5. FDATA Byte Write
Figure 3-6. FDATA Page Write
Frequently just a few bytes within a page must be updated while maintaining the state of the
other bytes. There are two options for handling this situation that allow the Flash Data memory
to emulate a traditional EEPROM memory. The simplest method is to copy the entire page into a
buffer allocated in RAM, modify the desired byte locations in the RAM buffer, and then load and
write back first the low half page (with auto-erase) and then the high half page to the Flash mem-
ory. This option requires that at least one page size of RAM is available as a temporary buffer.
The second option is to store only one half page in RAM. The unmodified bytes of the other page
are loaded directly into the Flash memory’s temporary load buffer before loading the updated
values of the modified bytes. For example, if just the low half page needs modification, the user
must first store the high half page to RAM, followed by reading and loading the unaffected bytes
of the low half page into the page buffer. Then the modified bytes of the low half page are stored
to the page buffer before starting the auto-erase sequence. The stored value of the high half
page must be written without auto-erase after the programming of the low half page completes.
This method reduces the amount of RAM required; however, more software overhead is needed
because the read-and-load-back routine must skip those bytes in the page that need to be
updated in order to prevent those locations in the buffer from being loaded with the previous
data, as this will block the new data from being loaded correctly.
A write sequence will not occur if the Brown-out Detector is active, even if the BOD reset has
been disabled. In cases where the BOD reset is disabled, the user should check the BOD status
by reading the WRTINH bit in MEMCON. If a write currently in progress is interrupted by the
BOD due to a low voltage condition, the ERR flag will be set. FDATA can always be read regard-
less of the BOD state.
For more details on using the Flash Data Memory, see the application note titled “AT89LP Flash
Data Memory”. FDATA may also be programmed by an external device programmer (See Sec-
tion 25. on page 157).
MWEN
DMEN
tWC
LDPG
IDLE
MOVX
tWC
MWEN
DMEN
tWC
LDPG
IDLE
MOVX
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AT89LP3240/6440
3.3.4 External Memory Interface
The AT89LP3240/6440 uses the standard 8051 external memory interface with the upper
address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE, RD
and WR strobes. The interface may be used in two different configurations depending on which
type of MOVX instruction is used to access XDATA.
Figure 3-7 shows a hardware configuration for accessing up to 64K bytes of external RAM using
a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The
Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-
ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte
throughout the operation. The MOVX @DPTR instructions use Linear Address mode
Figure 3-7. External Memory 16-bit Linear Address Mode
Table 3-3. MEMCON – Memory Control Register
MEMCON = 96H Reset Value = 0000 00XXB
Not Bit Addressable
IAP AERSLDPG MWEN DMEN ERR – WRTINH
Bit76543210
Symbol Function
IAP In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space
is enabled and MOVX @DPTR instructions will access CODE/SIG instead of EDATA or FDATA. Clear IAP to disable
programming of CODE/SIG and allow access to EDATA and FDATA.
AERSAuto-Erase Enable. Set to perform an auto-erase of a Flash memory page (CODE, SIG or FDATA) during the next write
sequence. Clear to perform write without erase.
LDPG Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded
more than once before a write. LDPG must be cleared before writing.
MWEN Memory Write Enable. Set to enable programming of a nonvolatile memory location (CODE, SIG or FDATA). Clear to
disable programming of all nonvolatile memories.
DMEN Data Memory Enable. Set to enable nonvolatile data memory and map it into the FDATA space. Clear to disable
nonvolatile data memory.
ERR Error Flag. Set by hardware if an error occurred during the last programming sequence due to a brownout condition (low
voltage on VDD). Must be cleared by software.
WRTINH Write Inhibit Flag. Cleared by hardware when the voltage on VDD has fallen below the minimum programming voltage.
Set by hardware when the voltage on VDD is above the minimum programming voltage.
P1 P0
ALE
P2
RD P3
WR
AT89LP
DATA
LATCH
EXTERNAL
DATA
MEMORY
WE
ADDR
OE
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AT89LP3240/6440
Figure 3-8 shows a hardware configuration for accessing 256-byte blocks of external RAM using
an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE
strobe is used to latch the address byte into an external register so that Port 0 can be freed for
data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-
ory; however, this operation is not handled automatically by hardware. The software application
must change the Port 2 register when appropriate to access different pages. The MOVX @Ri
instructions use Paged Address mode.
Figure 3-8. External Memory 8-bit Paged Address Mode
Note that prior to using the external memory interface, Port 2, WR (P3.6), RD (P3.7) and ALE
(P4.4) must be configured as outputs. See Section 10.1 “Port Configuration” on page 45. Port 0
is configured automatically to push-pull output mode when outputting address or data and is
P1 P0
I/O
ALE
P2
RD P3
WR
AT89LP
DATA
LATCH
EXTERNAL
DATA
MEMORY
WE
ADDR
PAG E
BITS OE
Table 3-4. AUXR – Auxiliary Control Register
AUXR = 8EH Reset Value = xxx0 0000B
Not Bit Addressable
–––XSTK WS1WS0 EXRAM ALES
Bit76543210
Symbol Function
XSTK
Extended Stack Enable. When XSTK = 0 the stack resides in IDATA and is limited to 256 bytes. Set XSTK = 1 to place
the stack in EDATA for up to 4K bytes of extended stack space. All PUSH, POP, CALL and RET instructions will incur a
one or two cycle penalty when accessing the extended stack.
WS[1-0] Wait State Select. Determines the number of wait states inserted into external memory accesses.
WS1WS0 Wait StatesRD / WR Strobe Width
000 1 x t
CYC
011 2 x t
CYC
102 3 x t
CYC
113 4 x t
CYC
EXRAM
External RAM Enable. When EXRAM = 0, MOVX instructions can access the internally mapped portions of the address
space. Accesses to addresses above internally mapped memory will access external memory. Set EXRAM = 1 to
bypass the internal memory and map the entire address space to external memory.
ALESALE Idle State. When ALES= 0 the idle polarity of ALE is high (active). When ALES= 1 the idle polarity of ALE is low
(inactive). The ALE strobe pulse is always active high. ALES must be zero in order to use P4.4 as a general I/O.
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AT89LP3240/6440
automatically tristated when inputting data regardless of the Port 0 configuration. The Port 0
configuration will determine the idle state of Port 0 when not accessing the external memory.
Figure 3-9 and Figure 3-10 show examples of external data memory write and read cycles,
respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle polarity of
ALE is controlled by ALES (AUXR.0). When ALES= 0 the idle polarity of ALE is high (active).
When ALES= 1 the idle polarity of ALE is low (inactive). The ALE strobe pulse is always active
high. Unlike standard 8051s, ALE will not toggle continuously when not accessing external
memory. ALES must be zero in order to use P4.4 as a general-purpose I/O. The WS bits in
AUXR can extended the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-11, 3-12
and 3-13. If a longer strobe is required, the application can scale the system clock with the clock
divider to meet the requirements (See Section 6.5 on page 32).
Figure 3-9. External Data Memory Write Cycle (WS=00B)
Figure 3-10. External Data Memory Read Cycle (WS= 00B)
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AT89LP3240/6440
Figure 3-11. MOVX with One Wait State (WS=01B)
Figure 3-12. MOVX with Two Wait States (WS=10B)
Figure 3-13. MOVX with Three Wait States (WS=11B)
3.4 Extended Stack
The AT89LP3240/6440 provides an extended stack space for applications requiring additional
stack memory. By default the stack is located in the 256-byte IDATA space of internal data
memory. The IDATA stack is referenced solely by the 8-bit Stack Pointer (SP: 81H). Setting the
XSTK bit in AUXR enables the extended stack. The extended stack resides in the EDATA space
for up to 4KB of stack memory. The extended stack is referenced by a 12-bit pointer formed from
SP and the four LSBs of the Extended Stack Pointer (SPX: 9EH) as shown in Figure 3-14. SP is
shared between both stacks. Note that the standard IDATA stack will not overflow to the EDATA
stack or vice versa. The stack and extended stack are mutually exclusive and SPX is ignored
when XTSK=0. An application choosing to switch between stacks by toggling XSTK must main-
S1 S2 S3W1
CLK
ALE
WR
DPL OUTP0 SFR P0 SFR
P0
P2 SFR P2 SFRDPH or P2 OUT
P2
DATA OUT
S4
RD
DPL OUTP0 SFR P0 SFR
P0 FLOAT
S1 S2 S3W1
CLK
ALE
WR
DPL OUTP0 SFR P0 SFR
P0
P2 SFR P2 SFRDPH or P2 OUT
P2
DATA OUT
W2
RD
DPL OUTP0 SFR P0 SFR
P0 FLOAT
S4
S1 S2 S3W1
CLK
ALE
WR
DPL OUTP0 SFR P0 SFR
P0
P2 SFR P2 SFRDPH or P2 OUT
P2
DATA OUT
W2
RD
DPL OUTP0 SFR P0 SFR
P0 FLOAT
W3S4
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AT89LP3240/6440
tain separate copies of SP for use with each stack space. Interrupts should be disabled while
swapping copies of SP in such an application to prevent illegal stack accesses.
All interrupt calls and PUSH, POP, ACALL, LCALL, RET and RETI instructions will incur a one
or two-cycle penalty while the extended stack is enabled, depending on the number of stack
access in each instruction. The extended stack may only exist within the internal EDATA space;
it cannot be placed in XDATA. The stack will continue to use EDATA even if EDATA is disabled
by setting EXRAM = 1.
Figure 3-14. Stack Configurations
3.5 In-Application Programming (IAP)
The AT89LP3240/6440 supports In-Application Programming (IAP), allowing the program mem-
ory to be modified during execution. IAP can be used to modify the user application on the fly or
to use program memory for nonvolatile data storage. The same page structure write protocol for
FDATA also applies to IAP (See Section 3.3.3.1 “Write Protocol” on page 14). The CPU is
always placed in idle while modifying the program memory. When the write completes, the CPU
will continue executing with the instruction after the MOVX @DPTR,A instruction that started the
write.
To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the
IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this
fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instruc-
tions will access the CODE space instead of EDATA/FDATA/XDATA. IAP also allows
reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are sum-
marized in Table 3-5.
70
00h
FFh
IDATA
(256)
SP
70
00h
FFFh
EDATA
(4K)
SP
30
SPX
XSTK = 0 XSTK = 1
Table 3-5. IAP Access Settings
IAP SIGEN DMEN MOVX @DPTR MOVC @DPTR
0 0 0 EDATA (0000–0FFFH) CODE (0000–FFFFH)
0 0 1 FDATA (1000–2FFFH) CODE (0000–FFFFH)
0 1 0 EDATA (0000–0FFFH) SIG (0000–01FFH)
0 1 1 FDATA (1000–2FFFH) SIG (0000–01FFH)
1 0 X CODE (0000–FFFFH) CODE (0000–FFFFH)
11X SIG (0000–01FFH) SIG (0000–01FFH)
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4. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 4-1. See also “Register Index” on page 153.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
Notes:1.All SFRs in the left-most column are bit-addressable.
2. Reset value is 1111 1111B when Tristate-Port Fuse is enabled and 0000 0000B when disabled.
Table 4-1. AT89LP3240/6440 SFR Map and Reset Values
89ABCDEF
0F8H0FFH
0F0H B
0000 0000
BX
0000 0000 0F7H
0E8HSPSR
000x x000
SPCR
0000 0000
SPDR
xxxx xxxx 0EFH
0E0H ACC
0000 0000
AX
0000 0000
DSPR
0000 0000
FIRD
0000 0000
MACL
0000 0000
MACH
0000 0000 0E7H
0D8HDADC
0000 0000
DADI
0000 0000
DADL
0000 0000
DADH
0000 0000 0DFH
0D0H PSW
0000 0000
T2CCA
0000 0000
T2CCL
0000 0000
T2CCH
0000 0000
T2CCC
0000 0000
T2CCF
0000 0000 0D7H
0C8HT2CON
0000 0000
T2MOD
0000 0000
RCAP2L
0000 000
RCAP2H
0000 0000
TL2
0000 000
TH2
0000 0000 0CFH
0C0H P4
xx11 1111
P1M0(2) P1M1
0000 0000
P2M0(2) P2M1
0000 0000
P3M0(2) P3M1
0000 0000 0C7H
0B8HIP
0000 0000
SADEN
0000 0000
P0M0
1111 1111
P0M1
0000 0000
P4M0(2) P4M1
xx00 0000 0BFH
0B0H P3
1111 1111
IE2
xxxx x000
IP2
xxxx x000
IP2H
xxxx x000
IPH
0000 0000 0B7H
0A8HIE
0000 0000
SADDR
0000 0000
TWCR
0000 0000
TWSR
0000 0000
TWAR
0000 0000
TWDR
0000 0000
TWBR
0000 0000
AREF
0000 0000 0AFH
0A0H P2
1111 1111
DPCF
0000 00x0
WDTRST
(write-only)
WDTCON
0000 x000 0A7H
98HSCON
0000 0000
SBUF
xxxx xxxx
GPMOD
0000 0000
GPLS
0000 0000
GPIEN
0000 0000
GPIF
0000 0000
SPX
xxxx 0000
ACSRB
1100 0000 9FH
90H P1
1111 1111
TCONB
0010 0100
RL0
0000 0000
RL1
0000 0000
RH0
0000 0000
RH1
0000 0000
MEMCON
0000 00xx
ACSRA
0000 0000 97H
88HTCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
0000 0000
CLKREG
0000 x000 8FH
80H SP
0000 0111
DP0L
0000 0000
DP0H
0000 0000
DP1L
0000 0000
DP1H
0000 0000
PAG E
0000 0000
PCON
0000 0000 87H
01234567
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5. Enhanced CPU
The AT89LP3240/6440 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of
standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in perfor-
mance is due to two factors. First, the CPU fetches one instruction byte from the code memory
every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute
instructions in parallel. This basic pipelining concept allows the CPU to obtain up to
1MIPSper MHz. A simple example is shown in Figure 5-1.
The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-
clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has
bytes to execute. The majority of instructions in the AT89LP3240/6440 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction, with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See “Instruction Set Summary” on
page 143. for more detailed information on individual instructions. Figures 5-2 and 5-3 show
examples of 1- and 2-byte instructions.
Figure 5-1. Parallel Instruction Fetches and Executions
Figure 5-2. Single-cycle ALU Operation (Example: INC R0)
System Clock
nth Instruction
(n+1)th Instruction
Fetch Execute
Fetch Execute
Fetch
TnTn+1 Tn+2
(n+2)th Instruction
System Clock
Tot al Execution Time
Register Operand Fetch
T1T2T3
ALU Operation Execute
Result Write Back
Fetch Next Instruction
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AT89LP3240/6440
Figure 5-3. Two-cycle ALU Operation (Example: ADD A, #data)
5.1 Multiply–Accumulate Unit (MAC)
The AT89LP3240/6440 includes a multiply and accumulate (MAC) unit that can significantly
speed up many mathematical operations required for digital signal processing. The MAC unit
includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multi-
ply-accumulate operations on signed 16-bit input values. The MAC unit also includes a 1-bit
arithmetic shifter that will left or right shift the contents of the 40-bit MAC accumulator register
(M).
A block diagram of the MAC unit is shown in Figure 5-4. The 16-bit signed operands are pro-
vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher
order bytes. The 16-by-16 bit multiplication is computed through partial products using the
AT89LP3240/6440’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumu-
lator register. The MAC operation is summarized as follows:
All computation is done in signed two’s complement form.
Figure 5-4. Multiply–Accumulate Unit
System Clock
Tot al Execution Time
Fetch Immediate Operand
T1T2T3
ALU Operation Execute
Result Write Back
Fetch Next Instruction
MAC AB: M M AX ACC{, } BX B{,}×+←
M3M4 M2 M1 M0
ACCAX BX B
8 x 8-bit Signed MULT
40-bit ADD Shifter
MACH MACL
PSW
MRW
SMLA
SMLB
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AT89LP3240/6440
The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This
two-byte instruction requires nine clock cycles to complete. The operand registers are not modi-
fied by the instruction and the result is stored in the 40-bit M register. MAC AB also updates the
C and OV flags in PSW. C represents the sign of the MAC result and OV is the two’s comple-
ment overflow. Note that MAC AB will not clear OV if it was previously set to one.
Three additional extended instructions operate directly on the M register. CLR M (A5 E4H)
clears the entire 40-bit register in two clock cycles. LSL M (A5 23H) and ASR (A5 03H) shift M
one bit to the left and right respectively. Right shifts are done arithmetically, i.e. the sign is
preserved.
The 40-bit M register is accessible 16-bits at a time through a sliding window as shown in Figure
5-5. The MRW1-0 bits in DSPR (Table 5-1) select which 16-bit segment is currently accessible
through the MACL and MACH addresses. For normal fixed point operations the window can be
fixed to the rank of interest. For example, multiplying two 1.15 format numbers places a 2.30 for-
mat result in the M register. If MRW is set to 10B, a 1.15 value is obtained after performing a
single LSL M.
Figure 5-5. M Register with Sliding Window
As a consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed
multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the
ACC and B registers, allowing any combination of signed and unsigned operand multiplication.
These bits have no effect on the MAC operation which always multiplies signed-by-signed.
5.2 Enhanced Dual Data Pointers
The AT89LP3240/6440 provides two 16-bit data pointers: DPTR0 formed by the register pair
DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H
and 85H). The data pointers are used by several instructions to access the program or data
memories. The Data Pointer Configuration Register (DPCF) controls operation of the dual data
pointers (Table 5-5 on page 28). The DPS bit in DPCF selects which data pointer is currently ref-
erenced by instructions including the DPTR operand. Each data pointer may be accessed at its
respective SFR addresses regardless of the DPS value. The AT89LP3240/6440 provides two
methods for fast context switching of the data pointers:
• Bit 2 of DPCF is hard-wired as a logic 0. The DPS bit may be toggled (to switch data pointers)
simply by incrementing the DPCF register, without altering other bits in the register
unintentionally. This is the preferred method when only a single data pointer will be used at
one time.
EX: INC DPCF ; Toggle DPS
M23 – 16 15 – 8 7 – 031 – 2439 – 32
Byte 4 Byte 3Byte 2 Byte 1 Byte 0
MACH MACL
MACH MACL
MACH MACL
MACH MACL
MRW1-0 = 00B
MRW1-0 = 01B
MRW1-0 = 10B
MRW1-0 = 11B
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•In some cases, both data pointers must be used simultaneously. To prevent frequent toggling
of DPS, the AT89LP3240/6440 supports a prefix notation for selecting the opposite data
pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when
prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data
pointer. Some assemblers may support this operation by using the /DPTR operand. For
example, the following code performs a block copy within EDATA:
MOV DPCF, #00H ; DPS = 0
MOV DPTR, #SRC ; load source address to dptr0
MOV /DPTR, #DST ; load destination address to dptr1
MOV R7, #BLKSIZE ; number of bytes to copy
COPY: MOVX A, @DPTR ; read source (dptr0)
INC DPTR ; next src (dptr0+1)
MOVX @/DPTR, A ; write destination (dptr1)
INC /DPTR ; next dst (dptr1+1)
DJNZ R7, COPY
For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:
EX: DB 0A5H
INC DPTR ; equivalent to INC /DPTR
Table 5-1. DSPR – Digital Signal Processing Configuration Register
DSPR = E2H Reset Value = 0000 0000B
Not Bit Addressable
MRW1 MRW0 SMLB SMLA CBE1 CBE0 MVCD DPRB
Bit76543210
Symbol Function
MRW1-0 M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and
MACL (E4H) as shown in Figure 5-5. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest
order portion of the fractional result is discarded.
SMLB Signed Multiply Operand B. When SMLB = 0, the MUL AB instruction treats the contents of B as an unsigned value.
When SMLB = 1, the MUL AB instruction interprets the contents of B as a signed two’s complement value. SMLB does
not affect the MAC operation.
SMLA Signed Multiply Operand A. When SMLA = 0, the MUL AB instruction treats the contents of ACC as an unsigned value.
When SMLA = 1, the MUL AB instruction interprets the contents of ACC as a signed two’s complement value. SMLA
does not affect the MAC operation.
CBE1 DPTR1 Circular Buffer Enable. Set CBE1 = 1 to configure DPTR1 for circular addressing over the two circular buffer
address ranges. Clear CBE1 for normal DPTR operation.
CBE0 DPTR0 Circular Buffer Enable. Set CBE0 = 1 to configure DPTR0 for circular addressing over the two circular buffer
address ranges. Clear CBE0 for normal DPTR operation.
MVCD
MOVC Index Disable. When MVCD = 0, the MOVC A, @A+DPTR instruction functions normally with indexed
addressing. Setting MVCD = 1 disables the indexed addressing mode such that MOVC A, @A+DPTR functions as
MOVC A, @DPTR.
DPRB
DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1.
When DPRB = 0, ACC is the source/destination. When DPRB = 1, B is the source/destination. DPRB does not change
the index register for MOVC instructions.
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AT89LP3240/6440
A summary of data pointer instructions with fast context switching is listed inTable 5-2.
5.2.1 Data Pointer Update
The Dual Data Pointers on the AT89LP3240/6440 include two features that control how the data
pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in DPCF, configure the
INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as
shown in Table 5-3.
The data pointer update bits, DPU1 and DPU0, allow MOVX @DPTR and MOVC @DPTR
instructions to update the selected data pointer automatically in a post-increment or post-decre-
ment fashion. The direction of update depends on the DPD1 and DPD0 bits as shown in Table
5-4.
Table 5-2. Data Pointer Instructions
Instruction
Operation
DPS = 0 DPS = 1
JMP @A+DPTR JMP @A+DPTR0 JMP @A+DPTR1
MOV DPTR, #data16 MOV DPTR0, #data16 MOV DPTR1, #data16
MOV /DPTR, #data16 MOV DPTR1, #data16 MOV DPTR0, #data16
INC DPTR INC DPTR0 INC DPTR1
INC /DPTR INC DPTR1 INC DPTR0
MOVC A,@A+DPTR MOVC A,@A+DPTR0 MOVC A,@A+DPTR1
MOVC A,@A+/DPTR MOVC A,@A+DPTR1 MOVC A,@A+DPTR0
MOVX A,@DPTR MOVX A,@DPTR0 MOVX A,@DPTR1
MOVX A,@/DPTR MOVX A,@DPTR1 MOVX A,@DPTR0
MOVX @DPTR, A MOVX @DPTR0, A MOVX @DPTR1, A
MOVX @/DPTR, A MOVX @DPTR1, A MOVX @DPTR0, A
Table 5-3. Data Pointer Decrement Behavior
DPD1 DPD0
Equivalent Operation for INC DPTR and INC /DPTR
DPS = 0 DPS = 1
INC DPTR INC /DPTR INC DPTR INC /DPTR
0 0 INC DPTR0 INC DPTR1 INC DPTR1 INC DPTR0
0 1 DEC DPTR0 INC DPTR1 INC DPTR1 DEC DPTR0
1 0 INC DPTR0 DEC DPTR1 DEC DPTR1 INC DPTR0
1 1 DEC DPTR0 DEC DPTR1 DEC DPTR1 DEC DPTR0
Table 5-4. Data Pointer Auto-Update
DPD1 DPD0
Update Operation for MOVX and MOVC (DPU1 = 1 & DPU0 = 1)
DPS = 0 DPS = 1
DPTR /DPTR DPTR /DPTR
0 0 DPTR0++ DPTR1++ DPTR1++ DPTR0++
0 1 DPTR0-- DPTR1++ DPTR1++ DPTR0--
1 0 DPTR0++ DPTR1-- DPTR1-- DPTR0++
1 1 DPTR0-- DPTR1-- DPTR1-- DPTR0--
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5.2.2 Data Pointer Operating Modes
The Dual Data Pointers on the AT89LP3240/6440 include three additional operating modes that
affect data pointer based instructions. These modes are controlled by bits in DSPR.
5.2.2.1 DPTR Redirect
The Data Pointer Redirect to B bit, DPRB (DSPR.0), allows MOVX and MOVC instructions to
use the B register as the data source/destination when the instruction references DPTR1 as
shown in Table 5-6 and Table 5-7. DPRB can improve the efficiency of routines that must fetch
multiple operands from different RAM locations.
Table 5-5. DPCF – Data Pointer Configuration Register
DPCF = A2H Reset Value = 0000 00X0B
Not Bit Addressable
DPU1 DPU0 DPD1 DPD0 SIGEN 0 – DPS
Bit76543210
Symbol Function
DPU1 Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update
DPTR1 based on DPD1. If DPD1 = 0 the operation is post-increment and if DPD1 = 1 the operation is post-decrement.
When DPU1 = 0, DPTR1 is not updated.
DPU0 Data Pointer 0 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR0 will also update
DPTR0 based on DPD0. If DPD0 = 0 the operation is post-increment and if DPD0 = 1 the operation is post-decrement.
When DPU0 = 0, DPTR0 is not updated.
DPD1 Data Pointer 1 Decrement. When set, INC DPTR instructions targeted to DPTR1 will decrement DPTR1. When cleared,
INC DPTR instructions will increment DPTR1. DPD1 also determines the direction of auto-update for DPTR1 when
DPU1 = 1.
DPD0 Data Pointer 0 Decrement. When set, INC DPTR instructions targeted to DPTR0 will decrement DPTR0. When cleared,
INC DPTR instructions will increment DPTR0. DPD0 also determines the direction of auto-update for DPTR0 when
DPU0 = 1.
SIGEN Signature Enable. When SIGEN = 1 all MOVC @DPTR instructions and all IAP accesses will target the signature array
memory. When SIGEN = 0, all MOVC and IAP accesses target CODE memory.
DPSData Pointer Select. DPS selects the active data pointer for instructions that reference DPTR. When DPS = 0, DPTR will
target DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0.
Table 5-6. MOVX @DPTR Operating Modes
DPRB DPS
Equivalent Operation for MOVX
MOVX A, @DPTR MOVX @DPTR, A
DPTR /DPTR DPTR /DPTR
00 MOVX
A, @DPTR0
MOVX
A, @DPTR1
MOVX
@DPTR0, A
MOVX
@DPTR1, A
01 MOVX
A, @DPTR1
MOVX
A, @DPTR0
MOVX
@DPTR1, A
MOVX
@DPTR0, A
10 MOVX
A, @DPTR0
MOVX
B, @DPTR1
MOVX
@DPTR0, A
MOVX
@DPTR1, B
11 MOVX
B, @DPTR1
MOVX
A, @DPTR0
MOVX
@DPTR1, B
MOVX
@DPTR0, A
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5.2.2.2 Index Disable
The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the
MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as
MOVC A, @DPTR with no indexing as shown in Table 5-7. MVCD can improve the efficiency of
routines that must fetch multiple operands from program memory. DPRB can change the MOVC
destination register from ACC to B, but has no effect on the MOVC index register.
5.2.2.3 Circular Buffers
The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in
circular buffer mode. The AT89LP3240/6440 maps circular buffers into two identically sized
regions of EDATA/XDATA. These buffers can speed up convolution computations such as FIR
and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) register
for up to 256 entries. Buffer A is mapped from 0000H to FIRD and Buffer B is mapped from
0100H to 100H+FIRD as shown in Figure 5-6. Both data pointers may operate in either buffer.
When circular buffer mode is enabled, updates to a data pointer referencing the buffer region will
follow circular addressing rules. If the data pointer is equal to FIRD or 100H+FIRD any incre-
ment will cause it to overflow to 0000H or 0100H respectively. If the data pointer is equal to
0000H or 0100H any decrement will cause it to underflow to FIRD or 100H+FIRD respectively.
In this mode, updates can be either an explicit INC DPTR or an automatic update using DPUn
where the DPDn bits control the direction. The data pointer will increment or decrement normally
at any other addresses. Therefore, when circular addressing is in use, the data pointers can still
operate as regular pointers in the FIRD+1 to 00FFH and greater than 100H+FIRD ranges.
Figure 5-6. Circular Buffer Mode
Table 5-7. MOVC @DPTR Operating Modes
MVCD DPRB
Equivalent Operation for MOVC A, @A+DPTR
DPS = 0 DPS = 1
DPTR /DPTR DPTR /DPTR
00 MOVC
A, @A+DPTR0
MOVC
A, @A+DPTR1
MOVC
A, @A+DPTR1
MOVC
A, @A+DPTR0
01 MOVC
A, @A+DPTR0
MOVC
B, @A+DPTR1
MOVC
B, @A+DPTR1
MOVC
A, @A+DPTR0
10 MOVC
A, @DPTR0
MOVC
A, @DPTR1
MOVC
A, @DPTR1
MOVC
A, @DPTR0
11 MOVC
A, @DPTR0
MOVC
B, @DPTR1
MOVC
B, @DPTR1
MOVC
A, @DPTR0
0000h
DPTR
0100h
FIRD
100h + FIRD
DPTR
DPDn = 0
DPDn = 1
DPDn = 0
DPDn = 1
A
B
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5.3 Instruction Set Extensions
Table 5-8 lists the additions to the 8051 instruction set that are supported by the
AT89LP3240/6440. For more information on the instruction set see Section 22. “Instruction Set
Summary” on page 143. For detailed descriptions of the extended instructions see Section 22.1
“Instruction Set Extensions” on page 147.
• The /DPTR instructions provide support for the dual data pointer features described above
(See Section 5.2).
•The ASR M, LSL M, CLR M and MAC AB instructions are part of the Multiply-Accumulate
Unit (See Section 5.1).
•The JMP @A+PC instruction supports localized jump tables without using a data pointer.
•The CJNE A, @R
i, rel instructions allow compares of array values with non-constant values.
• The BREAK instruction is used by the On-Chip Debug system. See Section 24. on page 155.
Table 5-8. AT89LP3240/6440 Extended Instructions
Opcode Mnemonic Description Bytes Cycles
A5 00 BREAK Software breakpoint 2 2
A5 03 ASR M Arithmetic shift right of M register 2 2
A5 23 LSL M Logical shift left of M register 2 2
A5 73 JMP @A+PC Indirect jump relative to PC 2 3
A5 90 MOV /DPTR, #data16 Move 16-bit constant to alternate data
pointer 44
A5 93 MOVC A, @A+/DPTR Move code location to ACC relative to
alternate data pointer 24
A5 A3 INC /DPTR Increment alternate data pointer 2 3
A5 A4 MAC AB Multiply and accumulate 2 9
A5 B6 CJNE A, @R0, rel Compare ACC to indirect RAM and
jump if not equal34
A5 B7 CJNE A, @R1, rel Compare ACC to indirect RAM and
jump if not equal34
A5 E0 MOVX A, @/DPTR Move external to ACC; 16-bit address
in alternate data pointer 23/5
A5 E4 CLR M Clear M register 2 2
A5 F0 MOVX @/DPTR, A Move ACC to external; 16-bit address
in alternate data pointer 23/5
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6. System Clock
The system clock is generated directly from one of three selectable clock sources. The three
sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The
on-chip crystal oscillator may also be configured for low or high speed operation. The clock
source is selected by the Clock Source User Fuses as shown in Table 6-1. See “User Configura-
tion Fuses” on page 164. By default, no internal clock division is used to generate the CPU clock
from the system clock. However, the system clock divider may be used to prescale the system
clock. The choice of clock source also affects the start-up time after a POR, BOD or Power-
down event (See “Reset” on page 33 or “Power-down Mode” on page 37)
6.1 Crystal Oscillator
When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and
XTAL2 for connection to an external quartz crystal or ceramic resonator. The oscillator may
operate in either high-speed or low-speed mode. Low-speed mode is intended for 32.768 kHz
watch crystals and consumes less power than high-speed mode. The configuration as shown in
Figure 6-1 applies for both high and low speed oscillators. Note that the internal structure of the
device adds about 10 pF of capacitance to both XTAL1 and XTAL2, so that in some cases less
external capacitance may be required. The total capacitance on XTAL1 or XTAL2, including the
external load capacitor plus internal device load, board trace and crystal loadings, should not
exceed 20 pF. An optional resistor R1 can be connected to XTAL1 in place of C1 for improved
startup performance with higher speed crystals. When using the crystal oscillator, P4.0 and P4.1
will have their inputs and outputs disabled. Also, XTAL2 in crystal oscillator mode should not be
used to directly drive a board-level clock without a buffer.
Figure 6-1. Crystal Oscillator Connections
Note: 1. C1/C2 = 5–15 pF for Crystals
= 5–15 pF for Ceramic Resonators
R1 = 4–5 MΩ
Table 6-1. Clock Source Settings
Clock Source
Fuse 1
Clock Source
Fuse 0 Selected Clock Source
0 0 High Speed Crystal Oscillator (f > 500 kHz)
01Low Speed Crystal Oscillator (f ≤ 100 kHz)
10External Clock on XTAL1
1 1 Internal 8 MHz RC Oscillator
~10 pF
~10 pF
C2
R1
C1
Optional
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6.2 External Clock Source
The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly
by an external clock source as shown in Figure 6-2. XTAL2 may be left unconnected, used as
general purpose I/O P4.1, or configured to output a divided version of the system clock.
Figure 6-2. External Clock Drive Configuration
6.3 Internal RC Oscillator
The AT89LP3240/6440 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±2.5%. When
enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1 respectively.
XTAL2 may also be configured to output a divided version of the system clock. The frequency of
the oscillator may be adjusted within limits by changing the RC Calibration Byte stored at byte
128 of the User Signature Array. This location may be updated using the IAP interface (location
0180H in SIG space) or by an external device programmer (UROW location 0080H). See Sec-
tion 25.8 “User Signature and Analog Configuration” on page 165. A copy of the factory
calibration byte is stored at byte 8 of the Atmel Signature Array (0008H in SIG space).
6.4 System Clock Out
When the AT89LP3240/6440 is configured to use either an external clock or the internal RC
oscillator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is
enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the
internal oscillator will result in a 4.0 MHz (±2.5%) clock output on P4.1. P4.1 must be configured
as an output in order to use the clock out feature.
6.5 System Clock Divider
The CDV2-0 bits in CLKREG allow the system clock to be divided down from the selected clock
source by powers of 2. The clock divider provides users with a greater frequency range when
using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using
the IRC, CDV2-0 should be set to 011B for divide-by-8 operation. The divider can also be used to
reduce power consumption by decreasing the operational frequency during non-critical periods.
The resulting system frequency is given by the following equation:
where fOSC is the frequency of the selected clock source. The clock divider will prescale the clock
for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-
ing normal execution. Changes to CDV are synchronized such that the system clock will not
XTAL2 (P4.1)
XTAL1 (P4.0)
GND
NC, GPIO, or
CLKOUT
EXTERNAL
OSCILLATOR
SIGNAL
fSYS
fOSC
2CDV
-------------=
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pass through intermediate frequencies. When CDV is updated, the new frequency will take
affect within a maximum period of 128 x tOSC.
7. Reset
During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the
program starts execution from the Reset Vector, 0000H. The AT89LP3240/6440 has five
sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software
reset.
7.1 Power-on Reset
A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level VPOR
is nominally 1.4V. The POR is activated whenever VDD is below the detection level. The POR cir-
cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices
without a brown-out detector. The POR circuit ensures that the device is reset from power-on. A
power-on sequence is shown in Figure 7-1 on page 34. When VDD reaches the Power-on Reset
threshold voltage VPOR, an initialization sequence lasting tPOR is started. When the initialization
sequence completes, the start-up timer determines how long the device is kept in POR after VDD
rise. The POR signal is activated again, without any delay, when VDD falls below the POR
threshold level. A Power-on Reset (i.e. a cold reset) will set the POF flag in PCON. The internally
Table 6-2. CLKREG – Clock Control Register
CLKREG = 8FH Reset Value = 0000 0000B
Not Bit Addressable
TPS3TPS2TPS1TPS0 CDV2 CDV1 CDV0 COE
Bit76543210
Symbol Function
TPS[3-0] Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer. The
prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value
stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycle (TPS =
0000B). To configure the timers to count at a standard 8051 rate of once every 12 clock cycles, TPS should be set to
1011B.
CDV[2-0]
System Clock Division. Determines the frequency of the system clock relative to the oscillator clock source.
CDIV2 CDIV1 CDIV0 System Clock Frequency
000f
OSC/1
001f
OSC/2
010f
OSC/4
011f
OSC/8
100f
OSC/16
101f
OSC/32
110f
OSC/64
111f
OSC/128
COE Clock Out Enable. Set COE to output the system clock divided by 2 on XTAL2 (P4.1). The internal RC oscillator or
external clock source must be selected in order to use this feature and P4.1 must be configured as an output.
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generated reset can be extended beyond the power-on period by holding the RST pin low longer
than the time-out.
Figure 7-1. Power-on Reset Sequence (BOD Disabled)
If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until
after VDD reaches the BOD threshold voltage VBOD as shown in Figure 7-2. However, if this event
occurs prior to the end of the initialization sequence, the timer must first wait for that sequence to
complete before counting.
Figure 7-2. Power-on Reset Sequence (BOD Enabled)
Note: tPOR is approximately 143 µs ± 5%.
The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on
the clock source (Table 7-1). The Start-Up Time fuses also control the length of the start-up time
after a Brown-out Reset or when waking up from Power-down during internally timed mode. The
start-up delay should be selected to provide enough settling time for VDD and the selected clock
source. The device operating environment (supply voltage, frequency, temperature, etc.) must
VDD
RST
Time-out
tPOR + tSUT
tRHD
VPOR
Internal
Reset
RST
Internal
Reset
VIH
(RST Tied to VCC)
(RST Controlled Externally)
VPOR
VDD
RST
Time-outtPOR
tRHD
VPOR
Internal
Reset
RST
Internal
Reset
VIH
tSUT
VBOD
(RST Tied to VCC)
(RST Controlled Externally)
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meet the minimum system requirements before the device exits reset and starts normal opera-
tion. The RST pin may be held low externally until these conditions are met.
7.2 Brown-out Reset
The AT89LP3240/6440 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VDD
level during operation by comparing it to a fixed trigger level. The trigger level VBOD for the BOD
is nominally 2.0V. The purpose of the BOD is to ensure that if VDD fails or dips while executing at
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. A BOD sequence is shown in Figure 7-3. When VDD decreases to a value below the
trigger level VBOD, the internal reset is immediately activated. When VDD increases above the
trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal reset after
the specified time-out period has expired (Table 7-1). The Brown-out Detector must be enabled
by setting the BOD Enable Fuse. (See “User Configuration Fuses” on page 164.)
Figure 7-3. Brown-out Detector Reset
The AT89LP3240/6440 allows for a wide VDD operating range. The on-chip BOD may not be suf-
ficient to prevent incorrect execution if VBOD is lower than the minimum required VDD range, such
as when a 3.6V supply is coupled with high frequency operation. In such cases an external
Brown-out Reset circuit connected to the RST pin may be required.
7.3 External Reset
The P4.2/RST pin can function as either an active-LOW reset input or as a digital general-
purpose I/O, P4.2. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input
function on P4.2. (See “User Configuration Fuses” on page 164.) When cleared, P4.2 may be
used as an input or output pin. When configured as a reset input, the pin must be held low for at
least two clock cycles to trigger the internal reset. The RST pin includes an on-chip pull-up resis-
tor tied to VDD. The pull-up is disabled when the pin is configured as P4.2.
Table 7-1. Start-up Timer Settings
SUT Fuse 1 SUT Fuse 0 Clock Source tSUT (± 5%) µs
00
Internal RC/External Clock 16
Crystal Oscillator 1024
01
Internal RC/External Clock 512
Crystal Oscillator 2048
10
Internal RC/External Clock 1024
Crystal Oscillator 4096
11
Internal RC/External Clock 4096
Crystal Oscillator 16384
VDD
Time-out
VPOR
Internal
Reset
tSUT
VBOD
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Note: During a power-up sequence, the fuse selection is always overridden and therefore the pin will
always function as a reset input. An external circuit connected to this pin should not hold this
pin LOW during a power-on sequence if the pin will be configured as a general I/O, as this
will keep the device in reset until the pin transitions high. After the power-up delay, this input
will function either as an external reset input or as a digital input as defined by the fuse bit. Only a
power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources
of reset will not override the reset fuse bit. P4.2/RST also serves as the In-System Programming
(ISP) enable. ISP is enabled when the external reset pin is held low. When the reset pin is dis-
abled by the fuse, ISP may only be entered by pulling P4.2 low during power-up.
7.4 Watchdog Reset
When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.
Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the
watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times
out. See “Programmable Watchdog Timer” on page 141. for details on the operation of the
Watchdog.
7.5 Software Reset
The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset
sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-
CON. See “Software Reset” on page 142 for more information on software reset. Writing any
sequences other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and
set both WDTOVF and SWRST to flag an error.
8. Power Saving Modes
The AT89LP3240/6440 supports two different power-reducing modes: Idle and Power-down.
These modes are accessed through the PCON register. Additional steps may be required to
achieve the lowest possible power consumption while using these modes.
8.1 Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The timers, UART, SPI, TWI, comparators, ADC, GPI and
CCA peripherals continue to function during Idle. If these functions are not needed during idle,
they should be explicitly disabled by clearing the appropriate control bits in their respective
SFRs. The watchdog may be selectively enabled or disabled during Idle by setting/clearing the
WDIDLE bit. The Brown-out Detector, if enabled, is always active during Idle. Any enabled inter-
rupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the
interrupt will immediately be serviced, and following RETI the next instruction to be executed will
be the one following the instruction that put the device into Idle.
The power consumption during Idle mode can be further reduced by prescaling down the system
clock using the System Clock Divider (Section 6.5 on page 32). Be aware that the clock divider
will affect all peripheral functions except the ADC. Therefore baud rates or PWM periods may
need to be adjusted to maintain their rate with the new clock frequency.
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.
8.2 Power-down Mode
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once VDD has been
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
8.2.1 Interrupt Recovery from Power-down
Three external interrupt sources may be configured to terminate Power-down mode: external
interrupts INT0 (P3.2) and INT1 (P3.3); and the general-purpose interrupts (GPI). To wake up by
external interrupt INT0 or INT1, that interrupt must be enabled by setting EX0 or EX1 in IE and
must be configured for level-sensitive operation by clearing IT0 or IT1. Any General-purpose
interrupt on Port 1 (GPI7-0) can also wake up the device. The GPI pin must be enabled in GPIEN
and configured for level-sensitive detection, and EGP in IE2 must be set in order to terminate
Power-down.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 8-1.
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 7-1 on page 35).
The interrupt pin need not remain low for the entire time-out period.
Table 8-1. PCON – Power Control Register
PCON = 87H Reset Value = 000X 0000B
Not Bit Addressable
SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL
Bit76543210
Symbol Function
SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
PWDEX Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
POF Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
GF1, GF0 General-purpose Flags
PD Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when
waking up from power-down.
IDL Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when
waking up from idle
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Figure 8-1. Interrupt Recovery from Power-down (PWDEX = 0)
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 8-
2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 8-2. Interrupt Recovery from Power-down (PWDEX = 1)
8.2.2 Reset Recovery from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in Figure 8-3. The internal clock will not be allowed to
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See Table 7-1 on page 35). If RST returns high before the time-out, a two
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought high.
8.3 Reducing Power Consumption
Several possibilities need consideration when trying to reduce the power consumption in an
AT89LP-based system. Generally, Idle or Power-down mode should be used as much as possi-
ble. All unneeded functions should be disabled. In particular, the following modules may need
special consideration when trying to achieve the lowest possible power consumption.
8.3.1 Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BOD Enable Fuse, it will be enabled in all modes
except Power-down. See Section 25.7 “User Configuration Fuses” on page 164.
PWD
INT1
XTAL1
tSUT
Internal
Clock
PWD
INT1
XTAL1
Internal
Clock
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Figure 8-3. Reset Recovery from Power-down
8.3.2 Analog Comparators
The comparators will operate during Idle mode if enabled. To save power, the comparators
should be disabled before entering Idle mode if possible. When the comparators are turned off
and on again, some settling time is required for the analog circuits to stabilize. If the comparators
are enabled, they will consume the least power when using an external reference, RFA1-0 =00B
and RFB1-0 =00B.
8.3.3 Analog-to-Digital Converter
The DADC will operate during Idle mode if enabled. To save power, the DADC should be dis-
abled before entering Idle mode if possible. When the DADC is turned off and on again, some
settling time is required for the analog circuits to stabilize. If the DADC is enabled, it will con-
sume the least power when configured to use the system clock instead of the internal RC
oscillator (unless the IRC is the system clock source) and when the internal reference is disabled
(IREF = 0). The DADC must always be disabled before entering power-down.
9. Interrupts
The AT89LP3240/6440 provides 12 interrupt sources: two external interrupts, three timer inter-
rupts, a serial port interrupt, an analog comparator interrupt, a general-purpose interrupt, a
compare/capture interrupt, a two-wire interrupt, an ADC interrupt and an SPI interrupt. These
interrupts and the system reset each have a separate program vector at the start of the program
memory space. Each interrupt source can be individually enabled or disabled by setting or clear-
ing a bit in the interrupt enable registers IE and IE2. The IE register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the interrupt priority registers IP, IPH, IP2 and IP2H. IP and IP2 hold the low order
priority bits and IPH and IP2H hold the high priority bits for each interrupt. An interrupt service
routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of
the same or lower priority. The highest priority interrupt cannot be interrupted by any other inter-
rupt source. If two requests of different priority levels are pending at the end of an instruction, the
request of higher priority level is serviced. If requests of the same priority level are pending at
the end of an instruction, an internal polling sequence determines which request is serviced. The
polling sequence is based on the vector address; an interrupt with a lower vector address has
higher priority than an interrupt with a higher vector address. Note that the polling sequence is
only used to resolve pending requests of the same priority level.
PWD
RST
XTAL1
tSUT
Internal
Clock
Internal
Reset
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The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all inter-
rupts of a given priority level, allowing software implementations of more complex interrupt
priority handling schemes such as level-based round-robin scheduling.
The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,
depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-
rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears
the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-
rupt was level activated, then the external requesting source (rather than the on-chip hardware)
controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou-
tine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt
and that bit must be cleared by software.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these
flags is cleared by hardware when the CPU vectors to the service routine. The service routine
normally must determine whether RI or TI generated the interrupt and that bit must be cleared by
software.
The Serial Peripheral Interface Interrupt is generated by the logic OR of SPIF, MODF and TXE
in SPSR. None of these flags is cleared by hardware when the CPU vectors to the service rou-
tine. The service routine normally must determine which bit generated the interrupt and that bit
must be cleared by software.
A logic OR of all eight flags in the GPIF register causes the General-purpose Interrupt. None of
these flags is cleared by hardware when the service routine is vectored to. The service routine
must determine which bit generated the interrupt and that bit must be cleared in software. If the
interrupt was level activated, then the external requesting source must de-assert the interrupt
before the flag may be cleared by software.
The CFA and CFB bits in ACSRA and ACSRB respectively generate the Comparator Interrupt.
The service routine must normally determine whether CFA or CFB generated the interrupt, and
the bit must be cleared by software. The DAC/ADC Conversion Interrupt is generated by ADIF in
DADC. On-chip hardware clears the ADIF flag when vectoring to the service routine.
A logic OR of the four least significant bits in the T2CCF register causes the Compare/Capture
Array Interrupt. None of these flags is cleared by hardware when the service routine is vectored
to. The service routine must determine which bit generated the interrupt and that bit must be
cleared in software.
The Two-Wire Interface Interrupt is generated by TWIF in TWCR. The flag is not cleared by
hardware when the CPU vectors to the service routine. The service routine normally must deter-
mine the status in TWSR and respond accordingly before the bit is cleared by software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software.
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9.1 Interrupt Response Time
The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls
the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine as the next instruction, provided that the interrupt is not blocked
by any of the following conditions: an interrupt of equal or higher priority level is already in prog-
ress; the instruction in progress is RETI or any write to the IE, IP, IPH, IE2, IP2 or IP2H registers;
the CPU is currently forced into idle by an IAP or FDATA write. Each of these conditions will
block the generation of the LCALL to the interrupt service routine. The second condition ensures
that if the instruction in progress is RETI or any access to IE, IP, IPH, IE2, IP2 or IP2H, then at
least one more instruction will be executed before any interrupt is vectored to. The polling cycle
is repeated at the last cycle of each instruction, and the values polled are the values that were
present at the previous clock cycle. If an active interrupt flag is not being serviced because of
one of the above conditions and is no longer active when the blocking condition is removed, the
denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once
active but not serviced is not remembered. Every polling cycle is new.
If a request is active and conditions are met for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction executed. The call itself takes
four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an
interrupt request and the beginning of execution of the first instruction of the service routine. A
longer response time results if the request is blocked by one of the previously listed conditions. If
an interrupt of equal or higher priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If the instruction in progress is not
in its final clock cycle, the additional wait time cannot be more than 8 cycles, since the longest
instruction is 9 cycles long. If the instruction in progress is RETI with XSTK, the additional wait
time cannot be more than 14 cycles (a maximum of 5 more cycles to complete the instruction in
progress, plus a maximum of 9 cycles to complete the next instruction). Thus, in a single-inter-
Table 9-1. Interrupt Vector Addresses
Interrupt Source Vector Address
System Reset RST or POR or BOD 0000H
External Interrupt 0 IE0 0003H
Timer 0 Overflow TF0 000BH
External Interrupt 1 IE1 0013H
Timer 1 Overflow TF1 001BH
Serial Port Interrupt RI or TI 0023H
Timer 2 Interrupt TF2 or EXF2 002BH
Analog Comparator Interrupt CFA or CFB 0033H
General-purpose Interrupt GPIF7-0 003BH
Compare/Capture Array Interrupt T2CCF3-0 0043H
Serial Peripheral Interface Interrupt SPIF or MODF or TXE 004BH
ADC Interrupt ADIF 0053H
Two-Wire Interface Interrupt TWIF 005BH
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AT89LP3240/6440
rupt system, the response time is always more than 5 clock cycles and less than 21 clock cycles.
See Figure 9-1 and Figure 9-2.
Figure 9-1. Minimum Interrupt Response Time
Figure 9-2. Maximum Interrupt Response Time
.
Clock Cycles
INT0
IE0
15
Instruction LCALL 1st ISR Instr.Cur. Instr.
Ack.
Clock Cycles
INT0
IE0
1 21
Instruction RETI MAC AB LCALL 1st ISR Instr.
Ack.
615
Table 9-2. IE – Interrupt Enable Register
IE = A8HReset Value = 0000 0000B
Bit Addressable
EA EC ET2 ESET1 EX1 ET0 EX0
Bit76543210
Symbol Function
EA Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled
by setting /clearing its own enable bit.
EC Comparator Interrupt Enable
ET2 Timer 2 Interrupt Enable
ESSerial Port Interrupt Enable
ET1 Timer 1 Interrupt Enable
EX1 External Interrupt 1 Enable
ET0 Timer 0 Interrupt Enable
EX0 External Interrupt 0 Enable
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Table 9-3. IE2 – Interrupt Enable 2 Register
IE = B4H Reset Value = xxxx x000B
Not Bit Addressable
– – – ETWI EADC ESPI ECC EGP
Bit76543210
Symbol Function
ETWI Two-Wire Interface Interrupt Enable
EADC ADC Interrupt Enable
ESPI Serial Peripheral Interface Interrupt Enable
ECC Compare/Capture Array Interrupt Enable
EGP General-purpose Interrupt Enable
Table 9-4. IP – Interrupt Priority Register
IP = B8HReset Value = 0000 0000B
Bit Addressable
IP0D PC PT2 PSPT1 PX1 PT0 PX0
Bit76543210
Symbol Function
IP0D Interrupt Priority 0 Disable. Set IP0D to 1 to disable all interrupts with priority level zero. Clear to 0 to enable all interrupts
with priority level zero when EA = 1.
PC Comparator Interrupt Priority Low
PT2 Timer 2 Interrupt Priority Low
PSSerial Port Interrupt Priority Low
PT1 Timer 1 Interrupt Priority Low
PX1 External Interrupt 1 Priority Low
PT0 Timer 0 Interrupt Priority Low
PX0 External Interrupt 0 Priority Low
Table 9-5. IP2 – Interrupt Priority 2 Register
IP = B5H Reset Value = 0xxx x000B
No Bit Addressable
IP2D – – PTWI PADC PSPPCCPGP
Bit76543210
Symbol Function
IP2D Interrupt Priority 2 Disable. Set IP2D to 1 to disable all interrupts with priority level two. Clear to 0 to enable all interrupts
with priority level two when EA = 1.
PTWI Two-wire Interface Interrupt Priority Low
PADC ADC Interrupt Priority Low
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PSPSerial Peripheral Interface Interrupt Priority Low
PCC Compare/Capture Array Interrupt Priority Low
PGP General-purpose Interrupt 0 Priority Low
Symbol Function
Table 9-6. IPH – Interrupt Priority High Register
IPH = B7H Reset Value = 0000 0000B
Not Bit Addressable
IP1D PCH PT2H PSH PT1H PX1H PT0H PX0H
Bit76543210
Symbol Function
IP1D Interrupt Priority 1 Disable. Set IP1D to 1 to disable all interrupts with priority level one. Clear to 0 to enable all interrupts
with priority level one when EA = 1.
PCH Comparator Interrupt Priority High
PT2H Timer 2 Interrupt Priority High
PSHSerial Port Interrupt Priority High
PT1H Timer 1 Interrupt Priority High
PX1H External Interrupt 1 Priority High
PT0H Timer 0 Interrupt Priority High
PX0H External Interrupt 0 Priority High
Table 9-7. IP2H – Interrupt Priority 2 High Register
IPH = B6H Reset Value = 0xxx x000B
Not Bit Addressable
IP3D – – PTWH PADH PSPH PCCH PGPH
Bit76543210
Symbol Function
IP3D Interrupt Priority 3 Disable. Set IP3D to 1 to disable all interrupts with priority level three. Clear to 0 to enable all
interrupts with priority level three when EA = 1.
PTWH Two-Wire Interface Interrupt Priority High
PADH ADC Interrupt Priority High
PSPH Serial Peripheral Interface Interrupt Priority High
PCCH Compare/Capture Array Interrupt Priority High
PGPH General-purpose Interrupt 0 Priority High
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10. I/O Ports
The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of
I/O pins available depends on the clock and reset options as shown in Table 10-1.
10.1 Port Configuration
All port pins on the AT89LP3240/6440 may be configured to one of four modes: quasi-bidirec-
tional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port
modes may be assigned in software on a pin-by-pin basis as shown in Table 10-2 using the reg-
isters listed in Table 10-3. The Tristate-Port User Fuse determines the default state of the port
pins. When the fuse is enabled, all port pins default to input-only mode after reset. When the
fuse is disabled, all port pins, with the exception of the analog inputs, P0.7-0, P2.4, P2.5, P2.6
and P2.7, default to quasi-bidirectional mode after reset and are weakly pulled high. The analog
input pins always reset to input-only (tristate) mode. Each port pin also has a Schmitt-triggered
input for improved input noise rejection. During Power-down all the Schmitt-triggered inputs are
disabled with the exception of P3.2 (INT0), P3.3 (INT1), P4.2 (RST), P4.0 (XTAL1) and P4.1
(XTAL2) which may be used to wake up the device. Therefore, P3.2, P3.3, P4.2, P4.0 and P4.1
should not be left floating during Power-down. In addition any pin of Port 1 configured as a Gen-
eral-Purpose interrupt input will also remain active during Power-down to wake-up the device.
These interrupt pins should either be disabled before entering Power-down or they should not be
left floating.
.
.
Table 10-1. I/O Pin Configurations
Clock Source Reset Option Number of I/O Pins
External Crystal or
Resonator
External RST Pin 35
No external reset 36
External Clock External RST Pin 36
No external reset 37
Internal RC Oscillator External RST Pin 37
No external reset 38
Table 10-2. Configuration Modes for Port x, Bit y
PxM0.y PxM1.y Port Mode
00Quasi-bidirectional
01Push-pull Output
10Input Only (High Impedance)
1 1 Open-Drain Output
Table 10-3. Port Configuration Registers
Port Port Data Port Configuration
0P0 (80H) P0M0 (BAH), P0M1 (BBH)
1 P1 (90H) P1M0 (C2H), P1M1 (C3H)
2 P2 (A0H) P2M0 (C4H), P2M1 (C5H)
3 P3 (B0H) P3M0 (C6H), P3M1 (C7H)
4 P4 (C0H) P4M0 (BEH), P4M1 (BFH)
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10.1.1 Quasi-bidirectional Output
Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-
bidirectional port can be used both as an input and output without the need to reconfigure the
port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an
external device to pull the pin low. When the pin is driven low, it is driven strongly and able to
sink a large current. There are three pull-up transistors in the quasi-bidirectional output that
serve different purposes.
One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port latch for the
pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the pin
high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains
a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source
current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external
device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the
pin low under these conditions, the external device has to sink enough current to overpower the
weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-
high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a
logic “1”. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the
port pin high. The quasi-bidirectional port configuration is shown in Figure 10-1.
Figure 10-1. Quasi-bidirectional Output
10.1.2 Input-only Mode
The input only port configuration is shown in Figure 10-2. The output drivers are tristated. The
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P3.2, P3.3, P4.2, P4.0 and P4.1 is not disabled during Power-down (see Figure 10-3) and there-
fore these pins should not be left floating during Power-down when configured in this mode.
Figure 10-2. Input Only
1 Clock Delay
(D Flip-Flop)
Strong Ver y
WeakWeak
Port
Pin
V
CC V
CC V
CC
From Port
Register
Input
Data
PWD
Port
Pin
Input
Data
PWD
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Figure 10-3. Input Circuit for P3.2, P3.3, P4.0, P4.1 and P4.2
10.1.3 Open-drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in Figure 10-4. The input circuitry of P3.2, P3.3, P4.0, P4.1 and P4.2 is not
disabled during Power-down (see Figure 10-3) and therefore these pins should not be left float-
ing during Power-down when configured in this mode.
Figure 10-4. Open-Drain Output
10.1.4 Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
latch contains a logic “1”. The push-pull mode may be used when more source current is needed
from a port output. The push-pull port configuration is shown in Figure 10-5.
Figure 10-5. Push-pull Output
Port
Pin
Input
Data
Port
Pin
From Port
Register
Input
Data
PWD
Port
Pin
V
CC
From Port
Register
Input
Data
PWD
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10.2 Port Analog Functions
The AT89LP3240/6440 incorporates two analog comparators and an 8-channel analog-to-digital
converter. In order to give the best analog performance and minimize power consumption, pins
that are being used for analog functions must have both their digital outputs and digital inputs
disabled. Digital outputs are disabled by putting the port pins into the input-only mode as
described in “Port Configuration” on page 45. The analog input pins will always default to input-
only mode after reset regardless of the state of the Tristate-Port Fuse.
Digital inputs on P2.4, P2.5, P2.6 and P2.7 are disabled whenever an analog comparator is
enabled by setting the CENA or CENB bits in ACSRA and ACSRB and that pin is configured for
input-only mode. To use an analog input pin as a high-impedance digital input while a compara-
tor is enabled, that pin should be configured in open-drain mode and the corresponding port
register bit should be set to 1.
Digital inputs on Port 0 are disabled for each pin configured for input-only mode whenever the
ADC is enabled by setting the ADCE bit and clearing the DAC bit in DADC. To use any Port 0
input pin as a high-impedance digital input while the ADC is enabled, that pin should be config-
ured in open-drain mode and the corresponding port register bit should be set to 1. When DAC
mode is enabled, P2.2 and P2.3 are forced to input-only mode.
10.3 Port Read-Modify-Write
A read from a port will read either the state of the pins or the state of the port register depending
on which instruction is used. Simple read instructions will always access the port pins directly.
Read-modify-write instructions, which read a value, possibly modify it, and then write it back, will
always access the port register. This includes bit write instructions such as CLR or SETB as they
actually read the entire port, modify a single bit, then write the data back to the entire port. See
Table 10-4 for a complete list of Read-Modify-Write instruction which may access the ports.
Table 10-4. Port Read-Modify-Write Instructions
Mnemonic Instruction Example
ANL Logical AND ANL P1, A
ORL Logical OR ORL P1, A
XRL Logical EX-OR XRL P1, A
JBC Jump if bit set and clear bit JBC P3.0, LABEL
CPL Complement bit CPL P3.1
INC Increment INC P1
DEC Decrement DEC P3
DJNZ Decrement and jump if not zero DJNZ P3, LABEL
MOV PX.Y, C Move carry to bit Y of Port X MOV P1.0, C
CLR PX.Y Clear bit Y of Port X CLR P1.1
SETB PX.Y Set bit Y of Port X SETB P3.2
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10.4 Port Alternate Functions
Most general-purpose digital I/O pins of the AT89LP3240/6440 share functionality with the vari-
ous I/Os needed for the peripheral units. Table 10-6 lists the alternate functions of the port pins.
Alternate functions are connected to the pins in a logic AND fashion. In order to enable the
alternate function on a port pin, that pin must have a “1” in its corresponding port register bit,
otherwisethe input/output will always be “0”. However, alternate functions may be temporarily
forced to “0” by clearing the associated port bit, provided that the pin is not in input-only mode.
Furthermore, each pin must be configured for the correct input/output mode as required by its
peripheral before it may be used as such. Table 10-5 shows how to configure a generic pin for
use with an alternate function.
Table 10-5. Alternate Function Configurations for Pin y of Port x
PxM0.y PxM1.y Px.y I/O Mode
00 1bidirectional (internal pull-up)
01 1output
10Xinput
11 1bidirectional (external pull-up)
Table 10-6. Port Pin Alternate Functions
Port Pin
Configuration Bits Alternate
Function NotesPxM0.y PxM1.y
P0.0 P0M0.0 P0M1.0 AD0 Automatic configuration
ADC0 input-only
P0.1 P0M0.1 P0M1.1 AD1 Automatic configuration
ADC1 input-only
P0.2 P0M0.2 P0M1.2 AD2 Automatic configuration
ADC2 input-only
P0.3 P0M0.3 P0M1.3 AD3 Automatic configuration
ADC3 input-only
P0.4 P0M0.4 P0M1.4 AD4 Automatic configuration
ADC4 input-only
P0.5 P0M0.5 P0M1.5 AD5 Automatic configuration
ADC5 input-only
P0.6 P0M0.6 P0M1.6 AD6 Automatic configuration
ADC6 input-only
P0.7 P0M0.7 P0M1.7 AD7 Automatic configuration
ADC7 input-only
P1.0 P1M0.0 P1M1.0 T2
GPI0
P1.1 P1M0.1 P1M1.1 T2EX
GPI1
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P1.2 P1M0.2 P1M1.2 SDA open-drain
GPI2
P1.3 P1M0.3 P1M1.3 SCL open-drain
GPI3
P1.4 P1M0.4 P1M1.4 SS
GPI4
P1.5 P1M0.5 P1M1.5 MOSI
GPI5
P1.6 P1M0.6 P1M1.6 MISO
GPI6
P1.7 P1M0.7 P1M1.7 SCK
GPI7
P2.0 P2M0.0 P2M1.0 CCA
P2.1 P2M0.1 P2M1.1 CCB
P2.2 P2M0.2 P2M1.2 CCC
DA+ input-only
P2.3 P2M0.3 P2M1.3 CCD
DA- input-only
P2.4 P2M0.4 P2M1.4 AIN0 input-only
P2.5 P2M0.5 P2M1.5 AIN1 input-only
P2.6 P2M0.6 P2M1.6 AIN2 input-only
P2.7 P2M0.7 P2M1.7 AIN3 input-only
P3.0 P3M0.0 P3M1.0 RXD
P3.1 P3M0.1 P3M1.1 TXD
P3.2 P3M0.2 P3M1.2 INT0
P3.3 P3M0.3 P3M1.3 INT1
P3.4 P3M0.4 P3M1.4 T0
P3.5 P3M0.5 P3M1.5 T1
P3.6 P3M0.6 P3M1.6 WR
P3.7 P3M0.7 P3M1.7 RD
P4.2 P3M0.5 P3M1.5 RST RST must be disabled to use P4.2
P4.6 not configurable CMPA Pin is tied to comparator output
P4.7 not configurable CMPB Pin is tied to comparator output
Table 10-6. Port Pin Alternate Functions
Port Pin
Configuration Bits Alternate
Function NotesPxM0.y PxM1.y
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11. Enhanced Timer 0 and Timer 1 with PWM
The AT89LP3240/6440 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following
features:
• Two 16-bit timer/counters with 16-bit reload registers
• Two independent 8-bit precision PWM outputs with 8-bit prescalers
•UART or SPI baud rate generation using Timer 1
•Output pin toggle on timer overflow
•Split timer mode allows for three separate timers (2 8-bit, 1 16-bit)
•Gated modes allow timers to run/halt based on an external input
Timer 0 and Timer 1 have similar modes of operation. As timers, the timer registers increase
every clock cycle by default. Thus, the registers count clock cycles. Since a clock cycle consists
of one oscillator period, the count rate is equal to the oscillator frequency. The timer rate can be
prescaled by a value between 1 and 16 using the Timer Prescaler (see Table 6-2 on page 33).
Both Timers share the same prescaler.
As counters, the timer registers are incremented in response to a 1-to-0 transition at the corre-
sponding input pins, T0 or T1. The external input is sampled every clock cycle. When the
samples show a high in one cycle and a low in the next cycle, the count is incremented. The new
count value appears in the register during the cycle following the one in which the transition was
detected. Since 2 clock cycles are required to recognize a 1-to-0 transition, the maximum count
rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle of the input sig-
nal, but it should be held for at least one full clock cycle to ensure that a given level is sampled at
least once before it changes.
Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:
variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control
bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit
pairs (M1, M0) in TMOD select the operating modes.
Table 11-1. Timer 0/1 Register Summary
Name Address Purpose Bit-Addressable
TCON 88H Control Y
TMOD 89H Mode N
TL0 8AH Timer 0 low-byte N
TL1 8BH Timer 1 low-byte N
TH0 8CH Timer 0 high-byte N
TH1 8DH Timer 1 high-byte N
TCONB 91H Mode N
RL0 92H Timer 0 reload low-byte N
RL1 93H Timer 1 reload low-byte N
RH0 94H Timer 0 reload high-byte N
RH1 95H Timer 1 reload high-byte N
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11.1 Mode 0 – Variable Width Timer/Counter
Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from
1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.
By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.
Figure 11-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count
rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled
to the Timer when TR1 = 1 and either GATE1 = 0 or INT1 =1. Setting GATE1 = 1 allows the
Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a
control bit in the Special Function Register TCON. GATE1 is in TMOD. The 13-bit register con-
sists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate
and should be ignored. Setting the run flag (TR1) does not clear the registers.
Note: RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage
registers.
Figure 11-1. Timer/Counter 1 Mode 0: Variable Width Counter
Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0, GATE0 and
INT0 replace the corresponding Timer 1 signals in Figure 11-1. There are two different C/T bits,
one for Timer 1 (TMOD.6) and one for Timer 0 (TMOD.2).
11.2 Mode 1 – 16-bit Auto-Reload Timer/Counter
In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all
16 bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The
clock is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are
received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-
0000H transition, upon which the timer register is reloaded with the value from RH1/RL1 and the
overflow flag bit in TCON is set. See Figure 11-2. The reload registers default to 0000H, which
gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the
same for Timer/Counter 0.
Mode 0: Time-out Period 256 2PSC0 1+
×
Oscillator Frequency
-------------------------------------------------------TPS1+()×=
OSC
T1 Pin
TR1
GATE1
INT1 Pin
TL1
(8 Bits)
Control
Interrupt
C/T = 0
C/T = 1
PSC1
TH1
(8 Bits)
TF1
÷TPS
Mode 1: Time-out Period 65536 RH0 RL0{,}–()
Oscillator Frequency
--------------------------------------------------------- TPS1+()×=
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Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload
11.3 Mode 2 – 8-bit Auto-Reload Timer/Counter
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown
in Figure 11-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of
TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the
same for Timer/Counter 0.
Figure 11-3. Timer/Counter 1 Mode 2: 8-bit Auto-Reload
Note: RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage
registers.
11.4 Mode 3 – 8-bit Split Timer
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in
Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 11-4. TL0 uses the Timer 0 control bits: C/T, GATE0, TR0, INT0, and TF0. TH0
is locked into a timer function (counting clock cycles) and takes over the use of TR1 and TF1
from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1
will still obey its settings in TMOD but cannot generate an interrupt.
OSC
T1 Pin
TR1
GATE1
INT1 Pin
TL1
(8 Bits)
Control
Interrupt
C/T = 0
C/T =1
TH1
(8 Bits)TF1
RL1
(8 Bits)
RH1
(8 Bits)
Reload
÷TPS
Mode 2: Time-out Period 256 TH0–()
Oscillator Frequency
-------------------------------------------------------TPS1+()×=
OSC
T1 Pin
TR1
GATE1
TF1
TL1
(8 Bits)
TH1
(8 Bits)
Control Reload
Interrupt
INT0 Pin
C/T = 0
C/T = 1
÷TPS
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Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the
AT89LP3240/6440 can appear to have four Timer/Counters. When Timer 0 is in Mode 3, Timer
1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1
can still be used by the serial port as a baud rate generator or in any application not requiring an
interrupt.
Figure 11-4. Timer/Counter 0 Mode 3: Two 8-bit Counters
Note: RH0/RL0 are not required by Timer 0 during Mode 3 and may be used as temporary storage
registers.
.
Control
Interrupt
Control
Interrupt
(8 Bits)
(8 Bits)
C/T = 0
C/T =1
T0 Pin
GATE0
INT0 Pin
÷TPS
÷TPS
Table 11-2. TCON – Timer/Counter Control Register
TCON = 88HReset Value = 0000 0000B
Bit Addressable
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit76543210
Symbol Function
TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors
to interrupt routine.
TR1 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.
TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors
to interrupt routine.
TR0 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.
IE1 Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
IE0 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.
IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
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Table 11-3. TMOD – Timer/Counter Mode Control Register
TMOD Address = 089H Reset Value = 0000 0000B
Not Bit Addressable
GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M0 T0M1
Bit76543210
Symbol Function
GATE1 Timer 1 Gating Control. When set, Timer/Counter 1 is enabled only while INT1 pin is high and TR1 control pin is set.
When cleared, Timer 1 is enabled whenever TR1 control bit isset.
C/T1 Timer or Counter Selector 1. Cleared for Timer operation (input from internal system clock). Set for Counter operation
(input from T1 input pin). C/T1 must be zero when using Timer 1 in PWM mode.
T1M1
T1M0
Timer 1 Operating Mode
Mode T1M1 T1M0 Operation
000Variable 9–16-bit Timer Mode. 8-bit Timer/Counter TH1 with TL1 as 1–8-bit prescaler.
10116-bit Auto-Reload Mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter
that is reloaded with RH1 and RL1 each time it overflows.
2108-bit Auto Reload Mode. TH1 holds a value which is reloaded into 8-bit Timer/Counter
TL1 each time it overflows.
311Timer/Counter 1 is stopped
GATE0 Timer 0 Gating Control. When set, Timer/Counter 0 is enabled only while INT0 pin is high and TR0 control pin is set.
When cleared, Timer 0 is enabled whenever TR0 control bit isset.
C/T0 Timer or Counter Selector 0. Cleared for Timer operation (input from internal system clock). Set for Counter operation
(input from T0 input pin). C/T0 must be zero when using Timer 0 in PWM mode.
T0M1
T0M0
Timer 0 Operating Mode
Mode T0M1 T0M0 Operation
000Variable 9–16-bit Timer Mode. 8-bit Timer/Counter TH0 with TL0 as 1–8-bit prescaler.
10116-bit Auto-Reload Mode. TH0 and TL0 are cascaded to form a 16-bit Timer/Counter
that is reloaded with RH0 and RL0 each time it overflows.
2108-bit Auto Reload Mode. TH0 holds a value which is reloaded into 8-bit Timer/Counter
TL0 each time it overflows.
311Split Timer Mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0
control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits.
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11.5 Pulse Width Modulation
On the AT89LP3240/6440, Timer 0 and Timer 1 may be independently configured as 8-bit
asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or
PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the
timer's input pin, T0 or T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0
(P3.4) and T1 (P3.5) must be configured in an output mode. The Timer Overflow Flags and
Interrupts will continue to function while in PWM Mode and Timer 1 may still generate the baud
rate for the UART. The timer GATE function also works in PWM mode, allowing the output to be
halted by an external input. Each PWM channel has four modes selected by the mode bits in
TMOD.
An example waveform for Timer 0 in PWM Mode 0 is shown in Figure 11-5. TH0 acts as an 8-bit
counter while RH0 stores the 8-bit compare value. When TH0 is 00H the PWM output is
set high. When the TH0 count reaches the value stored in RH0 the PWM output is set low.
Therefore, the pulse width is proportional to the value in RH0. To prevent glitches, writes to
RH0 only take effect on the FFH to 00H overflow of TH0. Setting RH0 to 00H will keep the PWM
output low.
Figure 11-5. 8-bit Asymmetrical Pulse Width Modulation
Table 11-4. TCONB – Timer/Counter Control Register B
TCONB = 91H Reset Value = 0010 0100B
Not Bit Addressable
PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02 PSC01 PSC00
Bit76543210
Symbol Function
PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5).
PWM0EN Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4).
PSC12
PSC11
PSC10
Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which
enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89S2051.
PSC02
PSC01
PSC00
Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which
enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C52.
FFH
00H
RH0
(P3.4)T0
TF0 Set
TH0
time
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AT89LP3240/6440
11.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler
In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see Figure 11-6). The
PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in RHx
is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the
output pin is cleared low. The following formulas give the output frequency and duty cycle for
Timer 0 in PWM Mode 0. Timer 1 in PWM Mode 0 is identical to Timer 0.
Figure 11-6. Timer/Counter 1 PWM Mode 0
11.5.2 Mode 1 – 8-bit PWM with 8-bit Linear Prescaler
In Mode 1, TLx provides linear prescaling with an 8-bit auto-reload from RLx (see Figure 11-7 on
page 58). On TLx overflow, TLx is loaded with the value of RLx. THx acts as an 8-bit counter. On
THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high.
When the count in THx matches OCRx, the output pin is cleared low. The following formulas
give the output frequency and duty cycle for Timer 0 in PWM Mode 1. Timer 1 in PWM Mode 1 is
identical to Timer 0.
11.5.3 Mode 2 – 8-bit Frequency Generator
Timer 0 in PWM Mode 2 functions as an 8-bit Auto-Reload timer, the same as normal Mode 2,
with the exception that the output pin T0 is toggled at every TL0 overflow (see Figure 11-8 and
Figure 11-9 on page 58). Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be
used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following
formula gives the output frequency for Timer 0 in PWM Mode 2.
Mode 0:
fout Oscillator Frequency
256 2PSC0 1+
×
-------------------------------------------------------1
TPS1+
---------------------
×=
Duty Cycle % 100 RH0
256
------------
×=
OSC
TR1
GATE1
INT1 Pin
TL1
(8 Bits)
Control
PSC1 TH1
(8 Bits)
OCR1
RH1
(8 Bits)
=
T1
÷TPS
Mode 1:
fout Oscillator Frequency
256 256 RL0–()×
-------------------------------------------------------1
TPS1+
---------------------
×=
Duty Cycle % 100 RH0
256
------------
×=
Mode 2: fout Oscillator Frequency
2256TH0–()×
-------------------------------------------------------1
TPS1+
---------------------
×=
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Figure 11-7. Timer/Counter 1 PWM Mode 1
Figure 11-8. Timer/Counter 1 PWM Mode 2
Note: {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be
used as temporary storage registers.
Figure 11-9. PWM Mode 2 Waveform
OSC
TR1
GATE1
INT1 Pin
TL1
(8 Bits)
Control
TH1
(8 Bits)
OCR1
RH1
(8 Bits)
=
T1
RL1
(8 Bits)
÷TPS
OSC
TR1
GATE1
INT1 Pin
TL1
(8 Bits)
Control
T1
TH1
(8 Bits)
÷TPS
Tx
THx
FFh
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11.5.4 Mode 3 – Split 8-bit PWM
Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.
Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate PWM counters in a manner
similar to normal Mode 3. PWM Mode 3 on Timer 0 is shown in Figure 11-10. Only the Timer
Prescaler is available to change the output frequency during PWM Mode 3. TL0 can use the
Timer 0 control bits: GATE, TR0, INT0, PWM0EN and TF0. TH0 is locked into a timer function
and uses TR1, PWM1EN and TF1. RL0 provides the duty cycle for TL0 and RH0 provides the
duty cycle for TH0.
PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM
channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP3240/6440
can appear to have four Timer/Counters. When Timer 0 is in PWM Mode 3, Timer 1 can be
turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be
used by the serial port as a baud rate generator or in any application not requiring an interrupt.
The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 3.
Figure 11-10. Timer/Counter 0 PWM Mode 3
Mode 3: fout Oscillator Frequency
256
-------------------------------------------------------1
TPS1+
---------------------
×=
Mode 3, T0: Duty Cycle % 100 RL0
256
-----------
×=
Mode 3, T1: Duty Cycle % 100 RH0
256
------------
×=
OSC
TR0
GATE0
INT0 Pin
Control
TL0
(8 Bits)
OCR0
RL0
(8 Bits)
=
T0
OSCTH0
(8 Bits)
OCR1
RH0
(8 Bits)
=
T1
TR1
÷TPS
÷TPS
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12. Enhanced Timer 2
The AT89LP3240/6440 includes a 16-bit Timer/Counter 2 with the following features:
•16-bit timer/counter with one 16-bit reload/capture register
• One external reload/capture input
• Up/Down counting mode with external direction control
•UART baud rate generation
•Output-pin toggle on timer overflow
•Dual slope symmetric operating modes
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes:
capture, auto-reload (up or down counting), and baud rate generator. The modes are selected
by bits in T2CON and T2MOD, as shown in Table 12-3. Timer 2 also serves as the time base for
the Compare/Capture Array (See Section 13. “Compare/Capture Array” on page 69).
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the register is incre-
mented every clock cycle. Since a clock cycle consists of one oscillator period, the count rate is
equal to the oscillator frequency. The timer rate can be prescaled by a value between 1 and 16
using the Timer Prescaler (see Table 6-2 on page 33).
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled every clock cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is incre-
mented. The new count value appears in the register during the cycle following the one in which
the transition was detected. Since two clock cycles are required to recognize a 1-to-0 transition,
the maximum count rate is 1/2 of the oscillator frequency. To ensure that a given level is sam-
pled at least once before it changes, the level should be held for at least one full clock cycle.
The following definitions for Timer 2 are used in the subsequent paragraphs:
Table 12-1. Timer 2 Operating Modes
RCLK + TCLK CP/RL2 DCEN T2OE TR2 MODE
0000116-bit Auto-reload
0010116-bit Auto-reload Up-Down
01X0116-bit Capture
1 XXX1Baud Rate Generator
XXX11Frequency Generator
X X X X 0 (Off)
Table 12-2. Timer 2 Definitions
Symbol Definition
MIN 0000H
MAX FFFFH
BOTTOM 16-bit value of {RCAP2H,RCAP2L} (standard modes)
TOP 16-bit value of {RCAP2H,RCAP2L} (enhanced modes)
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12.1 Timer 2 Registers
Control and status bits for Timer 2 are contained in registers T2CON (see Table 12-3) and
T2MOD (see Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the
16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and
0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes.
Table 12-3. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8HReset Value = 0000 0000B
Bit Addressable
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Bit76543210
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1) or dual-slope mode.
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
TCLK Tr ansmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Table 12-4. T2MOD – Timer 2 Mode Control Register
T2MOD Address = 0C9H Reset Value = 0000 0000B
Not Bit Addressable
PHSDPHS2PHS1PHS0 T2CM1 T2CM0 T2OE DCEN
Bit76543210
Symbol Function
PHSD CCA Phase Direction. For phase modes with 3 or 4 channels, PHSD determines the direction that the channels are
cycled through. PHSD also determines the initial phase relationship for 2 phase modes.
PHSD Direction
0 or or
1 or or
ABAB→→→
ABCABC→→→→→
ABCDABCD→→→→→→→
BABA→→→
CBACBA→→→→→
DCBADCBA→→→→→→→
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12.2 Capture Mode
In the Capture mode, Timer 2 is a fixed 16-bit timer or counter that counts up from MIN to MAX.
An overflow from MAX to MIN sets bit TF2 in T2CON. If EXEN2 = 1, a 1-to-0 transition at exter-
nal input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set.
The EXF2 and TF2 bits can generate an interrupt. Capture mode is illustrated in Figure 12-1.
The Timer 2 overflow rate in Capture mode is given by the following equation:
PHS [2-0] CCA Phase Mode. PWM channels may be grouped by 2, 3 or 4 such that only one channel in a group produces a pulse
in any one period. The PHS[2-0] bits may only be written when the timer is not active, i.e. TR2 = 0.
PHS2 PHS1 PHS0 Phase Mode
000Disabled, all channels active
0012-phase output on channels A & B
0103-phase output on channels A, B & C
0114-phase output on channels A, B, C & D
100Dual 2-phase output on channels A & B and C & D
101reserved
110reserved
111reserved
T2CM
[1-0]
Timer 2 Count Mode.
T2CM1 T2CM0 Count Mode
00Standard Timer 2 (up count: )
0 1 Clear on RCAP compare (up count: )
10Dual-slope with single update (up-down count: )
11Dual-slope with double update (up-down count: )
T2OE Timer 2 Output Enable. When T2OE = 1 and C/T2 = 0, the T2 pin will toggle after every Timer 2 overflow.
DCEN Timer 2 Down Count Enable. When Timer 2 operates in Auto-Reload mode and EXEN2 = 1, setting DCEN = 1 will cause
Timer 2 to count up or down depending on the state of T2EX.
Symbol Function
BOTTOM MAX→
MIN TOP→
MIN TOP MIN→→
MIN TOP MIN→→
Capture Mode: Time-out Period 65536
Oscillator Frequency
-------------------------------------------------------TPS1+()×=
63
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Figure 12-1. Timer 2 Diagram: Capture Mode
12.3 Auto-Reload Mode
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload
mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR
T2MOD (see Table 12-4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to
count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the
T2EX pin. The overflow and reload values depend on the Timer 2 Count Mode bits, T2CM1-0 in
T2MOD. A summary of the Auto-Reload behaviors is listed in Table 12-5.
12.3.1 Up Counter
Figure 12-2 shows Timer 2 automatically counting up when DCEN = 0 and T2CM1-0 = 00B. In
this mode Timer 2 counts up to MAX and then sets the TF2 bit upon overflow. The overflow also
causes the timer registers to be reloaded with BOTTOM, the 16-bit value in RCAP2H and
RCAP2L. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 tran-
sition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits
can generate an interrupt. The Timer 2 overflow rate for this mode is given in the following
equation:
Timer 2 may also be configured to count from MIN to TOP instead of BOTTOM to MAX by set-
ting T2CM1-0 = 01B. In this mode Timer 2 counts up to TOP, the 16-bit value in RCAP2H and
÷TPS
EXF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CAPTURE
OVERFLOW
TRANSITION
DETECTOR TIMER 2
INTERRUPT
RCAP2HRCAP2L
TL2 TH2 TF2
OSC
Table 12-5. Summary of Auto-Reload Modes
T2CM1-0 DCEN T2EX Direction Behavior
00 0 X Up reload to BOTTOM
00 1 0 Down underflow to MAX
00 1 1 Up overflow to BOTTOM
01 0 X Up reload to MIN
01 1 0 Down underflow to TOP
01 1 1 Up overflow to MIN
10 X X Up-Down and repeat
11 X X Up-Down and repeat
BOTTOM MAX→
MAX BOTTOM→
BOTTOM MAX→
MIN TOP→
TOP MIN→
MIN TOP→
MIN TOP MIN→→
MIN TOP MIN→→
Auto-Reload Mode:
DCEN = 0, T2CM = 00B Time-out Period 65536 RCAP2H RCAP2L{,}–
Oscillator Frequency
-------------------------------------------------------------------------------TPS1+()×=
64
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RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to be
reloaded with MIN. If EXEN2 = 1, a 1-to-0 transition on T2EX will clear the timer and set EXF2.
The Timer 2 overflow rate for this mode is given in the following equation:
Timer 2 Count Mode 1 is provided to support variable precision asymmetrical PWM in the CCA.
The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that a new TOP
value takes affect only after an overflow. The behavior of Count Mode 0 versus Count Mode 1 is
shown in Figure 12-3.
Figure 12-2. Timer 2 Diagram: Auto-Reload Mode (DCEN = 0)
Figure 12-3. Timer 2 Waveform: Auto-Reload Mode (DCEN = 0)
12.3.2 Up or Down Counter
Setting DCEN = 1 enables Timer 2 to count up or down, as shown in Figure 12-4. In this mode,
the T2EX pin controls the direction of the count (if EXEN2 = 1). A logic 1 at T2EX makes Timer 2
count up. When T2CM1-0 = 00B, the timer will overflow at MAX and set the TF2 bit. This overflow
also causes BOTTOM, the 16-bit value in RCAP2H and RCAP2L, to be reloaded into the timer
Auto-Reload Mode:
DCEN = 0, T2CM = 01B Time-out Period RCAP2H RCAP2L{,}1+
Oscillator Frequency
------------------------------------------------------------------TPS1+()×=
÷TPS
TL2 TH2
MAX
MIN
BOTTOM
T2CM1-0 = 00B, DCEN = 0
MAX
MIN
TOP
T2CM1-0 = 01B, DCEN = 0
TF2 Set
TF2 Set
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AT89LP3240/6440
registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and
RCAP2L. The underflow sets the TF2 bit and causes MAX to be reloaded into the timer regis-
ters. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th
bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
When T2EX = 1 and T2CM1-0 = 01B, the timer will overflow at TOP and set the TF2 bit. This
overflow also causes MIN to be reloaded into the timer registers. A logic 0 at T2EX makes Timer
2 count down. The timer underflows when TH2 and TL2 equal MIN. The underflow sets the TF2
bit and causes TOP to be reloaded into the timer registers. The behavior of Count Mode 0 ver-
sus Count Mode 0 when DCEN is enabled is shown in Figure 12-6.
Figure 12-4. Timer 2 Diagram: Auto-Reload Mode (T2CM1-0 = 00B, DCEN = 1)
The timer overflow/underflow rate for up-down counting mode is the same as for up counting
mode, provided that the count direction does not change. Changes to the count direction may
result in longer or shorter periods between time-outs.
Figure 12-5. Timer 2 Diagram: Auto-Reload Mode (T2CM1-0 = 01B, DCEN = 1)
÷TPS
÷TPS
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Figure 12-6. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1)
12.3.3 Dual Slope Counter
When Timer 2 Auto-Reload Mode uses Count Mode 2 (T2CM1-0 = 10B) or Count Mode 3
(T2CM1-0 = 11B), the timer operates in a dual slope fashion. The timer counts up from MIN to
TOP and then counts down from TOP to MIN, following a sawtooth waveform as shown in Fig-
ure 12-7. The EXF2 bit is set/cleared by hardware to reflect the current count direction (Up =
0and Down = 1). The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that
a new TOP value takes affect only after an underflow. The only difference between Mode 2 and
Mode 3 is when the interrupt flag is set. In Mode 2 TF2 is set once per count period when the
timer underflows at MIN. In Mode 3 TF2 is set twice per count period, once when the timer over-
flows at TOP and once when the timer underflows at MIN. The interrupt service routine can
check the EXF2 bit to determine if TF2 was set at TOP or MIN. These count modes are provided
to support variable precision symmetrical PWM in the CCA. DCEN has no effect when using
dual slope operation. The Timer 2 overflow rate for this mode is given in the following equation:
MAX
MIN
BOTTOM
T2CM1-0 = 00B, DCEN = 1
MAX
MIN
TOP
T2CM1-0 = 01B, DCEN = 1
T2EX
TF2 Set
TF2 Set
EXF2
Auto-Reload Mode:
DCEN = 0, T2CM = 10B Time-out Period RCAP2H RCAP2L{,}2×
Oscillator Frequency
-------------------------------------------------------------------TPS1+()×=
67
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Figure 12-7. Timer 2 Waveform: Dual Slope Modes
12.4 Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table
12-3). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the
receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK
puts Timer 2 into its baud rate generator mode, as shown in Figure 12-8.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2
causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and
RCAP2L, which are preset by software.
The baud rates in UART Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it is con-
figured for timer operation (CP/T2 = 0). The baud rate formulas are given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned
integer.
Timer 2 as a baud rate generator is shown in Figure 12-8. This figure is valid only if RCLK or
TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-
rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a
reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate gen-
MAX
MIN
TOP
T2CM1-0 = 10B
MAX
MIN
TOP
TF2 Set
TF2 Set
T2CM1-0 = 11B
EXF2
Modes 1 and 3 Baud RatesTimer 2 Overflow Rate
16
------------------------------------------------------------=
T2CM = 00B Modes 1, 3
Baud Rate
Oscillator Frequency
16 TPS1+()×65536 RCAP2H,RCAP2L()–[]×
---------------------------------------------------------------------------------------------------------------------------------=
T2CM = 01B Modes 1, 3
Baud Rate
Oscillator Frequency
16 TPS1+()×RCAP2H RCAP2L(,)1+[]×
-------------------------------------------------------------------------------------------------------------------=
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erator, T2EX can be used as an extra external interrupt. Also note that the Baud Rate and
Frequency Generator modes may be used simultaneously.
Figure 12-8. Timer 2 in Baud Rate Generator Mode
12.5 Frequency Generator (Programmable Clock Out)
Timer 2 can generate a 50% duty cycle clock on T2 (P1.0), as shown in Figure 12-9. This pin,
besides being a regular I/O pin, has two alternate functions. It can be programmed to input the
external clock for Timer/Counter 2 or to toggle its output at every timer overflow. To configure
the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE
(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2
capture registers (RCAP2H, RCAP2L), as shown in the following equations.
In the frequency generator mode, Timer 2 roll-overs will not generate an interrupt. This behavior
is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a
baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate
and clock-out frequencies cannot be determined independently from one another since they
both use RCAP2H and RCAP2L.
÷TPS SMOD1
RCLK
TCLK
Rx
CLOCK
Tx
CLOCK
T2EX PIN
T2 PIN
TR2
"1"
"1"
"1"
"0"
"0"
"0"
TIMER 1 OVERFLOW
TIMER 2
INTERRUPT
2
16
16
RCAP2HRCAP2L
TL2 TH2
C/T2 = 0
C/T2 = 1
EXF2
TRANSITION
DETECTOR
EXEN2
÷
÷
÷
OSC
T2CM = 00B Clock Out Frequency Oscillator Frequency
2 65536 RCAP2H,RCAP2L()–[]×
--------------------------------------------------------------------------------------------1
TPS1+
---------------------
×=
T2CM = 01B Clock Out Frequency Oscillator Frequency
2 RCAP2H,RCAP2L()1+[]×
-------------------------------------------------------------------------------1
TPS1+
---------------------
×=
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Figure 12-9. Timer 2 in Clock-out Mode
13. Compare/Capture Array
The AT89LP3240/6440 includes a four channel Compare/Capture Array (CCA) that performs a
variety of timing operations including input event capture, output compare waveform generation
and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit com-
pare/capture modules. The CCA has the following features:
•Four 16-bit Compare/Capture channels
• Common time base provided by Timer 2
•Selectable external and internal capture events including pin change, timer overflow and
comparator output change
•Symmetric/Asymmetric PWM with selectable polarity
•Multi-phasic PWM outputs
• One interrupt flag per channel with a common interrupt vector
The block diagram of the CCA is given in Figure 13-1. Each channel consists of an 8-bit control
register and a 16-bit data register. The channel registers are not directly accessible. The CCA
address register T2CCA provides an index into the array. The control, data low and data high
bytes of the currently indexed channel are accessed through the T2CCC, T2CCL and T2CCH
registers respectively.
Each channel can be individually configured for capture or compare mode. Capture mode is the
default setting. During capture mode the current value of the time base is copied into the chan-
nel’s data register when the specified external or internal event occurs. An interrupt flag is set at
the same time and the time base may be optionally cleared. To enable compare mode, the
CCMx bit in the channel’s control register (CCCx) should be set to 1. In compare mode an inter-
rupt flag is set and an output pin is optionally toggled when the value of the time base matches
the value of the channel’s data register. The time base may also be optionally cleared on a com-
pare match.
Timer 2 must be running (TR2 = 1) in order to perform captures or compares with the CCA.
However, when TR2 = 0 the external capture events will still set their associated flags and may
be used as additional external interrupts.
OSC
T2EX PIN
T2 PIN
TR2
TIMER 2
INTERRUPT
RCAP2HRCAP2L
TL2 TH2
C/T2
EXF2
TRANSITION
DETECTOR EXEN2
÷TPS
÷2
T2OE
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Figure 13-1. Compare/Capture Array Block Diagram
13.1 CCA Registers
The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL,
T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel. The
CCA interrupt is a logic OR of the bits in T2CCF. The flags are set by hardware when a com-
pare/capture event occurs on the relevant channel and must be cleared by software. The
T2CCF bits will only generate an interrupt when the ECC bit (IE2.1) is set and the CIENx bit in
the associated channel’s CCCx register is set.
The T2CCC, T2CCL and T2CCH register locations are not true SFRs. These locations represent
access points to the contents of the array. Writes/reads to/from the T2CCC, T2CCL and T2CCH
locations will access the control, data low and data high bytes of the CCA channel currently
selected by the index in T2CCA. Channels currently not indexed by T2CCA are not accessible.
When writing to T2CCH, the value is stored in a shadow register. When T2CCL is written, the
16-bit value formed by the contents of T2CCL and the T2CCH shadow is written into the array.
Therefore, T2CCH must be written prior to writing T2CCL. All four channels use the same
T2CCH shadow register. If the value of T2CCH remains constant for multiple writes, there is no
need to update T2CCH between T2CCL writes. Every write to T2CCL will use the last value of
T2CCH for the upper data byte. It is not possible to write to the data register of a channel config-
ured for capture mode.
The configuration bits for each channel are stored in the CCCx registers accessible through
T2CCC. See Table 13-5 on page 74 for a description of the CCCx register.
OSC
(P1.0) T2
TR2
TL2
Timer 2 Interrupt
C/T2 = 0
C/T2 =1
TH2
TF2
RCAP2L RCAP2H
÷TPS
CCAL CCAHCCCA
CCBL CCBHCCCB
CCCL CCCHCCCC
CCDL CCDHCCCD
T2CCF
CCA Interrupt
CCA (P2.0)
CCB (P2.1)
CCC (P2.2)
CCD (P2.3)
T2CCC T2CCL T2CCH
T2CCA
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Note: All writes/reads to/from T2CCH will access channel X as currently selected by T2CCA.The data registers for the remaining
unselected channels are not accessible.
Note: All writes/reads to/from T2CCL will access channel X as currently selected by T2CCA.The data registers for the remaining
unselected channels are not accessible.
Table 13-1. T2CCA – Timer/Counter 2 Compare/Capture Address
T2CCA Address = 0D1H Reset Value = xxxx xx00B
Not Bit Addressable
——————T2CCA.1T2CCA.0
Bit76543210
Symbol Function
T2CCA
[1-0]
Compare/Capture Address. Selects which CCA channel is currently accessible through the T2CCH, T2CCL and T2CCC
registers. Only one channel may be accessed at a time.
T2CCA1 T2CCA0 Channel
0 0 A – T2CCH, T2CCL and T2CCC access data and control for Channel A
0 1 B – T2CCH, T2CCL and T2CCC access data and control for Channel B
1 0 C – T2CCH, T2CCL and T2CCC access data and control for Channel C
1 1 D – T2CCH, T2CCL and T2CCC access data and control for Channel D
Table 13-2. T2CCH – Timer/Counter 2 Compare/Capture Data High
T2CCH Address = 0D2H Reset Value = 0000 0000B
Not Bit Addressable
T2CCD.15 T2CCD.14 T2CCD.13 T2CCD.12 T2CCD.11 T2CCD.10 T2CCD.9 T2CCD.8
Bit76543210
Symbol Function
T2CCD
[15-8]
Compare/Capture Data (High Byte). Reads from T2CCH will return the high byte from the CCA channel currently
selected by T2CCA. The high byte of the selected CCA channel will be updated with the contents of T2CCH when
T2CCL is written. When writing multiple channels with the same high byte, T2CCH need not be updated between writes
to T2CCL.
Table 13-3. T2CCL – Timer/Counter 2 Compare/Capture Data Low
T2CCC Address = 0D3H Reset Value = 0000 0000B
Not Bit Addressable
T2CCD.7 T2CCD.6 T2CCD.5 T2CCD.4 T2CCD.3 T2CCD.2 T2CCD.1 T2CCD.0
Bit76543210
Symbol Function
T2CCD
[7-0]
Compare/Capture Data (Low Byte). Reads from T2CCL will return the low byte from the CCA channel currently selected
by T2CCA. Writes to T2CCL will update the selected CCA channel with the 16-bit contents of T2CCH and T2CCL.
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13.2 Input Capture Mode
The Compare/Capture Array provides a variety of capture modes suitable for time-stamping
events or performing measurements of pulse width, frequency, slope, etc. CCA channels are
configured for capture mode by clearing the CCMx bit in the associated CCCx register to 0.
Each time a capture event occurs, the contents of Timer 2 (TH2 and TL2) are transferred to the
16-bit data register of the corresponding channel, and the channel’s interrupt flag CCFx is set in
T2CCF. Optionally, the capture event may also clear Timer 2 to 0000H by setting the CTCx bit in
CCCx. The capture event is defined by the CxM2-0 bits in CCCx and may be either externally or
internally generated. A diagram of a CCA channel in capture mode is shown in Figure 13-2.
Figure 13-2. CCA Capture Mode Diagram
Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC
(P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected
Table 13-4. T2CCF – Timer/Counter 2 Compare/Capture Flags
T2CCF Address = 0D5H Reset Value = XXXX 0000B
Not Bit Addressable
– – – – CCFD CCFC CCFB CCFA
Bit76543210
Symbol Function
CCFD Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software.
CCFD will generate an interrupt when CIEND = 1 and ECC = 1.
CCFC Channel C Compare/Capture Interrupt Flag. Set by a compare/capture event on channel C. Must be cleared by
software. CCFC will generate an interrupt when CIENC = 1 and ECC = 1.
CCFB Channel B Compare/Capture Interrupt Flag. Set by a compare/capture event on channel B. Must be cleared by software.
CCFB will generate an interrupt when CIENB = 1 and ECC = 1.
CCFA Channel A Compare/Capture Interrupt Flag. Set by a compare/capture event on channel A. Must be cleared by software.
CCFA will generate an interrupt when CIENA = 1 and ECC = 1.
TL2 TH2
CCxL CCxH
CCCx
Interrupt
(P2.x) CCx
T2CCCT2CCL T2CCH
0
1
2
3
4
5
6
7
“0”
Timer 0 Overflow
Timer 1 Overflow
Comparator A
Comparator B
00H 00H
CTCx
CCFx
CIENx
CxM
2-0
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to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled every
clock cycle and a new value must be held for at least 2 clock cycles to be correctly sampled by
the device. The maximum achievable capture rate will be determined by how fast the software
can retrieve the captured data. There is no protection against capture events overrunning the
data register.
Capture events may also be triggered internally by the overflows of Timer 0 or Timer 1, or by an
event from the dual analog comparators. Any comparator event which can generate a compara-
tor interrupt may also be used as a capture event. However, Timer 2 should not be selected as
the comparator clock source when using the comparator as the capture trigger.
When the DAC output is enabled on P2.2 and P2.3, channels C and D cannot use their external
pin capture modes. However, those channels may still use the timer or comparator triggers to
capture data. The same applies for all four channels when Port 2 is used for the external mem-
ory interface.
13.2.1 Timer 2 Operation for Capture Mode
Capture channels are intended to work with Timer 2 in capture mode CP/RL2 =1. Captures can
still occur when Timer 2 operates in other modes; however, the full 16-bit count range may not
be available. The TF2 flag can be used to determine if the timer overflowed before the capture
occurred. If the timer is operating in dual-slope mode (CP/RL2 =0, T2CM
1-0 =1xB), the count
direction (Up = 0 and Down = 1) at the time of the event will be captured into the channel’s
CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud
Rate mode or errors may occur in the serial communication.
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Notes: 1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain-
ing unselected channels are not accessible.
2. Analog Comparator A events are determined by the CMA2-0 bits in ACSRA. See Table 19-1 on page 130.
3. Analog Comparator B events are determined by the CMB2-0 bits in ACSRB. See Table 19-2 on page 131.
4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See Section 13.4 on page 77.
Table 13-5. T2CCC – Timer/Counter 2 Compare/Capture Control
T2CCC Address = 0D4H Reset Value = 00X0 0000B
Not Bit Addressable
CIENxCDIRx–CTCxCCMxCxM2 CxM1 CxM0
Bit76543210
Symbol Function
CIENxChannel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt when ECC
= 1. Clear to disable interrupts from channel X.
CDIRxChannel X Capture Direction. In dual-slope modes, a compare/capture event on channel X will store the current count
direction into CDIRx. Up-counting = 0 and down-counting = 1. Modifying this bit has no effect.
CTCxClear Timer on Compare/Capture of Channel X. When set, the Timer 2 registers TL2 and TH2 will be cleared by a
compare/capture event on channel X. When cleared, Timer 2 is unaffected by channel X events.
CCMxChannel X Compare/Capture Mode. When CCMx = 1, channel X operates in compare mode. When CCMx = 0, channel
X operates in capture mode.
CxM[2-0] Channel X Mode. Selects the output/input events for compare/capture channel X.
CxM2 CxM1 CxM0 Capture Event (CCMx = 0)
000Disabled
001Trigger on negative edge of CCx pin
010Trigger on positive edge of CCx pin
011Trigger on either edge of CCx pin
100Trigger on Timer 0 overflow
101Trigger on Timer 1 overflow
110Trigger on Analog Comparator A Event(2)
111Trigger on Analog Comparator B Event(3)
CxM2 CxM1 CxM0 Compare Action (CCMx = 1)
000Output disabled (interrupt only)
001Set CCx pin on compare match
010Clear CCx pin on compare match
011Toggle CCx pin on compare match
100Inverting Pulse Width Modulation(4)
101Non-Inverting Pulse Width Modulation(4)
110Reserved
111Reserved
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13.3 Output Compare Mode
The Compare/Capture Array provides a variety of compare modes suitable for event timing or
waveform generation. CCA channels are configured for compare mode by setting the CCMx bit
in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a
channel’s data register match the contents of Timer 2 (TH2 and TL2). The compare event also
sets the channel’s interrupt flag CCFx in T2CCF and may optionally clear Timer 2 to 0000H if the
CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in Figure 13-3.
Figure 13-3. CCA Compare Mode Diagram
13.3.1 Waveform Generation
Each CCA channel has an associated external compare output pin: CCA (P2.0), CCB (P2.1),
CCC (P2.2) and CCD (P2.3). The CxM2-0 bits in CCCx determine what action is taken when a
compare event occurs. The output pin may be set to 1, cleared to 0 or toggled. Output actions
take place even if the interrupt is disabled; however, the associated I/O pin must be set to the
desired output mode before the compare event occurs. The state of the compare outputs are ini-
tialized to 1 by reset. Channels C and D cannot use their output pin when the DAC is enabled.
These channels may still be used to generate interrupts or to clear the timebase. The same
applies to all four channels when Port 2 is used for the external memory interface.
Multiple compare events per channel can occur within a single time period, provided that the
software has time to update the compare value before the timer reaches the next compare point.
In this case other interrupts should be disabled or the CCA interrupt given a higher priority in
order to ensure that the interrupt is serviced in time.
A wide range of waveform generation configurations are possible using the various operating
modes of Timer 2 and the CCA. Some example configurations are detailed below. Pulse width
modulation is a special case of output compare. See Section 13.4 on page 77 for more details of
PWM operation.
TL2 TH2
CCxL CCxH CCCx
Interrupt
CCx (P2.x)
T2CCCT2CCL shadow
00H 00H
CTCx
CCFx
CIENx
CxM
2-0
=
T2CCH
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13.3.1.1 Normal Mode
The simplest waveform mode is when CP/RL2 =0 and T2CM1-0 = 01B. In this mode the fre-
quency of the output is determined by the TOP value stored in RCAP2L and RCAP2H and
output edges occur at fractions of the timer period. Figure 13-4 shows an example of outputting
two waveforms of the same frequency but different phase by using the toggle on match action.
More complex waveforms are achieved by changing the TOP value and the compare values
more frequently.
Figure 13-4. Normal Mode Waveform Example
13.3.1.2 Clear-Timer-on-Compare Mode
Clear-Timer-on-Compare (CTC) mode occurs when the CTCx bit of a compare channel is set to
one. CTC Mode works best when Timer 2 is in capture mode (CP/RL2 =1) to allow the full range
of compare values. In CTC Mode the compare value defines the interval between output events
because the timer is cleared after every compare match. Figure 13-5 shows an example wave-
form using the toggle on match action in CTC Mode.
Figure 13-5. CTC Mode Waveform Example
13.3.1.3 Dual-Slope Mode
The dual-slope mode occurs when CP/RL2 =0 and T2CM1-0 = 1xB. In this mode the frequency
of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges
occur at fractions of the timer period on both the up and down count. Figure 13-6 shows an
example of outputting two symmetrical waveforms using the toggle on match action. More com-
plex waveforms are achieved by changing the TOP value and the compare values more
frequently.
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 01B, DCEN = 0
CCA
{CCAH,CCAL}
{CCBH,CCBL}
CCB
CP/RL2 = 1
CCA
{CCAH,CCAL}
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Figure 13-6. Dual-Slope Waveform Example
13.3.2 Timer 2 Operation for Compare Mode
Compare channels will work with any Timer 2 operating mode. The full 16-bit compare range
may not be available in all modes. In order for a compare output action to take place, the com-
pare values must be within the counting range of Timer 2. CTCx must be cleared to 0 for all
channels if Timer 2 is operating in Baud Rate mode or errors may occur in the serial
communication.
13.4 Pulse Width Modulation Mode
In Pulse Width Modulation (PWM) Mode, a compare channel can output a square wave with pro-
grammable frequency and duty cycle. Setting CCMx = 1 and CxM2-0 = 10xB enables PWM
Mode. PWM Mode is similar to Output Compare Mode except that the compare value is double-
buffered. A diagram of a CCA channel in PWM Mode is shown in Figure 13-7. The PWM polarity
is selectable between inverting and non-inverting modes. PWM is intended for use with Timer 2
in Auto-Reload Mode (CP/RL2 =0, DCEN=0) using count modes 1, 2 or 3. The PWM can oper-
ate in asymmetric (edge-aligned) or symmetric (center-aligned) mode depending on the T2CM
selection. The CCA PWM has variable precision from 2 to 16 bits. A trade-off between frequency
and precision is made by changing the TOP value of the timer. The CCA PWM always uses the
greatest precision allowable for the selected output frequency, as compared to Timer 0 and 1
whose PWMs are fixed at 8-bit precision regardless of frequency.
Figure 13-7. CCA PWM Mode Diagram
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 10B, DCEN = 0
CCA
{CCAH,CCAL}
{CCBH,CCBL}
CCB
TL2 TH2
CCxL CCxH CCCx
Interrupt
CCx (P2.x)
T2CCCT2CCL
shadow CCFx
CIENx
CxM
2-0
=
T2CCH
shadow
shadow
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13.4.1 Asymmetrical PWM
For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1
(CP/RL2 =0, DCEN=0, T2CM1-0= 01B). Asymmetrical PWM uses single slope operation as
shown in Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT-
TOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2
(TL2, TH2) and the channel data register (CCxL, CCxH), and cleared at BOTTOM. In inverting
mode, the output CCx is cleared on the compare match between Timer 2 and the data register,
and set at BOTTOM. The resulting asymmetrical output waveform is left-edge aligned.
The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is
only updated at the TOP to BOTTOM overflow. The channel data register (CCxL, CCxH) is also
double-buffered such that the duty cycle is only updated at the TOP to BOTTOM overflow to pre-
vent glitches. The output frequency and duty cycle for asymmetrical PWM are given by the
following equations:
The extreme compare values represent special cases when generating a PWM waveform. If the
compare value is set equal to (or greater than) TOP, the output will remain low or high for non-
inverting and inverting modes, respectively. If the compare value is set to BOTTOM (0000H), the
output will remain high or low for non-inverting and inverting modes, respectively.
Figure 13-8. Asymmetrical (Edge-Aligned) PWM
13.4.2 Symmetrical PWM
For Symmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 2
or 3 (CP/RL2 = 0, DCEN = 0, T2CM1-0 =1xB). Symmetrical PWM uses dual-slope operation as
shown in Figure 13-9. The timer counts up from MIN to TOP and then counts down from TOP to
MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output
CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel
data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the
output CCx is set on the up-count compare match between Timer 2 and the data register, and
cleared at the down-count compare match. The resulting symmetrical PWM output waveform is
fOUT Oscillator Frequency
RCAP2H RCAP2L{,}1+
---------------------------------------------------------------- 1
TPS1+
---------------------
×=
Inverting: Duty Cycle 100% CCxH CCxL{,}
RCAP2H RCAP2L{,}1+
----------------------------------------------------------------
×=
Non-Inverting: Duty Cycle 100% RCAP2H RCAP2L{,}CCxH CCxL{,}–1+
RCAP2H RCAP2L{,}1+
-------------------------------------------------------------------------------------------------------------
×=
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 01B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-inverted
CCx
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center-aligned around the timer equal to TOP point. Symmetrical PWM may be used to generate
non-overlapping waveforms.
The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is
only updated at the underflow. The channel data register (CCxL, CCxH) is also double-buffered
to prevent glitches. The output frequency and duty cycle for symmetrical PWM are given by the
following equations:
The extreme compare values represent special cases when generating a PWM waveform. If the
compare value is set equal to (or greater than) TOP, the output will remain high or low for non-
inverting and inverting modes, respectively. If the compare value is set to MIN (0000H), the out-
put will remain low or high for non-inverting and inverting modes, respectively.
Figure 13-9. Non-overlapping Waveforms Using Symmetrical PWM
13.4.2.1 Phase and Frequency Correct PWM
When T2CM1-0 = 10B the Symmetrical PWM operates in phase and frequency correct mode. In
this mode the compare value double buffer is only updated when the timer equals MIN (under-
flow). This guarantees that the resulting waveform is always symmetrical around the TOP value
as shown in Figure 13-10 because the up and down count compare values are identical. The
TF2 interrupt flag is only set at underflow.
13.4.2.2 Phase Correct PWM
When T2CM1-0 = 11B the Symmetrical PWM operates in phase correct mode. In this mode the
compare value double buffer is updated when the timer equals MIN (underflow) and TOP (over-
flow). The resulting waveform may not be completely symmetrical around the TOP value as
shown in Figure 13-11 because the up and down count compare values may not be identical.
However, this allows the pulses to be weighted toward one edge or another. The TF2 interrupt
flag is set at both underflow and overflow.
fOUT Oscillator Frequency
2 RCAP2H RCAP2L{,}×
----------------------------------------------------------------- 1
TPS1+
---------------------
×=
Non-Inverting: Duty Cycle 100% CCxH CCxL{,}
RCAP2H RCAP2L{,}
------------------------------------------------------
×=
Inverting: Duty Cycle 100% RCAP2H RCAP2L{,}CCxH CCxL{,}–
RCAP2H RCAP2L{,}
---------------------------------------------------------------------------------------------------
×=
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 10B, DCEN = 0
(Inverted) CCA
{CCAH,CCAL}
(Non-Inverted) CCB
{CCBH,CCBL}
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Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWM
Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM
13.4.3 Multi-Phasic PWM
The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS2-0
bits in T2MOD. The AT89LP3240/6440 provides 1 out of 2, 1 out of 3, 1 out of 4 and 2 out of 4
phase modes (See Table 13-6). In Multi-phasic mode the PWM outputs on CCA, CCB, CCC and
CCD are connected to a one-hot shift register that selectively enables and disables the outputs
(See Figure 13-12). Compare points on disabled channels are blocked from toggling the output
as if the compare value was set equal to TOP. The PHSD bit in T2MOD controls the direction of
the shift register. Example waveforms are shown in Figure 13-14 on page 82. In order to use
multi-phasic PWM, the associated channels must be configured for PWM operation. Non-PWM
channels are not affected by multi-phasic operation. However, their locations in the shift register
are maintained such that some periods in the PWM outputs may not have any pulses as shown
in Figure 13-13.
The PHS2-0 bits may only be modified when the timer is not operational (TR2 = 0). Updates to
PHSD are allowed at any time. Note that channels C and D in 1:2 phase mode and channel D in
1:3 phase mode operate normally.
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 10B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-Inverted
CCx
Duty Cycle Updated
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM1-0 = 11B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-Inverted
CCx
Duty Cycle Updated
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Figure 13-12. Multi-Phasic PWM Output Stage
Figure 13-13. Three-Phase Mode with Channel B Disabled
Table 13-6. Summary of Multi-Phasic Modes
PHS2-0 Mode
Behavior
PHSD = 0 PHSD = 1
000 Off Normal Operation (all channels active at all times)
001 1:2
010 1:3
011 1:4
100 2:4
ABAB→→→
BABA→→→
ABCABC→→→→→
CBACBA→→→→→
ABCDABCD→→→→→→→
DCBADCBA→→→→→→→
ABAB→→→
CDCD→→→
BABA→→→
DCDC→→→
CCA
EN1
CCB
EN0
CCC
EN
1
CCD
EN
1
PHSD
PHSD
PHS = 001B
CCA
EN1
CCB
EN0
CCC
EN
0
CCD
EN
1
PHSD
PHSD
PHS = 010B
CCA
EN1
CCB
EN0
CCC
EN
0
CCD
EN
0
PHSD
PHSD
PHS = 011B
CCA
EN1
CCB
EN0
CCC
EN
1
CCD
EN
0
PHSD
PHSD
PHS = 100B
PHSD
PHSD
CCA
CCB
CCC
PHSD
PHS = 010B, CCB disabled
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Figure 13-14. Multi-Phasic PWM Modes
14. External Interrupts
The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 may be used as external inter-
rupt sources. The external interrupts can be programmed to be level-activated or transition-
activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is
triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In
this mode if successive samples of the INTx pin show a high in one cycle and a low in the next
cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the
external interrupt pins are sampled once each clock cycle, an input high or low should hold for at
least 2 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the
external source has to hold the request pin high for at least two clock cycles, and then hold it low
for at least two clock cycles to ensure that the transition is seen so that interrupt request flag IEx
will be set. IEx will be automatically cleared by the CPU when the service routine is called if gen-
erated in edge-triggered mode. If the external interrupt is level-activated, the external source has
to hold the request active until the requested interrupt is actually generated. Then the external
source must deactivate the request before the interrupt service routine is completed, or else
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
PHSD
CCA
CCB
CCC
CCD
PHSD
CCA
CCB
CCC
CCD
PHS = 000B
PHS = 001B
PHS = 010B
PHS = 011B
PHS = 100B
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another interrupt will be generated. Both INT0 and INT1 may wake up the device from the
Power-down state.
15. General-purpose Interrupts
The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on
Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register
select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS regis-
ters determine the mode for each individual pin. GPMOD selects between level-sensitive and
edge-triggered mode. GPLS selects between high/low in level mode and positive/negative in
edge mode. A block diagram is shown in Figure 15-1. The pins of Port 1 are sampled every
clock cycle. In level-sensitive mode, a valid level must appear in two successive samples before
generating the interrupt. In edge-triggered mode, a transition will be detected if the value
changes from one sample to the next. When an interrupt condition on a pin is detected, and that
pin is enabled, the appropriate flag in the GPIF register is set. The flags in GPIF must be cleared
by software. Any GPI interrupt may wake up the device from the Power-down state.
Figure 15-1. GPI Block Diagram
DQ
2
222
00
11
(P1.2) GPI2
DQ
1
111
00
11
(P1.1) GPI1
DQ
0
000
00
11
(P1.0) GPI0
DQ
3
333
00
11
(P1.3) GPI3
DQ
6
666
00
11
(P1.6) GPI6
DQ
5
555
00
11
(P1.5) GPI5
DQ
44 4 4
00
11
(P1.4) GPI4
DQ
7
777
00
11
(P1.7) GPI7
GPMODGPLS GPIEN GPIF
Interrupt
CLK
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.
.
.
Table 15-1. GPMOD – General-purpose Interrupt Mode Register
GPMOD = 9AH Reset Value = 0000 0000B
Not Bit Addressable
GPMOD7 GPMOD6 GPMOD5 GPMOD4 GPMOD3 GPMOD2 GPMOD1 GPMOD0
Bit76543210
GPMOD.x 0 = level-sensitive interrupt for P1.x
1 = edge-triggered interrupt for P1.x
Table 15-2. GPLS – General-purpose Interrupt Level Select Register
GPLS = 9BH Reset Value = 0000 0000B
Not Bit Addressable
GPLS7GPLS6GPLS5GPLS4GPLS3GPLS2GPLS1GPLS0
Bit76543210
GPMOD.x 0 = detect low level or negative edge on P1.x
1 = detect high level or positive edge on P1.x
Table 15-3. GPIEN – General-purpose Interrupt Enable Register
GPIEN = 9CH Reset Value = 0000 0000B
Not Bit Addressable
GPIEN7 GPIEN6 GPIEN5 GPIEN4 GPIEN3 GPIEN2 GPIEN1 GPIEN0
Bit76543210
GPIEN.x 0 = interrupt for P1.x disabled
1 = interrupt for P1.x enabled
Table 15-4. GPIF – General-purpose Interrupt Flag Register
GPIF = 9DH Reset Value = 0000 0000B
Not Bit Addressable
GPIF7 GPIF6 GPIF5 GPIF4 GPIF3 GPIF2 GPIF1 GPIF0
Bit76543210
GPIF.x 0 = interrupt on P1.x inactive
1 = interrupt on P1.x active. Must be cleared by software.
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16. Serial Interface (UART)
The serial interface on the AT89LP3240/6440 implements a Universal Asynchronous
Receiver/Transmitter (UART). The UART has the following features:
•Full-duplex Operation
•8 or 9 Data Bits
•Framing Error Detection
•Multiprocessor Communication Mode with Automatic Address Recognition
•Baud Rate Generator Using Timer 1 or Timer 2
• Interrupt on Receive Buffer Full or Transmission Complete
The serial interface is full-duplex, which means it can transmit and receive simultaneously. It is
also receive-buffered, which means it can begin receiving a second byte before a previously
received byte has been read from the receive register. (However, if the first byte still has not
been read when reception of the second byte is complete, one of the bytes will be lost.) The
serial port receive and transmit registers are both accessed at the Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically
separate receive register. The serial port can operate in the following four modes.
•Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data
bits are transmitted/received, with the LSB first. The baud rate is programmable to 1/2 or 1/4
the oscillator frequency, or variable based on Time 1.
•Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
8data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in the Special
Function Register SCON. The baud rate is variable based on Timer 1 or Timer 2.
•Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
8data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th
data bit (TB8 in SCON) can be assigned the value of “0” or “1”. For example, the parity bit
(P, in the PSW) can be moved into TB8. On receive, the 9th data bit goes into RB8 in the
Special Function Register SCON, while the stop bit is ignored. The baud rate is
programmable to either 1/16 or 1/32 the oscillator frequency.
•Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0),
8data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the
same as Mode 2 in all respects except the baud rate, which is variable based on Timer 1 or
Timer 3 in Mode 3.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initi-
ated in the other modes by the incoming start bit if REN = 1.
16.1 Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes,
9data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit.
The port can be programmed such that when the stop bit is received, the serial port interrupt is
activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON.
The following example shows how to use the serial interrupt for multiprocessor communications.
When the master processor must transmit a block of data to one of several slaves, it first sends
out an address byte that identifies the target slave. An address byte differs from a data byte in
that the 9th bit is “1” in an address byte and “0” in a data byte. With SM2 = 1, no slave is
interrupted by a data byte. An address byte, however, interrupts all slaves. Each slave can
examine the received byte and see if it is being addressed. The addressed slave clears its SM2
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bit and prepares to receive the data bytes that follows. The slaves that are not addressed set
their SM2 bits and ignore the data bytes. See “Automatic Address Recognition” on page 97.
The SM2 bit can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if
SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received.
Notes:1.SMOD0 is located at PCON.6.
2. fosc = oscillator frequency. The baud rate depends on SMOD1 (PCON.7).
Table 16-1. SCON – Serial Port Control Register
SCON Address = 98HReset Value = 0000 0000B
Bit Addressable
SM0/FE SM1 SM2 REN TB8RB8T1 RI
Bit7 6543210
(SMOD0 = 0/1)(1)
Symbol Function
FE
Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set
regardless of the state of SMOD0.
SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received
9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =
1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.
In Mode 0, SM2 determines the idle state of the shift clock such that the clock is the inverse of SM2, i.e. when SM2 = 0
the clock idles high and when SM2 = 1 the clock idles low.
REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Mode 0, setting TB8
enables Timer 1 as the shift clock generator.
RB8In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode
0, RB8 is not used.
TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the
other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0 SM1 Mode Description Baud Rate(2)
000shift register fosc/2 or fosc/4 or Timer 1
0118-bit UART variable (Timer 1 or Timer 2)
1029-bit UART fosc/32 or fosc/16
1139-bit UART variable (Timer 1 or Timer 2)
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16.2 Baud Rates
The baud rate in Mode 0 depends on the value of the SMOD1 bit in Special Function Register
PCON.7. If SMOD1 = 0 (the value on reset) and TB8= 0, the baud rate is 1/4 of the oscillator
frequency. If SMOD1 = 1 and TB8=0, the baud rate is 1/2 of the oscillator frequency, as shown
in the following equation:
The baud rate in Mode 2 also depends on the value of the SMOD1 bit. If SMOD1 = 0, the baud
rate is 1/32 of the oscillator frequency. If SMOD1 = 1, the baud rate is 1/16 of the oscillator fre-
quency, as shown in the following equation:
16.2.1 Using Timer 1 to Generate Baud Rates
Setting TB8= 1 in Mode 0 enables Timer 1 as the baud rate generator. When Timer 1 is the
baud rate generator for Mode 0, the baud rates are determined by the Timer 1 overflow rate and
the value of SMOD1 according to the following equation:
The Timer 1 overflow rate normally determines the baud rates in Modes 1 and 3. When Timer 1
is the baud rate generator, the baud rates are determined by the Timer 1 overflow rate and the
value of SMOD1 according to the following equation:
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured
for either timer or counter operation in any of its 3 running modes. In the most typical applica-
tions, it is configured for timer operation in auto-reload mode (high nibble of TMOD = 0010B). In
this case, the baud rate is given by the following formula:
Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a
16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by
the following formula.
Table 16-2 lists commonly used baud rates and how they can be obtained from Timer 1.
Mode 0 Baud Rate
TB8 = 0
2SMOD1
4
-------------------- Oscillator Frequency×=
Mode 2 Baud Rate 2SMOD1
32
-------------------- Oscillator Frequency×=
Mode 0 Baud Rate
TB8 = 1
2SMOD1
4
-------------------- (Timer 1 Overflow Rate)×=
Modes 1, 3
Baud Rate
2SMOD1
32
-------------------- (Timer 1 Overflow Rate)×=
Modes 1, 3
Baud Rate
2SMOD1
32
-------------------- Oscillator Frequency
256 TH1()–[]
-------------------------------------------------------1
TPS1+
---------------------
××=
Modes 1, 3
Baud Rate
2SMOD1
32
-------------------- Oscillator Frequency
65536 RH1,RL1()–[]
---------------------------------------------------------
×1
TPS1+
---------------------
×=
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16.2.2 Using Timer 2 to Generate Baud Rates
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Under
these conditions, the baud rates for transmit and receive can be simultaneously different by
using Timer 1 for transmit and Timer 2 for receive, or vice versa. The baud rate generator mode
is similar to the auto-reload mode, in that a rollover causes the Timer 2 registers to be reloaded
with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. In this
case, the baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation:.
Table 16-3 lists commonly used baud rates and how they can be obtained from Timer 2.
Table 16-2. Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B)
Baud Rate fOSC (MHz) SMOD1
Timer 1
C/T Mode Reload Value
Mode 0: 1 MHz 4 0 X X X
Mode 2: 750K 12 1 X X X
62.5K 12 1 0 2 F4H
38.4K 11.059 0 0 2 F7H
19.2K 11.059 1 0 2 DCH
9.6K 11.059 0 0 2 DCH
4.8K 11.059 0 0 2 B8H
2.4K 11.059 0 0 2 70H
1.2K 11.059 0 0 1 FEE0H
137.5 11.986001F55CH
110 6 0 0 1 F958H
110 12 0 0 1 F304H
Table 16-3. Commonly Used Baud Rates Generated by Timer 2 (TPS = 0000B)
Baud Rate fOSC (MHz)
Timer 2
CP/RL2 C/T2 TCLK or RCLK Reload Value
62.5K 12 0 0 1 FFF4H
19.2K 11.059 0 0 1 FFDCH
9.6K 11.059 0 0 1 FFB8H
4.8K 11.059 0 0 1 FF70H
2.4K 11.059 0 0 1 FEE0H
1.2K 11.059 0 0 1 FDC0H
137.5 11.986 0 0 1 EAB8H
110 6 0 0 1 F2AFH
110 12 0 0 1 E55EH
Modes 1 and 3
Baud Rate
1
16
------ Oscillator Frequency
65536 RCAP2H,RCAP2L()–[]
--------------------------------------------------------------------------------- 1
TPS1+
---------------------
××=
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16.3 More About Mode 0
In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Serial
data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit-
ted/received, with the LSB first. Figure 16-1 on page 90 shows a simplified functional diagram of
the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the
oscillator frequency by setting/clearing the SMOD1 bit. However, changing SMOD1 has an
effect on the relationship between the clock and data as described below. The baud rate can
also be generated by Timer 1 by setting TB8. Table 16-4 lists the baud rate options for Mode 0.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX
Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse
between “write to SBUF” and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and
also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the
right, “0”s come in from the left. When the MSB of the data byte is at the output position of the
shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain “0”s. This condition flags the TX Control block to do
one last shift, then deactivate SEND and set TI.
Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next
clock phase. RECEIVE enables Shift Clock to the alternate output function line of P3.1. As data
bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the
right-most position arrives at the left-most position in the shift register, it flags the RX Control
block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
The relationship between the shift clock and data is determined by the combination of the SM2
and SMOD1 bits as listed in Table 16-5 and shown in Figure 16-2. The SM2 bit determines the
idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the
output data is stable for both edges of the clock, or just one.
Table 16-4. Mode 0 Baud Rates
TB8 SMOD1 Baud Rate
00 f
SYS/4
01 f
SYS/2
1 0 (Timer 1 Overflow) / 4
1 1 (Timer 1 Overflow) / 2
Table 16-5. Mode 0 Clock and Data Modes
SM2 SMOD1 Clock Idle Data Changed Data Sampled
0 0 High While clock is high Positive edge of clock
0 1 High Negative edge of clock Positive edge of clock
1 0 Low While clock is low Negative edge of clock
1 1 Low Negative edge of clock Positive edge of clock
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Figure 16-1. Serial Port Mode 0
INTERNAL BUS
fosc
INTERNAL BUS
TXD (SHIFT CLOCK)
RXD (DATA OUT)
TXD (SHIFT CLOCK)
RXD (DATA IN)
WRITE TO SBUF
SEND
SHIFT
TI
WRITE TO SCON (CLEAR RI)
SHIFT
RECEIVE
RI
“1“
÷2
TB8
0
1
TIMER 1
OVERFLOW
÷2
SMOD1
01
SM2