BC549C - DIOTEC SEMICONDUCTOR AG - Datasheet.Directory

This is information on a product in full production.

May 2018 DocID031526 Rev 1 1/25

STCH03

Offline PWM controller for low standby adapters

Datasheet - production data

Features

Advanced power management for ultra-low

standby power consumption (under 10 mW at

230 VAC)

Fully integrated primary side constant current

output regulation (CC)

650 V embedded HV start-up circuit with zero

power consumption.

Quasi-resonant (QR) zero-voltage-switching

(ZVS) operation

Accurate and adjustable output OVP with

options auto-restart (STCH03) or latched

(STCH03L) after fault

Output undervoltage protection (UVP) with

auto-restart

Input voltage feedforward compensation for

mains-independent CC regulation

Embedded thermal shutdown

Intelligent frequency jitter for EMI suppression

SO8 package

Applications

AC-DC chargers for smartphones, tablets,

camcorders and other handheld equipment

AC/DC adapters for STB, notebooks and

auxiliary power supplies

Quick charger

Figure 1. Typical application

SO8

Table 1. Device summary

Order codes Package Packaging

STCH03

SO8

Tube

STCH03L

STCH03TR

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Contents STCH03

2/25 DocID031526 Rev 1

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Pin connection and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1 Gate-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2 Frequency jittering for EMI reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.3 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.4 Zero current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . .11

6.5 Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.6 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.7 Voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.8 Burst-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.9 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.11 Output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.12 Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.13 Overcurrent protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DocID031526 Rev 1 3/25

STCH03 Description

1 Description

The STCH03 current-mode controller is designed for an offline quasi-resonant ZVS (zero-

voltage-switching at switch turn-on) flyback converter.

It combines a high-performance low-voltage PWM controller chip and a 650V HV start-up

cell in the same package.

The device features a unique characteristic: it is capable of providing constant output

current (CC) regulation using primary-sensing feedback. This eliminates the need for

dedicated current reference IC, as well as the current sensor, still maintaining quite accurate

output current regulation.

The quasi-resonant operation is achieved by means of a transformer demagnetization

sensing input that triggers the turn-on of the MOSFET, connected on the ZCD pin. This input

serves also as both output voltage monitor, to achieve mains-independent CC regulation

(line voltage feedforward), and to implement OVP and UVP.

The maximum switching frequency is top-limited below 167 kHz, so that at the medium-light

load a special function automatically lowers the operating frequency whilst still maintaining

the operation as close to ZVS as possible. At the very light load, the device enters a

controlled burst-mode operation that, along with the zero-power high-voltage start-up circuit,

the extremely low quiescent current of the device, helps minimize the residual input

consumption, thus meeting the requirements of the most stringent standards.

During the burst-mode operation the VDD supply voltage has to be guaranteed by optimum

application design. In any case, an innovative adaptive UVLO helps to minimize the issues

related to the fluctuations of the auxiliary biasing voltage with the output load, due to

parasitic capacitance of the transformer and further reducing the IC's bias consumption.

In addition to these functions that optimize power handling under different operating

conditions, the device also offers the output overvoltage protection (OVP), overtemperature

protection (OTP), hiccup-mode protection that is invoked when the transformer saturates or

the secondary diode fails short and the output UVP protection that limits the average output

current in case of the output short-circuit. All the protections are auto-restart mode, except

the OVP protection, that can be internally selected to be auto-restart or latched mode.

The embedded leading-edge blanking on the current sense input for greater noise immunity

completes the equipment of this device.

Thermal data STCH03

4/25 DocID031526 Rev 1

2 Thermal data

3 Absolute maximum ratings

Table 2. Thermal data

Symbol Parameter Max. value Unit

Rth j-amb Thermal resistance, junction to ambient 150 °C/W

Table 3. Absolute maximum ratings

Symbol Pin Parameter Value Unit

VHV 1 Voltage range (referred to GND) -0.3 to 650 V

IHV 1 Charging current Self-limited mA

- 3 to 6 Analog inputs and outputs -0.3 to 3.6 V

IZCD 4 Zero current detector current ± 3 mA

IGD 6 Output totem pole peak current Self-limited -

VDD 8 Supply voltage (ICC < 25 mA) Self-limited V

IDD 8 Device supply current + internal Zener capability 25 mA

TJJunction temperature range -40 to 150 °C

TSTG Storage temperature -55 to 150 °C

DocID031526 Rev 1 5/25

STCH03 Pin connection and functions

4 Pin connection and functions

Figure 2. Pin connection (top view)

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Table 4. Pin functions

No. Name Function

1HV

High-voltage start-up. This pin is able to withstand 650 V and is tied directly to the rectified mains

voltage. When the voltage on the pin reaches the HVSTART voltage (50 V typ.) a 7 mA internal

current source charges the capacitor connected between VDD and GND to start-up the IC. When the

voltage on the VDD pin reaches the turn-on threshold (17 V typ.) the generator is shut down.

2 NC Not internally connected. Provision for clearance on the PCB to meet safety requirements.

3FB

Control input for duty cycle control. A voltage set 65 mV below the threshold VFBB activates the

burst-mode operation. A level close to the threshold VFBH means that we are approaching the cycle-

by-cycle overcurrent set point.

4ZCD

The transformer demagnetization sensing for quasi-resonant operation and input/output voltage

monitor. A negative-going edge triggers the MOSFET turn-on. The current sourced by the pin during

the MOSFET ON time is monitored for an image of the input voltage to the converter, in order to

compensate the internal delay of the current sensing circuit and achieve a CC regulation

independent of the mains voltage. At the same time the pin voltage is sampled-and-held right at the

end of the transformer demagnetization to get an accurate image of the output voltage to be used for

overvoltage protection (OVP) and undervoltage protection (UVP) sensing. Please note that

maximum IZCD sink/source current must not exceed 3 mA over the entire voltage range. No

capacitor is allowed between the pin and the auxiliary winding of the transformer.

5 SENSE

Input to the PWM comparators. The current flowing in the MOSFET is sensed through a resistor

connected between the pin and GND. The resulting voltage is compared with an internal reference

(0.75 V typ.) to determine MOSFET turn-off. The pin is equipped with 380 ns blanking time after the

gate-drive output goes high for improved noise immunity. If a second comparison level located at

1 V, is exceeded, the IC stops and restarts after VDD has dropped below VDDR (4.5 V typ.).

6GND

Circuit ground reference and current return for both the signal part of the IC and the gate-drive. All of

the ground connections of the bias components should be tied to an interconnect going to this pin

and kept separate from any pulsed current return.

7 GD Gate-driver with the totem pole output stage for the external power MOSFET.

Supply voltage of the device. An electrolytic capacitor, connected between this pin and ground, is

initially charged by the internal high-voltage start-up generator. It is recommended to place a small

bypass capacitor (0.1 µF typ.) connected between the pin and GND might be useful to get a clean

bias voltage for the signal part of the IC. To improve the ruggedness of the pin during electrical fast

transient events, an RC low-pass filter can be also connected on the pin.

Electrical characteristics STCH03

6/25 DocID031526 Rev 1

5 Electrical characteristics

Tj = - 25 °C to 125 °C, VDD = 14 V(a), unless otherwise specified

a. Adjust VDD above VDD-ON start-up threshold before settings to 14 V.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

HIGH-VOLTAGE START-UP GENERATOR

VHV HV voltage IHV < 2 µA, Tj = 25 °C - - 650 V

ILEAKAGE HV leakage current VHV = 400 V, Tj = 25 °C - - 1 µA

HVSTART HV start voltage - 40 50 60 V

ICHARGE VDD startup charge current

VHV > HVSTART

; VDD VDD_FOLD 0.3 0.6 0.9

VHV > HVSTART

; 2 V < VDD < VDDOn 4.5 7 10.3

VDD-FOLD VDD foldback threshold VHV > HVSTART 11.42 V

SUPPLY VOLTAGE

VDD Operating range After turn-on 11.5 - 23 V

VDD-ON Turn-on threshold - 15.7 17 18.3 V

VDD-OFF Restart threshold VFB > VFBF 91011V

VDD-UVLO UVLO threshold

VFB > VFBF 8.55 9.5 10.45 V

VFB < (VFBB - 65 mV) 6.75 7.5 8.25 V

VDDR VDD restart voltage (falling)

After protection tripping - 4.5 -

In burst-mode - 3.2 -

VZVZ clamping voltage IDD = 25 mA 23 - 26.5 V

SUPPLY CURRENT

IQQuiescent current Burst operation - 290 335 µA

IDD Operating supply current CGATE = 1 nF, FSW = 100 Khz - 2.5 2.9 mA

IDD-FAULT Fault quiescent current OCP, OVP, UVO, OTP - 330 420 µA

START-UP TIMER AND FREQUENCY LIMIT

TSTART Start timer period - - 220 - µs

FLIM_MAX Max. internal frequency limit - 145 167 196 kHz

ZERO CURRENT DETECTOR

IZCDB Input bias current VZCD = 0.1 to 2.7 V - - 1 µA

VZCDH Upper clamp voltage IZCD = 1 mA 2.7 3 3.5 V

VZCDL Lower clamp voltage IZCD = - 1 mA -90 -60 -30 mV

VZCDA Arming voltage Positive-going edge 100 110 120 mV

DocID031526 Rev 1 7/25

STCH03 Electrical characteristics

VZCDT Triggering voltage Negative-going edge 50 60 70 mV

TBLANK

Trigger blanking time after MOSFET

turn-on

VFB  1.65 V 4.3 5.7 7.1

µs

VFB = 0.6 V 27.2 32 36.8

TD-ON Turn-on delay time after triggering VGATE = 6 V, CGATE = 1 nF - 270 - ns

TFORCE Force turn-on time after blanking - 5.1 6 6.9 µs

LINE FEEDFORWARD

RFF Equivalent feedforward resistor IZCD = 1 mA 60 70 80 

GATE-DRIVER

VGDL Output high voltage

VDD = 8.5 V; IGATE = 5 mA 7 - -

IGATE = 5 mA 10.5 13 -

TRISE Rising time CGATE = 1 nF 70 110 150 ns

TFALL Falling time CGATE = 1 nF 20 40 60 ns

VGDL Output low voltage IGD-SINK = 50 mA - - 1 V

FEEDBACK INPUT

VFBH Upper saturation - - 3.45 - V

HFB Current sense gain - 3.22 3.29 3.36 -

IFB Feedback source current - 70 100 130 µA

RFB Dynamic feedback resistor - 25 30 41 k

VFBR Frequency reduction threshold - 1.4 1.65 1.9 V

VFBB Burst-mode threshold (1) Voltage falling 0.54 0.6 0.66 V

VFBF Exit burst-mode threshold (1) 0.64 0.72 0.8 V

VHYST Burst-mode hysteresis - 50 65 75 mV

CURRENT REFERENCE

VREFx Maximum value Internal, not measured - 0.8 - V

KICurrent loop gain - 0.19 0.2 0.21 V

OVERVOLTAGE PROTECTION

VOVP OVP threshold - 2.375 2.5 2.625 V

NOVP

Consecutive cycles for OVP

triggering VOVP = 2.5 V - 4 - -

UNDERVOLTAGE PROTECTION

VUVP UVP threshold - 0.522 0.55 0.578 V

TUVP UVP blanking time - 12 20 28 ms

NUVP

Consecutive cycles for UVP

triggering VUVP = 0.55 V - 4 - -

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Electrical characteristics STCH03

8/25 DocID031526 Rev 1

CURRENT SENSE

TLEB Leading-edge blanking (1) VGATE = 6 V, COUT = 1 nF 270 380 490 ns

TDGate delay-to-output (1) VGATE = 6 V, COUT = 1 nF - - 150 ns

VCSx Max. clamp value (1) dVCS/dt = 200 mV/µs 0.7 0.75 0.8 V

VOCP Hiccup-mode OCP level (1) 0.95 1 1.05 V

VSENSE_BM Minimum burst-mode sense voltage - - 72 - mV

FREQUENCY JITTERING

FDModulation frequency - - 9 - kHz

VZCDH Modulation duty cycle - - 50 - %

Ipk Peak current change - - 5 - %

THERMAL SHUTDOWN

TSD Thermal shutdown temperature Guaranteed by design and

characterization 135 150 165 °C

THYST Thermal shutdown hysteresis Guaranteed by design and

characterization -30-°C

1. Adjust VDD above VDD-ON start-up threshold before settings to 14 V.

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

DocID031526 Rev 1 9/25

STCH03 Application information

6 Application information

The STCH03 is an off-line CC-mode primary sensing switching controller, specific for offline

quasi-resonant ZVS (zero-voltage-switching at switch turn-on) flyback converters.

Depending on converter's load condition, the device is able to work in different modes (see

Figure 3):

1. QR mode at heavy load. Quasi resonant operation is achieved by synchronizing the

MOSFET turn-on to the transformer demagnetization by detecting the resulting

negative-going edge of the voltage across any winding of the transformer. Then the

system works close to the boundary between discontinuous (DCM) and continuous

conduction (CCM) of the transformer. As a result, the switching frequency will be

different for different line/load conditions (see the hyperbolic-like portion of the curves

in Figure 3). The minimum turn-on losses, low EMI emission and safe behavior in

short-circuit are the main benefits of this kind of operation.

2. Valley-skipping mode at medium/ light load. Depending on voltage on the FB pin, the

device defines the maximum operating frequency of the converter. As the load is

reduced the MOSFET turn-on will no longer occur on the first valley but on the second

one, the third one and so on. In this way the switching frequency will no longer

increase.

3. Burst-mode with no or very light load. When the load is extremely light or disconnected,

the converter will enter a controlled on/off operation with constant peak current.

Decreasing the load will then result in frequency reduction, which can go down even

reduce to a few hundred hertz, thus minimizing all frequency-related losses and

making it easier to comply with energy saving regulations or recommendations. As the

peak current is very low, no issue of audible noise arises.

Figure 3. Multi-mode operation of STCH03

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Application information STCH03

10/25 DocID031526 Rev 1

6.1 Gate-driver

The gate-driver of the power MOSFET is designed to supply a controlled gate current during

both turn-on and turn-off in order to minimize the common mode EMI. Under UVLO

conditions an internal pull-down circuit holds the gate low in order to ensure that the power

MOSFET cannot be turned on accidentally.

6.2 Frequency jittering for EMI reduction

Although the STCH03 works in the QR mode and the switching frequency is already

modulated at twice the mains frequency, a dedicated frequency jittering circuitry is

embedded inside the IC to further reduce the EMI filtering. A proprietary frequency jitter

technique is implemented in the controller, based on the injection of a modulating signal at

9 kHz (above the feedback loop bandwidth) with the 50% duty cycle on the current sense

signal: this signal is a square waveform that modulates the amplitude of the peak primary

current. The percentage of this amplitude is set at 5% as default. As the peak current

reduces with decreasing load levels, the effect of this modulation automatically attenuates at

lower loads, where the energy of EMI noise is highly reduced.

6.3 High voltage startup generator

Based on a 650 V rated depletion MOSFET embedded into the start-up cell, the HV current

generator is supplied through the DRAIN pin and is enabled only if the voltage on the HV pin

is higher than the HVSTART threshold (50 V typical value).

When the power is applied to the circuit and the voltage on the input bulk capacitor is high

enough, the HV generator is sufficiently biased to start operating, thus it will draw the current

ICHARGE (7 mA typ. value) through the HV pin and will charge the capacitor connected

between the VDD pin and ground. This charging current will be reduced at 0.6 mA in case

the voltage on VDD is lower than VDD_FOLD, in order to prevent exceeding the IC

dissipation when the pin is accidentally shorted to ground.

As the VDD voltage reaches the start-up threshold (17 V typ.) the chip starts operating and

the control logic disables the HV generator.

While the generator is off, there are virtually no losses across the HV start-up cell, except a

few hundred nA of leakage current through the depletion MOSFET.

The IC is powered by the energy stored in the VDD capacitor until the auxiliary winding

develops a voltage high enough to sustain the operation.

At converter power-down the system will lose regulation as soon as the input voltage falls

below HVSTART

. This prevents the converter restarting and ensures the monotonic output

voltage decay at system power-down.

To increase the ruggedness of the HV pin during electrical fast transient events it is

suggested a 47 k resistor between the HV pin and the mains.

DocID031526 Rev 1 11/25

STCH03 Application information

6.4 Zero current detection and triggering block

The zero current detection (ZCD) and triggering blocks switch on the power MOSFET if a

negative-going edge falling below 60 mV is applied to the ZCD pin. To do so, the triggering

block must be previously armed by a positive-going edge exceeding 110 mV.

This feature is used to detect transformer demagnetization for the QR operation, where the

signal for the ZCD input is obtained from the transformer auxiliary windings used also to

supply the IC.

The triggering block is blanked after MOSFET turn-on to prevent any negative-going edge

that follows leakage inductance demagnetization from triggering the ZCD circuit

erroneously.

The switching frequency is top-limited below 167 kHz.

To prevent the tendency of the system to excessively increase the frequency at the light

load and high input voltage, a variable blanking time function is implemented.

This blanking time is dependent on the voltage on the FB pin: it is TBLANK = 32 µs

for VFB = 0.6 V, and decreases linearly down to TBLANK = 5.7 µs for VFB  1.65 V. In this

way, the switching frequency is progressively reduced, resulting in lower frequency-related

losses.

If the demagnetization completes - hence a negative-going edge appears on the ZCD pin -

after a time exceeding time TBLANK from the previous turn-on, the MOSFET will be turned

on again, with some delay to ensure minimum voltage at turn-on (“QR mode”).

If, instead, the negative-going edge appears before TBLANK has elapsed, it will be ignored

and only the first negative-going edge after TBLANK will turn-on the MOSFET. In this way one

or more drain ringing cycles will be skipped (“valley-skipping mode”) and the switching

frequency will be prevented from exceeding 1/TBLANK.

The blanking time limits and the mode of operation are reported in Figure 4.

A forced turn-on time function is implemented in case the residual oscillation on ZCD are not

enough to trigger again the switching, during the low frequency operation: the power

MOSFET is forced to turn-on 6 µs (typical value) after the blanking time is elapsed.

A starter block is also used to start-up the system when the signal on the ZCD pin is not high

enough to trigger the MOSFET.

After the first few cycles initiated by the starter, as the voltage developed across the auxiliary

winding becomes large enough to arm the ZCD circuit, the MOSFET's turn-on will start to be

locked to transformer demagnetization, hence setting up the QR operation.

The starter is activated also when the IC is in CC regulation and the output voltage is not

high enough to allow the ZCD triggering.

The voltage on the ZCD pin is both top and bottom limited by a double clamp. The upper

clamp is typically located at 3 V, while the lower clamp is located at -60 mV. The interface

between the pin and the auxiliary winding will be a resistor divider. Its resistance ratio as

well as the individual resistance values will be properly chosen (see Section 6.10:

Overvoltage protection on page 16 and Section 6.7: Voltage feedforward block on page 14).

Please note that the maximum IZCD sink/source must not exceed ± 3 mA (AMR) in all

the input voltage range conditions (88 - 265 VAC). No capacitor is allowed between

the ZCD pin and the auxiliary winding of the transformer.

Application information STCH03

12/25 DocID031526 Rev 1

Note that when the system operates in the valley skipping-mode, uneven switching cycles

may be observed under some line/load conditions, due to the fact that the OFF-time of the

MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time

needed for cycle-by-cycle energy balance may fall in between. Thus one or more longer

switching cycles will be compensated by one or more shorter cycles and vice versa.

However, this mechanism is absolutely normal and there is no appreciable effect on the

performance of the converter or on its output voltage.

Figure 4. Frequency limits and modes of operations

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STCH03 Application information

6.5 Constant voltage operation

The device is specific for the secondary feedback. The FB pin is connected to an

optocoupler which transmits the error signal from the regulation loop located on the

secondary side of the converter. Typically, a TS431 is used as a voltage reference.

The FB pin is driven directly by the phototransistor's collector to modulate the duty cycle.

The voltage coming from the FB pin is compared with the voltage across the sense resistor,

controlling the peak drain current cycle-by-cycle.

Figure 5. Voltage control principle: internal schematic

6.6 Constant current operation

The voltage of the auxiliary winding is fed into the internal CC block trough the ZCD pin to

achieve an output constant current regulation.

Equation 1 can be used to define the output current in the CC-mode.

Equation 1

This formula shows that the average output current does not depend anymore on the input

or the output voltage, neither on transformer inductance values. The external parameters

defining the output current are the transformer ratio and the sense resistor RSENSE. The

current loop gain KI is internally defined.

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Application information STCH03

14/25 DocID031526 Rev 1

6.7 Voltage feedforward block

The current control structure uses the internal voltage VC to define the output current,

according to Equation 1. Actually, the CC comparator will be affected by an internal

propagation delay Td, which will switch off the MOSFET with a peak current higher than the

foreseen value.

The STCH03 device implements a line feedforward function, which solves the issue by

introducing an input voltage dependent offset on the current sense signal, in order to adjust

the cycle-by-cycle current limitation.

The external schematic configuration is shown in Figure 6.

Figure 6. Feedforward compensation: internal schematic

The RZCD resistor can be calculated as follows:

Equation 2

where RFF is an internal parameter, defined in Table 5: Electrical characteristics on page 6.

In this case the peak drain current does not depend on input voltage anymore.

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DocID031526 Rev 1 15/25

STCH03 Application information

6.8 Burst-mode operation

When the voltage at the FB pin fall to 65 mV below VFBB, the burst-mode operation starts:

the MOSFET is turned OFF in order to reduce the consumption. After the MOSFET turns

OFF, the FB pin voltage, as a result of the feedback reaction to the energy delivery stop,

increase up to VFBB and the device starts switching again.

During these switching cycles the max peak current is fixed (about VSENSE_BM/RSENSE) by

an internal clamp inside the current limit circuit. The effect of the burst-mode operation is to

reduce the equivalent switching frequency, which can go down even to few hundred hertz,

minimizing all frequency related losses and making it easier to comply with energy saving

regulations.

This kind of operation, shown in the timing diagrams of Figure 7 along with the other ones, is

audible noise-free since the peak current is low.

Figure 7. Burst-mode operation

Application information STCH03

16/25 DocID031526 Rev 1

6.9 Adaptive UVLO

A major problem when optimizing a converter for minimum no-load consumption is that the

voltage generated by the auxiliary winding under these conditions falls considerably as

compared even to a few mA load. This very often causes the supply voltage VDD of the

control IC to drop below the UVLO threshold so that the operation becomes intermittent,

which is undesired.

Furthermore, this must be traded off against the need of generating a voltage not exceeding

the maximum allowed by the control IC at full load but low enough to reduce the bias losses

as much as possible.

To help the designer overcome this problem the device, besides reducing its own

consumption during the burst-mode operation, also features a proprietary adaptive UVLO

function.

It consists of shifting the VDD-UVLO threshold downwards at the light load, namely when the

voltage at the pin FB falls 65 mV below the burst-mode threshold VFBB (0.6 V typ.), to have

more headroom.

To prevent any malfunction the normal threshold (9.5 V typ.) is re-established when the

voltage at the pin FB exceeds the exit burst-mode threshold VFBF

The normal UVLO threshold ensures that at full medium-heavy loads the MOSFET will be

driven with a proper gate-to-source voltage. The mode of the operation is reported in

Figure 7.

6.10 Overvoltage protection

The overvoltage function of the STCH03 device monitors the voltage on the ZCD pin during

MOSFET's OFF-time, where the voltage generated by the auxiliary winding tracks the

converter output voltage. If the voltage applied to the pin exceeds an internal 2.5 V

reference, a comparator is triggered, an overvoltage condition is assumed and the device is

shut down.

Once RZCD is fixed by feedforward considerations (see Section 6.7: Voltage feedforward

block), it is possible to calculate the value of the ROVP resistor to activate the OVP

protection for a certain output voltage level, VOUT-OVP:

Equation 3

where VOVP is the internal OVP threshold, NSEC and NAUX are the secondary and auxiliary

turns number respectively.

To reduce sensitivity to noise and prevent the protection from being erroneously activated,

the OVP comparator must be triggered for four consecutive oscillator cycles before the

STCH03 is stopped. A counter, which is reset every time the OVP comparator is not

triggered in one oscillator cycle, is provided to this purpose.

The IC is provided with an internal bit option, intended to select the OVP function to work in

the auto-restart mode or in the latch mode. This choice is taken during the final test and the

mode of operation cannot be changed anymore by the final user.

ROVP

VOVP

NAUX

NSEC

-------------- VOUT OVP–VOVP

–

---------------------------------------------------------------------- RZCD

=

DocID031526 Rev 1 17/25

STCH03 Application information

In the auto-restart mode, once the protection is tripped, the switching activity is stopped and

the condition is maintained until VDD goes below to VDDR restart voltage and then rises-up

again to VDD-ON. Ultimately, this will result in a low-frequency intermittent operation (hiccup-

mode operation), see Figure 8.

In the latched mode the protection is maintained until the input main is removed. During this

time the HV generator is activated periodically to recycle the supply voltage between

VDD-ON and VDD-OFF

. And the condition is indefinitely maintained until the AC main is

removed and the VDD voltage falls below VDDR which resets the latch.

The latched OVP protection operation is shown in the time diagram of Figure 9.

Figure 10 illustrates the timing of the function.

Figure 8. OVP timing diagram with auto-restart option

Figure 9. OVP timing diagram with latched option

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Application information STCH03

18/25 DocID031526 Rev 1

Figure 10. OVP function: timing diagram

6.11 Output undervoltage protection

The output undervoltage function (UVP) of the STCH03 device protects the converter in

case of the output short-circuit or for the CC-mode operation at low output voltage, forcing

the system in the hiccup-mode.

The voltage on the ZCD at the end of the transformer's demagnetization is monitored and

compared with an internal threshold, VUVP (0.55 V typ.). If the value goes down to the

threshold, an output undervoltage condition is assumed and the device enters in hiccup-

mode protection.

Similar to OVP, also the UVP protection must be triggered for four consecutive oscillator

cycles before the STCH03 is stopped, in order to provide better noise immunity against false

protection triggering.

A 20 ms (typ. value) UVP blanking time is provided to delay the protection during converter

power-on and at any restart after protection, to avoid erroneous UVP triggering during the

output voltage rise time.

Note that OVP and UVP cannot be defined independently but are in tracking between they.

Once the OVP is fixed using Equation 3, the output voltage level to activate the UVP

(VOUT-UVP) is:

Equation 4

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ROVP

------------------------------------



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DocID031526 Rev 1 19/25

STCH03 Application information

6.12 Soft-start and starter block

The soft-start feature is automatically implemented by the constant current block, as the

primary peak current will be limited from the voltage on the internal CC block capacitor.

During the start-up, as the output voltage is zero, the IC will start in the CC-mode with no

high peak current operations. In this way the voltage on the output capacitor will increase

slowly and the soft-start feature will be ensured.

6.13 Overcurrent protection (OCP)

The device is also protected against the short-circuit of the secondary rectifier, the short-

circuit on the secondary winding or a hard-saturated flyback transformer. A comparator

monitors continuously the voltage on the RSENSE and activates protection circuitry if this

voltage exceeds the VOCP value (1 V typ. value).

To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the

first time the comparator is tripped the protection circuit enters a “warning state”. If in the

subsequent switching cycle the comparator is not tripped, a temporary disturbance is

assumed and the protection logic will be reset in its idle state; if the comparator trips again a

real malfunction is assumed and the device will be stopped.

Once the protection is tripped, the condition is maintained until VDD goes below VDDR restart

voltage. While it is disabled, however, no energy is coming from the auxiliary winding; hence

the voltage on the VDD capacitor will decay and cross the UVLO threshold after some time,

which clears the latch. The internal start-up generator is still off, then the VDD voltage still

needs to go below its restart voltage before the VDD capacitor is charged again and the

device restarted. Ultimately, this will result in a low-frequency intermittent operation (hiccup-

mode operation), with very low stress on the power circuit. This special condition is

illustrated in the timing diagram of Figure 11.

Figure 11. Hiccup-mode OCP: timing diagram

Application information STCH03

20/25 DocID031526 Rev 1

6.14 Thermal shutdown protection

When the IC temperature exceeds the shutdown threshold, TSD (150 °C typ.) the device is

shut down to prevent any dangerous overheating for the system and the VDD pin will be

continuously recycled between VDD-ON and VDDR to keep the controller alive.

Once the temperature falls THYST below restart time the IC will start again, unless the

voltage on the VDD pin is below VDD-UVLO. In this case the pin is discharger down to VDDR

and recycled to VDD-ON before to start again.

This operation is shown in Figure 12.

Figure 12. OTP timing diagram with auto-restart option

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STCH03 Application information

Figure 13. Typical configuration

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Package information STCH03

22/25 DocID031526 Rev 1

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

7.1 SO8 package information

Figure 14. SO8 package outline

40

DocID031526 Rev 1 23/25

STCH03 Package information

Table 6. SO8 package mechanical data

Symbol

Dimensions (mm )

Note

Min. Typ. Max.

A - - 1.75 -

A1 0.10 - 0.25 -

A2 1.25 - - -

b 0.28 - 0.48 -

c 0.17 - 0.23 -

D 4.80 4.90 5.00 (1)

1. The dimension “D” does not include the mold flash, protrusions or gate burrs. The mold flash, protrusions

or gate burrs shall not exceed 0.15 mm in total (both sides).

E 5.80 6.00 6.20 -

E1 3.80 3.90 4.00 (2)

2. The dimension “E1” does not include the interlead flash or protrusions. The interlead flash or protrusions

shall not exceed 0.25 mm per side.

e - 1.27 - -

h 0.25 - 0.50 -

L 0.40 - 1.27 -

L1 - 1.04 - -

k 0 - 8

(3)

3. Degrees.

ccc - - 0.10 -

Revision history STCH03

24/25 DocID031526 Rev 1

8 Revision history

Table 7. Document revision history

Date Revision Changes

02-May-2018 1 Initial release.

DocID031526 Rev 1 25/25

STCH03

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