CY7C1301A - Cypress Semiconductor

256K X 36 Dual I/O, Dual Address Synchronous SRAM

CY7C1301A

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05076 Rev. *B Revised April 3, 2002

Features

• Fast Clock Speed: 100 and 83 MHz

• Fast Access Times: 5.0/6.0 ns Max.

• Single Clock Operat ion

• Single 3.3V –5% and +5% power supply VCC

• Separate VCCQ for output buffer

• Two Chip Enables for simple depth expansion

• Address, Data Input, CE1X, CE2X, CE1Y, CE2Y, PTX,

PTY, WEX, WEY, and Data Output Registers On-Chip

• Concurrent Reads and Writes

• Two bidirectional Data Buses

• Can be configured as separate I/O

• Pass-Through feature

• Asynchronous Output Enables (OEX, OEY)

• LVTTL-Com pati ble I/O

• Self-Timed write

• Automa tic power-down

• 176-Pin TQFP Package

Functional Description

The CY7C1301A SRAM integrates 262,144 x 36 SRAM cells

with advanced synchronous peripheral circuitry. It employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1301A allows the user to concurrently perform

reads, writes, or pass-through cycles in combination on the

two data ports. The two ad dress po rts (AX, AY) determ ine the

read or write locations for their respective data ports (DQX,

DQY).

All input pins except Output Enable pins (OEX, OEY) are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, depth-expansion Chip Enables

(CE1X, CE2X, CE1Y and CE2Y), Pass-Through controls (PTX

and PT Y), and Read-Write control (WEX and WEY).

The pass-through feature allows data to be passed from one

port to the other, in either direction. The PTX input must be

asserted to pass data from port X to port Y. The PTY will

likewise pass data from port Y to port X. A pass-through

operation takes precedence over a read operation.

For the c ase wh en AX and AY are the sa me, ce rtain p rotocol s

are foll owed. If both ports are read, the reads occur normally.

If one port is written and the other is read, the read from the

array will occur before the data is written. If both ports are

written, only the data on DQY will be written to the array.

The CY7C1301A operates from a +3.3V power supply. All

inputs and outputs are LVTTL-compatible. These dual I/O,

dual address synchronous SRAMs are well suited for ATM,

Ethernet switches, routers, cell/frame buffers, SNA switches

and shared memory applications.

The CY7C1 301A device needs one extra cycle after power for

proper pow e r on res et. Th e ex tra c ycle is nee ded afte r VCC is

stable on the device. This device is available in a 176-pin

TQFP package.

Note:

1. For 256 × 36 device, AX and AY are 18-bit-wide buses.

Data In

OEX#

*AX 256K/128K x 9 x 4

SRAM Array

DQX

CLK

18/17

CE1X#

CE2X

Address

Write X

Driver Sensing

Amplifiers Sensing

Amplifiers Write

Driver Write Y

Pass-Through

PTX

Data In

Chip Enable

DQY

WEX#

PTX#

AY*

WEY#

PTY#

PTX

CLK

18/17

OEY#

CE1Y#

CE2Y

Chip Enable

Logic Block Diagram[1]

CY7C1301A

Document #: 38-05076 Rev. *B Page 2 of 13

Selection Gu ide

-100 -83 Unit

Maximum Access Time 5.0 6.0 ns

Maximum Operating Current 500 430 mA

Maximum CMOS Standby Current 140 120 mA

Pin Configuration

132

VSS

46474849505152535455565758596061626364 656667686970717273747576777879808182838485868788

133

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

VSS

VCCQ

DQY35

DQX35

VSS

AY5

AX5

VSS

VCC

AX14

AY14

VCCQ

VSS

DQX1

DQY1

VSS

DQX0

DQY0

AX13

AY13

AX12

AY12

AX11

AY11

AX10

AY10

AY4

AX4

AY3

AX3

AY2

AX2

AY1

AX1

AY0

AX0

DQY34

DQX34

DQX20

DQY20

VSS

VCCQ

DQX21

DQY21

DQX22

DQY22

VSS

VCCQ

DQX23

DQY23

DQX24

DQY24

VSS

VCCQ

DQX25

DQY25

DQX26

DQY26

VSS

VCC

DQY27

DQX27

DQY28

DQX28

VSS

VCCQ

DQY29

DQX29

DQY30

DQX30

VSS

VCCQ

DQY31

DQX31

DQY32

DQX32

VSS

VCCQ

DQY33

DQX33

VSS

DQX15

DQY15

VCCQ

VSS

DQX14

DQY14

DQX13

DQY13

VCCQ

VSS

DQX12

DQY12

DQX11

DQY11

VCCQ

VSS

DQX10

DQY10

DQX9

DQY9

VCC

VSS

DQY8

DQX8

DQY7

DQX7

VCCQ

VSS

DQY6

DQX6

DQY5

DQX5

VCCQ

VSS

DQY4

DQX4

DQY3

DQX3

VCCQ

VSS

DQY2

DQX2

VSS

VCCQ

DQY18

DQX18

AX6

AY6

AX7

AY7

VCC

VSS

AX8

AY8

AX9

VCC

VSS

DQX16

DQY16

VSS

DQX17

DQY17

AY9

AX17*

AY17*

PTY#

PTX#

WEY#

WEX#

CE2X

CE1X#

OEY#

OEX#

VSS

CLK

DQY19

DQX19

AX16

AY16

AX15

AY15

CE2Y

CE1Y#

176-pin TQFP

CY7C1301A

Document #: 38-05076 Rev. *B Page 3 of 13

Pin Definitions (176-pin TQFP)

Pin Name I/O Pin Description

AX0–AX1

7Input-

Synchronous Synchronous Address Inputs of Port X: Do not allow address pins to float.

AY0–AY17 Input-

Synchronous Synchronous Address Inputs of Port Y: Do not allow address pins to float.

WEX Input-

Synchronous Read Write of Port X: WEX signal is a s yn ch rono us i npu t t hat identifies w he the r th e c urrent

loaded cycle is a Read or Write operation.

WEY Input-

Synchronous Read Write of Port Y: WEY signal is a synch rono us input that identifi es whet her the current

loaded cycle is a Read or Write operation.

PTX Input-

Synchronous Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input

to Port Y output.

PTY Input-

Synchronous Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input

to Port X output.

OEX Input Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is

HIGH, the DQXx pins are in high-impedance state.

OEY Input Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is

HIGH, the DQYx pins are in high-impedance state.

DQX0–

DQX35 Input/

Output Data Inputs/Outputs of Port X: Both the data inpu t path a nd data o utput path are r egistered

and triggered by the rising edge of CLK.

DQY0–

DQY35 Input/

Output Data Inputs/Outputs o f Port Y : Both the data i nput path and data o utput path are registered

and triggered by the rising edge of CLK.

CLK Input-

Synchronous Clock: This is the clock input to this device. Except for OEX and OEY, all timing references

of the address, data in, and all control signals for the device are made with respect to the rising

edge of CLK.

CE1X Input-

Synchronous Synchronous Ac tive LOW Chip Enable Port X: CE1X is used with CE 2X to en abl e Po rt X

of this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for

Port X.

CE2X Input-

Synchronous Synchronous Ac tive HIGH Chip Enable Port X: CE2X is used wi th CE1X to enable Port X

of this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for

Port X.

CE1Y Input-

Synchronous Synchronous Act ive LO W Chi p Enab le Port Y: CE1Y i s us ed with CE 2Y to ena ble Port Y

of this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for

Port Y.

CE2Y Input-

Synchronous Synchronous Activ e HIGH Chip En able Po rt Y: CE2Y is used with CE1Y to enab le Por t Y

of this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for

Port Y.

VCC Supply Power Supply: +3.3V –5% and +5%.

VSS Ground Ground: GND.

VSS Ground Ground: GND. No chip current flows through these pins. However, user needs to connect

GND to these pins. Pins 140 and 141 are VSS for 128K × 36 device.

VCCQ I/O Supply Output Buffer Supply: +3.3V –5% and +5%.

NC –No Connect: These signals are not internally connected. User can connect them to VCC, VSS,

or any signal lines or simply leave them floating.

CY7C1301A

Document #: 38-05076 Rev. *B Page 4 of 13

Cycle Descripti on Truth Table[2, 3, 4, 5, 6, 7, 8, 9]

Operation CE1X CE2X CE1Y CE2Y WEX WEY PTX PTY

Deselect Cycl e H X H X X X X X

Desele ct Cycle X L X L X X X X

Write Port X L HXX0XXX

Write Port Y X X L H X 0 X X

Pass-through from X to Y L H L H X X 0 X

Pass-through from Y to X L H L H X X X 0

Read Port X L H X X 1 X 1 1

Read Port Y X XLHX111

Notes:

2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.

4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For a Write and Pass-through operation following a READ

operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data

hold time.

5. Operation number 3–6 can be used in any combination.

6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined.

7. Operation number 5 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.

8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operations have higher priority over a Read operation.

9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

CY7C1301A

Document #: 38-05076 Rev. *B Page 5 of 13

Maximum Ratings

(Abov e wh ic h th e useful lif e m ay be im pa ired . Fo r us er gui de-

lines, not tested.)

Storage Temperature .....................................−55°C to +125°C

Ambient Temperature with

Pow er Applied.................................................... −10°C to +85°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

DC Voltage Applied to Outputs

in High Z State[10]....................................−0.5V to VCCQ + 0.5V

DC Input Voltage[10]................................−0.5V to VCCQ + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... >1601V

(per MIL-STD-883, Method 3015)

Latch-Up Current................................................... > 200 mA

Operating Range

Range Ambient Tempe r ature[11] VDD/VDDQ

Commercial 0°C to +70°C 3.3V ± 5%

Electri cal Characteristics Over the Operating R ange

Parame-

ter Description Test Conditions Min. Max. Unit

VDD Power Supply V oltage 3.135 3.465 V

VDDQ I/O Supply Voltage 3.135 3.465 V

VOH Output HI GH Volt age VDD = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Volta ge VDD = Min., IOL = 8.0 mA 0.4 V

VIH Input HIGH

Voltage[12] 2.0 VCC + 0.5V V

VIL Input LO W Voltage[13] −0.5 0.8 V

IXInput Load Current GND ≤ VIN ≤ VDDQ −5 5 µA

IOZ Output Lea ka ge

Current GND ≤ VIN ≤ VDDQ, Output Dis abl ed −5 5 µA

ICC VDD Operating

Supply VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 10.0 ns cycle 100 MHz 500 mA

12.0 ns cycle 83 MHz 430 mA

ISB Automatic CE

Power-Down

Current—CMOS

Inputs

Max. VDD, Device Deselected[14],

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

10.0 ns cycle100 MHzs 140 mA

12.0 ns cycle 83MHz 120 mA

Capacitance[15]

Parameter Description Te st Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.3V,

VCCQ = 3.3V

8pF

CCLK Clock Input Capacitance 9pF

CI/O Input/Output Capacitance 8pF

Notes:

10. Minimum voltage equals –2.0V for pulse duration less than 20 ns.

11. TA is the case temperature.

12. Overshoot: V IH ≤ +6.0V for t ≤ tKC /2.

13. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.

14. “Device Deselected” means the device is in Power-down mode as defined in the truth table.

CY7C1301A

Document #: 38-05076 Rev. *B Page 6 of 13

AC Test Loads and Waveforms[16]

Thermal Resistance[15]

Description Test Conditions Symbol TQFP Typ. Units

Thermal Resistance

(Junction t o Ambient) (@200 lfm) Single-layer printed circuit board ΘJA 40 °C/W

Thermal Resistance

(Junction t o Ambient) (@200 lfm) Four-layer printed circuit board ΘJC 35 °C/W

Thermal Resistance

(Junction to Board) Bottom ΘJA 23 °C/W

Thermal Resistance

(Junction to Case) Top ΘJC 9°C/W

Notes:

15. Tested initially and after any design or process change that may affect these parameters.

16. AC test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in

part (a) of AC Test Loads.

3.0V

GND

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

ALL INP U T PULSES

1350B-2

OUTPUT

RL= 50Ω

Z0= 50Ω

VL= 1.5V

3.3V [16]

1 V/ns 1 V/ns

CY7C1301A

Document #: 38-05076 Rev. *B Page 7 of 13

Switching Characteristics Over the Op erating Range[16 , 17 , 18 ]

-100 -83

Parameter Description Min. Max. Min. Max. Unit

Clock tKC Clock cy cle time 10 12 ns

tKH Clock HIGH time 3.5 4.0 ns

tKL Clock LOW time 3.5 4.0 ns

Output Times

tKQ Clock to output valid 5.0 6.0 ns

tKQX Clock to output invalid 1.5 1.5 ns

tKQLZ Clock to output in Low-Z[19] 0 0 ns

tKQHZ Clock to output in High-Z[19] 3.0 3.0 ns

tOEQ OEX/OEY to output valid 5.0 6.0 ns

tOELZ OEX/OEY to output in Low-Z[19] 0 0 ns

tOEHZ OEX/OEY to output in High-Z[19] 3.0 3.0 ns

Set-up Tim es

tSAddresses, Controls and Data In 1.8 2.0 ns

Hold Ti mes

tHAddresses, Controls and Data In 0.5 0.5 ns

Notes:

17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV fr om ste ady -s tate

voltage.

18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

19. This parameter is sampled and not 100% tested.

20. CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y)

equals LOW.

CY7C1301A

Document #: 38-05076 Rev. *B Page 8 of 13

Switching Waveforms [20]

Read Cycle Timing from Both Ports (WEX, WEY, PTX, PTY HIGH)[19]

CLK

CE#

(See Note)

OEX#

DQX

OELZ

OEQ

1 43 65 87 9

Q(1) Q(2) Q(3) Q(5) Q(6) Q(7)

OEY#

DQY

Q(12) Q(13) Q(14) Q(16) Q(6) Q(7)

1312 1514 616 197 20

KQHZ

OEHZ

KQLZ

PORT X

PORT Y

CY7C1301A

Document #: 38-05076 Rev. *B Page 9 of 13

Switching Waveforms (continued)[20]

CLK

CE#

(See Note)

OEX#

DQX

1 43 65 87 9

D(3)

OEY#

DQY

1312 1514 65 1918 20

WEX#

WEY#

PORT X

PORT Y

D(2) D(4) D(8) D(9)

D(14) D(15) D(19)D(5) D(6) D(18)

PORT Y TAKES

PRIORITY OVER PORT X

WHEN AX=AY AND

WRITING TO BOTH

Write Cycle Timing to Both Ports (PTX, PT Y HIGH)[19]

CY7C1301A

Document #: 38-05076 Rev. *B Page 10 of 13

Switching Waveforms (continued)[20]

CLK

CE#

(See Note)

OEX#

DQX

1 43 65 87 9

D(3)

OEY#

DQY

1312 1514 1716 1918 20

WEX#

WEY#

PORT X

PORT Y

D(2) D(X)

PTY#

D(Y) D(6)

Q(3) D(X) D(Y) Q(17)

KQHZ

KQX

Write to Port X and Pass-through to Port Y[19]

PTX#

CY7C1301A

Document #: 38-05076 Rev. *B Page 11 of 13

Switching Waveforms (continued)[20]

CLK

OEX#

DQX

1 1 2

OEY#

DQY

WEX#

WEY#

PORT X

PORT Y

D(DEF)

PORT Y TAKES

PRIORITY OVER PORT X

WHEN AX=AY AND

WRITING TO BOTH

PORTS.

D(ABC) Q(PQR) Q(XYZ) Q(JKL)

D(XYZ)D(PQR) Q(JKL)D(JKL)Q(PQR)

TRY TO

WRITE TRY TO

WRITE READ READ READ READ READ READ

21 1 2

WRITE WRITE READ READ READ READ READ READ

PTX# = PTY# = HIGH

D(Value) = Value is the input of the data port.

Q(Value) = Value is the output of the data port.

Combination Read/Write with Same Address on Each Port

CY7C1301A

Document #: 38-05076 Rev. *B Page 12 of 13

of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Speed

(MHz) Ordering Code Package

Name Package Type Operating

Range

100 CY7C1301A-100AC A176 176-lead TQFP (24 x 24 x 1.4 mm) Commercial

83 CY7C1301A-83AC A176 176-lead TQFP (24 x 24 x 1.4 mm)

Package Diagram

176-lead Thin Quad Flat Pack (24x24x1.4 mm) A176

51-85132

CY7C1301A

Document #: 38-05076 Rev. *B Page 13 of 13

Document Title: CY7C1301A 256K X 36 Dual I/O, Dual Address Synchronous SRAM

Docum ent: 38-0 507 6

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 107305 06/08/01 NSL New Data Sheet

*A 109297 09/07/01 CJM 1. Remove 133-MHz speed bin

2. Change ESD voltage from > 2001V to > 1601V

3. Change tS from 1.5 ns to 1.8 ns

*B 1 13340 04/11/02 GLC 1. Changed ISB from 100 mA to140 mA for 10 0 Mhz and 100 mA to 120 mA

for 83 Mhz

2. Changed CIN from 6 pf to 8 pf (all speeds)

3. Changed CCLk from 6pf to 9 pf (all speeds)

4. Changed Icc to reflect chara data (all speeds)

5. Removed Preliminary