MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits General Description Features Applications Ordering Information The MAX691A/MAX693A/MAX800L/MAX800M microprocessor (P) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30A supply current, 200ms typ reset active delay on power-up, and 6ns chip-enable propagation delay. Features include write protection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET output that is valid with VCC down to 1V. The MAX691A/ MAX800L have a 4.65V typical reset-threshold voltage, and the MAX693A/MAX800Ms' reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to 2%. Computers Controllers Intelligent Instruments Critical P Power Monitoring PINPACKAGE MAX691ACUE -0C to +70C 16 TSSOP MAX691ACSE -0C to +70C 16 Narrow SO MAX691ACWE -0C to +70C 16 Wide SO MAX691ACPE -0C to +70C 16 Plastic DIP MAX691AC/D -0C to +70C Dice* MAX691AEUE -0C to +70C 16 TSSOP MAX691AESE -40C to +85C 16 Narrow SO MAX691AEWE -40C to +85C 16 Wide SO MAX691AEPE -40C to +85C 16 Plastic DIP Ordering Information continued at end of data sheet. *Dice are specified at TA = +25C, DC parameters only. Devices in PDIP, SO, and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. PART Typical Operating Circuit +8V 5V REGULATOR 0.1F 3 VCC 1N4148 1 5 BATT ON VOUT VBATT CE OUT 0.47F* 2 12 MAX691A 9 MAX693A CE IN 13 PFI MAX800L MAX800M 4 7 NO CONNECTION 8 GND WDI OSC IN PFO OSC SEL LOW LINE WDO 6 14 *MaxCap RESET CMOS RAM ADDRESS DECODE 11 15 Pin Configuration VBATT 1 A0-A15 I/O 16 RESET VOUT 2 15 RESET NMI GND 4 P 10 TEMP RANGE TOP VIEW RESET AUDIBLE ALARM SYSTEM STATUS INDICATORS MaxCap is a registered trademark of Kanthal Globar, Inc. 19-0094; Rev 12; 9/14 200ms Power-OK/Reset Timeout Period 1A Standby Current, 30A Operating Current On-Board Gating of Chip-Enable Signals, 10ns max Delay MaxCap(R) or SuperCap Compatible Guaranteed RESET Assertion to VCC = +1V Voltage Monitor for Power-Fail or Low-Battery Warning Power-Fail Accuracy Guaranteed to 2% (MAX800L/M) Available in 16-Pin Narrow SO, Plastic DIP, and TSSOP Packages VCC 3 BATT ON 5 MAX691A MAX693A MAX800L MAX800M 14 WDO 13 CE IN 12 CE OUT LOW LINE 6 11 WDI OSC IN 7 10 PFO OSC SEL 8 9 DIP/SO/TSSOP PFI MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Absolute Maximum Ratings Terminal Voltage (with respect to GND) VCC......................................................................-0.3V to +6V VVBATT.................................................................-0.3V to +6V All Other Inputs....................................-0.3V to (VOUT + 0.3V) Input Current VCC Peak..........................................................................1.0A VCC Continuous............................................................250mA VBATT Peak..................................................................250mA VBATT Continuous..........................................................25mA GND, BATT ON.............................................................100mA All Other Outputs ............................................................25mA Continuous Power Dissipation (TA = +70C) TSSOP (derate 6.70mW/C above +70C)..................533mW Narrow SO (derate 8.70mW/C above +70C) ...........696mW Wide SO (derate 9.52mW/C above +70C)...............762mW Plastic DIP (derate 10.53mW/C above +70C) ..........842mW CERDIP (derate 10.00mW/C above +70C)..............800mW Operating Temperature Ranges MAX69_AC_ _/MAX800_C_ _............................0C to +70C MAX69_AE_ _/MAX800_E_ _.........................-40C to +85C MAX69_AMJE................................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. PARAMETER CONDITIONS MIN Operating Voltage Range, VCC, VVBATT (Note 1) 0 IOUT = 25mA VOUT Output TYP VCC = 4.5V IOUT = 250mA 5.5 VCC - 0.02 VCC - 0.05 MAX69_AC VCC - 0.2 VCC - 0.3 MAX69_AE, MAX800_C/E VCC - 0.2 VCC 0.35 MAX69_A/M VCC = 4.5V MAX69_AC/AE, MAX800_C/E VCC 0.3V MAX69_AC, MAX800_C 0.8 1.2 MAX69_AE, MAX800_E 0.8 1.4 0.8 1.6 MAX69_A/M VOUT in Battery-Backup Mode VBATT-to-VOUT On-Resistance Supply Current in Normal Operating Mode (excludes IOUT) Supply Current in BatteryBackup Mode (excludes IOUT) (Note 2) VVBATT = 4.5V, IOUT = 20mA VVBATT - 0.3 VVBATT = 2.0V, IOUT = 5mA VVBATT - 0.15 VVBATT = 2.8V, IOUT = 10mA VVBATT = 4.5V V V V 15 25 VVBATT = 2.0V 30 VCC > VVBATT - 1V VCC < VVBATT 1.2V, VVBATT = 2.8V TA = +25C VBATT Standby Current (Note 3) VVBATT + 0.2V VCC TA = +25C Battery Switchover Threshold Power-up www.maximintegrated.com VVBATT - 0.25 VVBATT = 2.8V Power-down UNITS VCC - 0.40 VCC 0.17 IOUT = 210mA VCC-to-VOUT On-Resistance MAX 30 100 0.04 1 TA = TMIN + TMIN TA = TMIN + TMIN 5 -0.1 0.02 -1.0 0.02 VVBATT + 0.3 VVBATT - 0.3 A A A V Maxim Integrated 2 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Electrical Characteristics (continued) (MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. PARAMETER CONDITIONS MIN Battery Switchover Hysteresis TYP MAX 60 UNITS mV BATT ON Output Low Voltage ISINK = 3.2mA 0.1 0.4 0.7 1.5 BATT ON Output Short-Circuit Current Sink current 60 100 mA 1 15 100 A MAX691A, MAX800L 4.50 4.65 4.75 MAX693A, MAX800M 4.25 4.40 4.50 MAX800L, TA = +25C, VCC falling 4.55 MAX800M, TA = +25C, VCC falling 4.30 ISINK = 25mA Source current V RESET AND WATCHDOG TIMER Reset Threshold Voltage Reset Threshold Hysteresis VCC to RESET Delay Power-down LOW LINE-to-RESET Delay Reset Active Timeout Period, Internal Oscillator Power-up Reset Active Timeout Period, External Clock (Note 4) Power-up 140 4.70 4.45 15 mV 80 s 800 ns 200 Long period 1.0 Short period 70 Watchdog Timeout Period, External Clock (Note 4) Long period 4096 Short period 1024 VIL = 0.8V, VIH = 0.75 x VCC RESET Output Short-Circuit Current Output source current RESET Output Voltage Low (Note 5) ISINK = 3.2mA LOW LINE Output Voltage LOW LINE Output Short-Circuit Current WDO Output Voltage WDO Output Short-Circuit Current WDI Threshold Voltage (Note 6) WDI Input Current www.maximintegrated.com 1.6 2.25 100 140 Output source current ISINK = 3.2mA ISOURCE = 500A, VCC = 5V 0.3 0.1 0.4 V 7 20 mA 3.5 0.1 0.4 0.4 1 15 WDI = VOUT 100 V A 0.4 3.5 3 10 0.75 x VCC VIL WDI = 0V V 3.5 Output source current VIH ms Clock Cycles 0.004 ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1A, VCC = 5V sec ns ISINK = 3.2mA, VCC = 4.25V ISOURCE = 1.6mA, VCC = 5V ms Clock Cycles 100 ISINK = 50A, VCC = 1V, VBATT = 0V, VCC falling RESET Output Voltage 280 2048 Watchdog Timeout Period, Internal Oscillator Minimum Watchdog Input Pulse Width V 0.8 -50 -10 20 50 mA V A Maxim Integrated 3 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Electrical Characteristics (continued) (MAX691A, MAX800L: VCC = +4.75V to +5.5V; MAX693A, MAX800M: VCC = +4.5V to +5.5V; VVBATT = 2.8V, TA = TMIN to TMAX, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX 1.2 1.25 1.3 1.225 1.25 1.275 0.01 25 UNITS POWER-FAIL COMPARATOR PFI Input Threshold MAX69_AC/AE/AM, VCC = 5V MAX800_C/E, VCC = 5V PFI Leakage Current PFO Output Voltage PFO Output Short-Circuit Current PFI-to-PFO Delay ISINK = 3.2mA ISOURCE = 1A, VCC = 5V Output source current 0.4 3.5 1 15 VIN = -20mV, VOD = 15mV 25 VIN = 20mV, VOD = 15mV 60 100 V nA V A s CHIP-ENABLE GATING CE IN Leakage Current Disable mode 0.005 1 A CE IN-to- CE OUT Resistance (Note 7) Enable mode 75 150 CE OUT Short-Circuit Current (Reset Active) Disable mode, CE OUT = 0V 0.75 2.0 mA CE IN-to- CE OUT Propagation Delay (Note 8) 50 source impedance driver, CLOAD = 50pF 6 10 ns CE OUT Output-Voltage High (Reset Active) VCC = 5V, IOUT = -100A RESET-to-CE OUT Delay Power-down VCC = 0V, VBATT = 2.8V, IOUT = 1A 0.1 3.5 V 2.7 12 s INTERNAL OSCILLATOR OSC IN Leakage Current OSC SEL = 0V 0.10 5 A OSC IN Input Pullup Current OSC SEL = VOUT or floating, OSC IN = 0V 10 100 A OSC SEL = 0V 10 100 A OSC SEL Input Pullup Current OSC IN Frequency Range OSC SEL = 0V OSC IN External Oscillator Threshold Voltage VIH OSC IN Frequency with External Capacitor VIL OSC SEL = 0V, COSC = 47pF VOUT 0.3 50 VOUT 0.6 3.65 100 kHz 2.00 V kHz Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding IOUT typically goes to 10A when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. Note 3: "+" = battery-discharging current, "--" = battery-charging current. Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. Note 5: RESET is an open-drain output and sinks current only. Note 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. Note 7: The chip-enable resistance is tested with VCC = +4.75V for the MAX691A/MAX800L and VCC = +4.5V for the MAX693A/ MAX800M. CE IN = CE OUT = VCC/2. Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. www.maximintegrated.com Maxim Integrated 4 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Typical Operating Characteristics (TA = +25C, unless otherwise noted.) 28 -30 0 30 60 90 120 0 150 TEMPERATURE (C) -60 VBATT to VOUT ON-RESISTANCE vs. TEMPERATURE VBATT = 2.8V 10 VBATT = 4.5V VCC = 0V -60 4.75 RESET THRESHOLD (V) 4.70 -30 0 30 60 90 120 -30 -60 -30 0 MAX691A toc03 60 30 120 150 180 TEMPERATURE (C) VCC to VOUT ON-RESISTANCE vs. TEMPERATURE PFI THRESHOLD vs. TEMPERATURE VCC = 5V, VBATT = 0V 0.9 0.8 1.50 1.25 0.7 1.00 0.75 0.50 VCC = +5V, VBATT = 0V NO LOAD ON PFO 0.25 -60 90 TEMPERATURE (C) -30 0 30 60 90 120 0 150 -60 -30 0 30 60 90 RESET DELAY vs. TEMPERATURE MAX693A MAX800M -60 40 150 RESET OUTPUT RESISTANCE vs. TEMPERATURE 4.45 4.30 120 RESET THRESHOLD vs. TEMPERATURE 4.50 4.35 90 TEMPERATURE (C) 4.55 4.40 60 60 TEMPERATURE (C) MAX691A MAX800L 4.60 30 80 TEMPERATURE (C) VBATT = 2.8V 4.65 0 1.0 0.6 150 0 30 60 90 TEMPERATURE (C) www.maximintegrated.com 120 150 600 RESET OUTPUT RESISTANCE () 5 1.1 -30 PFI THRESHOLD (V) 15 1.2 VCC-to-VOUT ON-RESISTANCE () MAX691A toc04 VBATT = 2.0V MAX691A toc07 VBATT-to-VOUT ON-RESISTANCE () 20 MAX691A TOC-02 0.5 100 VCC = 4.75V VBATT = 2.8V VCE IN = VCC/2 500 VCC = 5V, VBATT = 2.8V SOURCING CURRENT 400 300 200 VCC = 0V, VBATT = 2.8V SINKING CURRENT 100 0 -60 -30 0 30 60 230 120 150 120 150 MAX691A toc09 -60 1 VCC = 0V TO 5V STEP VBATT = 2.8V 220 RESET DELAY (ms) 26 1.5 120 CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE MAX691A toc06 30 VCC = 5V VBATT = 2.8V NO LOAD CE ON-RESISTANCE () 32 2 MAX691A toc08 34 BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE) MAX691A toc05 VCC = 5V VBATT = 2.8V PFI, CE IN = 0V BATTERY SUPPLY CURRENT (A) VCC SUPPLY CURRENT (A) 36 MAX691A toc01 VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE) 210 200 190 180 90 TEMPERATURE (C) 120 150 170 -60 -30 0 30 60 90 TEMPERATURE (C) Maxim Integrated 5 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Typical Operating Characteristics (continued) 12 8 4 3 2 4 5 SHORT WATCHDOG TIMEOUT PERIOD 10 100 16 8 4 0 1000 0 50 100 150 200 VCC TO VOUT vs. OUTPUT CURRENT (NORMAL OPERATING MODE) VBATT TO VOUT vs. OUTPUT CURRENT (BATTERY-BACKUP MODE) VCC TO LOW LINE AND CE OUT DELAY SLOPE = 0.8 1000 VCC = 0V VBATT = 4.5V 100 HI LOW LINE LO HI SLOPE = 8 10 10 100 IOUT (mA) www.maximintegrated.com 1000 1 1 10 250 300 5V VCC RESET THRESHOLD 80ms 800ns RESET LO HI CE OUT 1 MAX691A toc12 12 CLOAD (pF) 100 1 VCC = 5V CE IN = 0V TO 5V DRIVER SOURCE COSC (pF) VCC = 4.5V VBATT = 0V 10 RESET ACTIVE TIMEOUT PERIOD 1 0.1 20 VCC (V) VBATT to VOUT (mV) VCC TO VOUT (mV) 1000 1 LONG WATCHDOG TIMEOUT PERIOD CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE MAX691A toc15 0 MAX691A toc13 0 10 VCC = 5V VBATT = 2.8V PROPAGATION DELAY (ns) IBATT (A) 16 100 MAX691A toc11 VBATT = 2.8V IOUT = 0A WATCHDOG AND RESET TIMEOUT PERIOD vs. OSC IN TIMING CAPACITOR (COSC) MAX691A toc14 20 MAX691A toc10 BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE WATCHDOG AND RESET TIMEOUT PERIOD (sec) (TA = +25C, unless otherwise noted.) 100 LO 12s IOUT (mA) Maxim Integrated 6 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Pin Description PIN NAME 1 VBATT 2 VOUT 3 4 VCC GND FUNCTION Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND. Output Supply Voltage. When VCC is greater than VBATT and above the reset threshold, VOUT connects to VCC. When VCC falls below VBATT and is below the reset threshold, VOUT connects to VBATT. Connect a 0.1F capacitor from VOUT to GND. Connect VOUT to VCC if no backup battery is used. Input Supply Voltage, 5V Input. Ground. 0V reference for all signals. Battery-On Output. When VOUT switches to VBATT, BATT ON goes high. When VOUT switches to VCC, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current require- ments greater than 250mA. 5 BATT ON 6 LOW LINE LOW LINE output goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. 7 OSC IN External Oscillator Input. When OSC SEL is unconnected or driven high, a 10A pull-up connects from VOUT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). 8 OSC SEL 9 PFI 10 PFO Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. 11 WDI Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time- out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran- sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between VOUT and GND, which sets it to mid-supply when left unconnected. 12 CE OUT Chip-Enable Output. CE OUT goes low only when CE IN is low and VCC is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15s or until CE IN goes high, whichever occurs first. 13 CE IN Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or VOUT. 14 WDO Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. 15 RESET RESET Output goes low whenever VCC falls below the reset threshold. RESET will remain low typically for 200ms after VCC crosses the reset threshold on power-up. 16 RESET RESET is an active-high output. It is open drain, and the inverse of RESET. Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). OSC SEL has a 10A internal pull-up. Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. When PFI is not used, connect PFI to GND or VOUT. Detailed Description RESET and RESET Outputs The MAX691A/MAX693A/MAX800L/MAX800M's RESET and RESET outputs ensure that the P (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at typically VOUT - 0.5V. RESET output is open drain, active high, and typically www.maximintegrated.com sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10k pulldown resistor on RESET insures that it will be valid with VCC down to GND (Figure 1). As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10k pulldown resistor insures the parallel combination of switch plus resistor is around 10k and the output saturation voltage is below 0.4V while sinking 40A. When using a 10k external pulldown resistor, the high state for RESET output with VCC = 4.75V will be 4.5V typical. Maxim Integrated 7 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits WDI RESET 15 MAX691A MAX693A TO P RESET WDO 1k t2 RESET t1 t1 t3 t1 = RESET TIMEOUT PERIOD t2 = NORMAL WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET Figure 1. Adding an external pulldown resistor ensures RESET is valid with VCC down to GND. Figure 2. Watchdog Timeout Period and Reset Active Time For battery voltages 2V connected to VBATT, RESET and RESET remain valid for VCC from 0V to 5.5V. function is disabled and WDI is disconnected from its internal resistor network, thus becoming high impedance. RESET and RESET are asserted when VCC falls below the reset threshold (4.65V for the MAX691A/MAX800L, 4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after VCC rises above the reset threshold on power-up (Figure 5). The devices' batteryswitchover comparator does not affect reset assertion. However, both reset outputs are asserted in batterybackup mode since VCC must be below the reset threshold to enter this mode. Watchdog Output Watchdog Function The watchdog monitors P activity via the Watchdog Input (WDI). If the P becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or P I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal), WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page). Watchdog Input A change of state (high to low, low to high, or a minimum 100ns pulse) at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6s. To disable the watchdog function, leave WDI floating. An internal resistor network (100k equivalent impedance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When VCC is below the reset threshold, the watchdog www.maximintegrated.com The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when VCC is below the reset threshold, battery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical). WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic. Selecting an Alternative Watchdog and Reset Timeout Period The OSC SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC IN or tying them both to VOUT selects the nominal 1.6s watchdog timeout period and 200ms reset timeout period. Connecting OSC IN to GND and floating or connecting OSC SEL to VOUT selects the 100ms normal watchdog timeout delay and 1.6s delay immediately after reset. The reset timeout delay remains 200ms (Figure 2). Select alternative timeout periods by connecting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC IN (Table 1 and Figure 3). OSC IN is internally connected to a 100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watch- Maxim Integrated 8 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Table 1. Reset Pulse Width and Watchdog Timeout Selections WATCHDOG TIMEOUT PERIOD NORMAL IMMEDIATELY AFTER RESET RESET TIMEOUT PERIOD External Clock Input 1024 clks 4096 clks 2048 clks OSC SEL OSC IN Low Low External Capacitor (600/47pF x C)ms (2.4/47pF x C)sec (1200/47pF x C)ms Floating Low 100ms 1.6s 200ms Floating Floating 1.6s 1.6s 200ms MAX691A MAX693A MAX800L MAX800M EXTERNAL OSCILLATOR EXTERNAL CLOCK 8 7 8 OSC SEL 7 OSC IN OSC SEL OSC IN 50kHz INTERNAL OSCILLATOR 1.6s WATCHDOG N.C. N.C. 8 7 OSC SEL OSC IN INTERNAL OSCILLATOR 100ms WATCHDOG N.C. 8 7 OSC SEL OSC IN Figure 3. Oscillator Circuits dog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications Information section). Chip-Enable Signal Gating The MAX691A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous data from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. All these parts use a series transmission gate from CE IN to CE OUT (Figure 4). high or 15s after reset is asserted, whichever occurs first (Figure 5). During a power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period. In the high-impedance mode, the leakage currents into this terminal are 1A max over temperature. In the lowimpedance mode, the impedance of CE IN appears as a 75 resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on the Chip-Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point of CE IN to the 50% point of CE OUT using a 50 driver and 50pF of load capacitance (Figure 6). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low outputimpedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75 in series with the source driving CE IN. In the disabled mode, the 75 transmission gate is off and CE OUT is actively pulled to VOUT. This source turns off when the transmission gate is enabled. LOW LINE Output The 10ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most Ps. LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2mA at 0.1V. For normal operation (VCC above the LOW LINE threshold), LOW LINE is pulled to VOUT. Chip-Enable Input Power-Fail Comparator The Chip-Enable Input (CE IN) is high impedance (disabled mode) while RESET and RESET are asserted. During a power-down sequence where VCC falls below the reset threshold or a watchdog fault, CE IN assumes a high-impedance state when the voltage at CE IN goes www.maximintegrated.com The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Common uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating Circuit). Maxim Integrated 9 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits 5 BATT ON 4.65V* VCC 6 3 2 VBATT CE IN OSC IN OSC SEL WDI PFI LOW LINE CHIP-ENABLE OUTPUT CONTROL 1 13 12 16 MAX691A MAX693A MAX800L MAX800M 7 TIMEBASE FOR RESET AND WATCHDOG 8 WATCHDOG TRANSITION DETECTOR 11 9 RESET GENERATOR 15 WATCHDOG TIMER 14 10 VOUT CE OUT RESET RESET WDO PFO 1.25V 4 GND * 4.4V FOR THE MAX693A/MAX800M Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram 5.0V VCC RESET 4.0V THRESHOLD 5.0V 0V CE IN 5V 0V 5V 0V 5V 0V CE OUT 15s 100s 100s RESET RESET LOGIC LEVELS SHOWN ARE FROM 0V TO 5V. Figure 5. Reset and Chip-Enable Timing www.maximintegrated.com Maxim Integrated 10 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits +5V +5V VBATT VCC VBATT MAX691A MAX693A MAX800L MAX800M 2.8V CE OUT CE IN 50 OUTPUT IMPEDANCE 2.0V to 5.5V GND VCC MAX691A MAX693A MAX800L PFI MAX800M PFO GND CLOAD Figure 6. CE Propagation Delay Test Circuit Figure 7. Low-Battery Indicator Table 2. Input and Output Status in Battery-Backup Mode Power-Fail Input PIN NAME 1 VBATT 2 VOUT VOUT is connected to VBATT through an internal PMOS switch. 3 VCC Battery switchover comparator monitors VCC for active switchover. 4 GND GND 0V, 0V reference for all signals. BATT ON Logic high. The open-circuit output is equal to VOUT. 5 STATUS Supply current is 1A max. 6 LOWLINE 7 OSC IN Logic low* 8 OSC SEL 9 PFI The power-fail comparator remains active in the battery-backup mode for VCC VBATT - 1.2V typ. 10 PFO The power-fail comparator remains active in the battery-backup mode for VCC VBATT - 1.2V typ. Below this volt- age, PFO is forced low. 11 WDI Watchdog is ignored. 12 CE OUT 13 CE IN High impedance 14 WDO Logic high. The open-circuit voltage is equal to VOUT. 15 RESET Logic low* 16 RESET High impedance* OSC IN is ignored. OSC SEL is ignored. Logic high. The open-circuit voltage is equal to VOUT. *VCC must be below the reset threshold to enter battery-backup mode. www.maximintegrated.com LOW BATT Power-Fail Input (PFI) is the input to the power-fail comparator. It has a guaranteed input leakage of 25nA max over temperature. The typical comparator delay is 25s from VIL to VOL (power failing), and 60s from VIH to VOH (power being restored). If PFI is not used, connect it to ground. Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above 1.25V, PFO is actively pulled to VOUT. Battery-Backup Mode Two conditions are required to switch to battery-backup mode: 1) VCC must be below the reset threshold, and 2) VCC must be below VBATT. Table 2 lists the status of the inputs and outputs in battery-backup mode. Battery-On Output The Battery-On (BATT ON) output indicates the status of the internal VCC/battery-switchover comparator, which controls the internal VCC and VBATT switches. For VCC greater than VBATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.1V saturation voltage. In battery-backup mode, this terminal sources approximately 10A from VOUT. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications (see Typical Operating Circuit). Input Supply Voltage The Input Supply Voltage (VCC) should be a regulated 5V. VCC connects to VOUT via a parallel diode and a large PMOS switch. The switch carries the entire cur-rent Maxim Integrated 11 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 1 each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A. Battery-Backup Input The Battery-Backup Input (VBATT) is similar to the VCC input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1A over temperature and supply voltage (Figure 8). Output Supply Voltage The Output Supply Voltage (VOUT) pin is internally connected to the substrate of the IC and supplies current to the external system and internal circuitry. All opencircuit outputs will, for example, assume the VOUT voltage in their high states rather than the VCC voltage. At the maximum source current of 250mA, VOUT will typically be 200mV below VCC. Decouple this terminal with a 0.1F capacitor. Applications Information The MAX691A/MAX693A/MAX800L/MAX800M are not short-circuit protected. Shorting VOUT to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. All open-circuit outputs swing between VOUT and GND rather than VCC and GND. If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip's protection diodes. There are three distinct modes of operation: 1) Normal operating mode with all circuitry powered up. Typical supply current from VCC is 35A while only leakage currents flow from the battery. 2) Battery-backup mode where VCC is typically within 0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 60A. 3) Battery-backup mode where VCC is less than VBATT by at least 0.7V. VBATT supply current is 1A max. Using SuperCap or MaxCap with the MAX691A/MAX693A/MAX800L/MAX800M VBATT has the same operating voltage range as VCC, and the battery switchover threshold voltages are typically 30mV centered at VBATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 9). If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. For example, with a SuperCap connected to VBATT and through a diode to VCC, if VCC quickly changes from 5.4V to 4.9V, the capacitor discharges through VOUT and VCC until VBATT reaches 5.1V typ. Leakage current through the SuperCap charging diode and the internal power diode eventually discharges the SuperCap to VCC. Also, if VCC and VBATT start from 0.1V above the reset thresh- +5V 3 VCC 1N4148 VBATT MAX691A MAX693A MAX800L MAX800M 1 VOUT 0.1F 0.47F* VCC VBATT VOUT 2 MAX691A MAX693A MAX800L MAX800M GND * MaxCap Figure 8. VCC and VBATT to VOUT Switch www.maximintegrated.com 4 Figure 9. SuperCap or MaxCap on VBATT Maxim Integrated 12 MAX691A/MAX693A/ MAX800L/MAX800M VIN Rp* CE CE VOUT CE IN Microprocessor Supervisory Circuits RAM 1 +5V R1 C1* CE OUT CE MAX691A MAX693A MAX800L MAX800M CE RAM 2 R3 R2 CE CE CE MAX691A MAX693A MAX800L MAX800M PFO CE GND VCC PFI RAM 3 GND TO P *OPTIONAL 5V RAM 4 PFO 0V VL VTRIP VH VIN 0V VTRIP = 1.25 *MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM Rp VALUE IS 1k. ACTIVE-HIGH CE LINES FROM LOGIC Figure10. Alternate CE Gating VH = 1.25 / R1 + R2 R2 R2 I I R3 R1 + R2 I I R3 VL - 1.25 + 5 - 1.25 = 1.25 R1 R3 R2 Figure 11. Adding Hysteresis to the Power-Fail Comparator old and power is lost at VCC, the SuperCap on VBATT discharges through VCC until VBATT reaches the reset threshold; then the battery-backup mode is initiated and the current through VCC goes to zero. +5V R1 VCC Using Separate Power Supplies for VBATT and VCC If using separate power supplies for VCC and VBATT, VBATT must be less than 0.3V above VCC when VCC is above the reset threshold. As described in the previous section, if VBATT exceeds this limit and power is lost at VCC, current flows continuously from VBATT to VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC switch until the circuit is broken (Figure 8). Alternate Chip-Enable Gating Using memory devices with both CE and CE inputs allows the CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to VOUT, and connect CE OUT to the CE input of each memory device (Figure 10). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated. www.maximintegrated.com PFO PFI MAX691A MAX693A MAX800L MAX800M R2 GND 5V V- PFO 0V 5 - 1.25 = 1.25 - VTRIP R1 R2 VTRIP V- 0V NOTE: VTRIP IS NEGATIVE. Figure 12. Monitoring a Negative Voltage Maxim Integrated 13 MAXIMUM TRANSIENT DURATION (s) 100 Microprocessor Supervisory Circuits VCC = 5V TA = +25C 0.1F CAPACITOR FROM VOUT TO GND 80 MAX791-16 MAX691A/MAX693A/ MAX800L/MAX800M 60 Backup-Battery Replacement The backup battery may be disconnected while VCC is above the reset threshold. No precautions are necessary to avoid spurious reset pulses. Negative-Going VCC Transients 40 20 0 accuracy is affected by the PFI threshold tolerance, the VCC voltage, and resistors R1 and R2. 10 100 1000 10000 RESET COMPARATOR OVERDRIVE, (Reset Threshold Voltage - VCC) (mV) Figure 13. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdriv Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is near the power-fail comparator trip point. Figure 11 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1A to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k to prevent it from loading down the PFO pin. Capacitor C1 adds noise rejection. Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply voltage using Figure 12's circuit. When the negative supply is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's www.maximintegrated.com While issuing resets to the P during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going VCC transients (glitches). It is usually undesirable to reset the P when VCC experiences only small glitches. Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts for 40s or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the VCC pin provides additional transient immunity. Connecting a Timing Capacitor at OSC IN When OSC SEL is connected to ground, OSC IN disconnects from its internal 10A (typ) pullup and is internally connected to a 100nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout periods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator startup prob- Maxim Integrated 14 MAX691A/MAX693A/ MAX800L/MAX800M lems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to 100nA. Microprocessor Supervisory Circuits START Maximum VCC Fall Time The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/s. A standard rule of thumb for filter capacitance on most regulators is on the order of 100F per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse or 1A/100F = 0.01V/s. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement. Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or lowhigh-low. This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 14 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. www.maximintegrated.com SET WDI LOW SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 14. Watchdog Flow Diagram Maxim Integrated 15 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Ordering Information (continued) PART TEMP RANGE MAX691AEJE MAX691AMJE MAX691AMSE/PR MAX691AMSE/PR-T MAX693ACUE MAX693ACSE MAX693ACWE MAX693ACPE MAX693AC/D MAX693AEUE MAX693AESE MAX693AEWE MAX693AEPE MAX693AEJE MAX693AMJE MAX800LCUE MAX800LCSE MAX800LCPE MAX800LEUE MAX800LESE MAX800LEPE MAX800MCUE MAX800MCSE MAX800MCPE MAX800MEUE MAX800MESE MAX800MEPE -40C to +85C -55C to +125C -55C to +125C -55C to +125C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C -0C to +70C -0C to +70C -0C to +70C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 CERDIP 16 CERDIP** 16 Wide SO** 16 Wide SO** 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP Dice* 16 TSSOP 16 Narrow SO 16 Wide SO 16 Plastic DIP 16 CERDIP 16 CERDIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP 16 TSSOP 16 Narrow SO 16 Plastic DIP *Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883B. Devices in PDIP, SO and TSSOP packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. www.maximintegrated.com Chip Topography VOUT VBATT RESET RESET VCC WDO CE IN CE OUT GND 0.11" (2.794mm) BATT ON LOW LINE WDI PFI PFO OSC IN OSC SEL 0.07" (1.778mm) SUBSTRATE CONNECTED TO VOUT Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PKG CODE OUTLINE NO. LAND PATTERN NO. 16 TSSOP U16-1 21-0066 90-0117 16 CERDIP J16-3 21-0045 -- 16 Narrow SO S16-3 21-0041 90-0097 16 Plastic DIP P16-1 21-0043 -- 16 Wide SO W16-1 21-0042 90-0107 Maxim Integrated 16 MAX691A/MAX693A/ MAX800L/MAX800M Microprocessor Supervisory Circuits Revision History REVISION NUMBER REVISION DATE 0 09/92 Initial release 1 12/92 Update Electrical Characteristics table. 2 5/93 Update Electrical Characteristics table, Tables 1 and 2. 3 12/93 Update Electrical Characteristics table. 2, 3, 4 4 3/94 Update Electrical Characteristics table. 2, 3, 4 5 8/94 Correction to Figure 4. 10 6 1/95 Update to new revision and correct errors. -- 7 12/96 Update Electrical Characteristics table. 2, 3, 4 12/99 Updated Ordering Information, Pin Configuration, Absolute Maximum Ratings, and Package Information. 1, 2, 16 8 PAGES CHANGED DESCRIPTION -- 2, 3, 4 2, 3, 4, 9, 11 9 4/02 Corrected Ordering Information. 10 11/05 Added lead-free information. 1, 16 1 11 8/08 Updated Ordering Information. 1, 16 12 9/14 No /V OPNs; removed automotive reference from Applications section; updated Package Information table 1, 16 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2014 Maxim Integrated Products, Inc. 17 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX691ACPE+ MAX691ACSE+ MAX691ACWE+ MAX691AEPE+ MAX691AESE+ MAX691AEWE+ MAX693ACPE+ MAX693ACSE+ MAX693AEPE+ MAX800LCPE+ MAX800LCSE+ MAX800LCSE+T MAX800LCUE+ MAX800LCUE+T MAX800LEUE+ MAX800LEUE+T MAX800MCPE+ MAX800MCSE+ MAX800MCSE+T MAX800MCUE+ MAX800MCUE+T MAX800MEUE+ MAX800MEUE+T MAX691ACSE+T MAX691ACUE+ MAX691ACUE+T MAX691ACWE+T MAX691AESE+T MAX691AEUE+ MAX691AEUE+T MAX691AEWE+T MAX693ACSE+T MAX693ACUE+ MAX693ACUE+T MAX693ACWE+ MAX693ACWE+T MAX693AESE+ MAX693AESE+T MAX693AEUE+ MAX693AEUE+T MAX693AEWE+ MAX693AEWE+T MAX693AMJE MAX691AMSE/PR-T MAX691AMSE/PR MAX691AEJE MAX800LESE+ MAX691AMJE/883B MAX693ACUE MAX800LESE MAX691ACUE