PS024314-0308
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
Warning:
PS024314-0308 Revision History
Z8 Encore! XP® F0823 Series
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Date
Revision
Level Description Page No
March
2008
14 Changed title to Z8 Encore! XP F0823 Series and the
contents to match the title.
All
December
2007
13 Updated title from Z8 Encore! 8K and 4K Series to Z8
Encore! XP Z8F0823 Series. Updated Figure 3, Table
15, Table 35, Table 59 through Table 61, Table 119,
and Part Number Suffix Designations section.
8, 39,
59, 91,
196, and
226
August
2007
12 Updated Table 1, Table 16, and Program Memory
section.
2, 42,
and 13
June 2007 11 Updated to combine Z8 Encore! 8K and Z8 Encore! 4K
Series.
All
December
2006
10 Updated Ordering Information chapter. 217
PS024314-0308 Table of Contents
Z8 Encore! XP® F0823 Series
Product Specification
iv
Table of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Voltage Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Z8 Encore! XP® F0823 Series
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On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . . 27
Stop Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . 27
Stop Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . . 28
Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Shared Debug Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A–C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port A–C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port A–C Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–C Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port A–C Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LED Drive Level High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Z8 Encore! XP® F0823 Series
Product Specification
vi
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Watchdog Timer Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 60
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 80
Timer 0-1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 81
Timer 0–1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . 89
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . 90
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . 93
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . 95
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . 96
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Z8 Encore! XP® F0823 Series
Product Specification
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Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . 98
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
MULTIPROCESSOR (9-Bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . 107
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 110
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . 116
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ADC Control/Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Product Specification
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Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . 133
Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . 133
Flash Code Protection Against Accidental Program and Erasure . . . . . . . 133
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Flash Controller Behavior in DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . 136
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 139
Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Reading the Flash Information Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 143
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Trim Bit Address 0000H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Trim Bit Address 0001H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Trim Bit Address 0003H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Trim Bit Address 0004H—Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Randomized Lot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
PS024314-0308 Table of Contents
Z8 Encore! XP® F0823 Series
Product Specification
ix
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
OCD Unlock Sequence (8-Pin Devices Only) . . . . . . . . . . . . . . . . . . . . . . 156
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 161
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . 171
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . 199
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . 202
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 204
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
PS024314-0308 Table of Contents
Z8 Encore! XP® F0823 Series
Product Specification
x
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
1
Overview
Zilog’s Z8 Encore! XP® microcontroller unit (MCU) family of products are the first
Zilog® microcontroller products based on the 8-bit eZ8 CPU core. Z8 Encore! XP F0823
Series products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash
in-circuit programming capability allows for faster development time and program
changes in the field. The new eZ8 CPU is upward compatible with existing Z8® instruc-
tions. The rich peripheral set of Z8 Encore! XP F0823 Series makes it suitable for a vari-
ety of applications including motor control, security systems, home appliances, personal
electronic devices, and sensors.
Features
The key features of Z8 Encore! XP F0823 Series include:
•
5 MHz eZ8 CPU
•
1 KB, 2 KB, 4 KB, or 8 KB Flash memory with in-circuit programming capability
•
256 B, 512 B, or 1 KB register RAM
•
6 to 24 I/O pins depending upon package
•
Internal precision oscillator (IPO)
•
Full-duplex UART
•
The universal asynchronous receiver/transmitter (UART) baud rate generator (BRG) can
be configured and used as a basic 16-bit timer
•
Infrared data association (IrDA)-compliant infrared encoder/decoders, integrated with
UART
•
Two enhanced 16-bit timers with capture, compare, and PWM capability
•
Watchdog Timer (WDT) with dedicated internal RC oscillator
•
On-Chip Debugger (OCD)
•
Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC)
•
On-Chip analog comparator
•
Up to 20 vectored interrupts
•
Direct LED drive with programmable drive strengths
•
Voltage Brownout (VBO) protection
•
Power-On Reset (POR)
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
2
•
2.7 V to 3.6 V operating voltage
•
Up to thirteen 5 V-tolerant input pins
•
8-, 20-, and 28-pin packages
•
0 °C to +70 °C and -40 °C to +105 °C for operating temperature ranges
Part Selection Guide
Table 1 lists the basic features and package styles available for each device within the
Z8 Encore! XP® F0823 Series product line.
Table 1. Z8 Encore! XP F0823 Series Family Part Selection Guide
Part
Number
Flash
(KB)
RAM
(B) I/O
ADC
Inputs Packages
Z8F0823 8 1024 6–22 4–8 8-, 20-, and 28-pins
Z8F0813 8 1024 6–24 0 8-, 20-, and 28-pins
Z8F0423 4 1024 6–22 4–8 8-, 20-, and 28-pins
Z8F0413 4 1024 6–24 0 8-, 20-, and 28-pins
Z8F0223 2 512 6–22 4–8 8-, 20-, and 28-pins
Z8F0213 2 512 6–24 0 8-, 20-, and 28-pins
Z8F0123 1 256 6–22 4–8 8-, 20-, and 28-pins
Z8F0113 1 256 6–24 0 8-, 20-, and 28-pins
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
3
Block Diagram
Figure 1 on page 3 displays the block diagram of the architecture of Z8 Encore! XP F0823
Series devices.
Figure 1. Z8 Encore! XP® F0823 Series Block Diagram
GPIO
IrDA
UARTTimers ADC
Flash
Flash
Controller
RAM
RAM
Controller
Memory
Interrupt
Controller
On-Chip
Debugger
eZ8
CPU WDT
POR/VBO
and Reset
Controller
Register Bus
Memory Busses
System
Clock
Comparator
Low Power
RC Oscillator
Oscillator
Control
Internal
Precision
Oscillator
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
4
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8 CPU, Zilog’s latest 8-bit central processing unit (CPU), meets the continuing
demand for faster and code-efficient microcontrollers. The eZ8 CPU executes a superset
of the original Z8® instruction set. The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory.
•
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks.
•
Compatible with existing Z8 code.
•
Expanded internal Register File allows access of up to 4 KB.
•
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C.
•
Pipelined instruction fetch and execution.
•
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL.
•
New instructions support 12-bit linear addressing of the Register file.
•
Up to 10 MIPS operation.
•
C-Compiler friendly.
•
2 to 9 clock cycles per instruction.
For more information on eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) avail-
able for download at www.zilog.com.
General-Purpose I/O
Z8 Encore! XP F0823 Series features 6 to 24 port pins (Ports A–C) for general-purpose
I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is
individually programmable. 5 V tolerant input pins are available on all I/Os on 8-pin
devices, most I/Os on other package types.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports
protection against accidental program and erasure, as well as factory serialization and read
protection.
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
5
Internal Precision Oscillator
The internal precision oscillator (IPO) is a trimmable clock source that requires no
external components.
10-Bit Analog-to-Digital Converter
The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit
binary number. The ADC accepts inputs from eight different analog input pins in both sin-
gle-ended and differential modes.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal
programmable voltage reference or a second input pin. The comparator output can be used
to drive either an output pin or to generate an interrupt.
Universal Asynchronous Receiver/Transmitter
The UART is full-duplex and capable of handling asynchronous data transfers. The UART
supports 8- and 9-bit data modes and selectable parity. The UART also supports multi-
drop address processing in hardware. The UART baud rate generator can be
configured and used as a basic 16-bit timer.
Timers
Two enhanced 16-bit reloadable timers can be used for timing/counting events or for
motor control operations. These timers provide a 16-bit programmable reload counter and
operate in ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART,
COMPARE, CAPTURE AND COMPARE, PWM SINGLE OUTPUT, and PWM DUAL
OUTPUT modes.
Interrupt Controller
Z8 Encore! XP® F0823 Series products support up to 20 interrupts. These interrupts
consist of eight internal peripheral interrupts and 12 general-purpose I/O pin interrupt
sources. The interrupts have three levels of programmable interrupt priority.
PS024314-0308 Overview
Z8 Encore! XP® F0823 Series
Product Specification
6
Reset Controller
Z8 Encore! XP® F0823 Series products can be reset using the RESET pin, POR, WDT
time-out, STOP mode exit, or Voltage Brownout warning signal. The RESET pin is
bidirectional, that is, it functions as reset source as well as a reset indicator.
On-Chip Debugger
Z8 Encore! XP F0823 Series products feature an integrated On-Chip Debugger. The OCD
provides a rich-set of debugging capabilities, such as reading and writing registers, pro-
gramming Flash memory, setting breakpoints and executing code. A single-pin
interface provides communication to the OCD.
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
7
Pin Description
Z8 Encore! XP® F0823 Series products are available in a variety of package styles and pin
configurations. This chapter describes the signals and pin configurations available for
each of the package styles. For information on physical package specifications, see Pack-
aging on page 209.
Available Packages
Table 2 lists the package styles that are available for each device in the Z8 Encore! XP
F0823 Series product line.
Pin Configurations
Figure 2 through Figure 4 displays the pin configurations for all packages available in the
Z8 Encore! XP F0823 Series. For description of signals, see Table 3. The analog input
alternate functions (ANAx) are not available on the Z8F0x13 devices. The analog supply
pins (AVDD and AVSS) are also not available on these parts, and are replaced by PB6 and
PB7.
At reset, all pins of Ports A, B, and C default to an input state. In addition, any alternate
functionality is not enabled, so the pins function as general-purpose input ports until
programmed otherwise.
Table 2. Z8 Encore! XP F0823 Series Package Options
Part
Number ADC
8-pin
PDIP
8-pin
SOIC
20-pin
PDIP
20-pin
SOIC
20-pin
SSOP
28-pin
PDIP
28-pin
SOIC
28-pin
SSOP
8-pin QFN/
MLF-S
Z8F0823 Yes X X X X X X X X X
Z8F0813 No X X X X X X X X X
Z8F0423 Yes X X X X X X X X X
Z8F0413 No X X X X X X X X X
Z8F0223 Yes X X X X X X X X X
Z8F0213 No X X X X X X X X X
Z8F0123 Yes X X X X X X X X X
Z8F0113 No X X X X X X X X X
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
8
The pin configurations listed are preliminary and subject to change based on manufactur-
ing limitations.
Figure 2. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 8-Pin SOIC, QFN/MLF-S, or PDIP Package*
Figure 3. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 20-Pin SOIC, SSOP or PDIP Package*
Figure 4. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 28-Pin SOIC, SSOP or PDIP Package*
VSS
PA5/TXD0/T1OUT/ANA0/CINP
PA4/RXD0/ANA1/CINN
PA3/CTS0/ANA2/COUT/T1IN
VDD
PA0/T0IN/T0OUT/DBG
PA1/T0OUT/ANA3/VREF/CLKIN
PA2/RESET/DE0/T1OUT
2
1
3
4
7
8
6
5
PB0/ANA0
PC3/COUT/LED
PC2/ANA6/LED/VREF
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET
PA7/T1OUT
PA6/T1IN/T1OUT
PB1/ANA1
PB2/ANA2
PB3/CLKIN/ANA3
VDD
PA0/T0IN/T0OUT
PA1/T0OUT
VSS
PA2/DE0
1
PA5/TXD0
PA3/CTS0
5
10
PA4/RXD0
2
3
4
6
7
8
9
20
16
11
19
18
17
15
14
13
12
PB1/ANA1
PB0/ANA0
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET
PC7/LED
PB2/ANA2
PB3/CLKIN/ANA3
PB4/ANA7
PB5/VREF
(PB6) AVDD
VDD
PA0/T0IN/T0OUT
PA1/T0OUT
1
PC6/LED
VSS
5
10
(PB7) AVSS
PA2/DE0
PA3/CTS0
PA4/RXD0
14
PA5/TXD0
2
3
4
6
7
8
9
11
12
13
PC5/LED
PC4/LED
PA7/T1OUT
PA6/T1IN/T1OUT
28
24
19
15
27
26
25
23
22
21
20
18
17
16
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
9
*Analog input alternate functions (ANA) are not available on the Z8F0x13 devices.
Signal Descriptions
Table 3 lists the Z8 Encore! XP® F0823 Series signals. To determine the signals available
for the specific package styles, see Pin Configurations on page 7.
Table 3. Signal Descriptions
Signal Mnemonic I/O Description
General-Purpose I/O Ports A–D
PA[7:0] I/O Port A. These pins are used for general-purpose I/O.
PB[7:0] I/O Port B. These pins are used for general-purpose I/O. PB6 and PB7 are
available only in those devices without an ADC.
PC[7:0] I/O Port C. These pins are used for general-purpose I/O.
Note: PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS.
UART Controllers
TXD0 O Transmit Data. This signal is the transmit output from the UART and IrDA.
RXD0 I Receive Data. This signal is the receive input for the UART and IrDA.
CTS0 I Clear To Send. This signal is the flow control input for the UART.
DE O Driver Enable. This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the TXE (Transmit
Empty) bit in the UART Status 0 register. The DE signal can be used to
ensure the external RS-485 driver is enabled when data is transmitted by
the UART.
Timers
T0OUT/T1OUT O Timer Output 0–1. These signals are output from the timers.
T0OUT/T1OUT O Timer Complement Output 0–1. These signals are output from the timers
in PWM Dual Output mode.
T0IN/T1IN I Timer Input 0–1. These signals are used as the capture, gating and
counter inputs. The T0IN signal is multiplexed T0OUT signals.
Comparator
CINP/CINN I Comparator Inputs. These signals are the positive and negative inputs to
the comparator.
COUT O Comparator Output. This is the output of the comparator.
Note:
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
10
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on
Z8 Encore! XP F0823 Series 20- and 28-pin devices. Data in Table 4 is sorted alphabeti-
cally by the pin symbol mnemonic.
Analog
ANA[7:0] I Analog port. These signals are used as inputs to the ADC. The ANA0,
ANA1, and ANA2 pins can also access the inputs and output of the
integrated transimpedance amplifier.
VREF I/O Analog-to-Digital Converter reference voltage input.
Clock Input
CLKIN I Clock Input Signal. This pin can be used to input a TTL-level signal to be
used as the system clock.
LED Drivers
LED O Direct LED drive capability. All port C pins have the capability to drive an
LED without any other external components. These pins have
programmable drive strengths set by the GPIO block.
On-Chip Debugger
DBG I/O Debug. This signal is the control and data input and output to and from the
OCD.
The DBG pin is open-drain and requires an external pull-
up resistor to ensure proper operation.
Reset
RESET I/O RESET. Generates a reset when asserted (driven Low). Also serves as a
reset indicator; the Z8 Encore! XP forces this pin Low when in reset. This
pin is open-drain and features an enabled internal pull-up resistor.
Power Supply
VDD I Digital Power Supply.
AVDD I Analog Power Supply.
VSS I Digital Ground.
AVSS I Analog Ground.
Note: The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
Table 3. Signal Descriptions (Continued)
Signal Mnemonic I/O Description
Caution:
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
11
Table 5 provides detailed information about the characteristics for each pin available on
Z8 Encore! XP® F0823 Series 8-pin devices.
All six I/O pins on the 8-pin packages are 5 V-tolerant (unless the pull-up devices are
enabled). The column in Table 4 below describes 5 V-tolerance for the 20- and 28-pin
packages only.
PB6 and PB7 are available only in the devices without ADC.
Table 4. Pin Characteristics (20- and 28-pin Devices)
Symbol
Mnemonic Direction
Reset
Direction
Active
Low or
Active
High
Tristate
Output
Internal Pull-up
or Pull-down
Schmitt-
Trigger
Input
Open Drain
Output
5 V
Tolerance
AVDD N/A N/A N/A N/A N/A N/A N/A N/A
AVSS N/A N/A N/A N/A N/A N/A N/A NA
DBG I/O I N/A Yes No Yes Yes Yes
PA[7:0] I/O I N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
PA[7:2]
only
PB[7:0] I/O I N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
PB[7:6]
only
PC[7:0] I/O I N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
PC[7:3]
only
RESET I/O I/O
(defaults
to RESET)
Low (in
Reset
mode)
Yes (PD0
only)
Always on for
RESET
Yes Always on for
RESET
Yes
VDD N/A N/A N/A N/A N/A N/A
VSS N/A N/A N/A N/A N/A N/A
Note:
Note:
PS024314-0308 Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
12
)
Table 5. Pin Characteristics (8-Pin Devices)
Symbol
Mnemonic Direction
Reset
Direction
Active Low
or Active
High
Tristate
Output
Internal Pull-up
or Pull-down
Schmitt-
Trigger
Input
Open Drain
Output
5 V
Tolerance
PA0/DBG I/O I (but can
change
during
reset if key
sequence
detected)
N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
Yes, unless
pull-ups
enabled
PA1 I/O I N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
Yes, unless
pull-ups
enabled
RESET/
PA2
I/O I/O
(defaults
to RESET)
N/A Yes Programmable
for PA2; always
on for RESET
Yes Programmable
for PA2; always
on for RESET
Yes, unless
pull-ups
enabled
PA[5:3] I/O I N/A Yes Programmable
Pull-up
Yes Yes,
Programmable
Yes, unless
pull-ups
enabled
VDD N/A N/A N/A N/A N/A N/A N/A N/A
VSS N/A N/A N/A N/A N/A N/A N/A N/A
PS024314-0308 Address Space
Z8 Encore! XP® F0823 Series
Product Specification
13
Address Space
The eZ8 CPU can access three distinct address spaces:
•
The Register File contains addresses for the general-purpose registers and the eZ8 CPU,
peripheral, and general-purpose I/O port control registers.
•
The Program Memory contains addresses for all memory locations having executable
code and/or data.
•
The Data Memory contains addresses for all memory locations that contain data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to eZ8 CPU Core
User Manual (UM0128) available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore! XP® MCU is 4 KB (4096 bytes). The
Register File is composed of two sections: control registers and general-purpose registers.
When instructions are executed, registers defined as sources are read, and registers defined
as destinations are written. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4 KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256 B control register
section are reserved (unavailable). Reading from a reserved Register File address returns
an undefined value. Writing to reserved Register File addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space.
Z8 Encore! XP F0823 Series devices contain 256 B-1 KB of on-chip RAM. Reading from
Register File addresses outside the available RAM addresses (and not within the control
register address space) returns an undefined value. Writing to these Register File addresses
produces no effect.
Program Memory
The eZ8 CPU supports 64 KB of Program Memory address space. Z8 Encore! XP F0823
Series devices contain 1 KB to 8 KB of on-chip Flash memory in the Program Memory
address space. Reading from Program Memory addresses outside the available Flash
PS024314-0308 Address Space
Z8 Encore! XP® F0823 Series
Product Specification
14
memory addresses returns FFH. Writing to these unimplemented Program Memory
addresses produces no effect. Table 6 describes the Program Memory maps for the Z8
Encore! XP® F0823 Series products.
Table 6. Z8 Encore! XP F0823 Series Program Memory Maps
Program Memory Address (Hex) Function
Z8F0823 and Z8F0813 Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–003D Oscillator Fail Traps*
003E–0FFF Program Memory
Z8F0423 and Z8F0413 Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–003D Oscillator Fail Traps*
003E–0FFF Program Memory
Z8F0223 and Z8F0213 Products
0000–0001 Flash Option Bits
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–003D Oscillator Fail Traps*
003E–07FF Program Memory
Z8F0123 and Z8F0113 Products
0000–0001 Flash Option Bits
PS024314-0308 Address Space
Z8 Encore! XP® F0823 Series
Product Specification
15
Data Memory
Z8 Encore! XP® F0823 Series does not use the eZ8 CPU’s 64 KB Data Memory address
space.
Flash Information Area
Table 7 lists the Z8 Encore! XP F0823 Series Flash Information Area. This 128 B
Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When
access is enabled, the Flash Information Area is mapped into the Program Memory and
overlays the 128 bytes at addresses FE00H to FF7FH. When the Information Area access is
enabled, all reads from these Program Memory addresses return the Information Area data
rather than the Program Memory data. Access to the Flash Information Area is read-only.
0002–0003 Reset Vector
0004–0005 WDT Interrupt Vector
0006–0007 Illegal Instruction Trap
0008–0037 Interrupt Vectors*
0038–003D Oscillator Fail Traps*
003E–03FF Program Memory
*See Table 33 on page 54 for a list of the interrupt vectors and traps.
Table 7. Z8 Encore! XP F0823 Series Flash Memory Information Area Map
Program Memory Address
(Hex) Function
FE00–FE3F Zilog Option Bits.
FE40–FE53 Part Number.
20-character ASCII alphanumeric code
Left justified and filled with FH.
FE54–FE5F Reserved.
FE60–FE7F Zilog Calibration Data.
FE80–FFFF Reserved.
Table 6. Z8 Encore! XP F0823 Series Program Memory Maps (Continued)
Program Memory Address (Hex) Function
PS024314-0308 Address Space
Z8 Encore! XP® F0823 Series
Product Specification
16
PS024314-0308 Register Map
Z8 Encore! XP® F0823 Series
Product Specification
17
Register Map
Table 8 lists the address map for the Register File of the Z8 Encore! XP® F0823 Series
devices. Not all devices and package styles in the Z8 Encore! XP F0823 Series support the
ADC, or all GPIO ports. Consider registers for unimplemented peripherals as reserved.
Table 8. Register File Address Map
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
General-Purpose RAM
Z8F0823/Z8F0813 Devices
000–3FF General-Purpose Register File RAM — XX
400–EFF Reserved — XX
Z8F0423/Z8F0413 Devices
000–3FF General-Purpose Register File RAM — XX
400–EFF Reserved — XX
Z8F0223/Z8F0213 Devices
000–1FF General-Purpose Register File RAM — XX
200–EFF Reserved — XX
Z8F0123/Z8F0113 Devices
000–0FF General-Purpose Register File RAM — XX
100–EFF Reserved — XX
Timer 0
F00 Timer 0 High Byte T0H 00 80
F01 Timer 0 Low Byte T0L 01 80
F02 Timer 0 Reload High Byte T0RH FF 81
F03 Timer 0 Reload Low Byte T0RL FF 81
F04 Timer 0 PWM High Byte T0PWMH 00 81
F05 Timer 0 PWM Low Byte T0PWML 00 82
F06 Timer 0 Control 0 T0CTL0 00 82
F07 Timer 0 Control 1 T0CTL1 00 83
Timer 1
F08 Timer 1 High Byte T1H 00 80
F09 Timer 1 Low Byte T1L 01 80
F0A Timer 1 Reload High Byte T1RH FF 81
F0B Timer 1 Reload Low Byte T1RL FF 81
PS024314-0308 Register Map
Z8 Encore! XP® F0823 Series
Product Specification
18
F0C Timer 1 PWM High Byte T1PWMH 00 81
F0D Timer 1 PWM Low Byte T1PWML 00 82
F0E Timer 1 Control 0 T1CTL0 00 82
F0F Timer 1 Control 1 T1CTL1 00 80
F10–F3F Reserved — XX
UART
F40 UART0 Transmit Data U0TXD XX 104
UART0 Receive Data U0RXD XX 105
F41 UART0 Status 0 U0STAT0 0000011Xb 105
F42 UART0 Control 0 U0CTL0 00 107
F43 UART0 Control 1 U0CTL1 00 107
F44 UART0 Status 1 U0STAT1 00 106
F45 UART0 Address Compare U0ADDR 00 109
F46 UART0 Baud Rate High Byte U0BRH FF 110
F47 UART0 Baud Rate Low Byte U0BRL FF 110
F48–F6F Reserved — XX
Analog-to-Digital Converter (ADC)
F70 ADC Control 0 ADCCTL0 00 122
F71 ADC Control 1 ADCCTL1 80 122
F72 ADC Data High Byte ADCD_H XX 124
F73 ADC Data Low Bits ADCD_L XX 124
F74–F7F Reserved — XX
Low Power Control
F80 Power Control 0 PWRCTL0 80 33
F81 Reserved — XX
LED Controller
F82 LED Drive Enable LEDEN 00 51
F83 LED Drive Level High Byte LEDLVLH 00 51
F84 LED Drive Level Low Byte LEDLVLL 00 52
F85 Reserved — XX
Oscillator Control
F86 Oscillator Control OSCCTL A0 167
F87–F8F Reserved — XX
Comparator 0
F90 Comparator 0 Control CMP0 14 128
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
PS024314-0308 Register Map
Z8 Encore! XP® F0823 Series
Product Specification
19
F91–FBF Reserved — XX
Interrupt Controller
FC0 Interrupt Request 0 IRQ0 00 58
FC1 IRQ0 Enable High Bit IRQ0ENH 00 60
FC2 IRQ0 Enable Low Bit IRQ0ENL 00 61
FC3 Interrupt Request 1 IRQ1 00 59
FC4 IRQ1 Enable High Bit IRQ1ENH 00 62
FC5 IRQ1 Enable Low Bit IRQ1ENL 00 62
FC6 Interrupt Request 2 IRQ2 00 60
FC7 IRQ2 Enable High Bit IRQ2ENH 00 63
FC8 IRQ2 Enable Low Bit IRQ2ENL 00 63
FC9–FCC Reserved — XX
FCD Interrupt Edge Select IRQES 00 64
FCE Shared Interrupt Select IRQSS 00 64
FCF Interrupt Control IRQCTL 00 65
GPIO Port A
FD0 Port A Address PAADDR 00 43
FD1 Port A Control PACTL 00 45
FD2 Port A Input Data PAIN XX 45
FD3 Port A Output Data PAOUT 00 45
GPIO Port B
FD4 Port B Address PBADDR 00 43
FD5 Port B Control PBCTL 00 45
FD6 Port B Input Data PBIN XX 45
FD7 Port B Output Data PBOUT 00 45
GPIO Port C
FD8 Port C Address PCADDR 00 43
FD9 Port C Control PCCTL 00 45
FDA Port C Input Data PCIN XX 45
FDB Port C Output Data PCOUT 00 45
FDC–FEF Reserved — XX
Watchdog Timer (WDT)
FF0 Reset Status RSTSTAT XX 90
Watchdog Timer Control WDTCTL XX 90
FF1 Watchdog Timer Reload Upper Byte WDTU FF 91
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
PS024314-0308 Register Map
Z8 Encore! XP® F0823 Series
Product Specification
20
FF2 Watchdog Timer Reload High Byte WDTH FF 91
FF3 Watchdog Timer Reload Low Byte WDTL FF 91
FF4–FF5 Reserved — XX
Trim Bit Control
FF6 Trim Bit Address TRMADR 00 143
FF7 Trim Data TRMDR XX 144
Flash Memory Controller
FF8 Flash Control FCTL 00 137
FF8 Flash Status FSTAT 00 137
FF9 Flash Page Select FPS 00 138
Flash Sector Protect FPROT 00 139
FFA Flash Programming Frequency High Byte FFREQH 00 140
FFB Flash Programming Frequency Low Byte FFREQL 00 140
eZ8 CPU
FFC Flags — XX Refer to eZ8
CPU Core
User Manual
(UM0128)
FFD Register Pointer RP XX
FFE Stack Pointer High Byte SPH XX
FFF Stack Pointer Low Byte SPL XX
XX=Undefined
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description Mnemonic Reset (Hex) Page No
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
21
Reset and Stop Mode Recovery
The Reset Controller within the Z8 Encore! XP® F0823 Series controls Reset and Stop
Mode Recovery operation and provides indication of low supply voltage conditions. In
typical operation, the following events cause a Reset:
•
Power-On Reset (POR)
•
Voltage Brownout (VBO)
•
Watchdog Timer time-out (when configured by the WDT_RES Flash Option Bit to
initiate a reset)
•
External RESET pin assertion (when the alternate RESET function is enabled by the
GPIO register)
•
On-chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the device is in STOP mode, a Stop Mode Recovery is initiated by either of the
following:
•
Watchdog Timer time-out
•
GPIO port input pin transition on an enabled Stop Mode Recovery source
The VBO circuitry on the device performs the following function:
•
Generates the VBO reset when the supply voltage drops below a minimum safe level
Reset Types
Z8 Encore! XP F0823 Series provides several different types of Reset operation. Stop
Mode Recovery is considered a form of Reset. Table 9 lists the types of Reset and their
operating characteristics. The System Reset is longer if the external crystal oscillator is
enabled by the Flash option bits, allowing additional time for oscillator start-up.
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
22
During a System Reset or Stop Mode Recovery, the IPO requires 4 µs to start up. Then the
Z8 Encore! XP F0823 Series device is held in Reset for 66 cycles of the Internal Precision
Oscillator. If the crystal oscillator is enabled in the Flash option bits, this reset period is
increased to 5000 IPO cycles. When a reset occurs because of a low voltage condition or
Power-On Reset, this delay is measured from the time that the supply voltage first exceeds
the POR level. If the external pin reset remains asserted at the end of the reset period, the
device remains in reset until the pin is deasserted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor
disabled.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
When the control registers are re-initialized by a system reset, the system clock after reset
is always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
Reset Sources
Table 10 lists the possible sources of a System Reset.
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
Reset
Type
Reset Characteristics and Latency
Control Registers
eZ8
CPU Reset Latency (Delay)
System
Reset
Reset (as applicable) Reset 66 Internal Precision Oscillator Cycles
Stop Mode
Recovery
Unaffected, except
WDT_CTL and OSC_CTL
registers
Reset 66 Internal Precision Oscillator Cycles
+ IPO startup time
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
23
Power-On Reset
Each device in the Z8 Encore! XP F0823 Series contains an internal POR circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer.
After the Z8 Encore! XP F0823 Series device exits the POR state, the eZ8 CPU fetches the
Reset vector. Following the POR, the POR status bit in Watchdog Timer Control
(WDTCTL) register is set to 1.
Figure 5 displays POR operation. For the POR threshold voltage (VPOR), see Electrical
Characteristics on page 193.
Table 10. Reset Sources and Resulting Reset Type
Operating Mode Reset Source Special Conditions
NORMAL or HALT
modes
Power-On Reset/Voltage
Brownout
Reset delay begins after supply voltage exceeds
POR level.
Watchdog Timer time-out
when configured for Reset
None.
RESET pin assertion All reset pulses less than three system clocks in
width are ignored.
OCD initiated Reset
(OCDCTL[0] set to 1)
System Reset, except the OCD is unaffected by
the reset.
STOP mode Power-On Reset/Voltage
Brownout
Reset delay begins after supply voltage exceeds
POR level.
RESET pin assertion All reset pulses less than the specified analog
delay are ignored. See Electrical Characteristics
on page 193.
DBG pin driven Low None.
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
24
Figure 5. Power-On Reset Operation
Voltage Brownout Reset
The devices in the Z8 Encore! XP F0823 Series provide low VBO protection. The VBO
circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold
voltage) and forces the device into the Reset state. While the supply voltage remains
below the POR voltage threshold (VPOR), the VBO block holds the device in the Reset.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the device
progresses through a full System Reset sequence, as described in the POR section.
Following POR, the POR status bit in the Reset Status (RSTSTAT) register is set to 1.
Figure 6 displays Voltage Brownout operation. For the VBO and POR threshold
voltages (VVBO and VPOR), see Electrical Characteristics on page 193.
The VBO circuit can be either enabled or disabled during STOP mode. Operation during
STOP mode is set by the VBO_AO Flash Option bit. For information on configuring
VBO_AO, see Flash Option Bits on page 141.
VCC = 0.0 V
VCC = 3.3 V
VPOR
VVBO
Internal Precision
Internal RESET
signal
Program
Execution
POR
counter delay
Oscillator
Note: Not to Scale
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
25
Figure 6. Voltage Brownout Reset Operation
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a POR after recovering from a VBO condition.
Watchdog Timer Reset
If the device is in NORMAL or STOP mode, the Watchdog Timer can initiate a System
Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the
unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it
configures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control register is set to signify that the reset was
initiated by the Watchdog Timer.
External Reset Input
The RESET pin has a Schmitt-Triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
VCC = 3.3 V
VPOR
VVBO
Internal RESET
signal
Program
Execution
Program
Execution
Voltage
Brownout
VCC = 3.3 V
System Clock
WDT Clock
POR
counter delayNote: Not to Scale
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
26
clock and reset signals, the required reset duration can be as short as three clock periods
and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP F0823 Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the WDT Control (WDTCTL) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see Port A–C Control Registers
on page 44), the RESET pin functions as an open-drain (active Low) reset mode indicator
in addition to the input functionality. This reset output feature allows an Z8 Encore! XP
F0823 Series device to reset other components to which it is connected, even if that reset
is caused by internal sources such as POR, VBO, or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 9 has elapsed.
On-Chip Debugger Initiated Reset
A POR is initiated using the On-Chip Debugger by setting the RST bit in the OCD Control
register. The OCD block is not reset but the rest of the chip goes through a normal system
reset. The RST bit automatically clears during the System Reset. Following the System
Reset, the POR bit in the Reset Status (RSTSTAT) register is set.
Stop Mode Recovery
The device enters into STOP mode when eZ8 CPU executes a STOP instruction. For more
details on STOP mode, see Low-Power Modes on page 31. During Stop Mode Recovery,
the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or 5000
cycles if it is enabled. The SMR delay also included the time required to start up the IPO.
Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer
Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any
Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another
system clock source is required or IPO disabling is required, the Stop Mode Recovery
code must reconfigure the oscillator control block such that the correct system clock
source is enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
27
vector address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer
Control Register is set to 1. Table 11 lists the Stop Mode Recovery sources and resulting
actions. The section following the table provides more detailed information on each of the
Stop Mode Recovery sources.
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during STOP mode, the device undergoes a Stop Mode
Recovery sequence. In the Watchdog Timer Control register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
Z8 Encore! XP® F0823 Series device is configured to respond to interrupts, the eZ8 CPU
services the Watchdog Timer interrupt request following the normal Stop Mode Recovery
sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
The SMR pulses shorter than specified does not trigger a recovery. When this happens, the
STOP bit in the Reset Status (RSTSTAT) register is set to 1.
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the port transition only if the signal stays on the port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can
initiate Stop Mode Recovery without being written to the Port Input Data register or
without initiating an interrupt (if enabled for that pin).
Table 11. Stop Mode Recovery Sources and Resulting Action
Operating Mode Stop Mode Recovery Source Action
STOP mode Watchdog Timer time-out when configured
for Reset
Stop Mode Recovery
Watchdog Timer time-out when configured
for interrupt
Stop Mode Recovery followed by interrupt
(if interrupts are enabled)
Data transition on any GPIO port pin
enabled as a Stop Mode Recovery source
Stop Mode Recovery
Assertion of external RESET Pin System Reset
Debug Pin driven Low System Reset
Note:
Caution:
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
28
Stop Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP F0823 Series device is in STOP mode and the external RESET
pin is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. For
more details, see Electrical Characteristics on page 193.
Reset Register Definitions
Reset Status Register
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of
the most recent Reset event, indicates a Stop Mode Recovery event, and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer control register, which is write-
only (Table 12).
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event is occurred. This bit is reset to 0 if a WDT
time-out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is
read.
Table 12. Reset Status Register (RSTSTAT)
BITS 7 6 5 4 3 2 1 0
FIELD POR STOP WDT EXT Reserved
RESET See descriptions below 0 0 0 0 0
R/W RRRRRRRR
ADDR FF0H
Reset or Stop Mode Recovery Event POR STOP WDT EXT
Power-On Reset 1 0 0 0
Reset using RESET pin assertion 0 0 0 1
Reset using WDT time-out 0 0 1 0
Reset using the OCD (OCTCTL[1] set to 1) 1 0 0 0
Reset from STOP Mode using DBG Pin driven Low 1 0 0 0
Stop Mode Recovery using GPIO pin transition 0 1 0 0
Stop Mode Recovery using WDT time-out 0 1 1 0
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
29
STOP—Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery is occurred. If the STOP and WDT bits are both
set to 1, the Stop Mode Recovery occurred because of a WDT time-out. If the STOP bit is
1 and the WDT bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This
bit is reset by a POR or a WDT time-out that occurred while not in STOP mode. Reading
this register also resets this bit.
WDT—Watchdog Timer time-out Indicator
If this bit is set to 1, a WDT time-out occurred. A POR resets this pin. A Stop Mode
Recovery from a change in an input pin also resets this bit. Reading this register resets this
bit. This read must occur before clearing the WDT interrupt.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Reserved—0 when read
PS024314-0308 Reset and Stop Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
30
PS024314-0308 Low-Power Modes
Z8 Encore! XP® F0823 Series
Product Specification
31
Low-Power Modes
Z8 Encore! XP® F0823 Series products contain power-saving features. The highest level
of power reduction is provided by the STOP mode, in which nearly all device functions
are powered down. The next lower level of power reduction is provided by the HALT
mode, in which the CPU is powered down.
Further power savings can be implemented by disabling individual peripheral blocks
while in ACTIVE mode (defined as being in neither STOP nor HALT mode).
STOP Mode
Executing the eZ8 CPU’s Stop instruction places the device into STOP mode, powering
down all peripherals except the Voltage Brownout detector, and the Watchdog Timer.
These two blocks may also be disabled for additional power savings. In STOP mode, the
operating characteristics are:
•
Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT (if
previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the
GPIO registers.
•
System clock is stopped.
•
eZ8 CPU is stopped.
•
Program counter (PC) stops incrementing.
•
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscillator
Control Register.
•
If enabled, the Watchdog Timer logic continues to operate.
•
If enabled for operation in STOP mode by the associated Flash Option Bit, the Voltage
Brownout protection circuit continues to operate.
•
All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs config-
ured as outputs must also be driven to one of the supply rails. The device can be brought
out of STOP mode using Stop Mode Recovery. For more information on Stop Mode
Recovery, see Reset and Stop Mode Recovery on page 21.
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HALT Mode
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode, which
powers down the CPU but leaves all other peripherals active. In HALT mode, the
operating characteristics are:
•
Primary oscillator is enabled and continues to operate.
•
System clock is enabled and continues to operate.
•
eZ8 CPU is stopped.
•
Program counter stops incrementing.
•
Watchdog Timer’s internal RC oscillator continues to operate.
•
If enabled, the Watchdog Timer continues to operate.
•
All other on-chip peripherals continue to operate.
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
Interrupt
•
Watchdog Timer time-out (interrupt or reset)
•
Power-On Reset
•
Voltage Brownout reset
•
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP F0823 Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
The following sections describe the power control registers.
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
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This register is only reset during a Power-On Reset sequence. Other System Reset events
do not affect it.
Reserved—Must be 1
Reserved—Must be 0
VBO—Voltage Brownout Detector Disable
This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be
active.
0 = VBO enabled
1 = VBO disabled
ADC—Analog-to-Digital Converter Disable
0 = Analog-to-Digital Converter enabled
1 = Analog-to-Digital Converter disabled
COMP—Comparator Disable
0 = Comparator is enabled
1 = Comparator is disabled
Reserved—Must be 0
Table 13. Power Control Register 0 (PWRCTL0)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved Reserved VBO Reserved ADC COMP Reserved
RESET 10000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F80H
Note:
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PS024314-0308 General-Purpose Input/Output
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General-Purpose Input/Output
Z8 Encore! XP® F0823 Series products support a maximum of 24 port pins (Ports A–C)
for general-purpose input/output (GPIO) operations. Each port contains control and data
registers. The GPIO control registers determine data direction, open-drain, output drive
current, programmable pull-ups, Stop Mode Recovery functionality, and alternate pin
functions. Each port pin is individually programmable. In addition, the Port C pins are
capable of direct LED drive at programmable drive strengths.
GPIO Port Availability By Device
Table 14 lists the port pins available with each device and package type.
Table 14. Port Availability by Device and Package Type
Devices Package 10-Bit ADC Port A Port B Port C Total I/O
Z8F0823SB, Z8F0823PB
Z8F0423SB, Z8F0423PB
Z8F0223SB, Z8F0223PB
Z8F0123SB, Z8F0123PB
8-pin Yes [5:0] No No 6
Z8F0813SB, Z8F0813PB
Z8F0413SB, Z8F0413PB
Z8F0213SB, Z8F0213PB
Z8F0113SB, Z8F011vPB
8-pin No [5:0] No No 6
Z8F0823PH, Z8F0823HH
Z8F0423PH, Z8F0423HH
Z8F0223PH, Z8F0223HH
Z8F0123PH, Z8F0123HH
20-pin Yes [7:0] [3:0] [3:0] 16
Z8F0813PH, Z8F0813HH
Z8F0413PH, Z8F0413HH
Z8F0213PH, Z8F0213HH
Z8F0113PH, Z8F0113HH
20-pin No [7:0] [3:0] [3:0] 16
Z8F0823PJ, Z8F0823SJ
Z8F0423PJ, Z8F0423SJ
Z8F0223PJ, Z8F0223SJ
Z8F0123PJ, Z8F0123SJ
28-pin Yes [7:0] [5:0] [7:0] 22
Z8F0813PJ, Z8F0813SJ
Z8F0413PJ, Z8F0413SJ
Z8F0213PJ, Z8F0213SJ
Z8F0113PJ, Z8F0113SJ
28-pin No [7:0] [7:0] [7:0] 24
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Architecture
Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure,
the ability to accommodate alternate functions and variable port current drive strength is
not displayed.
Figure 7. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins are used for general-purpose I/O and access to on-chip
peripheral functions such as the timers and serial communication devices. The port A–D
Alternate Function sub-registers configure these pins for either GPIO or alternate function
operation. When a pin is configured for alternate function, control of the port pin direction
(input/output) is passed from the Port A–D Data Direction registers to the alternate func-
tion assigned to this pin. Table 15 on page 39 lists the alternate functions possible with
each port pin. The alternate function associated at a pin is defined through Alternate
Function Sets sub-registers AFS1 and AFS2.
The crystal oscillator functionality is not controlled by the GPIO block. When the crystal
oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1
is overridden. In that case, those pins function as input and output for the crystal oscillator.
DQ
DQ
DQ
GND
VDD
Port Output Control
Port Data Direction
Port Output
Data Register
Port Input
Data Register
Port
Pin
DATA
Bus
System
Clock
System
Clock
Schmitt-Trigger
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PA0 and PA6 contain two different timer functions, a timer input and a complementary
timer output. Both of these functions require the same GPIO configuration, the selection
between the two is based on the timer mode. For more details, see Timers on page 67.
For pin with multiple alternate functions, it is recommended to write to the
AFS1 and AFS2 sub-registers before enabling the alternate function via
the AF sub-register. This prevents spurious transitions through unwanted
alternate function modes.
Direct LED Drive
The Port C pins provide a current sinked output capable of driving an LED without
requiring an external resistor. The output sinks current at programmable levels of 3 mA,
7 mA, 13 mA, and 20 mA. This mode is enabled through the Alternate Function
sub-register AFS1 and is programmable through the LED control registers. The LED
Drive Enable (LEDEN) register turns on the drivers. The LED Drive Level (LEDLVLH
and LEDLVLL) registers select the sink current.
For correct function, the LED anode must be connected to VDD and the cathode to the
GPIO pin. Using all Port C pins in LED drive mode with maximum current can result in
excessive total current. For the maximum total current for the applicable package, see
Electrical Characteristics on page 193.
Shared Reset Pin
On the 8-pin product versions, the reset pin is shared with PA2, but the pin is not
limited to output-only when in GPIO mode.
If PA2 on the 8-pin product is reconfigured as an input, take care that no
external stimulus drives the pin Low during any reset sequence. Since PA2
returns to its RESET alternate function during system resets, driving it Low
holds the chip in a reset state until the pin is released.
Shared Debug Pin
On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO
pin. This pin performs as a general purpose input pin on power-up, but the debug logic
monitors this pin during the reset sequence to determine if the unlock sequence occurs. If
the unlock sequence is present, the debug function is unlocked and the pin no longer func-
Caution:
Caution:
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Z8 Encore! XP® F0823 Series
Product Specification
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tions as a GPIO pin. If it is not present, the debug feature is disabled until/unless another
reset event occurs. For more details, see On-Chip Debugger on page 151.
Crystal Oscillator Override
For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When
the crystal oscillator is enabled (see Oscillator Control Register Definitions on page 167),
the GPIO settings are overridden and PA0 and PA1 are disabled.
5 V Tolerance
All six I/O pins on the 8-pin devices are 5 V-tolerant, unless the programmable pull-ups
are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these
parts, excessive current flows through those pull-up devices and can damage the chip.
In the 20- and 28-pin versions of this device, any pin which shares functionality with an
ADC, crystal or comparator port is not 5 V-tolerant, including PA[1:0], PB[5:0], and
PC[2:0]. All other signal pins are 5 V-tolerant, and can safely handle inputs higher than
VDD even with the pull-ups enabled.
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin
devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator
Control Register (see Oscillator Control Register Definitions on page 167) such that the
external oscillator is selected as the system clock. For 8-pin devices use PA1 instead of
PB3.
Note:
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Table 15. Port Alternate Function Mapping (Non 8-Pin Parts)
Port Pin Mnemonic Alternate Function Description
Alternate Function
Set Register AFS1
Port A PA0 T0IN/T0OUT*Timer 0 Input/Timer 0 Output Complement N/A
Reserved
PA1 T0OUT Timer 0 Output
Reserved
PA2 DE0 UART 0 Driver Enable
Reserved
PA3 CTS0 UART 0 Clear to Send
Reserved
PA4 RXD0/IRRX0 UART 0 / IrDA 0 Receive Data
Reserved
PA5 TXD0/IRTX0 UART 0 / IrDA 0 Transmit Data
Reserved
PA6 T1IN/T1OUT*Timer 1 Input/Timer 1 Output Complement
Reserved
PA7 T1OUT Timer 1 Output
Reserved
Note: Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are
not implemented for Port A. Enabling alternate function selections as described in Port A–C Alternate Function
Sub-Registers automatically enables the associated alternate function.
* Whether PA0/PA6 take on the timer input or timer output complement function depends on the timer
configuration as described in Timer Pin Signal Operation on page 79.
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Port B PB0 Reserved AFS1[0]: 0
ANA0 ADC Analog Input AFS1[0]: 1
PB1 Reserved AFS1[1]: 0
ANA1 ADC Analog Input AFS1[1]: 1
PB2 Reserved AFS1[2]: 0
ANA2 ADC Analog Input AFS1[2]: 1
PB3 CLKIN External Clock Input AFS1[3]: 0
ANA3 ADC Analog Input AFS1[3]: 1
PB4 Reserved AFS1[4]: 0
ANA7 ADC Analog Input AFS1[4]: 1
PB5 Reserved AFS1[5]: 0
VREF* ADC Voltage Reference AFS1[5]: 1
PB6 Reserved AFS1[6]: 0
Reserved AFS1[6]: 1
PB7 Reserved AFS1[7]: 0
Reserved AFS1[7]: 1
Note: Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set
register AFS2 is implemented but not used to select the function. Also, alternate function selection as described
in Port A–C Alternate Function Sub-Registers must also be enabled.
* VREF is available on PB5 in 28-pin products only.
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Port Pin Mnemonic Alternate Function Description
Alternate Function
Set Register AFS1
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Port C PC0 Reserved AFS1[0]: 0
ANA4/CINP/LED
Drive
ADC or Comparator Input, or LED drive AFS1[0]: 1
PC1 Reserved AFS1[1]: 0
ANA5/CINN/ LED
Drive
ADC or Comparator Input, or LED drive AFS1[1]: 1
PC2 Reserved AFS1[2]: 0
ANA6/LED/
VREF*
ADC Analog Input or LED Drive or ADC
Voltage Reference
AFS1[2]: 1
PC3 COUT Comparator Output AFS1[3]: 0
LED LED drive AFS1[3]: 1
PC4 Reserved AFS1[4]: 0
LED LED Drive AFS1[4]: 1
PC5 Reserved AFS1[5]: 0
LED LED Drive AFS1[5]: 1
PC6 Reserved AFS1[6]: 0
LED LED Drive AFS1[6]: 1
PC7 Reserved AFS1[7]: 0
LED LED Drive AFS1[7]: 1
Note: Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set
register AFS2 is implemented but not used to select the function. Also, Alternate Function selection as
described in Port A–C Alternate Function Sub-Registers must also be enabled.
*VREF is available on PC2 in 20-pin parts only.
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Port Pin Mnemonic Alternate Function Description
Alternate Function
Set Register AFS1
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Table 16. Port Alternate Function Mapping (8-Pin Parts)
Port Pin Mnemonic
Alternate Function
Description
Alternate
Function Select
Register AFS1
Alternate
Function
Select
Register
AFS2
Port A PA0 T0IN Timer 0 Input AFS1[0]: 0 AFS2[0]: 0
Reserved AFS1[0]: 0 AFS2[0]: 1
Reserved AFS1[0]: 1 AFS2[0]: 0
T0OUT Timer 0 Output Complement AFS1[0]: 1 AFS2[0]: 1
PA1 T0OUT Timer 0 Output AFS1[1]: 0 AFS2[1]: 0
Reserved AFS1[1]: 0 AFS2[1]: 1
CLKIN External Clock Input AFS1[1]: 1 AFS2[1]: 0
Analog Functions* ADC Analog Input/VREF AFS1[1]: 1 AFS2[1]: 1
PA2 DE0 UART 0 Driver Enable AFS1[2]: 0 AFS2[2]: 0
RESET External Reset AFS1[2]: 0 AFS2[2]: 1
T1OUT Timer 1 Output AFS1[2]: 1 AFS2[2]: 0
Reserved AFS1[2]: 1 AFS2[2]: 1
PA3 CTS0 UART 0 Clear to Send AFS1[3]: 0 AFS2[3]: 0
COUT Comparator Output AFS1[3]: 0 AFS2[3]: 1
T1IN Timer 1 Input AFS1[3]: 1 AFS2[3]: 0
Analog Functions* ADC Analog Input AFS1[3]: 1 AFS2[3]: 1
PA4 RXD0 UART 0 Receive Data AFS1[4]: 0 AFS2[4]: 0
Reserved AFS1[4]: 0 AFS2[4]: 1
Reserved AFS1[4]: 1 AFS2[4]: 0
Analog Functions* ADC/Comparator Input (N) AFS1[4]: 1 AFS2[4]: 1
PA5 TXD0 UART 0 Transmit Data AFS1[5]: 0 AFS2[5]: 0
T1OUT Timer 1 Output Complement AFS1[5]: 0 AFS2[5]: 1
Reserved AFS1[5]: 1 AFS2[5]: 0
Analog Functions* ADC/Comparator Input (P) AFS1[5]: 1 AFS2[5]: 1
Note: * Analog Functions include ADC inputs, ADC reference and comparator inputs. Also, alternate function selection
as described in Port A–C Alternate Function Sub-Registers must be enabled.
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GPIO Interrupts
Many of the GPIO port pins are used as interrupt sources. Some port pins are
configured to generate an interrupt request on either the rising edge or falling edge of the
pin input signal. Other port pin interrupt sources generate an interrupt when any edge
occurs (both rising and falling). For more information about interrupts using the GPIO
pins, see Interrupt Controller on page 53.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 17 lists these Port registers. Use the Port A–D Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Table 17. GPIO Port Registers and Sub-Registers
Port Register
Mnemonic Port Register Name
PxADDR Port A–C Address Register (Selects sub-registers)
PxCTL Port A–C Control Register (Provides access to sub-registers)
PxIN Port A–C Input Data Register
PxOUT Port A–C Output Data Register
Port Sub-Register
Mnemonic Port Register Name
PxDD Data Direction
PxAF Alternate Function
PxOC Output Control (Open-Drain)
PxHDE High Drive Enable
PxSMRE Stop Mode Recovery Source Enable
PxPUE Pull-up Enable
PxAFS1 Alternate Function Set 1
PxAFS2 Alternate Function Set 2
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Port A–C Address Registers
The Port A–C Address registers select the GPIO Port functionality accessible through the
Port A–C Control registers. The Port A–C Address and Control registers combine to
provide access to all GPIO Port controls (Table 18).
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control
register.
Port A–C Control Registers
The Port A–C Control registers set the GPIO port operation. The value in the
corresponding Port A–C Address register determines which sub-register is read from or
written to by a Port A–C Control register transaction (Table 19).
Table 18. Port A–C GPIO Address Registers (PxADDR)
BITS 7 6 5 4 3 2 1 0
FIELD PADDR[7:0]
RESET 00H
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FD0H, FD4H, FD8H
PADDR[7:0] Port Control Sub-register Accessible Using the Port A–C Control Registers
00H No function. Provides some protection against accidental Port reconfiguration.
01H Data Direction.
02H Alternate Function.
03H Output Control (Open-Drain).
04H High Drive Enable.
05H Stop Mode Recovery Source Enable.
06H Pull-up Enable.
07H Alternate Function Set 1.
08H Alternate Function Set 2.
09H–FFH No function.
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PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
Port A–C Data Direction Sub-Registers
The Port A–C Data Direction sub-register is accessed through the Port A–C Control
register by writing 01H to the Port A–C Address register (Table 20).
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function
operation overrides the Data Direction register setting.
0 = Output. Data in the Port A–C Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–C Input Data
Register. The output driver is tristated.
Port A–C Alternate Function Sub-Registers
The Port A–C Alternate Function sub-register (Table 21) is accessed through the Port A–C
Control register by writing 02H to the Port A–C Address register. The Port A–C Alternate
Function sub-registers enable the alternate function selection on pins. If disabled, pins
functions as GPIO. If enabled, select one of four alternate functions using alternate
function set subregisters 1 and 2 as described in the Port A–C Alternate Function Set 1
Sub-Registers on page 48 and Port A–C Alternate Function Set 2 Sub-Registers on
Table 19. Port A–C Control Registers (PxCTL)
BITS 7 6 5 4 3 2 1 0
FIELD PCTL
RESET 00H
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FD1H, FD5H, FD9H
Table 20. Port A–C Data Direction Sub-Registers (PxDD)
BITS 7 6 5 4 3 2 1 0
FIELD DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 01H in Port A–C Address Register, accessible through the Port A–C Control Register
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page 49.
See GPIO Alternate Functions on page 36 to determine the alternate
function associated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline can result in
unpredictable operation.
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–C Data Direction sub-
register determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set sub-registers is
enabled. Port pin operation is controlled by the alternate function.
Port A–C Output Control Sub-Registers
The Port A–C Output Control sub-register (Table 22) is accessed through the Port A–C
Control register by writing 03H to the Port A–C Address register. Setting the bits in the
Port A–C Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate
functions are also affected.
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and always disable the
drains if set to 1.
Table 21. Port A–C Alternate Function Sub-Registers (PxAF)
BITS 7 6 5 4 3 2 1 0
FIELD AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 00H (Ports A–C); 04H (Port A of 8-pin device)
R/W R/W
ADDR If 02H in Port A–C Address Register, accessible through the Port A–C Control Register
Table 22. Port A–C Output Control Sub-Registers (PxOC)
BITS 7 6 5 4 3 2 1 0
FIELD POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 03H in Port A–C Address Register, accessible through the Port A–C Control Register
Caution:
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0 = The drains are enabled for any output mode (unless overridden by the alternate
function).
1 = The drain of the associated pin is disabled (open-drain mode).
Port A–C High Drive Enable Sub-Registers
The Port A–C High Drive Enable sub-register (Table 23) is accessed through the Port
A–C Control register by writing 04H to the Port A–C Address register. Setting the bits in
the Port A–C High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–C High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled.
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–C Stop Mode Recovery Source Enable Sub-Registers
The Port A–C Stop Mode Recovery Source Enable sub-register (Table 24) is accessed
through the Port A–C Control register by writing 05H to the Port A–C Address register.
Setting the bits in the Port A–C Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
Table 23. Port A–C High Drive Enable Sub-Registers (PxHDE)
BITS 7 6 5 4 3 2 1 0
FIELD PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 04H in Port A–C Address Register, accessible through the Port A–C Control Register
Table 24. Port A–C Stop Mode Recovery Source Enable Sub-Registers (PxSMRE)
BITS 7 6 5 4 3 2 1 0
FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
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PSMRE[7:0]—Port Stop Mode Recovery Source Enabled.
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this pin
during STOP mode do not initiate Stop Mode Recovery.
1 = The Port pin is configured as a Stop Mode Recovery source. Any logic transition on
this pin during STOP mode initiates Stop Mode Recovery.
Port A–C Pull-up Enable Sub-Registers
The Port A–C Pull-up Enable sub-register (Table 25) is accessed through the Port A–C
Control register by writing 06H to the Port A–C Address register. Setting the bits in the
Port A–C Pull-up Enable sub-registers enables a weak internal resistive pull-up on the
specified Port pins.
PPUE[7:0]—Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Port A–C Alternate Function Set 1 Sub-Registers
The Port A–C Alternate Function Set1 sub-register (Table 26) is accessed through the Port
A–C Control register by writing 07H to the Port A–C Address register. The Alternate
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register are defined in GPIO Alternate
Functions on page 36.
Alternate function selection on port pins must also be enabled as described in Port A–C
Alternate Function Sub-Registers on page 45
.
Table 25. Port A–C Pull-Up Enable Sub-Registers (PxPUE)
BITS 7 6 5 4 3 2 1 0
FIELD PPUE7 PPUE6 PPUE5 PPUE4 PPUE3 PPUE2 PPUE1 PPUE0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 06H in Port A–C Address Register, accessible through the Port A–C Control Register
Note:
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PAFS1[7:0]—Port Alternate Function Set to 1
0 = Port Alternate Function selected as defined in Table 14 (see GPIO Alternate Functions
on page 36).
1 = Port Alternate Function selected as defined in Table 14 (see GPIO Alternate Functions
on page 36).
Port A–C Alternate Function Set 2 Sub-Registers
The Port A–C Alternate Function Set 2 sub-register (Table 27) is accessed through the
Port A–C Control register by writing 08H to the Port A–C Address register. The Alternate
Function Set 2 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register is defined in Table 14 in the
section GPIO Alternate Functions on page 36.
PAFS2[7:0]—Port Alternate Function Set 2
0 = Port Alternate Function selected as defined in Table 14 (see GPIO Alternate Functions
on page 36).
1 = Port Alternate Function selected as defined in Table 14.
Port A–C Input Data Registers
Reading from the Port A–C Input Data registers (Table 28) returns the sampled values
from the corresponding port pins. The Port A–C Input Data registers are read-only. The
value returned for any unused ports is 0. Unused ports include those missing on the 8- and
28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 26. Port A–C Alternate Function Set 1 Sub-Registers (PxAFS1)
BITS 7 6 5 4 3 2 1 0
FIELD PAFS17 PAFS16 PAFS15 PAFS14 PAFS13 PAFS12 PAFS11 PAFS10
RESET 00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device)
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 07H in Port A–C Address Register, accessible through the Port A–C Control Register
Table 27. Port A–C Alternate Function Set 2 Sub-Registers (PxAFS2)
BITS 7 6 5 4 3 2 1 0
FIELD PAFS27 PAFS26 PAFS25 PAFS24 PAFS23 PAFS22 PAFS21 PAFS20
RESET 00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device)
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR If 08H in Port A–C Address Register, accessible through the Port A–C Control Register
PS024314-0308 General-Purpose Input/Output
Z8 Encore! XP® F0823 Series
Product Specification
50
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low)
1 = Input data is logical 1 (High)
Port A–C Output Data Register
The Port A–C Output Data register (Table 29) controls the output data to the pins.
POUT[7:0]—Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate
function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by
setting the corresponding Port Output Control register bit to 1.
LED Drive Enable Register
The LED Drive Enable register (Table 30) activates the controlled current drive. The Port
C pin must first be enabled by setting the Alternate Function register to select the LED
function.
Table 28. Port A–C Input Data Registers (PxIN)
BITS 7 6 5 4 3 2 1 0
FIELD PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET XXXXXXXX
R/W RRRRRRRR
ADDR FD2H, FD6H, FDAH
Table 29. Port A–C Output Data Register (PxOUT)
BITS 7 6 5 4 3 2 1 0
FIELD POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FD3H, FD7H, FDBH
PS024314-0308 General-Purpose Input/Output
Z8 Encore! XP® F0823 Series
Product Specification
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.
LEDEN[7:0]—LED Drive Enable
These bits determine which Port C pins are connected to an internal current sink.
0 = Tristate the Port C pin.
1= Connect controlled current sink to the Port C pin.
LED Drive Level High Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 31).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
LEDLVLH[7:0]—LED Level High Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each
Port C pin.
00 = 3 mA
01= 7 mA
10= 13 mA
11= 20 mA
LED Drive Level Low Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 32).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 30. LED Drive Enable (LEDEN)
BITS 7 6 5 4 3 2 1 0
FIELD LEDEN[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F82H
Table 31. LED Drive Level High Register (LEDLVLH)
BITS 7 6 5 4 3 2 1 0
FIELD LEDLVLH[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F83H
PS024314-0308 General-Purpose Input/Output
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Product Specification
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LEDLVLH[7:0]—LED Level High Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each
Port C pin.
00 = 3 mA
01 = 7 mA
10 = 13 mA
11 = 20 mA
Table 32. LED Drive Level Low Register (LEDLVLL)
BITS 7 6 5 4 3 2 1 0
FIELD LEDLVLL[7:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F84H
PS024314-0308 Interrupt Controller
Z8 Encore! XP® F0823 Series
Product Specification
53
Interrupt Controller
The interrupt controller on the Z8 Encore! XP® F0823 Series products prioritizes the
interrupt requests from the on-chip peripherals and the GPIO port pins. The features of
interrupt controller include:
•
20 unique interrupt vectors
–12 GPIO port pin interrupt sources (two are shared)
–8 on-chip peripheral interrupt sources (two are shared)
•
Flexible GPIO interrupts
–Eight selectable rising and falling edge GPIO interrupts
–Four dual-edge interrupts
•
Three levels of individually programmable interrupt priority
•
Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control
information between the CPU and the interrupting peripheral. When the service routine is
completed, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. For more information on interrupt
servicing by the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) available for
download at www.zilog.com.
Interrupt Vector Listing
Table 33 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most-significant byte (MSB) at the even Program Memory address and the
least-significant byte (LSB) at the following odd Program Memory address.
Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt
is unavailable on devices not containing an ADC.
Note:
PS024314-0308 Interrupt Controller
Z8 Encore! XP® F0823 Series
Product Specification
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Table 33. Trap and Interrupt Vectors in Order of Priority
Priority
Program
Memory
Vector Address Interrupt or Trap Source
Highest 0002H Reset (not an interrupt)
0004H Watchdog Timer (see Watchdog Timer on page 87)
003AH Primary Oscillator Fail Trap (not an interrupt)
003CH Watchdog Timer Oscillator Fail Trap (not an interrupt)
0006H Illegal Instruction Trap (not an interrupt)
0008H Reserved
000AH Timer 1
000CH Timer 0
000EH UART 0 receiver
0010H UART 0 transmitter
0012H Reserved
0014H Reserved
0016H ADC
0018H Port A Pin 7, selectable rising or falling input edge
001AH Port A Pin 6, selectable rising or falling input edge or Comparator Output
001CH Port A Pin 5, selectable rising or falling input edge
001EH Port A Pin 4, selectable rising or falling input edge
0020H Port A Pin 3 or Port D Pin 3, selectable rising or falling input edge
0022H Port A Pin 2 or Port D Pin 2, selectable rising or falling input edge
0024H Port A Pin 1, selectable rising or falling input edge
0026H Port A Pin 0, selectable rising or falling input edge
0028H Reserved
002AH Reserved
002CH Reserved
002EH Reserved
0030H Port C Pin 3, both input edges
0032H Port C Pin 2, both input edges
0034H Port C Pin 1, both input edges
PS024314-0308 Interrupt Controller
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Architecture
Figure 8 displays the interrupt controller block diagram.
Figure 8. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
Execution of an Enable Interrupt (EI) instruction
•
Execution of an Return from Interrupt (IRET) instruction
Lowest 0036H Port C Pin 0, both input edges
0038H Reserved
Table 33. Trap and Interrupt Vectors in Order of Priority (Continued)
Priority
Program
Memory
Vector Address Interrupt or Trap Source
Vector
IRQ Request
High
Priority
Medium
Priority
Low
Priority
Priority
Mux
Interrupt Request Latches and Control
Port Interrupts
Internal Interrupts
PS024314-0308 Interrupt Controller
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•
Writing a 1 to the IRQE bit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
•
Execution of a Disable Interrupt (DI) instruction
•
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
•
Writing a 0 to the IRQE bit in the Interrupt Control register
•
Reset
•
Execution of a Trap instruction
•
Illegal Instruction Trap
•
Primary Oscillator Fail Trap
•
Watchdog Timer Oscillator Fail Trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all
interrupts are enabled with identical interrupt priority (for example, all as Level 2
interrupts), the interrupt priority is assigned from highest to lowest as specified in Table 33
on page 54. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 33. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap,
Watchdog Timer Oscillator Fail Trap, and Illegal Instruction Trap always have
highest (Level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the Interrupt Request register is cleared until the next interrupt
occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise
clears the interrupt request.
The following coding style that clears bits in the Interrupt Request registers is not
recommended. All incoming interrupts received between execution of the first LDX
command and the final LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
Caution:
PS024314-0308 Interrupt Controller
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To avoid missing interrupts, use the following coding style to clear bits in the Interrupt
Request 0 register:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code generates interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
The following coding style used to generate software interrupts by setting bits in the
Interrupt Request registers is not recommended. All incoming interrupts received
between execution of the first LDX command and the final LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the following coding style to set bits in the Interrupt
Request registers:
Good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Watchdog Timer Interrupt Assertion
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the timeout condi-
tion continues. As it operates on a different (and usually slower) clock domain than the
rest of the device, the Watchdog Timer continues to assert this interrupt for many system
clocks until the counter rolls over.
To avoid re-triggerings of the Watchdog Timer interrupt after exiting the associated in-
terrupt service routine, it is recommended that the service routine continues to read from
the RSTSTAT register until the WDT bit is cleared as given in the following coding
sample:
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt
bit
BTJNZ 5, r0, CLEARWDT ; loop until bit is cleared
Caution:
Caution:
Caution:
Caution:
PS024314-0308 Interrupt Controller
Z8 Encore! XP® F0823 Series
Product Specification
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Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Timer Oscillator Fail Trap, the interrupt control registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 0 register to determine if any interrupt requests are pending.
Reserved—Must be 0
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1
1 = An interrupt request from Timer 1 is awaiting service
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0
1 = An interrupt request from Timer 0 is awaiting service
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver
1 = An interrupt request from the UART 0 receiver is awaiting service
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter
1 = An interrupt request from the UART 0 transmitter is awaiting service
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the ADC
1 = An interrupt request from the ADC is awaiting service
Table 34. Interrupt Request 0 Register (IRQ0)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved T1I T0I U0RXI U0TXI Reserved Reserved ADCI
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC0H
PS024314-0308 Interrupt Controller
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Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 35) stores interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 register to determine if any interrupt requests are pending.
PA7VI—Port A7 Interrupt Request
0 = No interrupt request is pending for GPIO Port A
1 = An interrupt request from GPIO Port A
PA6CI—Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator
1 = An interrupt request from GPIO Port A or Comparator
PAxI—Port A Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port A pin x
1 = An interrupt request from GPIO Port A pin x is awaiting service
where x indicates the specific GPIO Port pin number (0–5)
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 36) stores interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 1 Register (IRQ1)
BITS 7 6 5 4 3 2 1 0
FIELD PA7VI PA6CI PA5I PA4I PA3I PA2I PA1I PA0I
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC3H
PS024314-0308 Interrupt Controller
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Reserved—Must be 0
PCxI—Port C Pin xInterrupt Request
0 = No interrupt request is pending for GPIO Port C pin x
1 = An interrupt request from GPIO Port C pin x is awaiting service
where x indicates the specific GPIO Port C pin number (0–3)
IRQ0 Enable High and Low Bit Registers
Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit
registers (Table 38 and Table 39) form a priority encoded enabling for interrupts in the
Interrupt Request 0 register. Priority is generated by setting bits in each register.
Table 36. Interrupt Request 2 Register (IRQ2)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved PC3I PC2I PC1I PC0I
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC6H
Table 37. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
1 1 Level 3 High
where x indicates the register bits from 0–7.
Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved T1ENH T0ENH U0RENH U0TENH Reserved Reserved ADCENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC1H
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Reserved—Must be 0
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—0 when read
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 40 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit
registers (Table 41 and Table 42) form a priority encoded enabling for interrupts in the
Interrupt Request 1 register. Priority is generated by setting bits in each register.
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved T1ENL T0ENL U0RENL U0TENL Reserved Reserved ADCENL
RESET 00000000
R/W R R/W R/W R/W R/W R R R/W
ADDR FC2H
Table 40. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]IRQ1ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
11Level 3 High
where x indicates the register bits from 0–7.
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PA7VENH—Port A Bit[7] Interrupt Request Enable High Bit
PA6CENH—Port A Bit[7] or Comparator Interrupt Request Enable High Bit
PAxENH—Port A Bit[x] Interrupt Request Enable High Bit
For selection of Port A as the interrupt source, see Shared Interrupt Select Register on
page 64.
PA7VENH—Port A Bit[7] Interrupt Request Enable Low Bit
PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
Table 43 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit
registers (Table 44 and Table 45) form a priority encoded enabling for interrupts in the
Interrupt Request 2 register. Priority is generated by setting bits in each register.
Table 41. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS 7 6 5 4 3 2 1 0
FIELD PA7VENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC4H
Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS 7 6 5 4 3 2 1 0
FIELD PA7VENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC5H
Table 43. IRQ2 Enable and Priority Encoding
IRQ2ENH[x]IRQ2ENL[x] Priority Description
0 0 Disabled Disabled
0 1 Level 1 Low
1 0 Level 2 Nominal
PS024314-0308 Interrupt Controller
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Reserved—Must be 0
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Reserved—Must be 0
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 46) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input
pin.
1 1 Level 3 High
where x indicates the register bits from 0–7.
Table 44. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved C3ENH C2ENH C1ENH C0ENH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC7H
Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved C3ENL C2ENL C1ENL C0ENL
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FC8H
Table 43. IRQ2 Enable and Priority Encoding (Continued)
IRQ2ENH[x]IRQ2ENL[x] Priority Description
PS024314-0308 Interrupt Controller
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IESx—Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx
1 = An interrupt request is generated on the rising edge of the PAx input PDx
where x indicates the specific GPIO port pin number (0 through 7)
Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) register (Table 47) determines the source of the
PADxS interrupts. The Shared Interrupt Select register selects between Port A and
alternate sources for the individual interrupts.
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
PA6CS—PA6/Comparator S election
0 = PA6 is used for the interrupt for PA6CS interrupt request
1 = The Comparator is used for the interrupt for PA6CS interrupt request
Reserved—Must be 0
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 48) contains the master enable bit for all
interrupts.
Table 46. Interrupt Edge Select Register (IRQES)
BITS 7 6 5 4 3 2 1 0
FIELD IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FCDH
Table 47. Shared Interrupt Select Register (IRQSS)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved PA6CS Reserved
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FCEH
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IRQE—Interrupt Request Enable
This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, reset or by a direct register
write of a 0 to this bit.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved—0 when read
Table 48. Interrupt Control Register (IRQCTL)
BITS 7 6 5 4 3 2 1 0
FIELD IRQE Reserved
RESET 00000000
R/W R/WRRRRRRR
ADDR FCFH
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PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
Product Specification
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Timers
Z8 Encore! XP® F0823 Series products contain up to two 16-bit reloadable timers that are
used for timing, event counting, or generation of PWM signals. The timers’ features
include:
•
16-bit reload counter.
•
Programmable prescaler with prescale values from 1 to 128.
•
PWM output generation.
•
Capture and compare capability.
•
External input pin for timer input, clock gating, or capture signal. External input pin signal
frequency is limited to a maximum of one-fourth the system clock frequency.
•
Timer output pin.
•
Timer interrupt.
In addition to the timers described in this chapter, the baud rate generator of the UART (if
unused) also provides basic timing functionality. For information on using the baud rate
generator as an additional timer, see Universal Asynchronous Receiver/Transmitter on
page 93.
Architecture
Figure 9 displays the architecture of the timers.
Figure 9. Timer Block Diagram
16-Bit
PWM/Compare
16-Bit Counter
with Prescaler
16-Bit
Reload Register
Timer
Control
Compare Compare
Interrupt,
PWM,
and
Timer Output
Control
Timer
Timer Block
System
Timer
Data
Block
Output
Control
Bus
Clock
Input
Gate
Input
Capture
Input
Timer
Interrupt
Timer
Output
Complement
Timer
Output
Complement
PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
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Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops
counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is appropriate to have the Timer Output make a state change at a One-Shot time-out
(rather than a single cycle pulse), first set the TPOL bit in the Timer Control register to the
start value before enabling ONE-SHOT mode. After starting the timer, set TPOL to the
opposite bit value.
Follow the steps below for configuring a timer for ONE-SHOT mode and initiating the
count:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for ONE-SHOT mode
–Set the prescale value
–Set the initial output level (High or Low) if using the Timer Output alternate
function
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
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6. Write to the Timer Control register to enable the timer and initiate counting.
In ONE-SHOT mode, the system clock always provides the timer input. The timer period
is given by the following equation:
CONTINUOUS Mode
In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer
Output alternate function is enabled, the Timer Output pin changes state (from Low to
High or from High to Low) at timer Reload.
Follow the steps below to configure a timer for CONTINUOUS mode and to initiate the
count:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for CONTINUOUS mode
–Set the prescale value
–If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This action only affects the first pass in CONTINUOUS mode. After the first
timer Reload in CONTINUOUS mode, counting always begins at the reset value of
0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by
writing to the relevant interrupt registers.
5. Configure the associated GPIO port pin (if using the Timer Output function) for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In CONTINUOUS mode, the system clock always provides the timer input. The timer
period is given by the following equation:
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT mode equation to determine the first time-out period.
ONE-SHOT Mode Time-Out Period (s) Reload Value Start Value
–()Prescale×
System Clock Frequency (Hz)
-----------------------------------------------------------------------------------------------=
CONTINUOUS Mode Time-Out Period (s) Reload Value Prescale
×
System Clock Frequency (Hz)
------------------------------------------------------------------------=
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COUNTER Mode
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO port pin Timer Input alternate function. The TPOL bit in the
Timer Control register selects whether the count occurs on the rising edge or the falling
edge of the timer input signal. In COUNTER mode, the prescaler is disabled.
The input frequency of the timer input signal must not exceed one-fourth the system
clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
Follow the steps below for configuring a timer for COUNTER mode and initiating the
count:
1. Write to the Timer Control register to:
–Disable the timer.
–Configure the timer for COUNTER mode.
–Select either the rising edge or falling edge of the Timer Input signal for the count.
This selection also sets the initial logic level (High or Low) for the Timer Output
alternate function. However, the Timer Output function is not required to be
enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in COUNTER mode. After the first timer Reload in
COUNTER mode, counting always begins at the reset value of 0001H. In COUNTER
mode the Timer High and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control register to enable the timer.
In COUNTER mode, the number of Timer Input transitions since the timer start is given
by the following equation:
Caution:
COUNTER Mode Timer Input Transitions Current Count Value Start Value–=
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COMPARATOR COUNTER Mode
In COMPARATOR COUNTER mode, the timer counts input transitions from the analog
comparator output. The TPOL bit in the Timer Control Register selects whether the count
occurs on the rising edge or the falling edge of the comparator output signal. In
COMPARATOR COUNTER mode, the prescaler is disabled.
The frequency of the comparator output signal must not exceed one-fourth the system
clock frequency.
After reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
Follow the steps below for configuring a timer for COMPARATOR COUNTER mode and
initiating the count:
1. Write to the Timer Control register to:
–Disable the timer.
–Configure the timer for COMPARATOR COUNTER mode.
–Select either the rising edge or falling edge of the comparator output signal for the
count. This also sets the initial logic level (High or Low) for the Timer Output
alternate function. However, the Timer Output function is not required to be
enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
action only affects the first pass in COMPARATOR COUNTER mode. After the first
timer Reload in COMPARATOR COUNTER mode, counting always begins at the
reset value of 0001H. Generally, in COMPARATOR COUNTER mode the Timer
High and Low Byte registers must be written with the value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer.
In COMPARATOR COUNTER mode, the number of comparator output transitions since
the timer start is given by the following equation:
Caution:
Comparator Output Transitions Current Count Value Start Value–=
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PWM SINGLE OUTPUT Mode
In PWM SINGLE OUTPUT mode, the timer outputs a PWM output signal through a
GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-bit
PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the Reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is
reset to 0001H.
Follow the steps below for configuring a timer for PWM Single Output mode and initiat-
ing the PWM operation:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for PWM mode
–Set the prescale value
–Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
PWM Period (s) Reload Value Prescale
×
System Clock Frequency (Hz)
------------------------------------------------------------------------=
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If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, use the ONE-SHOT mode equation to determine the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is
represented by the following equation:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is
represented by the following equation:
PWM Dual Output Mode
In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal pair (basic PWM
signal and its complement) through two GPIO port pins. The timer input is the system
clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM
High and Low Byte registers. When the timer count value matches the PWM value, the
Timer Output toggles. The timer continues counting until it reaches the Reload value
stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the Reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is
reset to 0001H.
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A
programmable deadband delay can be configured to time delay (0 to 128 system clock
cycles) PWM output transitions on these two pins from a low to a high (inactive to active).
This ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
Follow the steps below for configuring a timer for PWM Dual Output mode and initiating
the PWM operation:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for PWM Dual Output mode. Setting the mode also involves
writing to TMODEHI bit in TxCTL1 register
–Set the prescale value
PWM Output High Time Ratio (%) Reload Value PWM Value
–
Reload Value
------------------------------------------------------------------- 100×=
PWM Output High Time Ratio (%) PWM Value
Reload Value
------------------------------------100×=
PS024314-0308 Timers
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–Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control register to set the PWM dead band delay value. The
deadband delay must be less than the duration of the positive phase of the PWM signal
(as defined by the PWM high and low byte registers). It must also be less than the
duration of the negative phase of the PWM signal (as defined by the difference
between the PWM registers and the Timer Reload registers).
5. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
7. Configure the associated GPIO port pin for the Timer Output and Timer Output
Complement alternate functions. The Timer Output Complement function is shared
with the Timer Input function for both timers. Setting the timer mode to Dual PWM
automatically switches the function from Timer In to Timer Out Complement.
8. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the ONE-SHOT mode equation determines the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the
Timer Control register determines if the Capture occurs on a rising edge or a falling edge
PWM Period (s) Reload Value Prescale
×
System Clock Frequency (Hz)
------------------------------------------------------------------------=
PWM Output High Time Ratio (%) Reload Value PWM Value–
Reload Value
-------------------------------------------------------------------100×=
PWM Output High Time Ratio (%) PWM Value
Reload Value
------------------------------------100×=
PS024314-0308 Timers
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of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the
timer continues counting. The INPCAP bit in TxCTL1 register is set to indicate the timer
interrupt is because of an input capture event.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting. The INPCAP bit in TxCTL1 register clears indicating
the timer interrupt is not because of an input capture event.
Follow the steps below for configuring a timer for CAPTURE mode and initiating the
count:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for CAPTURE mode
–Set the prescale value
–Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these
registers allows the software to determine if interrupts were generated by either a
Capture or a Reload event. If the PWM High and Low Byte registers still contain
0000H after the interrupt, the interrupt was generated by a Reload.
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input Capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the Reload event by setting TICONFIG
field of the TxCTL1 register.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
CAPTURE RESTART Mode
In CAPTURE RESTART mode, the current timer count value is recorded when the
acceptable external Timer Input transition occurs. The Capture count value is written to
the Timer PWM High and Low Byte Registers. The timer input is the system clock. The
TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or
a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is
Capture Elapsed Time (s) Capture Value Start Value–()Prescale
×
System Clock Frequency (Hz)
--------------------------------------------------------------------------------------------------=
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generated and the count value in the Timer High and Low Byte registers is reset to 0001H
and counting resumes. The INPCAP bit in TxCTL1 register is set to indicate the timer
interrupt is because of an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate
the timer interrupt is not caused by an input capture event.
Follow the steps below for configuring a timer for CAPTURE RESTART mode and initi-
ating the count:
1. Write to the Timer Control register to:
–Disable the timer.
–Configure the timer for CAPTURE RESTART mode. Setting the mode also
involves writing to TMODEHI bit in TxCTL1 register.
–Set the prescale value.
–Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows the
software to determine if interrupts were generated by either a Capture or a Reload
event. If the PWM High and Low Byte registers still contain 0000H after the interrupt,
the interrupt was generated by a Reload.
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input Capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input Capture event or the Reload event by setting TICONFIG
field of the TxCTL1 register.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
COMPARE Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
Capture Elapsed Time (s) Capture Value Start Value–()Prescale
×
System Clock Frequency (Hz)
--------------------------------------------------------------------------------------------------=
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timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon
Compare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. Follow
the steps below to configure a timer for COMPARE mode and to initiate the count:
1. Write to the Timer Control register to:
–Disable the timer.
–Configure the timer for Compare mode.
–Set the prescale value.
–Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate.
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control register to enable the timer and initiate counting.
In COMPARE mode, the system clock always provides the timer input. The Compare time
can be calculated by the following equation:
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer Reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal remains asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
COMPARE Mode Time (s) Compare Value Start Value–()Prescale
×
System Clock Frequency (Hz)
-----------------------------------------------------------------------------------------------------=
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Follow the steps below to configure a timer for GATED mode and to initiate the count:
1. Write to the Timer Control register to:
–Disable the timer
–Configure the timer for Gated mode
–Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. Writing
these registers only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input deassertion and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input deassertion event or the Reload event by setting
TICONFIG field of the TxCTL1 register.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer
Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the Timer Input signal captures
the current count value. The Capture value is written to the Timer PWM High and Low
Byte Registers. When the Capture event occurs, an interrupt is generated, the count value
in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. The
INPCAP bit in TxCTL1 register is set to indicate the timer interrupt is caused by an input
Capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate
the timer interrupt is not because of an input Capture event.
Follow the steps below for configuring a timer for CAPTURE/COMPARE mode and initi-
ating the count:
1. Write to the Timer Control register to:
–Disable the timer
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–Configure the timer for CAPTURE/COMPARE mode
–Set the prescale value
–Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers.By default, the timer interrupt are generated for both
input Capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input Capture event or the Reload event by setting TICONFIG
field of the TxCTL1 register.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In CAPTURE/COMPARE mode, the elapsed time from timer start to Capture event can be
calculated using the following equation:
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte
register is read, the contents of the Timer Low Byte register are placed in a holding
register. A subsequent read from the Timer Low Byte register returns the value in the hold-
ing register. This operation allows accurate reads of the full 16-bit timer count value while
enabled. When the timers are not enabled, a read from the Timer Low Byte register returns
the actual value in the counter.
Timer Pin Signal Operation
Timer Output is a GPIO port pin alternate function. The Timer Output is toggled every
time the counter is reloaded.
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output. When selected by the GPIO Alternate Function Registers,
this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT
mode. For this mode, there is no timer input available.
Capture Elapsed Time (s)
C
ap
t
ure
V
a
l
ue
St
ar
t
V
a
l
ue–()
P
resca
l
e×
System Clock Frequency (Hz)
------------------------------------------------------------------------------------------------------------------------
=
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Timer Control Register Definitions
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) registers (Table 49 and Table 50)
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TxL
always returns this temporary register when the timers are enabled. When the timer is dis-
abled, reads from the TxL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
TH and TL—Timer High and Low Bytes
These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value
Timer Reload High and Low Byte Registers
The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers (Table 51 and
Table 52) store a 16-bit Reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer
Reload High Byte register are stored in a temporary holding register. When a write to the
Timer Reload Low Byte register occurs, the temporary holding register value is written to
the Timer High Byte register. This operation allows simultaneous updates of the 16-bit
Timer Reload value.
Table 49. Timer 0–1 High Byte Register (TxH)
BITS 7 6 5 4 3 2 1 0
FIELD TH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F00H, F08H
Table 50. Timer 0–1 Low Byte Register (TxL)
BITS 7 6 5 4 3 2 1 0
FIELD TL
RESET 00000001
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F01H, F09H
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In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit
Compare value.
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H. In Compare mode, these
two bytes form the 16-bit Compare value.
Timer 0-1 PWM High and Low Byte Registers
The Timer 0-1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Table 53
and Table 54) control pulse-width modulator (PWM) operations. These registers also store
the Capture values for the CAPTURE and CAPTURE/COMPARE modes.
Table 51. Timer 0–1 Reload High Byte Register (TxRH)
BITS 7 6 5 4 3 2 1 0
FIELD TRH
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F02H, F0AH
Table 52. Timer 0–1 Reload Low Byte Register (TxRL)
BITS 7 6 5 4 3 2 1 0
FIELD TRL
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F03H, F0BH
Table 53. Timer 0–1 PWM High Byte Register (TxPWMH)
BITS 7 6 5 4 3 2 1 0
FIELD PWMH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F04H, F0CH
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PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1)
register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Timer 0–1 Control Registers
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1)
determine the timer operating mode. It also includes a programmable PWM deadband
delay, two bits to configure timer interrupt definition, and a status bit to identify if the
most recent timer interrupt is caused by an input Capture event.
TMODEHI—Timer Mode High Bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most-significant bit of the Timer mode selection value. See the
TxCTL1 register description for more details.
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
Table 54. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS 7 6 5 4 3 2 1 0
FIELD PWML
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F05H, F0DH
Table 55. Timer 0–1 Control Register 0 (TxCTL0)
BITS 7 6 5 4 3 2 1 0
FIELD TMODEHI TICONFIG Reserved PWMD INPCAP
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F06H, F0EH
PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
Product Specification
83
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events
10 = Timer Interrupt only on defined Input Capture/Deassertion Events
11 = Timer Interrupt only on defined Reload/Compare Events
Reserved—Must be 0
PWMD—PWM Delay value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
INPCAP—Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture
Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event
1 = Previous timer interrupt is a result of Timer Input Capture Event
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
TEN—Timer Enable
0 = Timer is disabled
1 = Timer enabled to count
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer
Table 56. Timer 0–1 Control Register 1 (TxCTL1)
BITS 7 6 5 4 3 2 1 0
FIELD TEN TPOL PRES TMODE
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F07H, F0FH
PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
Product Specification
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ONE-SHOT Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
CONTINUOUS Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
COUNTER Mode
If the timer is enabled the Timer Output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal
1 = Count occurs on the falling edge of the Timer Input signal
PWM SINGLE OUTPUT Mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
CAPTURE Mode
0 = Count is captured on the rising edge of the Timer Input signal
1 = Count is captured on the falling edge of the Timer Input signal
COMPARE Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
GATED Mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
Product Specification
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CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
PWM DUAL OUTPUT Mode
0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1)
when the timer is disabled. When enabled, the Timer Output is forced High (1) upon
PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output
Complement is forced Low (0) upon PWM count match and forced High (1) upon
Reload. The PWMD field in TxCTL0 register is a programmable delay to control the
number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0)
when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon
PWM count match and forced High (1) upon Reload.When enabled, the Timer Output
Complement is forced High (1) upon PWM count match and forced Low (0) upon
Reload. The PWMD field in TxCTL0 register is a programmable delay to control the
number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to Low (0).
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the Timer Input signal
1 = Count is captured on the falling edge of the Timer Input signal
COMPARATOR COUNTER Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, Tx-
OUT changes to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit with the timer enabled and running does not
immediately change the TxOUT.
PRES—Prescale value.
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This reset ensures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
Caution:
PS024314-0308 Timers
Z8 Encore! XP® F0823 Series
Product Specification
86
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE—Timer mode
This field along with the TMODEHI bit in TxCTL0 register determines the operating
mode of the timer. TMODEHI is the most significant bit of the Timer mode selection
value.
0000 = ONE-SHOT mode
0001 = CONTINUOUS mode
0010 = COUNTER mode
0011 = PWM SINGLE OUTPUT mode
0100 = CAPTURE mode
0101 = COMPARE mode
0110 = GATED mode
0111 = CAPTURE/COMPARE mode
1000 = PWM DUAL OUTPUT mode
1001 = CAPTURE RESTART mode
1010 = COMPARATOR COUNTER Mode
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
87
Watchdog Timer
The Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults,
and other system-level problems which can place Z8 Encore! XP® F0823 Series devices
into unsuitable operating states. The features of Watchdog Timer include:
•
On-chip RC oscillator
•
A selectable time-out response: reset or interrupt
•
24-bit programmable time-out value
Operation
The WDT is a retriggerable one-shot timer that resets or interrupts Z8 Encore! XP F0823
Series devices when the WDT reaches its terminal count. The Watchdog Timer uses a ded-
icated on-chip RC oscillator as its clock source. The Watchdog Timer operates in only two
modes: ON and OFF. Once enabled, it always counts and must be refreshed to prevent a
time-out. Perform an enable by executing the WDT instruction or by setting the WDT_AO
Flash Option Bit. The WDT_AO bit forces the Watchdog Timer to operate immediately
upon reset, even if a WDT instruction has not been executed.
The Watchdog Timer is a 24-bit reloadable down counter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
described by the following equation:
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator
frequency is 10 kHz. The Watchdog Timer cannot be refreshed after it reaches 000002H.
The WDT Reload Value must not be set to values below 000004H. Table 57 provides
information about approximate time-out delays for the minimum and maximum WDT
reload values.
Table 57. Watchdog Timer Approximate Time-Out Delays
WDT Reload Value
(Hex)
WDT Reload Value
(Decimal)
Approximate Time-Out Delay
(with 10 kHz typical WDT oscillator frequency)
Typical Description
000004 4 400 µs Minimum time-out delay
FFFFFF 16,777,215 28 minutes Maximum time-out delay
WDT Time-out Period (ms) WDT Reload Value
10
------------------------------------------
=
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
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Watchdog Timer Refresh
When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload
registers. The Watchdog Timer counts down to 000000H unless a WDT instruction is
executed by the eZ8 CPU. Execution of the WDT instruction causes the down counter to be
reloaded with the WDT Reload value stored in the Watchdog Timer Reload registers.
Counting resumes following the reload operation.
When Z8 Encore! XP® F0823 Series devices are operating in DEBUG Mode (using the
OCD), the Watchdog Timer is continuously refreshed to prevent any Watchdog Timer
time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
Option Bit determines the time-out response of the Watchdog Timer. For information on
programming of the WDT_RES Flash Option Bit, see Flash Option Bits on page 141.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFH and continues counting. The Watchdog Timer
counter is not automatically returned to its Reload Value.
The Reset Status Register (see Reset Status Register on page 28) must be read before
clearing the WDT interrupt. This read clears the WDT time-out Flag and prevents further
WDT interrupts for immediately occurring.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and Z8 Encore! XP F0823
Series are in STOP mode, the Watchdog Timer automatically initiates a Stop Mode Recov-
ery and generates an interrupt request. Both the WDT status bit and the STOP bit in the
Watchdog Timer Control register are set to 1 following a WDT time-out in STOP mode.
For more information on Stop Mode Recovery, see Reset and Stop Mode Recovery on
page 21.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and
executing code from the vector address.
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
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WDT Reset in NORMAL Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer Control
register is set to 1. For more information on System Reset, see Reset and Stop Mode
Recovery on page 21.
WDT Reset in STOP Mode
If configured to generate a Reset when a time-out occurs and the device is in STOP mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Watchdog Timer Control register are set to 1 following WDT time-out in
STOP mode. For more information, see Reset and Stop Mode Recovery on page 21.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer Control Register (WDTCTL) address
unlocks the three Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL)
to allow changes to the time-out period. These write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the Reload registers. The following sequence is required to
unlock the Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL) for
write access.
1. Write 55H to the Watchdog Timer Control register (WDTCTL).
2. Write AAH to the Watchdog Timer Control register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte register (WDTU).
4. Write the Watchdog Timer Reload High Byte register (WDTH).
5. Write the Watchdog Timer Reload Low Byte register (WDTL).
All three Watchdog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
Watchdog Timer Control Register Definitions
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) register is a write-only control register. Writing
the 55H, AAH unlock sequence to the WDTCTL register address unlocks the three
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
90
Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to
the time-out period. These write operations to the WDTCTL register address produce no
effect on the bits in the WDTCTL register. The locking mechanism prevents spurious
writes to the Reload registers.
This register address is shared with the read-only Reset Status Register.
WDTUNLK—Watchdog Timer Unlock
The software must write the correct unlocking sequence to this register before it is allowed
to modify the contents of the Watchdog Timer reload registers.
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL)
registers (Tables 59 through Table 61) form the 24-bit reload value that is loaded into the
Watchdog Timer when a WDT instruction executes. The 24-bit reload value is
{WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate
Reload Value. Reading from these registers returns the current Watchdog Timer count
value.
The 24-bit WDT Reload Value must not be set to a value less than 000004H.
Table 58. Watchdog Timer Control Register (WDTCTL)
BITS 7 6 5 4 3 2 1 0
FIELD WDTUNLK
RESET XXXXXXXX
R/W WWWWWWWW
ADDR FF0H
Caution:
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
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WDTU—WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
WDTH—WDT Reload High Byte
Middle byte, Bits[15:8], of the 24-bit WDT reload value.
WDTL—WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
Table 59. Watchdog Timer Reload Upper Byte Register (WDTU)
BITS 7 6 5 4 3 2 1 0
FIELD WDTU
RESET 00H
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF1H
R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
Table 60. Watchdog Timer Reload High Byte Register (WDTH)
BITS 76543210
FIELD WDTH
RESET 04H
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF2H
R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
Table 61. Watchdog Timer Reload Low Byte Register (WDTL)
BITS 7654321 0
FIELD WDTL
RESET 00H
R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
ADDR FF3H
R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
PS024314-0308 Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
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PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
93
Universal Asynchronous
Receiver/Transmitter
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication
channel capable of handling asynchronous data transfers. The UART uses a single 8-bit
data mode with selectable parity. The features of UART include:
•
8-bit asynchronous data transfer
•
Selectable even- and odd-parity generation and checking
•
Option of one or two STOP bits
•
Separate transmit and receive interrupts
•
Framing, parity, overrun, and break detection
•
Separate transmit and receive enables
•
16-bit baud rate generator (BRG)
•
Selectable MULTIPROCESSOR (9-bit) mode with three configurable interrupt schemes
•
BRG can be configured and used as a basic 16-bit timer
•
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate
generator. The UART’s transmitter and receiver function independently, but employ the
same baud rate and data format. Figure 10 displays the UART architecture.
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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Figure 10. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
(lsb) first. An even or odd parity bit can be added to the data stream. Each character begins
with an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figure 11
and Figure 12 display the asynchronous data format employed by the UART without par-
ity and with parity, respectively.
Receive Shifter
Receive Data
Transmit Data
Transmit Shift
TXD
RXD
System Bus
Parity Checker
Parity Generator
Receiver Control
Control Registers
Transmitter Control
CTS
Status Register
Register
Register
Register
Baud Rate
Generator
DE
with Address Compare
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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Figure 11. UART Asynchronous Data Format without Parity
Figure 12. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow the steps below to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the required baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the UART Control 1 register, if MULTIPROCESSOR mode is appropriate, to
enable MULTIPROCESSOR (9-bit) mode functions.
4. Set the Multiprocessor Mode Select (MPEN) bit to enable MULTIPROCESSOR mode.
5. Write to the UART Control 0 register to:
–Set the transmit enable bit (TEN) to enable the UART for data transmission
–Set the parity enable bit (PEN), if parity is appropriate and MULTIPROCESSOR
mode is not enabled, and select either even or odd parity (PSEL).
–Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin.
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Data Field
lsb msb
Idle State
of Line
Stop Bit(s)
1
2
1
0
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity
Data Field
lsb msb
Idle State
of Line
Stop Bit(s)
1
2
1
0
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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6. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data
register is empty (indicated by a 1). If empty, continue to step 7. If the Transmit Data
register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data register becomes available to receive new data.
7. Write the UART Control 1 register to select the outgoing address bit.
8. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
9. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate
and MULTIPROCESSOR mode is enabled,.
11. To transmit additional bytes, return to step 5.
Transmitting Data using the Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow the steps below to configure the UART for
interrupt-driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the acceptable priority.
5. Write to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode
functions, if MULTIPROCESSOR mode is appropriate.
6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
7. Write to the UART Control 0 register to:
–Set the transmit enable bit (TEN) to enable the UART for data transmission.
–Enable parity, if appropriate and if MULTIPROCESSOR mode is not enabled, and
select either even or odd parity.
–Set or clear CTSE to enable or disable control from the remote receiver using the
CTS pin.
8. Execute an EI instruction to enable interrupts.
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data register is empty, an interrupt is generated immediately. When the UART
Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Write the UART Control 1 register to select the multiprocessor bit for the byte to be
transmitted:
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
2. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow the steps below to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud
rate for the incoming data stream.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the UART Control 1 register to enable MULTIPROCESSOR mode functions,
if appropriate.
4. Write to the UART Control 0 register to:
–Set the receive enable bit (REN) to enable the UART for data reception
–Enable parity, if appropriate and if Multiprocessor mode is not enabled, and select
either even or odd parity
5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data
register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to step 6. If the Receive Data register is empty (indicated by a
0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data register. If operating in MULTIPROCESSOR
(9-bit) mode, further actions may be required depending on the MULTIPROCESSOR
mode bits MPMD[1:0].
7. Return to step 4 to receive additional data.
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
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Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow the steps below to configure the UART receiver for interrupt-driven
operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the acceptable priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode
functions, if appropriate.
–Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR
mode
–Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address
matching scheme
–Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore! XP devices
without a DMA block)
7. Write the device address to the Address Compare Register (automatic
MULTIPROCESSOR modes only).
8. Write to the UART Control 0 register to:
– Set the receive enable bit (REN) to enable the UART for data reception
– Enable parity, if appropriate and if multiprocessor mode is not enabled, and select
either even or odd parity
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Checks the UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. Reads the data from the UART Receive Data register if the interrupt was because of
data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the MULTIPROCESSOR mode bits MPMD[1:0].
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
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3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.
4. Executes the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this action is typically performed during Stop Bit transmission. If CTS deasserts
in the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-Bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for
selective communication when a number of processors share a common UART bus. In
MULTIPROCESSOR mode (also referred to as 9-bit mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as displayed in Figure 13. The character format is given below:
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the
Multiprocessor control bit. The UART Control 1 and Status 1 registers provide
MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 MP
Data Field
lsb msb
Idle State
of Line
Stop Bit(s)
1
2
1
0
PS024314-0308 Universal Asynchronous Receiver/Transmitter
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100
in hardware, software or some combination of the two, depending on the multiprocessor
configuration bits. In general, the address compare feature reduces the load on the CPU,
because it does not require access to the UART when it receives data directed to other
devices on the multi-node network. The following three MULTIPROCESSOR modes are
available in hardware:
•
Interrupt on all address bytes
•
Interrupt on matched address bytes and correctly framed data bytes
•
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all
multiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. Each new incoming byte
interrupts the CPU. The software is responsible for determining the end of the frame. It
checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for
each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame
is different from the UART’s address, MPMD[0] must be set to 1 causing the UART
interrupts to go inactive until the next address byte. If the new frame’s address matches the
UART’s, the data in the new frame is processed as well.
The second scheme requires the following: set MPMD[1:0] to 10B and write the UART’s
address into the UART Address Compare register. This mode introduces additional
hardware control, interrupting only on frames that match the UART’s address. When an
incoming address byte does not match the UART’s address, it is ignored. All successive
data bytes in this frame are also ignored. When a matching address byte occurs, an inter-
rupt is issued and further interrupts now occur on each successive data byte. When the first
data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted.
All successive data bytes have NEWFRM=0. When the next address byte occurs, the hard-
ware compares it to the UART’s address. If there is a match, the interrupts continues and
the NEWFRM bit is set for the first byte of the new frame. If there is no match, the UART
ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame remains accompanied by a NEWFRM assertion.
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
101
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in Figure 14. The Driver Enable signal asserts
when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the final Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data
Register before the previous character is completely transmitted) the DE signal is not
deasserted between characters. The DEPOL bit in the UART Control Register 1 sets the
polarity of the Driver Enable signal.
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity
Data Field
lsb msb
Idle State
of Line
Stop Bit
1
1
0
0
1
DE
1
Baud Rate (Hz)
-----------------------------------------
DE to Start Bit Setup Time (s) 2
Baud Rate (Hz)
-----------------------------------------
≤≤
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
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102
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for
transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the
first bit of data out. The Transmit Data register can now be written with the next character
to send. This action provides 7 bit periods of latency to load the Transmit Data register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data register clears the TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte is received and is available in the UART Receive Data register. This interrupt
can be disabled independently of the other receiver interrupt sources. The received data in-
terrupt occurs after the receive character has been received and placed in the Receive Data
register. To avoid an overrun error, software must respond to this received data available
condition before the next character is completely received.
In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
•
A break is received
•
An overrun is detected
•
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte cannot contain valid data and must be ignored. The BRKD bit indicates
if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data register must be read again to clear the error
bits is the UART Status 0 register. Updates to the Receive Data register occur only when
the next data word is received.
UART Data and Error Handling Procedure
Figure 15 displays the recommended procedure for use in UART receiver interrupt
service routines.
Note:
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
103
Figure 15. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This condition allows the Baud
Rate Generator to function as an additional counter if the UART functionality is not
employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the Baud Rate Generator is the system clock. The UART Baud
Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
Receiver
Errors?
No
Yes
Read Status
Discard Data
Read Data which
Interrupt
Receiver
Ready
clears RDA bit and
resets error bits
Read Data
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
104
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer
with interrupt on time-out. Follow the steps below to configure the Baud Rate Generator
as a timer with interrupt on time-out:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register
to 0.
2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the UART Control 1 register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/
Decoders. For more information on the infrared operation, see Infrared Encoder/Decoder
on page 113.
UART Transmit Data Register
Data bytes written to the UART Transmit Data register (Table 62) are shifted out on the
TXDx pin. The Write-only UART Transmit Data register shares a Register File address
with the read-only UART Receive Data register.
TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
Table 62. UART Transmit Data Register (U0TXD)
BITS 7 6 5 4 3 2 1 0
FIELD TXD
RESET XXXXXXXX
R/W WWWWWWWW
ADDR F40H
UART Data Rate (bits/s) System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value
×
---------------------------------------------------------------------------------
=
Interrupt Interval (s) System Clock Period (s) BRG[15:0]×=
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
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UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data register
(Table 63). The read-only UART Receive Data register shares a Register File address with
the Write-only UART Transmit Data register.
RXD—Receive Data
UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 64 and Table 65) identify the current
UART operating configuration and status.
RDA—Receive Data Available
This bit indicates that the UART Receive Data register has received data. Reading the
UART Receive Data register clears this bit.
0 = The UART Receive Data register is empty
1 = There is a byte in the UART Receive Data register
PE—Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data
register clears this bit.
0 = No parity error has occurred
1 = A parity error has occurred
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
Table 63. UART Receive Data Register (U0RXD)
BITS 7 6 5 4 3 2 1 0
FIELD RXD
RESET XXXXXXXX
R/W RRRRRRRR
ADDR F40H
Table 64. UART Status 0 Register (U0STAT0)
BITS 7 6 5 4 3 2 1 0
FIELD RDA PE OE FE BRKD TDRE TXE CTS
RESET 000001 1X
R/W RRRRRR R R
ADDR F41H
PS024314-0308 Universal Asynchronous Receiver/Transmitter
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received and the UART Receive Data register has not been read. If the RDA bit is reset to
0, reading the UART Receive Data register clears this bit.
0 = No overrun error occurred
1 = An overrun error occurred
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data register clears this bit.
0 = No framing error occurred
1 = A framing error occurred
BRKD—Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data register clears this bit.
0 = No break occurred
1 = A break occurred
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data register is empty and ready for additional
data. Writing to the UART Transmit Data register resets this bit.
0 = Do not write to the UART Transmit Data register
1 = The UART Transmit Data register is ready to receive an additional byte to be transmit-
ted
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting
1 = Transmission is complete
CTS—CTS signal
When this bit is read it returns the level of the CTS signal. This signal is active Low.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 65. UART Status 1 Register (U0STAT1)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved NEWFRM MPRX
RESET 000000 0 0
R/W RRRRR/WR/WR R
ADDR F44H
PS024314-0308 Universal Asynchronous Receiver/Transmitter
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Reserved—R/W bits must be 0 during writes; 0 when read.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame
1 = The current byte is the first data byte of a new frame
MPRX—Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Table 66 and Table 67) configure the
properties of the UART’s transmit and receive operations. The UART Control registers
must not be written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled
1 = Transmitter enabled
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled
1 = Receiver enabled
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter
1 = The UART recognizes the CTS signal as an enable control from the transmitter
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit
Table 66. UART Control 0 Register (U0CTL0)
BITS 7 6 5 4 3 2 1 0
FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F42H
PS024314-0308 Universal Asynchronous Receiver/Transmitter
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PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data
1 = Odd parity is transmitted and expected on all received data
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent
1 = Forces a break condition by setting the output of the transmitter to zero
STOP—Stop Bit Select
0 = The transmitter sends one stop bit
1 = The transmitter sends two stop bits
LBEN—Loop Back Enable
0 = Normal operation
1 = All transmitted data is looped back to the receiver
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address)
01 = The UART generates an interrupt request only on received address bytes
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs
11 = The UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the Address Compare Register
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode
1 = Enable MULTIPROCESSOR (9-bit) mode
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit
is used by the receiving device to determine if the data byte contains address or data infor-
mation.
Table 67. UART Control 1 Register (U0CTL1)
BITS 7 6 5 4 3 2 1 0
FIELD MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN
RESET 000000 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
ADDR F43H
PS024314-0308 Universal Asynchronous Receiver/Transmitter
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0 = Send a 0 in the multiprocessor bit location of the data stream (data byte)
1 = Send a 1 in the multiprocessor bit location of the data stream (address byte)
DEPOL—Driver Enable Polarity
0 = DE signal is Active High
1 = DE signal is Active Low
BRGCTL—Baud Rate Control
This bit causes an alternate UART behavior depending on the value of the REN bit in the
UART Control 0 Register.
When the UART receiver is not enabled (REN=0), this bit determines whether the Baud
Rate Generator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate
Registers to return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High
Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt
Controller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register stores the multi-node network address of the UART.
When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes are
compared to the value stored in the Address Compare register. Receive interrupts and
RDA assertions only occur in the event of a match.
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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COMP_ADDR—Compare Address
This 8-bit value is compared to incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Table 69 and Table 70) combine to
create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate
(baud rate) of the UART.
The UART data rate is calculated using the following equation:
For a given UART data rate, calculate the integer baud rate divisor value using the
following equation:
Table 68. UART Address Compare Register (U0ADDR)
BITS 7 6 5 4 3 2 1 0
FIELD COMP_ADDR
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F45H
Table 69. UART Baud Rate High Byte Register (U0BRH)
BITS 7 6 5 4 3 2 1 0
FIELD BRH
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F46H
Table 70. UART Baud Rate Low Byte Register (U0BRL)
BITS 7 6 5 4 3 2 1 0
FIELD BRL
RESET 11111111
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F47H
UART Baud Rate (bits/s) System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value
×
---------------------------------------------------------------------------------
=
UART Baud Rate Divisor Value (BRG) Round System Clock Frequency (Hz)
16 UART Data Rate (bits/s)
×
------------------------------------------------------------------
=
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
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The baud rate error relative to the acceptable baud rate is calculated using the following
equation:
For reliable communication, the UART baud rate error must never exceed five percent.
Table 71 provides information about data rate errors for 5.5296 MHz System Clock.
Table 71. UART Baud Rates
5.5296 MHz System Clock
Acceptable Rate
(kHz)
BRG Divisor
(Decimal)
Actual Rate
(kHz) Error (%)
1250.0 N/A N/A N/A
625.0 N/A N/A N/A
250.0 1 345.6 38.24
115.2 3 115.2 0.00
57.6 6 57.6 0.00
38.4 9 38.4 0.00
19.2 18 19.2 0.00
9.60 36 9.60 0.00
4.80 72 4.80 0.00
2.40 144 2.40 0.00
1.20 288 1.20 0.00
0.60 576 0.60 0.00
0.30 1152 0.30 0.00
UART Baud Rate Error (%) 100 Actual Data Rate Desired Data Rate
–
Desired Data Rate
-------------------------------------------------------------------------------------
×=
PS024314-0308 Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP® F0823 Series
Product Specification
112
PS024314-0308 Infrared Encoder/Decoder
Z8 Encore! XP® F0823 Series
Product Specification
113
Infrared Encoder/Decoder
Z8 Encore! XP® F0823 Series products contain a fully-functional, high-performance
UART with Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an
on-chip UART to allow easy communication between the Z8 Encore! XP and IrDA Phys-
ical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communi-
cation provides secure, reliable, low-cost, point-to-point communication between PCs,
PDAs, cell phones, printers and other infrared enabled devices.
Architecture
Figure 16 displays the architecture of the Infrared Endec.
Figure 16. Infrared Data Communication System Block Diagram
Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the
infrared transceiver through the TXD pin. Similarly, data received from the infrared
transceiver is passed to the Infrared Endec through the RXD pin, decoded by the Infrared
Interrupt
Signal
RXD
TXD
Infrared
Encoder/Decoder
UART
RxD
TxD
System
Clock
I/O
Address
Data
Infrared
Transceiver
RXD
TXD
Baud Rate
Clock
(Endec)
PS024314-0308 Infrared Encoder/Decoder
Z8 Encore! XP® F0823 Series
Product Specification
114
Endec, and passed to the UART. Communication is half-duplex, which means
simultaneous data transmission and reception is not allowed.
The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud
rates from 9600 baud to 115.2 kbaud. Higher baud rates are possible, but do not meet IrDA
specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec
data rate is calculated using the following equation:
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
low for the full 16 clock period. If the data to be transmitted is 0, the transmitter first
outputs a 7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse
is output to complete the full 16 clock data period. Figure 17 displays IrDA data transmis-
sion. When the Infrared Endec is enabled, the UART’s TXD signal is internal to
Z8 Encore! XP® F0823 Series products while the IR_TXD signal is output through the
TXD pin.
Figure 17. Infrared Data Transmission
Infrared Data Rate (bits/s) System Clock Frequency (Hz)
16 UART Baud Rate Divisor Value
×
---------------------------------------------------------------------------------
=
Baud Rate
IR_TXD
UART’s
16 clock
period
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
7-clock
delay
3 clock
pulse
TXD
Clock
PS024314-0308 Infrared Encoder/Decoder
Z8 Encore! XP® F0823 Series
Product Specification
115
Receiving IrDA Data
Data received from the infrared transceiver using the IR_RXD signal through the RXD pin
is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is
used by the Infrared Endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 displays data
reception. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the
Z8 Encore! XP® F0823 Series products while the IR_RXD signal is received through the
RXD pin.
Figure 18. IrDA Data Reception
Infrared Data Reception
The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.4
µ
s minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (that is, 24 baud clock periods
since the previous pulse was detected), giving the Endec a sampling window of minus four
Baud Rate
UART’s
IR_RXD
16 clock
period
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
8 clock
delay
Clock
RXD
16 clock
period
16 clock
period
16 clock
period
16 clock
period
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
min. 1.4 µs
pulse
Caution:
PS024314-0308 Infrared Encoder/Decoder
Z8 Encore! XP® F0823 Series
Product Specification
116
baud rate clocks to plus eight baud rate clocks around the expected time of an incoming
pulse. If an incoming pulse is detected inside this window this process is repeated. If the
incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for
the next falling edge. As each falling edge is detected, the Endec clock counter is reset,
resynchronizing the Endec to the incoming signal, allowing the Endec to tolerate jitter and
baud rate errors in the incoming datastream. Resynchronizing the Endec does not alter the
operation of the UART, which ultimately receives the data. The UART is only synchro-
nized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control
registers as defined in Universal Asynchronous Receiver/Transmitter on page 93.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO port alternate function for the corresponding pin.
Caution:
PS024314-0308 Analog-to-Digital Converter
Z8 Encore! XP® F0823 Series
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Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to its digital
representation. The features of this sigma-delta ADC include:
•
10-bit resolution
•
Eight single-ended analog input sources are multiplexed with general-purpose I/O ports
•
Interrupt upon conversion complete
•
Bandgap generated internal voltage reference generator with two selectable levels
•
Factory offset and gain calibration
Architecture
Figure 19 displays the major functional blocks of the ADC. An analog multiplexer
network selects the ADC input from the available analog pins, ANA0 through ANA7.
PS024314-0308 Analog-to-Digital Converter
Z8 Encore! XP® F0823 Series
Product Specification
118
Figure 19. Analog-to-Digital Converter Block Diagram
Operation
Data Format
The output of the ADC is an 11-bit, signed, two’s complement digital value. The output
generally ranges from 0 to +1023, but offset errors can cause small negative values.
The ADC registers return 13 bits of data, but the two LSBs are intended for compensation
use only. When the compensation routine is performed on the 13 bit raw ADC value, two
Analog Input
Multiplexer
Internal Voltage
Reference Generator
Analog Input
Ref Input
VREF
ADC
IRQ
ADC
Data
Vrefsel
2
11
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
VREFEXT
ANAIN
4
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bits of resolution are lost because of a rounding error. As a result, the final value is an
11- bit number.
Automatic Powerdown
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered down. From this powerdown state, the
ADC requires 40 system clock cycles to powerup. The ADC powers up when a conversion
is requested by the ADC Control register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a single-
shot conversion:
1. Enable the acceptable analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write the ADC Control/Status Register 1 to configure the ADC
–Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in the ADC Control/Status Register 1.
3. Write to the ADC Control Register 0 to configure the ADC and begin the conversion.
The bit fields in the ADC Control register can be written simultaneously:
–Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device).
–Clear CONT to 0 to select a single-shot conversion.
–If the internal voltage reference must be output to a pin, set the REFEXT bit to 1.
The internal voltage reference must be enabled in this case.
–Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in the ADC Control Register 0.
–Set CEN to 1 to start the conversion.
4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
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5. When the conversion is complete, the ADC control logic performs the following
operations:
–11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}.
–CEN resets to 0 to indicate the conversion is complete.
6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the
ADC and the latency of the ADC and its digital filter. Step changes at the input are not
detected at the next output from the ADC. The response of the ADC (in all modes) is lim-
ited by the input signal bandwidth and the latency.
Follow the steps below for setting up the ADC and initiating continuous conversion:
1. Enable the acceptable analog input by configuring the general-purpose I/O pins for
alternate function. This action disables the digital input and output driver.
2. Write the ADC Control/Status Register 1 to configure the ADC:
–Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in the ADC Control/Status Register 1.
3. Write to the ADC Control Register 0 to configure the ADC for continuous conversion.
The bit fields in the ADC Control register can be written simultaneously:
–Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device).
–Set CONT to 1 to select continuous conversion.
–If the internal VREF must be output to a pin, set the REFEXT bit to 1. The
internal voltage reference must be enabled in this case.
–Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in ADC Control Register 0.
–Set CEN to 1 to start the conversions.
Caution:
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4. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
–CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation.
–An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete.
5. The ADC writes a new data result every 256 system clock cycles. For each completed
conversion, the ADC control logic performs the following operations:
–Writes the 11-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:5]}.
–An interrupt request to the Interrupt Controller denoting conversion complete.
6. To disable continuous conversion, clear the CONT bit in the ADC Control register
to 0.
Interrupts
The ADC is able to interrupt the CPU whenever a conversion has been completed and the
ADC is enabled.
When the ADC is disabled, an interrupt is not asserted; however, an interrupt pending
when the ADC is disabled is not cleared.
Calibration and Compensation
Z8 Encore! XP® F0823 Series ADC can be factory calibrated for offset error and gain
error, with the compensation data stored in Flash memory. Alternatively, user code can
perform its own calibration, storing the values into Flash themselves.
Factory Calibration
Devices that have been factory calibrated contain nine bytes of calibration data in the
Flash option bit space. This data consists of three bytes for each reference type. For a list
of input modes for which calibration data exists, see Zilog Calibration Data on page 147.
There is 1 byte for offset, 2 bytes for gain correction.
User Calibration
If you have precision references available, its own external calibration can be performed,
storing the values into Flash themselves.
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Software Compensation Procedure
The value read from the ADC high and low byte registers are uncompensated. The user
mode software must apply gain and offset correction to this uncompensated value for
maximum accuracy. The following formula yields the compensated value:
where GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and
ADCuncomp is the uncompensated value read from the ADC. The OFFCAL value is in
two’s complement format, as are the compensated and uncompensated ADC values.
The offset compensation is performed first, followed by the gain compensation. One bit of
resolution is lost because of rounding on both the offset and gain computations. As a result
the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and
10 data bits. Also note that in the second term, the multiplication must be performed
before the division by 216. Otherwise, the second term evaluates to zero incorrectly.
Although the ADC can be used without the gain and offset compensation, it does exhibit
non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
ADC Control Register Definitions
The following sections define the ADC control registers.
ADC Control Register 0
The ADC Control register selects the analog input channel and initiates the
analog-to-digital conversion.
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion is complete.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Table 72. ADC Control Register 0 (ADCCTL0)
BITS 7 6 5 4 3 2 1 0
FIELD CEN REFSELL REFEXT CONT ANAIN[3:0]
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F70H
ADCcomp ADCuncomp OFFCAL–()ADCuncomp OFFCAL–()
∗GAINCAL()216
⁄+=
Note:
Caution:
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Z8 Encore! XP® F0823 Series
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REFSELL—Voltage Reference Level Select Low Bit; in conjunction with the High bit
(REFSELH) in ADC Control/Status Register 1, this determines the level of the internal
voltage reference; the following details the effects of {REFSELH, REFSELL};
This reference is independent of the Comparator reference.
00= Internal Reference Disabled, reference comes from external pin.
01= Internal Reference set to 1.0 V
10= Internal Reference set to 2.0 V (default)
REFEXT—External Reference Select
0 = External reference buffer is disabled; Vref pin is available for GPIO functions
1 = The internal ADC reference is buffered and connected to the Vref pin
CONT
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system
clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN[3:0]—Analog Input Select
These bits select the analog input for conversion. Not all port pins in this list are available
in all packages for Z8 Encore! XP® F0823 Series. For information on the port pins avail-
able with each package style, see Pin Description on page 7. Do not enable unavailable
analog inputs. Usage of these bits changes depending on the buffer mode selected in ADC
Control/Status Register 1.
For the reserved values, all input switches are disabled to avoid leakage or other undesir-
able operation. ADC samples taken with reserved bit settings are undefined.
Single-Ended:
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = Reserved
1001 = Reserved
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
Note:
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ADC Control/Status Register 1
The second ADC Control register contains the voltage reference level selection bit.
REFSELH—Voltage Reference Level Select High Bit; in conjunction with the Low bit
(REFSELL) in ADC Control Register 0, this determines the level of the internal voltage
reference; the following details the effects of {REFSELH, REFSELL}; this reference is
independent of the Comparator reference
00= Internal Reference Disabled, reference comes from external pin
01= Internal Reference set to 1.0 V
10= Internal Reference set to 2.0 V (default)
ADC Data High Byte Register
The ADC Data High Byte register contains the upper eight bits of the ADC output. The
output is an 11-bit two’s complement value. During a single-shot conversion, this value is
invalid. Access to the ADC Data High Byte register is read-only. Reading the ADC Data
High Byte register latches data in the ADC Low Bits register.
ADCDH—ADC Data High Byte
This byte contains the upper eight bits of the ADC output. These bits are not valid during a
single-shot conversion. During a continuous conversion, the most recent conversion out-
put is held in this register. These bits are undefined after a Reset.
Table 73. ADC Control/Status Register 1 (ADCCTL1)
BITS 7 6 5 4 3 2 1 0
FIELD REFSELH Reserved
RESET 10000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F71H
Table 74. ADC Data High Byte Register (ADCD_H)
BITS 7 6 5 4 3 2 1 0
FIELD ADCDH
RESET XXXXXXXX
R/W RRRRRRRR
ADDR F72H
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ADC Data Low Bits Register
The ADC Data Low Byte register contains the lower bits of the ADC output as well as an
overflow status bit. The output is a 11-bit two’s complement value. During a single-shot
conversion, this value is invalid. Access to the ADC Data Low Byte register is read-only.
Reading the ADC Data High Byte register latches data in the ADC Low Bits register.
ADCDL—ADC Data Low Bits
These bits are the least significant three bits of the 11-bits of the ADC output. These bits
are undefined after a Reset.
Reserved—Undefined when read
OVF—Overflow Status
0= An overflow did not occur in the digital filter for the current sample
1= An overflow did occur in the digital filter for the current sample
Table 75. ADC Data Low Bits Register (ADCD_L)
BITS 7 6 5 4 3 2 1 0
FIELD ADCDL Reserved OVF
RESET XXXXXXXX
R/W RRRRRRRR
ADDR F73H
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PS024314-0308 Comparator
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Product Specification
127
Comparator
Z8 Encore! XP® F0823 Series devices feature a general purpose comparator that com-
pares two analog input signals. A GPIO (CINP) pin provides the positive comparator
input. The negative input (CINN) can be taken from either an external GPIO pin or an
internal reference. The output is available as an interrupt source or can be routed to an
external pin using the GPIO multiplex. The features of Comparator include:
•
Two inputs which can be connected up using the GPIO multiplex (MUX)
•
One input can be connected to a programmable internal reference
•
One input can be connected to the on-chip temperature sensor
•
Output can be either an interrupt source or an output to an external pin
Operation
One of the comparator inputs can be connected to an internal reference which is a user
selectable reference that is user programmable with 200 mV resolution.
The comparator can be powered down to save on supply current. For details, see Power
Control Register 0 on page 32.
Because of the propagation delay of the comparator, it is not recommended to enable
the comparator without first disabling interrupts and waiting for the comparator output
to settle. Doing so can result in spurious interrupts after comparator enabling. The fol-
lowing example shows how to safely enable the comparator:
di
ld cmp0
nop
nop ; wait for output to settle
clr irq0 ; clear any spurious interrupts pending
ei
Comparator Control Register Definitions
Comparator Control Register
The Comparator Control register (CMPCTL) configures the comparator inputs and sets
the value of the internal voltage reference.
Caution:
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INPSEL—Signal Select for Positive Input
0 = GPIO pin used as positive comparator input
1 = temperature sensor used as positive comparator input
INNSEL—Signal Select for Negative Input
0 = internal reference disabled, GPIO pin used as negative comparator input
1 = internal reference enabled as negative comparator input
REFLVL—Internal Reference Voltage Level
This reference is independent of the ADC voltage reference.
0000 = 0.0 V
0001 = 0.2 V
0010 = 0.4 V
0011 = 0.6 V
0100 = 0.8 V
0101 = 1.0 V (Default)
0110 = 1.2 V
0111 = 1.4 V
1000 = 1.6 V
1001 = 1.8 V
1010–1111 = Reserved
Reserved—R/W bits must be 0 during writes; 0 when read
Table 76. Comparator Control Register (CMP0)
BITS 7 6 5 4 3 2 1 0
FIELD INPSEL INNSEL REFLVL Reserved
RESET 00010100
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F90H
Note:
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Z8 Encore! XP® F0823 Series
Product Specification
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Flash Memory
The products in Z8 Encore! XP® F0823 Series features either 8 KB (8192), 4 KB (4096),
2 KB (2048) or 1 KB (1024) of non-volatile Flash memory with read/write/erase capabil-
ity. Flash Memory can be programmed and erased in-circuit by either user code or through
the On-Chip Debugger.
The Flash Memory array is arranged in pages with 512 bytes per page. The 512-byte page
is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64
bytes.
For program/data protection, the Flash memory is also divided into sectors. In the
Z8 Encore! XP F0823 Series, these sectors are either 1024 bytes (in the 8 KB devices) or
512 bytes in size (all other memory sizes); each sector maps to a page. Page and sector
sizes are not generally equal.
The first two bytes of the Flash Program memory are used as Flash Option Bits. For more
information on their operation, see Flash Option Bits on page 141.
Table 77 describes the Flash memory configuration for each device in the Z8 Encore! XP
F0823 Series. Figure 20 displays the Flash memory arrangement.
Table 77. Z8 Encore! XP F0823 Series Flash Memory Configurations
Part Number
Flash Size
KB (Bytes)
Flash
Pages
Program Memory
Addresses
Flash Sector
Size (bytes)
Z8F08x3 8 (8192) 16 0000H–1FFFH 1024
Z8F04x3 4 (4096) 8 0000H–0FFFH 512
Z8F02x3 2 (2048) 4 0000H–07FFH 512
Z8F01x3 1 (1024) 2 0000H–03FFH 512
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Figure 20. Flash Memory Arrangement
Flash Information Area
The Flash information area is separate from program memory and is mapped to the
address range FE00H to FFFFH. Not all these addresses are accessible. Factory trim values
for the analog peripherals are stored here. Factory calibration data for the ADC is also
stored here.
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Operation
The Flash Controller programs and erases Flash memory. The Flash Controller provides
the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase
of Flash memory.
The Flash Controller contains several protection mechanisms to prevent accidental
programming or erasure. These mechanism operate on the page, sector and full-memory
levels.
The Flowchart in Figure 21 displays basic Flash Controller operation. The following sub-
sections provide details about the various operations (Lock, Unlock, Byte Programming,
Page Protect, Page Unprotect, Page Select Page Erase, and Mass Erase) displayed in
Figure 21.
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Figure 21. Flash Controller Operation Flowchart
Reset
Page
73H
No
Yes
8CH
No
Yes
Program/Erase
Enabled
95H
No
Yes
Write FCTL
Lock State 0
Lock State 1
Write FCTL
Write FCTLByte Program
Page Erase
Write Page
Select Register
Write Page
Select Register
Page in
No
No
Unlocked
Protected Sector?
Writes to Page Select
Register in Lock State 1
result in a return to
Lock State 0
Page Select
Yes
values match?
Yes
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Flash Operation Timing Using the Flash Frequency Registers
Before performing either a program or erase operation on Flash memory, you must first
configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis-
ters allow programming and erasing of the Flash with system clock frequencies ranging
from 32 kHz (32768 Hz) through 20 MHz.
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash
Frequency value must contain the system clock frequency (in kHz). This value is
calculated using the following equation:
Flash programming and erasure are not supported for system clock frequencies below
32 kHz (32768 Hz) or above 20 MHz. The Flash Frequency High and Low Byte
registers must be loaded with the correct value to ensure operation of Z8 Encore! XP®
F0823 Series devices.
Flash Code Protection Against External Access
The user code contained within the Flash memory can be protected against external access
with the On-Chip Debugger. Programming the FRP Flash Option Bit prevents reading of
the user code with the On-Chip Debugger. For more information, see Flash Option Bits on
page 141 and On-Chip Debugger on page 151.
Flash Code Protection Against Accidental Program and Erasure
Z8 Encore! XP F0823 Series provides several levels of protection against accidental pro-
gram and erasure of the Flash memory contents. This protection is provided by a combina-
tion of the Flash Option bits, the register locking mechanism, the page select redundancy
and the sector level protection control of the Flash Controller.
Flash Code Protection Using the Flash Option Bits
The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program
Memory protection as listed in Table 78. For more information, see Flash Option Bits on
page 141.
FFREQ[15:0] System Clock Frequency (Hz)
1000
-------------------------------------------------------------------------------=
Caution:
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.
Flash Code Protection Using the Flash Controller
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the Flash memory, first write the Page Select Register with
the target page. Unlock the Flash Controller by making two consecutive writes to the
Flash Control register with the values 73H and 8CH, sequentially. The Page Select Register
must be rewritten with the same page previously stored there. If the two Page Select writes
do not match, the controller reverts to a locked state. If the two writes match, the selected
page becomes active. For more details, see Figure 21.
After unlocking a specific page, you can enable either Page Program or Erase. Writing the
value 95H causes a Page Erase only if the active page resides in a sector that is not
protected. Any other value written to the Flash Control register locks the Flash Controller.
Mass Erase is not allowed in the user code but only in through the Debug Port.
After unlocking a specific page, you can also write to any byte on that page. After a byte is
written, the page remains unlocked, allowing for subsequent writes to other bytes on the
same page. Further writes to the Flash Control Register cause the active page to revert to a
locked state.
Sector Based Flash Protection
The final protection mechanism is implemented on a per-sector basis. The Flash memories
of Z8 Encore! XP devices are divided into maximum number of 8 sectors. A sector is 1/8
of the total size of the Flash memory, unless this value is smaller than the page size, in
which case the sector and page sizes are equal.
The Sector Protect Register controls the protection state of each Flash sector. This register
is shared with the Page Select Register. It is accessed by writing 73H followed by 5EH to
the Flash controller. The next write to the Flash Control Register targets the Sector Protect
Register.
The Sector Protect Register is initialized to 0 on reset, putting each sector into an
unprotected state. When a bit in the Sector Protect Register is written to 1, the
corresponding sector can no longer be written or erased by the CPU. External Flash pro-
gramming through the OCD or via the Flash Controller Bypass mode are unaffected. After
Table 78. Flash Code Protection Using the Flash Option Bits
FWP Flash Code Protection Description
0 Programming and erasing disabled for all of Flash Program Memory. In user
code programming, Page Erase, and Mass Erase are all disabled. Mass Erase
is available through the On-Chip Debugger.
1 Programming, Page Erase, and Mass Erase are enabled for all of Flash
Program Memory.
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a bit of the Sector Protect Register has been set, it cannot be cleared except by powering
down the device.
Byte Programming
The Flash Memory is enabled for byte programming after unlocking the Flash Controller
and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is
unlocked and Mass Erase is successfully completed, all Program Memory locations are
available for byte programming. In contrast, when the Flash Controller is unlocked and
Page Erase is successfully enabled, only the locations of the selected page are available for
byte programming. An erased Flash byte contains all 1’s (FFH). The programming
operation can only be used to change bits from 1 to 0. To change a Flash bit (or multiple
bits) from 0 to 1 requires execution of either the Page Erase or Mass Erase commands.
Byte Programming is accomplished using the On-Chip Debugger's Write Memory
command or eZ8 CPU execution of the LDC or LDCI instructions. For a description of the
LDC and LDCI instructions, refer to eZ8 CPU Core User Manual (UM0128) available for
download at www.zilog.com. While the Flash Controller programs the Flash memory, the
eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To exit
programming mode and lock the Flash, write any value to the Flash Control register,
except the Mass Erase or Page Erase commands.
The byte at each address of the Flash memory cannot be programmed (any bits written
to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted
data at the target byte.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Flash Page Select register
identifies the page to be erased. Only a page residing in an unprotected sector can be
erased. With the Flash Controller unlocked and the active page set, writing the value 95h
to the Flash Control register initiates the Page Erase operation. While the Flash Controller
executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip
peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase
operation completes. If the Page Erase operation is performed using the On-Chip Debug-
ger, poll the Flash Status register to determine when the Page Erase operation is complete.
When the Page Erase is complete, the Flash Controller returns to its locked state.
Mass Erase
The Flash memory can also be Mass Erased using the Flash Controller, but only by using
the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH.
With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the
Caution:
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value 63H to the Flash Control register initiates the Mass Erase operation. While the Flash
Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and
on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash
Status register to determine when the Mass Erase operation is complete. When the Mass
Erase is complete, the Flash Controller returns to its locked state.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program-
ming algorithms by controlling the Flash programming signals directly.
Row programing is recommended for gang programming applications and large volume
customers who do not require in-circuit initial programming of the Flash memory. Page
Erase operations are also supported when the Flash Controller is bypassed.
For more information on bypassing the Flash Controller, refer to Third-Party Flash Pro-
gramming Support for Z8 Encore! (AN0117) available for download at www.zilog.com.
Flash Controller Behavior in DEBUG Mode
The following changes in behavior of the Flash Controller occur when the Flash
Controller is accessed using the On-Chip Debugger:
•
The Flash Write Protect option bit is ignored
•
The Flash Sector Protect register is ignored for programming and erase operations
•
Programming operations are not limited to the page selected in the Page Select
register
•
Bits in the Flash Sector Protect register can be written to one or zero
•
The second write of the Page Select register to unlock the Flash Controller is not
necessary
•
The Page Select register can be written when the Flash Controller is unlocked
•
The Mass Erase command is enabled through the Flash Control register
For security reasons, Flash controller allows only a single page to be opened for write/
erase. When writing multiple Flash pages, the Flash controller must go through the un-
lock sequence again to select another page.
Caution:
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Flash Control Register Definitions
Flash Control Register
The Flash Controller must be unlocked using the Flash Control (FTCTL) register before
programming or erasing the Flash memory. Writing the sequence 73H 8CH, sequentially,
to the Flash Control register unlocks the Flash Controller. When the Flash Controller is
unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the
appropriate enable command to the FCTL. Page Erase applies only to the active page
selected in Flash Page Select register. Mass Erase is enabled only through the On-Chip
Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to
its locked state. The Write-only Flash Control Register shares its Register File address
with the read-only Flash Status Register.
FCMD—Flash Command
73H = First unlock command
8CH = Second unlock command
95H = Page Erase command (must be third command in sequence to initiate Page Erase)
63H = Mass Erase command (must be third command in sequence to initiate Mass Erase)
5EH = Enable Flash Sector Protect Register Access
Flash Status Register
The Flash Status register indicates the current state of the Flash Controller. This register
can be read at any time. The read-only Flash Status Register shares its Register File
address with the write-only Flash Control Register.
Table 79. Flash Control Register (FCTL)
BITS 7 6 5 4 3 2 1 0
FIELD FCMD
RESET 00000000
R/W WWWWWWWW
ADDR FF8H
Table 80. Flash Status Register (FSTAT)
BITS 7 6 5 4 3 2 1 0
FIELD Reserved FSTAT
RESET 00000000
R/W RRRRRRRR
ADDR FF8H
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Reserved—0 when read
FSTAT—Flash Controller Status
000000 = Flash Controller locked
000001 = First unlock command received (73H written)
000010 = Second unlock command received (8CH written)
000011 = Flash Controller unlocked
000100 = Sector protect register selected
001xxx = Program operation in progress
010xxx = Page erase operation in progress
100xxx = Mass erase operation in progress
Flash Page Select Register
The Flash Page Select (FPS) register shares address space with the Flash Sector Protect
Register. Unless the Flash controller is unlocked and written with 5EH, writes to this
address target the Flash Page Select Register.
The register is used to select one of the eight available Flash memory pages to be pro-
grammed or erased. Each Flash Page contains 512 bytes of Flash memory. During a Page
Erase operation, all Flash memory having addresses with the most significant 7-bits given
by FPS[6:0] are chosen for program/erase operation.
INFO_EN—Information Area Enable
0 = Information Area us not selected
1 = Information Area is selected. The Information Area is mapped into the Program Mem-
ory address space at addresses FE00H through FFFFH.
PAGE—Page Select
This 7-bit field identifies the Flash memory page for Page Erase and page unlocking.
Program Memory Address[15:9] = PAGE[6:0]. For the Z8F04x3 devices, the upper 4 bits
must always be 0. For the Z8F02x3 devices, the upper 5 bits must always be 0. For the
Z8F01x3 devices, the upper 6 bits must always be 0.
Table 81. Flash Page Select Register (FPS)
BITS 7 6 5 4 3 2 1 0
FIELD INFO_EN PAGE
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FF9H
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Product Specification
139
Flash Sector Protect Register
The Flash Sector Protect (FPROT) register is shared with the Flash Page Select Register.
When the Flash Control Register is written with 73H followed by 5EH, the next write to
this address targets the Flash Sector Protect Register. In all other cases, it targets the Flash
Page Select Register.
This register selects one of the 8 available Flash memory sectors to be protected. The reset
state of each Sector Protect bit is an unprotected state. After a sector is protected by setting
its corresponding register bit, it cannot be unprotected (the register bit cannot be cleared)
without powering down the device.
SPROT7-SPROT0—Sector Protection
Each bit corresponds to a 512 bytes Flash sector. For the Z8F08x3 devices, the upper 3 bits
must be zero. For the Z8F04x3 devices all bits are used. For the Z8F02x3 devices, the
upper 4 bits are unused. For the Z8F01x3 devices, the upper 6 bits are unused.
Flash Frequency High and Low Byte Registers
The Flash Frequency High (FFREQH) and Low Byte (FFREQL) registers combine to
form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit binary Flash Frequency value must contain the system clock frequency (in
kHz) and is calculated using the following equation:
The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper operation of the device. Also, Flash programming and erasure is not
supported for system clock frequencies below 20 kHz or above 20 MHz.
Table 82. Flash Sector Protect Register (FPROT)
BITS 7 6 5 4 3 2 1 0
FIELD SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FF9H
FFREQ[15:0] FFREQH[7:0],FFREQL[7:0]{}
System Clock Frequency
1000
------------------------------------------------------------------==
Caution:
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Product Specification
140
FFREQH—Flash Frequency High Byte
High byte of the 16-bit Flash Frequency value
FFREQL—Flash Frequency Low Byte
Low byte of the 16-bit Flash Frequency value
Table 83. Flash Frequency High Byte Register (FFREQH)
BITS 7 6 5 4 3 2 1 0
FIELD FFREQH
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FFAH
Table 84. Flash Frequency Low Byte Register (FFREQL)
BITS 7 6 5 4 3 2 1 0
FIELD FFREQL
RESET 0
R/W R/W
ADDR FFBH
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Product Specification
141
Flash Option Bits
Programmable Flash option bits allow user configuration of certain aspects of
Z8 Encore! XP® F0823 Series operation. The feature configuration data is stored in the
Flash program memory and loaded into holding registers during Reset. The features
available for control through the Flash Option Bits include:
•
Watchdog Timer time-out response selection–interrupt or system reset
•
Watchdog Timer always on (enabled at Reset)
•
The ability to prevent unwanted read access to user code in Program Memory
•
The ability to prevent accidental programming and erasure of all or a portion of the
user code in Program Memory
•
Voltage Brownout configuration-always enabled or disabled during STOP mode to
reduce STOP mode power consumption
•
Factory trimming information for the internal precision oscillator
•
Factory calibration values for ADC
•
Factory serialization and randomized lot identifier (optional)
Operation
Option Bit Configuration By Reset
Each time the Flash Option Bits are programmed or erased, the device must be Reset for
the change to take effect. During any reset operation (System Reset, Power-On Reset, or
Stop Mode Recovery), the Flash Option Bits are automatically read from the Flash
Program Memory and written to Option Configuration registers. The Option
Configuration registers control operation of the devices within the Z8 Encore! XP F0823
Series. Option Bit control is established before the device exits Reset and the eZ8 CPU
begins code execution. The Option Configuration registers are not part of the Register File
and are not accessible for read or write access.
Option Bit Types
User Option Bits
The user option bits are contained in the first two bytes of program memory. Access to
these bits has been provided because these locations contain application-specific device
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Product Specification
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configurations. The information contained here is lost when page 0 of the Program
Memory is erased.
Trim Option Bits
The trim option bits are contained in the information page of the Flash memory. These bits
are factory programmed values required to optimize the operation of onboard analog cir-
cuitry and cannot be permanently altered. Program Memory may be erased without endan-
gering these values. It is possible to alter working values of these bits by accessing the
Trim Bit Address and Data Registers, but these working values are lost after a power loss
or any other reset event.
There are 32 bytes of trim data. To modify one of these values the user code must first
write a value between 00H and 1FH into the Trim Bit Address Register. The next write to
the Trim Bit Data register changes the working value of the target trim data byte.
Reading the trim data requires the user code to write a value between 00H and 1FH into the
Trim Bit Address Register. The next read from the Trim Bit Data register returns the work-
ing value of the target trim data byte.
The trim address range is from information address 20-3F only. The remainder of the
information page is not accessible through the trim bit address and data registers.
Calibration Option Bits
The calibration option bits are also contained in the information page. These bits are fac-
tory programmed values intended for use in software correcting the device’s analog per-
formance. To read these values, the user code must employ the LDC instruction to access
the information area of the address space as defined in Flash Information Area on page 15
Serialization Bits
As an optional feature, Zilog® is able to provide factory-programmed serialization. For
serialized products, the individual devices are programmed with unique serial numbers.
These serial numbers are binary values, four bytes in length. The numbers increase in size
with each device, but gaps in the serial sequence may exist.
These serial numbers are stored in the Flash information page (for more details, see Read-
ing the Flash Information Page on page 143 and Serialization Data on page 148) and are
unaffected by mass erasure of the device’s Flash memory.
Randomized Lot Identification Bits
As an optional feature, Zilog is able to provide a factory-programmed random lot
identifier. With this feature, all devices in a given production lot are programmed with the
same random number. This random number is uniquely regenerated for each successive
production lot and is not likely to be repeated.
Note:
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Product Specification
143
The randomized lot identifier is a 32 byte binary value, stored in the flash information
page (for more details, see Reading the Flash Information Page on page 143 and Random-
ized Lot Identifier on page 149) and is unaffected by mass erasure of the device's flash
memory.
Reading the Flash Information Page
The following code example shows how to read data from the Flash Information Area.
; get value at info address 60 (FE60h)
ldx FPS, #%80 ; enable access to flash info page
ld R0, #%FE
ld R1, #%60
ldc R2, @RR0 ; R2 now contains the calibration value
Flash Option Bit Control Register Definitions
Trim Bit Address Register
The Trim Bit Address (TRMADR) register contains the target address for an access to the
trim option bits.
Table 85. Trim Bit Address Register (TRMADR)
BITS 7 6 5 4 3 2 1 0
FIELD TRMADR - Trim Bit Address (00H to 1FH)
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FF6H
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Trim Bit Data Register
The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim
option bits.
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved
for the user-programmable Flash option bits.
Flash Program Memory Address 0000H
WDT_RES—Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watchdog Timer Always ON
0 = Watchdog Timer is automatically enabled upon application of system power. Watch-
dog Timer can not be disabled.
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled, the
Table 86. Trim Bit Data Register (TRMDR)
BITS 7 6 5 4 3 2 1 0
FIELD TRMDR - Trim Bit Data
RESET 00000000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR FF7H
Table 87. Flash Option Bits at Program Memory Address 0000H
BITS 7 6 5 4 3 2 1 0
FIELD WDT_RES WDT_AO Reserved VBO_AO FRP Reserved FWP
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
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Product Specification
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Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This setting is
the default for unprogrammed (erased) Flash.
Reserved—R/W bits must be 1 during writes; 1 when read.
VBO_AO—Voltage Brownout Protection Always ON
0 = Voltage Brownout Protection can be disabled in STOP mode to reduce total power
consumption. For the block to be disabled, the power control register bit must also be writ-
ten (see Power Control Register 0 on page 32).
1 = Voltage Brownout Protection is always enabled including during STOP mode. This
setting is the default for unprogrammed (erased) Flash.
FRP—Flash Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
Reserved—Must be 1
FWP—Flash Write Protect
This Option Bit provides Flash Program Memory protection:
0 = Programming and erasure disabled for all of Flash Program Memory. Programming,
Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available using
the On-Chip Debugger.
1 = Programming, Page Erase, and Mass Erase are enabled for all of Flash program
memory.
Flash Program Memory Address 0001H
Reserved—R/W must be 1 during writes; 1 when read
XTLDIS—State of Crystal Oscillator at Reset
Table 88. Flash Options Bits at Program Memory Address 0001H
BITS 7 6 5 4 3 2 1 0
FIELD Reserved XTLDIS Reserved
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Program Memory 0001H
Note: U = Unchanged by Reset. R/W = Read/Write.
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Product Specification
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This bit only enables the crystal oscillator. Its selection as system clock must be done man-
ually.
0 = Crystal oscillator is enabled during reset, resulting in longer reset timing
1 = Crystal oscillator is disabled during reset, resulting in shorter reset timing
Programming the XTLDIS bit to zero on 8-pin versions of this device prevents any fur-
ther communication via the debug pin. This is due to the fact that the XIN and DBG
functions are shared on pin 2 of this package. Do not program this bit to zero on 8-pin
devices unless no further debugging or Flash programming is required.
Trim Bit Address Space
All available Trim bit addresses and their functions are listed in Table 89 through
Table 91.
Trim Bit Address 0000H—Reserved
Reserved—Altering this register may result in incorrect device operation.
Trim Bit Address 0001H—Reserved
Table 89. Trim Options Bits at Address 0000H
BITS 7 6 5 4 3 2 1 0
FIELD Reserved
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Information Page Memory 0020H
Note: U = Unchanged by Reset. R/W = Read/Write.
Table 90. Trim Option Bits at 0001H
BITS 7 6 5 4 3 2 1 0
FIELD Reserved
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Information Page Memory 0021H
Note: U = Unchanged by Reset. R/W = Read/Write.
Note:
Warning:
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Product Specification
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Reserved— Altering this register may result in incorrect device operation.
Trim Bit Address 0002H
IPO_TRIM—Internal Precision Oscillator Trim Byte
Contains trimming bits for Internal Precision Oscillator.
Trim Bit Address 0003H—Reserved
Trim Bit Address 0004H—Reserved
Zilog Calibration Data
ADC Calibration Data
ADC_CAL—Analog-to-Digital Converter Calibration Values
Contains factory calibrated values for ADC gain and offset compensation. Each of the ten
supported modes has one byte of offset calibration and two bytes of gain calibration.
These values are read by the software to compensate ADC measurements as detailed in
Table 91. Trim Option Bits at 0002H (TIPO)
BITS 7 6 5 4 3 2 1 0
FIELD IPO_TRIM
RESET U
R/W R/W
ADDR Information Page Memory 0022H
Note: U = Unchanged by Reset. R/W = Read/Write.
Table 92. ADC Calibration Bits
BITS 7 6 5 4 3 2 1 0
FIELD ADC_CAL
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Information Page Memory 0060H–007DH
Note: U = Unchanged by Reset. R/W = Read/Write.
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Software Compensation Procedure on page 122. The location of each calibration byte is
provided in Table 93 on page 148.
Serialization Data
S_NUM— Serial Number Byte
The serial number is a unique four-byte binary value.
Table 93. ADC Calibration Data Location
Info Page
Address
Memory
Address
Compensation
Usage ADC Mode
Reference
Type
60 FE60 Offset Single-Ended Unbuffered Internal 2.0 V
08 FE08 Gain High Byte Single-Ended Unbuffered Internal 2.0 V
09 FE09 Gain Low Byte Single-Ended Unbuffered Internal 2.0 V
63 FE63 Offset Single-Ended Unbuffered Internal 1.0 V
0A FE0A Gain High Byte Single-Ended Unbuffered Internal 1.0 V
0B FE0B Gain Low Byte Single-Ended Unbuffered Internal 1.0 V
66 FE66 Offset Single-Ended Unbuffered External 2.0 V
0C FE0C Gain High Byte Single-Ended Unbuffered External 2.0 V
0D FE0D Gain Low Byte Single-Ended Unbuffered External 2.0 V
Table 94. Serial Number at 001C-001F (S_NUM)
BITS 7 6 5 4 3 2 1 0
FIELD S_NUM
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Information Page Memory 001C-001F
Note: U = Unchanged by Reset. R/W = Read/Write.
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Product Specification
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Randomized Lot Identifier
RAND_LOT— Randomized Lot ID
The randomized lot ID is a 32 byte binary value that changes for each production lot.
Table 95. Serialization Data Locations
Info Page
Address Memory Address Usage
1C FE1C Serial Number Byte 3 (most
significant)
1D FE1D Serial Number Byte 2
1E FE1E Serial Number Byte 1
1F FE1F Serial Number Byte 0 (least
significant)
Table 96. Lot Identification Number (RAND_LOT)
BITS 7 6 5 4 3 2 1 0
FIELD RAND_LOT
RESET UUUUUUUU
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR Interspersed throughout Information Page Memory
Note: U = Unchanged by Reset. R/W = Read/Write.
Table 97. Randomized Lot ID Locations
Info Page
Address
Memory
Address Usage
3C FE3C Randomized Lot ID Byte 31 (most significant)
3D FE3D Randomized Lot ID Byte 30
3E FE3E Randomized Lot ID Byte 29
3F FE3F Randomized Lot ID Byte 28
58 FE58 Randomized Lot ID Byte 27
59 FE59 Randomized Lot ID Byte 26
5A FE5A Randomized Lot ID Byte 25
5B FE5B Randomized Lot ID Byte 24
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5C FE5C Randomized Lot ID Byte 23
5D FE5D Randomized Lot ID Byte 22
5E FE5E Randomized Lot ID Byte 21
5F FE5F Randomized Lot ID Byte 20
61 FE61 Randomized Lot ID Byte 19
62 FE62 Randomized Lot ID Byte 18
64 FE64 Randomized Lot ID Byte 17
65 FE65 Randomized Lot ID Byte 16
67 FE67 Randomized Lot ID Byte 15
68 FE68 Randomized Lot ID Byte 14
6A FE6A Randomized Lot ID Byte 13
6B FE6B Randomized Lot ID Byte 12
6D FE6D Randomized Lot ID Byte 11
6E FE6E Randomized Lot ID Byte 10
70 FE70 Randomized Lot ID Byte 9
71 FE71 Randomized Lot ID Byte 8
73 FE73 Randomized Lot ID Byte 7
74 FE74 Randomized Lot ID Byte 6
76 FE76 Randomized Lot ID Byte 5
77 FE77 Randomized Lot ID Byte 4
79 FE79 Randomized Lot ID Byte 3
7A FE7A Randomized Lot ID Byte 2
7C FE7C Randomized Lot ID Byte 1
7D FE7D Randomized Lot ID Byte 0 (least significant)
Table 97. Randomized Lot ID Locations (Continued)
Info Page
Address
Memory
Address Usage
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Product Specification
151
On-Chip Debugger
Z8 Encore! XP® F0823 Series devices contain an integrated On-Chip Debugger (OCD)
that provides advanced debugging features that include:
•
Single pin interface
•
Reading and writing of the register file
•
Reading and writing of program and data memory
•
Setting of breakpoints and watchpoints
•
Executing eZ8 CPU instructions
•
Debug pin sharing with general-purpose input-output function to maximize the pins
available
Architecture
The on-chip debugger consists of four primary functional blocks: transmitter, receiver,
auto-baud detector/generator, and debug controller. Figure 22 displays the architecture of
the OCD.
Figure 22. On-Chip Debugger Block Diagram
Auto-Baud
System Clock
Transmitter
Receiver
DBG Pin
Debug Controller
eZ8 CPU Control
Detector/Generator
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Operation
The following sections describes the operation of OCD.
OCD Interface
The OCD uses the DBG pin for communication with an external host. This one-pin
interface is a bidirectional open-drain interface that transmits and receives data. Data
transmission is half-duplex, in that transmit and receive cannot occur simultaneously. The
serial data on the DBG pin is sent using the standard asynchronous data format defined in
RS-232. This pin creates an interface from the Z8 Encore! XP F0823 Series products to
the serial port of a host PC using minimal external hardware.Two different methods for
connecting the DBG pin to an RS-232 interface are displayed in Figure 23 and Figure 24.
The recommended method is the buffered implementation depicted in Figure 24. The
DBG pin has a internal pull-up resistor which is sufficient for some applications (for more
details on the pull-up current, see Electrical Characteristics on page 193). For OCD
operation at higher data rates or in noisy systems, an external pull-up resistor is
recommended.
For operation of the OCD, all power pins (VDD and AVDD) must be supplied with power,
and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-
drain and may require an external pull-up resistor to ensure proper operation.
Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)
Caution:
RS-232 TX
RS-232 RX
RS-232
Transceiver
VDD
DBG Pin
10 kΩ
Schottky
Diode
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Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions
•
The system clock operates unless in STOP mode
•
All enabled on-chip peripherals operate unless in STOP mode
•
Automatically exits HALT mode
•
Constantly refreshes the Watchdog Timer, if enabled.
Entering DEBUG Mode
The device enters DEBUG mode following the operations below:
•
The device enters DEBUG mode after the eZ8 CPU executes a BRK (breakpoint) instruc-
tion
•
If the DBG pin is held Low during the most recent clock cycle of System Reset, the part
enters DEBUG mode upon exiting System Reset
Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset
(making sure to account for any specified frequency error if using an internal oscillator)
prevents a false interpretation of an Autobaud sequence (see OCD Auto-Baud Detector/
Generator on page 154).
•
If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/DBG
pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled high. At this
RS-232 TX
RS-232 RX
RS-232
Transceiver
VDD
DBG Pin
10 kΩ
Open-Drain
Buffer
Note:
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Product Specification
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point, the PA0/DBG pin can be used to autobaud and cause the device to enter
DEBUG mode. For more details, see OCD Unlock Sequence (8-Pin Devices Only) on
page 156.
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
Clearing the DBGMODE bit in the OCD Control Register to 0
•
Power-On Reset
•
Voltage Brownout reset
•
Watchdog Timer reset
•
Asserting the RESET pin Low to initiate a Reset
•
Driving the DBG pin Low while the device is in STOP mode initiates a system reset
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit as
displayed in Figure 25.
Figure 25. OCD Data Format
When responding to a request for data, the OCD may commence transmitting immediately
after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the
host must not actively drive the DBG pin High for more than 0.5 bit times. It is recom-
mended that, if possible, the host drives the DBG pin using an open-drain output.
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock
frequencies, the OCD contains an auto-baud detector/generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7
data bits), framed between High bits. The auto-baud detector measures this period and sets
the OCD baud rate generator accordingly.
The auto-baud detector/generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation with asynchronous
STARTD0D1D2D3D4D5D6D7STOP
Note:
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datastreams, the maximum recommended baud rate is the system clock frequency divided
by eight. The maximum possible baud rate for asynchronous datastreams is the system
clock frequency divided by four, but this theoretical maximum is possible only for low
noise designs with clean signals. Table 98 lists minimum and recommended maximum
baud rates for sample crystal frequencies.
If the OCD receives a Serial Break (nine or more continuous bits Low) the auto-baud
detector/generator resets. Reconfigure the auto-baud detector/generator by sending 80H.
OCD Serial Errors
The OCD detects any of the following error conditions on the DBG pin:
•
Serial Break (a minimum of nine continuous bits Low)
•
Framing Error (received Stop bit is Low)
•
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long Serial Break back to the host, and resets the auto-baud
detector/generator. A Framing Error or Transmit Collision may be caused by the host
sending a Serial Break to the OCD. Because of the open-drain nature of the interface,
returning a Serial Break break back to the host only extends the length of the Serial Break
if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the Z8 Encore!
XP F0823 Series devices or when recovering from an error. A Serial Break from the host
resets the auto-baud generator/detector but does not reset the OCD Control register. A
Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is
held in Reset until the end of the Serial Break when the DBG pin returns High. Because of
the open-drain nature of the DBG pin, the host sends a Serial Break to the OCD even if the
OCD is transmitting a character.
Table 98. OCD Baud-Rate Limits
System Clock
Frequency (MHz)
Recommended
Maximum Baud
Rate (kbps)
Recommended
Standard PC
Baud Rate (bps)
Minimum Baud
Rate (kbps)
5.5296 1382.4 691,200 1.08
0.032768 (32 kHz) 4.096 2400 0.064
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OCD Unlock Sequence (8-Pin Devices Only)
Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to
access the DBG pin. If this sequence is not completed during a system reset, then the PA0/
DBG pin functions only as a GPIO pin.
The following sequence unlocks the DBG pin:
1. Hold PA2/RESET Low.
2. Wait 5 ms for the internal reset sequence to complete.
3. Send the following bytes serially to the debug pin:
DBG ← 80H (autobaud)
DBG ← EBH
DBG ← 5AH
DBG ← 70H
DBG ← CDH (32-bit unlock key)
4. Release PA2/RESET. The PA0/DBG pin is now identical in function to that of the
DBG pin on the 20- or 28-pin device. To enter DEBUG mode, re-autobaud and write
80H to the OCD control register (see On-Chip Debugger Commands on page 157).
Breakpoints
Execution breakpoints are generated using the BRK instruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the OCD. If breakpoints are enabled, the
OCD enters DEBUG mode and idles the eZ8 CPU. If breakpoints are not enabled, the
OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction.
Breakpoints in Flash Memory
The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a
byte in Flash memory. To implement a breakpoint, write 00H to the required break
address, overwriting the current instruction. To remove a breakpoint, the corresponding
page of Flash memory must be erased and reprogrammed with the original data.
Runtime Counter
The OCD contains a 16-bit Runtime Counter. It counts system clock cycles between
breakpoints. The counter starts counting when the OCD leaves DEBUG mode and stops
counting when it enters DEBUG mode again or when it reaches the maximum count of
FFFFH.
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On-Chip Debugger Commands
The host communicates to the OCD by sending OCD commands using the DBG interface.
During normal operation, only a subset of the OCD commands are available. In DEBUG
mode, all OCD commands become available unless the user code and control registers are
protected by programming the Flash Read Protect Option bit (FRP). The Flash Read
Protect Option bit prevents the code in memory from being read out of Z8 Encore! XP®
F0823 Series products. When this option is enabled, several of the OCD commands are
disabled. Table 99 on page 162 is a summary of the OCD commands. Each OCD com-
mand is described in further detail in the bulleted list following this table. Table 99 on
page 162 also indicates those commands that operate when the device is not in DEBUG
mode (normal operation) and those commands that are disabled by programming the Flash
Read Protect Option bit.
Debug Command
Command
Byte
Enabled when
NOT in DEBUG
mode?
Disabled by Flash Read Protect
Option Bit
Read OCD Revision 00H Yes –
Reserved 01H – –
Read OCD Status Register 02H Yes –
Read Runtime Counter 03H – –
Write OCD Control Register 04H Yes Cannot clear DBGMODE bit.
Read OCD Control Register 05H Yes –
Write Program Counter 06H – Disabled.
Read Program Counter 07H – Disabled.
Write Register 08H – Only writes of the Flash Memory Control
registers are allowed. Additionally, only
the Mass Erase command is allowed to
be written to the Flash Control register.
Read Register 09H – Disabled.
Write Program Memory 0AH – Disabled.
Read Program Memory 0BH – Disabled.
Write Data Memory 0CH – Yes.
Read Data Memory 0DH – –
Read Program Memory CRC 0EH – –
Reserved 0FH – –
Step Instruction 10H – Disabled.
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In the following list of OCD Commands, data and commands sent from the host to the
OCD are identified by ’DBG ← Command/Data’. Data sent from the OCD back to the host
is identified by ’DBG → Data’.
•
Read OCD Revision (00H)—The Read OCD Revision command determines the ver-
sion of the OCD. If OCD commands are added, removed, or changed, this revision number
changes.
DBG ← 00H
DBG → OCDRev[15:8] (Major revision number)
DBG → OCDRev[7:0] (Minor revision number)
•
Read OCD Status Register (02H)—The Read OCD Status register command reads the
OCDSTAT register.
DBG ← 02H
DBG → OCDSTAT[7:0]
•
Read Runtime Counter (03H)—The Runtime Counter counts system clock cycles in
between breakpoints. The 16-bit Runtime Counter counts up from 0000H and stops at the
maximum count of FFFFH. The Runtime Counter is overwritten during the Write Memo-
ry, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction,
Stuff Instruction, and Execute Instruction commands.
DBG ← 03H
DBG → RuntimeCounter[15:8]
DBG → RuntimeCounter[7:0]
•
Write OCD Control Register (04H)—The Write OCD Control Register command
writes the data that follows to the OCDCTL register. When the Flash Read Protect Option
Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared
to 0 and the only method of returning the device to normal operating mode is to reset the
device.
DBG ← 04H
DBG ← OCDCTL[7:0]
•
Read OCD Control Register (05H)—The Read OCD Control Register command reads
the value of the OCDCTL register.
Stuff Instruction 11H – Disabled.
Execute Instruction 12H – Disabled.
Reserved 13H–FFH – –
Debug Command
Command
Byte
Enabled when
NOT in DEBUG
mode?
Disabled by Flash Read Protect
Option Bit
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DBG ← 05H
DBG → OCDCTL[7:0]
•
Write Program Counter (06H)—The Write Program Counter command writes the data
that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode
or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are
discarded.
DBG ← 06H
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
•
Read Program Counter (07H)—The Read Program Counter command reads the value
in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the
Flash Read Protect Option bit is enabled, this command returns FFFFH.
DBG ← 07H
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
•
Write Register (08H)—The Write Register command writes data to the Register File.
Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If
the device is not in DEBUG mode, the address and data values are discarded. If the Flash
Read Protect Option bit is enabled, only writes to the Flash Control Registers are allowed
and all other register write data values are discarded.
DBG ← 08H
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1-256 data bytes
•
Read Register (09H)—The Read Register command reads data from the Register File.
Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the
device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this com-
mand returns FFH for all the data values.
DBG ← 09H
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG → 1-256 data bytes
•
Write Program Memory (0AH)—The Write Program Memory command writes data
to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data
can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0).
The on-chip Flash Controller must be written to and unlocked for the programming oper-
ation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device
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is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is dis-
carded.
DBG ← 0AH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
•
Read Program Memory (0BH)—The Read Program Memory command reads data
from Program Memory. This command is equivalent to the LDC and LDCI instructions.
Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If
the device is not in DEBUG mode or if the Flash Read Protect Option Bit is enabled, this
command returns FFH for the data.
DBG ← 0BH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
•
Write Data Memory (0CH)—The Write Data Memory command writes data to Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be writ-
ten 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device
is not in DEBUG mode or if the Flash Read Protect Option Bit is enabled, the data is dis-
carded.
DBG ← 0CH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
•
Read Data Memory (0DH)—The Read Data Memory command reads from Data Mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to
65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
DEBUG mode, this command returns FFH for the data.
DBG ← 0DH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
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•
Read Program Memory CRC (0EH)—The Read Program Memory Cyclic Redundan-
cy Check (CRC) command computes and returns the CRC of Program Memory using the
16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command re-
turns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay
from issuing of the command until the OCD returns the data. The OCD reads the Program
Memory, calculates the CRC value, and returns the result. The delay is a function of the
Program Memory size and is approximately equal to the system clock period multiplied
by the number of bytes in the Program Memory.
DBG ← 0EH
DBG → CRC[15:8]
DBG → CRC[7:0]
•
Step Instruction (10H)—The Step Instruction command steps one assembly instruction
at the current Program Counter (PC) location. If the device is not in DEBUG mode or the
Flash Read Protect Option bit is enabled, the OCD ignores this command.
DBG ← 10H
•
Stuff Instruction (11H)—The Stuff Instruction command steps one assembly instruction
and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the
instruction are read from Program Memory. This command is useful for stepping over in-
structions where the first byte of the instruction has been overwritten by a Breakpoint. If
the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, the
OCD ignores this command.
DBG ← 11H
DBG ← opcode[7:0]
•
Execute Instruction (12H)—The Execute Instruction command allows sending an
entire instruction to be executed to the eZ8 CPU. This command can also step over break-
points. The number of bytes to send for the instruction depends on the opcode. If the device
is not in DEBUG mode or the Flash Read Protect Option bit is enabled, this command
reads and discards one byte.
DBG ← 12H
DBG ← 1-5 byte opcode
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register controls the state of the OCD. This register is used to enter or
exit DEBUG mode and to enable the BRK instruction. It also resets Z8 Encore! XP® F0823
Series device.
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A reset and stop function can be achieved by writing 81H to this register. A reset and go
function can be achieved by writing 41H to this register. If the device is in DEBUG mode,
a run function can be implemented by writing 40H to this register.
.
DBGMODE—DEBUG Mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = Z8 Encore! XP F0823 Series device is operating in NORMAL mode
1 = Z8 Encore! XP F0823 Series device is in DEBUG mode
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1,
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled
1 = Breakpoints are enabled
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled
1 = Debug Acknowledge is enabled
Reserved—0 when read
RST—Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the OCD is not reset. This bit is auto-
matically cleared to 0 at the end of reset.
0 = No effect
1 = Reset the Flash Read Protect Option Bit device
Table 99. OCD Control Register (OCDCTL)
BITS 7 6 5 4 3 2 1 0
FIELD DBGMODE BRKEN DBGACK Reserved RST
RESET 00000000
R/W R/WR/WR/WRRRRR/W
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OCD Status Register
The OCD Status register reports status information about the current state of the debugger
and the system.
DBG—Debug Status
0 = NORMAL mode
1 = DEBUG mode
HALT—HALT Mode
0 = Not in HALT mode
1 = In HALT mode
FRPENB—Flash Read Protect Option Bit Enable
0 = FRP bit enabled, that allows disabling of many OCD commands
1 = FRP bit has no effect
Reserved—0 when read
Table 100. OCD Status Register (OCDSTAT)
BITS 76543210
FIELD DBG HALT FRPENB Reserved
RESET 00000000
R/W RRRRRRRR
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PS024314-0308 Oscillator Control
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Oscillator Control
Z8 Encore! XP® F0823 Series devices uses three possible clocking schemes, each
user-selectable:
•
On-chip precision trimmed RC oscillator
•
External clock drive
•
On-chip low power Watchdog Timer oscillator
In addition, Z8 Encore! XP F0823 Series devices contain clock failure detection and
recovery circuitry, allowing continued operation despite a failure of the primary oscillator.
Operation
This chapter discusses the logic used to select the system clock and handle primary
oscillator failures. A description of the specific operation of each oscillator is outlined
elsewhere in this document.
System Clock Selection
The oscillator control block selects from the available clocks. Table 101 details each clock
source and its usage.
Table 101. Oscillator Configuration and Selection
Clock Source Characteristics Required Setup
Internal Precision
RC Oscillator
• 32.8 kHz or 5.53 MHz
• ± 4% accuracy when trimmed
• No external components required
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and
select oscillator at either 5.53 MHz or
32.8 kHz
External Clock
Drive
• 0 to 20 MHz
• Accuracy dependent on external clock
source
• Write GPIO registers to configure PB3
pin for external clock function
• Unlock and write OSCCTL to select
external system clock
• Apply external clock signal to GPIO
Internal Watchdog
Timer Oscillator
• 10 kHz nominal
• ± 40% accuracy; no external
components required
• Very Low power consumption
• Enable WDT if not enabled and wait
until WDT Oscillator is operating.
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and
select oscillator
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Unintentional accesses to the oscillator control register can actually stop the chip by
switching to a non-functioning oscillator. To prevent this condition, the oscillator con-
trol block employs a register unlocking/locking scheme.
OSC Control Register Unlocking/Locking
To write the oscillator control register, unlock it by making two writes to the OSCCTL
register with the values E7H followed by 18H. A third write to the OSCCTL register
changes the value of the actual register and returns the register to a locked state. Any other
sequence of oscillator control register writes has no effect. The values written to unlock
the register must be ordered correctly, but are not necessarily consecutive. It is possible to
write to or read from other registers within the unlocking/locking operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a
different oscillator, it is appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
Z8 Encore! XP® F0823 Series devices can generate non-maskable interrupt-like events
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the Watchdog Timer on page 87.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be deasserted in
the OSCCTL register).
Caution:
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Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL register.
The Watchdog Timer oscillator failure detection circuit counts system clocks while
searching for a Watchdog Timer clock. The logic counts 8004 system clock cycles before
determining that a failure has occurred. The system clock rate determines the speed at
which the Watchdog Timer failure can be detected. A very slow system clock results in
very slow detection times.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! XP F0823 Series device ceases functioning
and can only be recovered by Power-On Reset.
Oscillator Control Register Definitions
The following section provides the bit definitions for the Oscillator Control register.
Oscillator Control Register
The Oscillator Control register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control register must be unlocked before writing. Writing the two step
sequence E7H followed by 18H to the Oscillator Control Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL.
Table 102. Oscillator Control Register (OSCCTL)
BITS 7 6 5 4 3 2 1 0
FIELD INTEN Reserved WDTEN POFEN WDFEN SCKSEL
RESET 10100000
R/W R/WR/WR/WR/WR/WR/WR/WR/W
ADDR F86H
Caution:
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INTEN—Internal Precision Oscillator Enable
1 = Internal precision oscillator is enabled
0 = Internal precision oscillator is disabled
Reserved—R/W bits must be 0 during writes; 0 when read
WDTEN—Watchdog Timer Oscillator Enable
1 = Watchdog Timer oscillator is enabled
0 = Watchdog Timer oscillator is disabled
POFEN—Primary Oscillator Failure Detection Enable
1 = Failure detection and recovery of primary oscillator is enabled
0 = Failure detection and recovery of primary oscillator is disabled
WDFEN—Watchdog Timer Oscillator Failure Detection Enable
1 = Failure detection of Watchdog Timer oscillator is enabled
0 = Failure detection of Watchdog Timer oscillator is disabled
SCKSEL—System Clock Oscillator Select
000 = Internal precision oscillator functions as system clock at 5.53 MHz
001 = Internal precision oscillator functions as system clock at 32 kHz
010 = Reserved
011 = Watchdog Timer oscillator functions as system clock
100 = External clock signal on PB3 functions as system clock
101 = Reserved
110 = Reserved
111 = Reserved
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Internal Precision Oscillator
The internal precision oscillator (IPO) is designed for use without external components.
You can either manually trim the oscillator for a non-standard frequency or use the
automatic factory-trimmed version to achieve a 5.53 MHz frequency. The features of IPO
include:
•
On-chip RC oscillator that does not require external components
•
Output frequency of either 5.53 MHz or 32.8 kHz (contains both a fast and a slow mode)
•
Trimming possible through Flash option bits with user override
•
Elimination of crystals or ceramic resonators in applications where high timing accuracy
is not required
Operation
An 8-bit trimming register, incorporated into the design, compensates for absolute varia-
tion of oscillator frequency. Once trimmed the oscillator frequency is stable and does not
require subsequent calibration. Trimming is performed during manufacturing and is not
necessary for you to repeat unless a frequency other than 5.53 MHz (fast mode) or 32.8
kHz (slow mode) is required. This trimming is done at +30 °C and a supply voltage of 3.3
V, so accuracy of this operating point is optimal.
Power down this block for minimum system power. By default, the oscillator is configured
through the Flash Option bits. However, the user code can override these trim values as
described in Trim Bit Address Space on page 146.
Select one of the two frequencies for the oscillator: 5.53 MHz and 32.8 kHz, using the
OSCSEL bits in the Oscillator Control on page 165.
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PS024314-0308 eZ8 CPU Instruction Set
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eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(opcodes and operands) to represent the instructions themselves. The opcodes identify the
instruction while the operands represent memory locations, registers, or immediate data
values.
Each assembly language program consists of a series of symbolic commands called
statements. Each statement can contain labels, operations, operands, and comments.
Labels are assigned to a particular instruction step in a source program. The label
identifies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine
language program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the following example.
Assembly Language Source Program Example
JP START ; Everything after the semicolon is a comment.
START: ; A label called ‘START’. The first instruction (JP START) in this
; example causes program execution to jump to the point within the
; program where the START label occurs.
LD R4, R7 ; A Load (LD) instruction with two operands. The first operand,
; Working Register R4, is the destination. The second operand,
; Working Register R7, is the source. The contents of R7 is
; written into R4.
LD 234H, #%01 ; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address 234H,
; identifies the destination. The second operand, Immediate Data
; value 01H, is the source. The value 01H is written into the
; Register at address 234H.
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Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually has
the operands in the order ‘source, destination’, but ordering is opcode-dependent. The
following instruction examples illustrate the format of some basic assembly instructions
and the resulting object code produced by the assembler. You must follow this binary for-
mat if you prefer manual program coding or intend to implement your own assembler.
Example 1
If the contents of Registers 43H and 08H are added and the result is stored in 43H, the
assembly syntax and resulting object code is:
Example 2
In general, when an instruction format requires an 8-bit register address, that address can
specify any register location in the range 0–255 or, using Escaped Mode Addressing, a
Working Register R0–R15. If the contents of Register 43H and Working Register R8 are
added and the result is stored in 43H, the assembly syntax and resulting object code is:
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 105.
Table 103. Assembly Language Syntax Example 1
Assembly Language Code ADD 43H, 08H (ADD dst, src)
Object Code 04 08 43 (OPC src, dst)
Table 104. Assembly Language Syntax Example 2
Assembly Language Code ADD 43H, R8 (ADD dst, src)
Object Code 04 E8 43 (OPC src, dst)
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.
Table 105. Notational Shorthand
Notation Description Operand Range
b Bit b b represents a value from 0 to 7 (000B to 111B).
cc Condition Code — See Condition Codes overview in the eZ8 CPU
User Manual.
DA Direct Address Addrs Addrs represents a number in the range of 0000H
to FFFFH.
ER Extended Addressing Register Reg Reg represents a number in the range of 000H to
FFFH.
IM Immediate Data #Data Data is a number between 00H to FFH.
Ir Indirect Working Register @Rn n = 0–15.
IR Indirect Register @Reg Reg. represents a number in the range of 00H to
FFH.
Irr Indirect Working Register Pair @RRp p = 0, 2, 4, 6, 8, 10, 12, or 14.
IRR Indirect Register Pair @Reg Reg represents an even number in the range 00H
to FEH
p Polarity p Polarity is a single bit binary value of either 0B or
1B.
r Working Register Rn n = 0–15.
R Register Reg Reg. represents a number in the range of 00H to
FFH.
RA Relative Address X X represents an index in the range of +127 to –
128 which is an offset relative to the address of
the next instruction
rr Working Register Pair RRp p = 0, 2, 4, 6, 8, 10, 12, or 14.
RR Register Pair Reg Reg. represents an even number in the range of
00H to FEH.
Vector Vector Address Vector Vector represents a number in the range of 00H
to FFH.
X Indexed #Index The register or register pair to be indexed is offset
by the signed Index value (#Index) in a +127 to
-128 range.
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Table 106 lists additional symbols that are used throughout the Instruction Summary and
Instruction Set Description sections.
Assignment of a value is indicated by an arrow. For example,
dst ← dst + src
indicates the source data is added to the destination data and the result is stored in the
destination location.
eZ8 CPU Instruction Classes
eZ8 CPU instructions are divided functionally into the following groups:
•
Arithmetic
•
Bit Manipulation
•
Block Transfer
•
CPU Control
•
Load
•
Logical
•
Program Control
Table 106. Additional Symbols
Symbol Definition
dst Destination Operand
src Source Operand
@ Indirect Address Prefix
SP Stack Pointer
PC Program Counter
FLAGS Flags Register
RP Register Pointer
# Immediate Operand Prefix
B Binary Number Suffix
% Hexadecimal Number Prefix
H Hexadecimal Number Suffix
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•
Rotate and Shift
Tables 107 through Table 114 contain the instructions belonging to each group and the
number of operands required for each instruction. Some instructions appear in more than
one table as these instruction can be considered as a subset of more than one category.
Within these tables, the source operand is identified as ‘src’, the destination operand
is ‘dst’ and a condition code is ‘cc’.
Table 107. Arithmetic Instructions
Mnemonic Operands Instruction
ADC dst, src Add with Carry
ADCX dst, src Add with Carry using Extended Addressing
ADD dst, src Add
ADDX dst, src Add using Extended Addressing
CP dst, src Compare
CPC dst, src Compare with Carry
CPCX dst, src Compare with Carry using Extended Addressing
CPX dst, src Compare using Extended Addressing
DA dst Decimal Adjust
DEC dst Decrement
DECW dst Decrement Word
INC dst Increment
INCW dst Increment Word
MULT dst Multiply
SBC dst, src Subtract with Carry
SBCX dst, src Subtract with Carry using Extended Addressing
SUB dst, src Subtract
SUBX dst, src Subtract using Extended Addressing
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Table 108. Bit Manipulation Instructions
Mnemonic Operands Instruction
BCLR bit, dst Bit Clear
BIT p, bit, dst Bit Set or Clear
BSET bit, dst Bit Set
BSWAP dst Bit Swap
CCF — Complement Carry Flag
RCF — Reset Carry Flag
SCF — Set Carry Flag
TCM dst, src Test Complement Under Mask
TCMX dst, src Test Complement Under Mask using Extended Addressing
TM dst, src Test Under Mask
TMX dst, src Test Under Mask using Extended Addressing
Table 109. Block Transfer Instructions
Mnemonic Operands Instruction
LDCI dst, src Load Constant to/from Program Memory and Auto-Increment
Addresses
LDEI dst, src Load External Data to/from Data Memory and Auto-Increment
Addresses
Table 110. CPU Control Instructions
Mnemonic Operands Instruction
ATM — Atomic Execution
CCF — Complement Carry Flag
DI — Disable Interrupts
EI — Enable Interrupts
HALT — HALT Mode
NOP — No Operation
RCF — Reset Carry Flag
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
177
SCF — Set Carry Flag
SRP src Set Register Pointer
STOP — STOP Mode
WDT — Watchdog Timer Refresh
Table 111. Load Instructions
Mnemonic Operands Instruction
CLR dst Clear
LD dst, src Load
LDC dst, src Load Constant to/from Program Memory
LDCI dst, src Load Constant to/from Program Memory and Auto-Increment
Addresses
LDE dst, src Load External Data to/from Data Memory
LDEI dst, src Load External Data to/from Data Memory and Auto-Increment
Addresses
LDWX dst, src Load Word using Extended Addressing
LDX dst, src Load using Extended Addressing
LEA dst, X(src) Load Effective Address
POP dst Pop
POPX dst Pop using Extended Addressing
PUSH src Push
PUSHX src Push using Extended Addressing
Table 112. Logical Instructions
Mnemonic Operands Instruction
AND dst, src Logical AND
ANDX dst, src Logical AND using Extended Addressing
COM dst Complement
OR dst, src Logical OR
Table 110. CPU Control Instructions (Continued)
Mnemonic Operands Instruction
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
178
ORX dst, src Logical OR using Extended Addressing
XOR dst, src Logical Exclusive OR
XORX dst, src Logical Exclusive OR using Extended Addressing
Table 113. Program Control Instructions
Mnemonic Operands Instruction
BRK — On-Chip Debugger Break
BTJ p, bit, src, DA Bit Test and Jump
BTJNZ bit, src, DA Bit Test and Jump if Non-Zero
BTJZ bit, src, DA Bit Test and Jump if Zero
CALL dst Call Procedure
DJNZ dst, src, RA Decrement and Jump Non-Zero
IRET — Interrupt Return
JP dst Jump
JP cc dst Jump Conditional
JR DA Jump Relative
JR cc DA Jump Relative Conditional
RET — Return
TRAP vector Software Trap
Table 114. Rotate and Shift Instructions
Mnemonic Operands Instruction
BSWAP dst Bit Swap
RL dst Rotate Left
RLC dst Rotate Left through Carry
RR dst Rotate Right
RRC dst Rotate Right through Carry
Table 112. Logical Instructions (Continued)
Mnemonic Operands Instruction
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
179
eZ8 CPU Instruction Summary
Table 115 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
SRA dst Shift Right Arithmetic
SRL dst Shift Right Logical
SWAP dst Swap Nibbles
Table 115. eZ8 CPU Instruction Summary
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
ADC dst, src dst ← dst + src + C r r 12 ****0* 2 3
rIr 13 24
RR 14 3 3
RIR 15 3 4
RIM 16 3 3
IR IM 17 3 4
ADCX dst, src dst ← dst + src + C ER ER 18 ****0* 4 3
ER IM 19 4 3
ADD dst, src dst ← dst + src r r 02 ****0* 2 3
rIr 03 24
RR 04 3 3
RIR 05 3 4
RIM 06 3 3
IR IM 07 3 4
ADDX dst, src dst ← dst + src ER ER 08 ****0* 4 3
ER IM 09 4 3
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
Table 114. Rotate and Shift Instructions (Continued)
Mnemonic Operands Instruction
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
180
AND dst, src dst ← dst AND src r r 52 – * * 0 – – 2 3
rIr 53 24
RR 54 3 3
RIR 55 3 4
RIM 56 3 3
IR IM 57 3 4
ANDX dst, src dst ← dst AND src ER ER 58 – * * 0 – – 4 3
ER IM 59 4 3
ATM Block all interrupt and
DMA requests during
execution of the next 3
instructions
2F ––––– – 1 2
BCLR bit, dst dst[bit] ← 0 r E2 ––––– – 2 2
BIT p, bit, dst dst[bit] ← p r E2 –––0– – 2 2
BRK Debugger Break 00 – – – – – – 1 1
BSET bit, dst dst[bit] ← 1 r E2 –––0– – 2 2
BSWAP dst dst[7:0] ← dst[0:7] R D5 X * * 0 – – 2 2
BTJ p, bit, src, dst if src[bit] = p
PC ← PC + X
r F6 ––––– – 3 3
Ir F7 3 4
BTJNZ bit, src, dst if src[bit] = 1
PC ← PC + X
r F6 ––––– – 3 3
Ir F7 3 4
BTJZ bit, src, dst if src[bit] = 0
PC ← PC + X
r F6 ––––– – 3 3
Ir F7 3 4
CALL dst SP ← SP -2
@SP ← PC
PC ← dst
IRR D4 ––––– – 2 6
DA D6 3 3
CCF C ← ~C EF * –––––- 1 2
CLR dst dst ← 00H R B0 – – – – – – 2 2
IR B1 2 3
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
181
COM dst dst ← ~dst R 60 – * * 0 – – 2 2
IR 61 2 3
CP dst, src dst - src r r A2 ****–– 2 3
rIr A3 24
RR A4 3 3
RIR A5 3 4
RIM A6 3 3
IR IM A7 3 4
CPC dst, src dst - src - C r r 1F A2 ****–– 3 3
rIr1F A3 34
RR1F A4 4 3
RIR1F A5 4 4
RIM1F A6 4 3
IR IM 1F A7 4 4
CPCX dst, src dst - src - C ER ER 1F A8 ****–– 5 3
ER IM 1F A9 5 3
CPX dst, src dst - src ER ER A8 ****–– 4 3
ER IM A9 4 3
DA dst dst ← DA(dst) R 40 * * * X – – 2 2
IR 41 2 3
DEC dst dst ← dst - 1 R 30 –***–– 2 2
IR 31 2 3
DECW dst dst ← dst - 1 RR 80 –***–– 2 5
IRR 81 2 6
DI IRQCTL[7] ← 0 8F ––––– – 1 2
DJNZ dst, RA dst ← dst – 1
if dst ≠ 0
PC ← PC + X
r 0A-FA ––––– – 2 3
EI IRQCTL[7] ← 1 9F ––––– – 1 2
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
182
HALT HALT Mode 7F – – – – – – 1 2
INC dst dst ← dst + 1 R 20 – * * – – – 2 2
IR 21 2 3
r0E-FE 12
INCW dst dst ← dst + 1 RR A0 –***–– 2 5
IRR A1 2 6
IRET FLAGS ← @SP
SP ← SP + 1
PC ← @SP
SP ← SP + 2
IRQCTL[7] ← 1
BF ***** * 1 5
JP dst PC ← dst DA 8D ––––– – 3 2
IRR C4 2 3
JP cc, dst if cc is true
PC ← dst
DA 0D-FD ––––– – 3 2
JR dst PC ← PC + X DA 8B ––––– – 2 2
JR cc, dst if cc is true
PC ← PC + X
DA 0B-FB ––––– – 2 2
LD dst, rc dst ← src r IM 0C-FC – – – – – – 2 2
r X(r) C7 3 3
X(r) r D7 3 4
rIr E3 23
RR E4 3 2
RIR E5 3 4
RIM E6 3 2
IR IM E7 3 3
Ir r F3 2 3
IR R F5 3 3
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
183
LDC dst, src dst ← src r Irr C2 ––––– – 2 5
Ir Irr C5 2 9
Irr r D2 2 5
LDCI dst, src dst ← src
r ← r + 1
rr ← rr + 1
Ir Irr C3 ––––– – 2 9
Irr Ir D3 2 9
LDE dst, src dst ← src r Irr 82 ––––– – 2 5
Irr r 92 2 5
LDEI dst, src dst ← src
r ← r + 1
rr ← rr + 1
Ir Irr 83 ––––– – 2 9
Irr Ir 93 2 9
LDWX dst, src dst ← src ER ER 1FE8 ––––– – 5 4
LDX dst, src dst ← src r ER 84 ––––– – 3 2
Ir ER 85 3 3
RIRR 86 3 4
IR IRR 87 3 5
r X(rr) 88 3 4
X(rr) r 89 3 4
ER r 94 3 2
ER Ir 95 3 3
IRR R 96 3 4
IRR IR 97 3 5
ER ER E8 4 2
ER IM E9 4 2
LEA dst, X(src) dst ← src + X r X(r) 98 – – – – – – 3 3
rr X(rr) 99 3 5
MULT dst dst[15:0] ←
dst[15:8] * dst[7:0]
RR F4 ––––– – 2 8
NOP No operation 0F – – – – – – 1 2
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
184
OR dst, src dst ← dst OR src r r 42 – * * 0 – – 2 3
rIr 43 24
RR 44 3 3
RIR 45 3 4
RIM 46 3 3
IR IM 47 3 4
ORX dst, src dst ← dst OR src ER ER 48 – * * 0 – – 4 3
ER IM 49 4 3
POP dst dst ← @SP
SP ← SP + 1
R 50 ––––– – 2 2
IR 51 2 3
POPX dst dst ← @SP
SP ← SP + 1
ER D8 ––––– – 3 2
PUSH src SP ← SP – 1
@SP ← src
R 70 ––––– – 2 2
IR 71 2 3
IM IF70 3 2
PUSHX src SP ← SP – 1
@SP ← src
ER C8 ––––– – 3 2
RCF C ← 0 CF 0–––– – 1 2
RET PC ← @SP
SP ← SP + 2
AF ––––– – 1 4
RL dst R 90 ****–– 2 2
IR 91 2 3
RLC dst R 10 ****–– 2 2
IR 11 2 3
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
185
RR dst R E0 ****–– 2 2
IR E1 2 3
RRC dst R C0 ****–– 2 2
IR C1 2 3
SBC dst, src dst ← dst – src - C r r 32 ****1* 2 3
rIr 33 24
RR 34 3 3
RIR 35 3 4
RIM 36 3 3
IR IM 37 3 4
SBCX dst, src dst ← dst – src - C ER ER 38 ****1* 4 3
ER IM 39 4 3
SCF C ← 1 DF 1–––– – 1 2
SRA dst R D0 * * * 0 – – 2 2
IR D1 2 3
SRL dst R 1F C0 * * 0 * – – 3 2
IR 1F C1 3 3
SRP src RP ← src IM 01 ––––– – 2 2
STOP STOP Mode 6F – – – – – – 1 2
SUB dst, src dst ← dst – src r r 22 ****1* 2 3
rIr 23 24
RR 24 3 3
RIR 25 3 4
RIM 26 3 3
IR IM 27 3 4
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
C0
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
186
SUBX dst, src dst ← dst – src ER ER 28 ****1* 4 3
ER IM 29 4 3
SWAP dst dst[7:4] ↔ dst[3:0] R F0 X * * X – – 2 2
IR F1 2 3
TCM dst, src (NOT dst) AND src r r 62 – * * 0 – – 2 3
rIr 63 24
RR 64 3 3
RIR 65 3 4
RIM 66 3 3
IR IM 67 3 4
TCMX dst, src (NOT dst) AND src ER ER 68 – * * 0 – – 4 3
ER IM 69 4 3
TM dst, src dst AND src r r 72 – * * 0 – – 2 3
rIr 73 24
RR 74 3 3
RIR 75 3 4
RIM 76 3 3
IR IM 77 3 4
TMX dst, src dst AND src ER ER 78 – * * 0 – – 4 3
ER IM 79 4 3
TRAP Vector SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
Vector F2 ––––– – 2 6
WDT 5F ––––– – 1 2
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 eZ8 CPU Instruction Set
Z8 Encore! XP® F0823 Series
Product Specification
187
XOR dst, src dst ← dst XOR src r r B2 – * * 0 – – 2 3
rIr B3 24
RR B4 3 3
RIR B5 3 4
RIM B6 3 3
IR IM B7 3 4
XORX dst, src dst ← dst XOR src ER ER B8 – * * 0 – – 4 3
ER IM B9 4 3
Table 115. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic Symbolic Operation
Address Mode Opcode(s)
(Hex)
Flags Fetch
Cycles
Instr.
Cyclesdst src CZSVDH
Flags Notation: * = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS024314-0308 Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
188
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 26.
Figure 27 and Figure 28 provide information about each of the eZ8 CPU instructions.
Table 116 lists Opcode Map abbreviations.
Figure 26. Opcode Map Cell Description
CP
3.3
R2,R1
A
4
Opcode
Lower Nibble
Second Operand
After Assembly
First Operand
After Assembly
Opcode
Upper Nibble
Instruction CyclesFetch Cycles
PS024314-0308 Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
189
Table 116. Opcode Map Abbreviations
Abbreviation Description Abbreviation Description
b Bit position IRR Indirect Register Pair
cc Condition code p Polarity (0 or 1)
X 8-bit signed index or
displacement
r 4-bit Working Register
DA Destination address R 8-bit register
ER Extended Addressing register r1, R1, Ir1, Irr1, IR1,
rr1, RR1, IRR1, ER1
Destination address
IM Immediate data value r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2
Source address
Ir Indirect Working Register RA Relative
IR Indirect register rr Working Register Pair
Irr Indirect Working Register Pair RR Register Pair
PS024314-0308 Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
190
Figure 27. First Opcode Map
CP
3.3
R2,R1
CP
3.4
IR2,R1
CP
2.3
r1,r2
CP
2.4
r1,Ir2
CPX
4.3
ER2,ER1
CPX
4.3
IM,ER1
CP
3.3
R1,IM
CP
3.4
IR1,IM
RRC
2.2
R1
RRC
2.3
IR1
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Lower Nibble (Hex)
Upper Nibble (Hex)
BRK
1.1
SRP
2.2
IM
ADD
2.3
r1,r2
ADD
2.4
r1,Ir2
ADD
3.3
R2,R1
ADD
3.4
IR2,R1
ADD
3.3
R1,IM
ADD
3.4
IR1,IM
ADDX
4.3
ER2,ER1
ADDX
4.3
IM,ER1
DJNZ
2.3
r1,X
JR
2.2
cc,X
LD
2.2
r1,IM
JP
3.2
cc,DA
INC
1.2
r1
NOP
1.2
RLC
2.2
R1
RLC
2.3
IR1
ADC
2.3
r1,r2
ADC
2.4
r1,Ir2
ADC
3.3
R2,R1
ADC
3.4
IR2,R1
ADC
3.3
R1,IM
ADC
3.4
IR1,IM
ADCX
4.3
ER2,ER1
ADCX
4.3
IM,ER1
INC
2.2
R1
INC
2.3
IR1
SUB
2.3
r1,r2
SUB
2.4
r1,Ir2
SUB
3.3
R2,R1
SUB
3.4
IR2,R1
SUB
3.3
R1,IM
SUB
3.4
IR1,IM
SUBX
4.3
ER2,ER1
SUBX
4.3
IM,ER1
DEC
2.2
R1
DEC
2.3
IR1
SBC
2.3
r1,r2
SBC
2.4
r1,Ir2
SBC
3.3
R2,R1
SBC
3.4
IR2,R1
SBC
3.3
R1,IM
SBC
3.4
IR1,IM
SBCX
4.3
ER2,ER1
SBCX
4.3
IM,ER1
DA
2.2
R1
DA
2.3
IR1
OR
2.3
r1,r2
OR
2.4
r1,Ir2
OR
3.3
R2,R1
OR
3.4
IR2,R1
OR
3.3
R1,IM
OR
3.4
IR1,IM
ORX
4.3
ER2,ER1
ORX
4.3
IM,ER1
POP
2.2
R1
POP
2.3
IR1
AND
2.3
r1,r2
AND
2.4
r1,Ir2
AND
3.3
R2,R1
AND
3.4
IR2,R1
AND
3.3
R1,IM
AND
3.4
IR1,IM
ANDX
4.3
ER2,ER1
ANDX
4.3
IM,ER1
COM
2.2
R1
COM
2.3
IR1
TCM
2.3
r1,r2
TCM
2.4
r1,Ir2
TCM
3.3
R2,R1
TCM
3.4
IR2,R1
TCM
3.3
R1,IM
TCM
3.4
IR1,IM
TCMX
4.3
ER2,ER1
TCMX
4.3
IM,ER1
PUSH
2.2
R2
PUSH
2.3
IR2
TM
2.3
r1,r2
TM
2.4
r1,Ir2
TM
3.3
R2,R1
TM
3.4
IR2,R1
TM
3.3
R1,IM
TM
3.4
IR1,IM
TMX
4.3
ER2,ER1
TMX
4.3
IM,ER1
DECW
2.5
RR1
DECW
2.6
IRR1
LDE
2.5
r1,Irr2
LDEI
2.9
Ir1,Irr2
LDX
3.2
r1,ER2
LDX
3.3
Ir1,ER2
LDX
3.4
IRR2,R1
LDX
3.5
IRR2,IR1
LDX
3.4
r1,rr2,X
LDX
3.4
rr1,r2,X
RL
2.2
R1
RL
2.3
IR1
LDE
2.5
r2,Irr1
LDEI
2.9
Ir2,Irr1
LDX
3.2
r2,ER1
LDX
3.3
Ir2,ER1
LDX
3.4
R2,IRR1
LDX
3.5
IR2,IRR1
LEA
3.3
r1,r2,X
LEA
3.5
rr1,rr2,X
INCW
2.5
RR1
INCW
2.6
IRR1
CLR
2.2
R1
CLR
2.3
IR1
XOR
2.3
r1,r2
XOR
2.4
r1,Ir2
XOR
3.3
R2,R1
XOR
3.4
IR2,R1
XOR
3.3
R1,IM
XOR
3.4
IR1,IM
XORX
4.3
ER2,ER1
XORX
4.3
IM,ER1
LDC
2.5
r1,Irr2
LDCI
2.9
Ir1,Irr2
LDC
2.5
r2,Irr1
LDCI
2.9
Ir2,Irr1
JP
2.3
IRR1
LDC
2.9
Ir1,Irr2
LD
3.4
r1,r2,X
PUSHX
3.2
ER2
SRA
2.2
R1
SRA
2.3
IR1
POPX
3.2
ER1
LD
3.4
r2,r1,X
CALL
2.6
IRR1
BSWAP
2.2
R1
CALL
3.3
DA
LD
3.2
R2,R1
LD
3.3
IR2,R1
BIT
2.2
p,b,r1
LD
2.3
r1,Ir2
LDX
4.2
ER2,ER1
LDX
4.2
IM,ER1
LD
3.2
R1,IM
LD
3.3
IR1,IM
RR
2.2
R1
RR
2.3
IR1
MULT
2.8
RR1
LD
3.3
R2,IR1
TRAP
2.6
Vector
LD
2.3
Ir1,r2
BTJ
3.3
p,b,r1,X
BTJ
3.4
p,b,Ir1,X
SWAP
2.2
R1
SWAP
2.3
IR1
RCF
1.2
WDT
1.2
STOP
1.2
HALT
1.2
DI
1.2
EI
1.2
RET
1.4
IRET
1.5
SCF
1.2
CCF
1.2
Opcode
See 2nd
Map
1, 2
ATM
PS024314-0308 Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
191
Figure 28. Second Opcode Map after 1FH
CPC
4.3
R2,R1
CPC
4.4
IR2,R1
CPC
3.3
r1,r2
CPC
3.4
r1,Ir2
CPCX
5.3
ER2,ER1
CPCX
5.3
IM,ER1
CPC
4.3
R1,IM
CPC
4.4
IR1,IM
SRL
3.2
R1
SRL
3.3
IR1
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Lower Nibble (Hex)
Upper Nibble (Hex)
3, 2
PUSH
IM
LDWX
5, 4
ER2,ER1
PS024314-0308 Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
192
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
193
Electrical Characteristics
The data in this chapter is pre-qualification and pre-characterization and is subject to
change. Additional electrical characteristics may be found in the individual chapters.
Absolute Maximum Ratings
Stresses greater than those listed in Table 117 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS).
Table 117. Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias -40 +105 °C
Storage temperature -65 +150 °C
Voltage on any pin with respect to VSS -0.3 +5.5 V 1
-0.3 +3.9 V 2
Voltage on VDD pin with respect to VSS -0.3 +3.6 V
Maximum current on input and/or inactive output pin -5 +5 µA
Maximum output current from active output pin -25 +25 mA
8-pin Packages Maximum Ratings at 0 °C to 70 °C
Total power dissipation 220 mW
Maximum current into VDD or out of VSS 60 mA
20-pin Packages Maximum Ratings at 0 °C to 70 °C
Total power dissipation 430 mW
Maximum current into VDD or out of VSS 120 mA
28-pin Packages Maximum Ratings at 0 °C to 70 °C
Total power dissipation 450 mW
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
194
DC Characteristics
Table 118 lists the DC characteristics of the Z8 Encore! XP® F0823 Series products. All
voltages are referenced to VSS, the primary system ground.
Maximum current into VDD or out of VSS 125 mA
Operating temperature is specified in DC Characteristics.
1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Port B[5:0], Port
C[2:0]) and pins supporting the crystal oscillator (PA0 and PA1). On the 8-pin packages, this applies to all pins
but VDD.
2. This voltage applies to pins on the 20/28 pin packages supporting analog input (Port B[5:0], Port C[2:0]) and pins
supporting the crystal oscillator (PA0 and PA1).
Table 118. DC Characteristics
Symbol Parameter
TA = -40 °C to +105 °C
(unless otherwise specified)
Units ConditionsMinimum Typical Maximum
VDD Supply Voltage 2.7 – 3.6 V
VIL1 Low Level Input
Voltage
-0.3 – 0.3*VDD V
VIH1 High Level Input
Voltage
0.7*VDD – 5.5 V For all input pins without analog
or oscillator function. For all
signal pins on the 8-pin devices.
Programmable pull-ups must
also be disabled.
VIH2 High Level Input
Voltage
0.7*VDD –V
DD+0.3 V For those pins with analog or
oscillator function (20-/28-pin
devices only), or when
programmable pull-ups are
enabled.
VOL1 Low Level Output
Voltage
––0.4VI
OL = 2 mA; VDD = 3.0 V
High Output Drive disabled.
VOH1 High Level Output
Voltage
2.4 – – V IOH = -2 mA; VDD = 3.0 V
High Output Drive disabled.
VOL2 Low Level Output
Voltage
––0.6VI
OL = 20 mA; VDD = 3.3 V
High Output Drive enabled.
Table 117. Absolute Maximum Ratings (Continued)
Parameter Minimum Maximum Units Notes
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
195
VOH2 High Level Output
Voltage
2.4 – – V IOH = -20 mA; VDD = 3.3 V
High Output Drive enabled.
IIH Input Leakage
Current
–+0.002 +5µAV
IN = VDD
VDD = 3.3 V;
IIL Input Leakage
Current
–+0.007 +5µAV
IN = VSS
VDD = 3.3 V;
ITL Tristate Leakage
Current
––+5µA
ILED Controlled Current
Drive
1.8 3 4.5 mA {AFS2,AFS1} = {0,0}
2.8 7 10.5 mA {AFS2,AFS1} = {0,1}
7.8 13 19.5 mA {AFS2,AFS1} = {1,0}
12 20 30 mA {AFS2,AFS1} = {1,1}
CPAD GPIO Port Pad
Capacitance
–8.0
2–pF
CXIN XIN Pad
Capacitance
–8.0
2–pF
CXOUT XOUT Pad
Capacitance
–9.5
2–pF
IPU Weak Pull-up
Current
30 100 350 µA VDD = 3.0 V–3.6 V
VRAM RAM Data
Retention Voltage
TBD V Voltage at which RAM retains
static values; no reading or
writing is allowed.
Notes
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
Table 118. DC Characteristics (Continued)
Symbol Parameter
TA = -40 °C to +105 °C
(unless otherwise specified)
Units ConditionsMinimum Typical Maximum
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
196
Table 119. Power Consumption
Symbol Parameter
VDD = 2.7 V to 3.6 V
Units ConditionsTypical1
Maximum2
Std Temp
Maximum3
Ext Temp
IDD Stop Supply Current in STOP
Mode
0.1 2 7.5 µA No peripherals enabled.
All pins driven to VDD or
VSS.
IDD Halt Supply Current in HALT
Mode (with all
peripherals disabled)
35 55 65 µA 32 kHz
520 630 700 µA 5.5 MHz
IDD Supply Current in
ACTIVE Mode (with all
peripherals disabled)
2.8 4.5 4.8 mA 32 kHz
4.5 5.2 5.2 mA 5.5 MHz
IDD WDT Watchdog Timer Supply
Current
0.9 1.0 1.1 µA
IDD IPO Internal Precision
Oscillator Supply
Current
350 500 550 µA
IDD VBO Voltage Brownout
Supply Current
50 µA For 20-/28-pin devices
(VBO only); see Note 4
For 8-pin devices; See
Note 4
IDD ADC Analog-to-Digital
Converter Supply
Current (with External
Reference)
2.8 3.1 3.2 mA 32 kHz
3.1 3.6 3.7 mA 5.5 MHz
3.3 3.7 3.8 mA 10 MHz
3.7 4.2 4.3 mA 20 MHz
IDD
ADCRef
ADC Internal Reference
Supply Current
0µASee Note 4
IDD CMP Comparator supply
Current
150 180 190 µA See Note 4
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
197
AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing
information assumes a standard load of 50 pF on all outputs.
IDD BG Band Gap Supply
Current
320 480 500 µA For 20-/28-pin devices
For 8-pin devices
Notes
1. Typical conditions are defined as VDD = 3.3 V and +30 °C.
2. Standard temperature is defined as TA = 0 °C to +70 °C; these values not tested in production for worst case
behavior, but are derived from product characterization and provided for design guidance only.
3. Extended temperature is defined as TA = -40 °C to +105 °C; these values not tested in production for worst case
behavior, but are derived from product characterization and provided for design guidance only.
4. For this block to operate, the bandgap circuit is automatically turned on and must be added to the total supply
current. This bandgap current is only added once, regardless of how many peripherals are using it.
Table 120. AC Characteristics
Symbol Parameter
VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
(unless otherwise
stated)
Units ConditionsMinimum Maximum
FSYSCLK System Clock Frequency – 20.01MHz Read-only from Flash memory
0.032768 20.01MHz Program or erasure of the
Flash memory
TXIN System Clock Period 50 – ns TCLK = 1/Fsysclk
TXINH System Clock High Time 20 30 ns TCLK = 50 ns
TXINL System Clock Low Time 20 30 ns TCLK = 50 ns
TXINR System Clock Rise Time – 3 ns TCLK = 50 ns
TXINF System Clock Fall Time – 3 ns TCLK = 50 ns
1System Clock Frequency is limited by the Internal Precision Oscillator on the Z8 Encore! XP® F0823 Series. See
Table 121 on page 198.
Table 119. Power Consumption (Continued)
Symbol Parameter
VDD = 2.7 V to 3.6 V
Units ConditionsTypical1
Maximum2
Std Temp
Maximum3
Ext Temp
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
198
Table 121. Internal Precision Oscillator Electrical Characteristics
Symbol Parameter
VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
(unless otherwise stated)
Units ConditionsMinimum Typical Maximum
FIPO Internal Precision Oscillator
Frequency (High Speed)
5.53 MHz VDD = 3.3 V
TA = 30 °C
FIPO Internal Precision Oscillator
Frequency (Low Speed)
32.7 kHz VDD = 3.3 V
TA = 30 °C
FIPO Internal Precision Oscillator
Error
+1+4%
TIPOST Internal Precision Oscillator
Startup Time
3µs
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
199
On-Chip Peripheral AC and DC Electrical Characteristics
Table 122. Power-On Reset and Voltage Brownout Electrical Characteristics and Timing
Symbol Parameter
TA = -40 °C to +105 °C
Units ConditionsMinimum Typical1Maximum
VPOR Power-On Reset
Voltage Threshold
2.20 2.45 2.70 V VDD = VPOR
VVBO Voltage Brownout Reset
Voltage Threshold
2.15 2.40 2.65 V VDD = VVBO
VPOR to VVBO hysteresis 50 75 mV
Starting VDD voltage to
ensure valid Power-On
Reset.
–V
SS –V
TANA Power-On Reset Analog
Delay
–70 –µsV
DD > VPOR; TPOR Digital
Reset delay follows TANA
TPOR Power-On Reset Digital
Delay
16 µs 66 Internal Precision
Oscillator cycles + IPO
startup time (TIPOST)
TSMR Stop Mode Recovery 16 µs 66 Internal Precision
Oscillator cycles
TVBO Voltage Brownout Pulse
Rejection Period
–10 –µs Period of time in which VDD
< VVBO without generating
a Reset.
TRAMP Time for VDD to
transition from VSS to
VPOR to ensure valid
Reset
0.10 – 100 ms
TSMP Stop Mode Recovery pin
pulse rejection period
20 ns For any SMR pin or for the
Reset pin when it is
asserted in STOP mode.
1Data in the typical column is from characterization at 3.3 V and 30 °C. These values are provided for design guidance
only and are not tested in production.
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
200
Table 123. Flash Memory Electrical Characteristics and Timing
Parameter
VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
(unless otherwise stated)
Units NotesMinimum Typical Maximum
Flash Byte Read Time 100 – – ns
Flash Byte Program Time 20 – 40 µs
Flash Page Erase Time 10 – – ms
Flash Mass Erase Time 200 – – ms
Writes to Single Address
Before Next Erase
–– 2
Flash Row Program Time – – 8 ms Cumulative program time for
single row cannot exceed limit
before next erase. This
parameter is only an issue
when bypassing the Flash
Controller.
Data Retention 100 – – years 25 °C
Endurance 10,000 – – cycles Program/erase cycles
Table 124. Watchdog Timer Electrical Characteristics and Timing
Symbol Parameter
VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
(unless otherwise stated)
Units ConditionsMinimum Typical Maximum
FWDT WDT Oscillator Frequency 10 kHz
FWDT WDT Oscillator Error +50 %
TWDTCAL WDT Calibrated Timeout 0.98 1 1.02 s VDD = 3.3 V;
TA = 30 °C
0.70 1 1.30 s VDD = 2.7 V to 3.6 V
TA = 0 °C to 70 °C
0.50 1 1.50 s VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
201
Table 125. Analog-to-Digital Converter Electrical Characteristics and Timing
Symbol Parameter
VDD = 3.0 V to 3.6 V
TA = 0 °C to +70 °C
(unless otherwise stated)
Units ConditionsMinimum Typical Maximum
Resolution 10 – bits
Differential Nonlinearity
(DNL)
-1.0 – 1.0 LSB3External VREF = 2.0 V;
RS ← 3.0 kΩ
Integral Nonlinearity (INL) -3.0 – 3.0 LSB3External VREF = 2.0 V;
RS ← 3.0 kΩ
Offset Error with Calibration +1LSB
3
Absolute Accuracy with
Calibration
+3LSB
3
VREF Internal Reference Voltage 1.0
2.0
1.1
2.2
1.2
2.4
V REFSEL=01
REFSEL=10
VREF Internal Reference
Variation with Temperature
+1.0 % Temperature variation
with VDD = 3.0
VREF Internal Reference Voltage
Variation with VDD
+0.5 % Supply voltage variation
with TA = 30 °C
RREFOUT Reference Buffer Output
Impedance
850 ΩWhen the internal
reference is buffered and
driven out to the VREF
pin (REFOUT = 1)
Single-Shot Conversion
Time
– 5129 – System
clock
cycles
All measurements but
temperature sensor
10258 Temperature sensor
measurement
Continuous Conversion
Time
– 256 – System
clock
cycles
All measurements but
temperature sensor
512 Temperature sensor
measurement
Signal Input Bandwidth – 10 kHz As defined by -3 dB point
RSAnalog Source Impedance4 ––10kΩIn unbuffered mode
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
202
Table 126. Comparator Electrical Characteristics
General Purpose I/O Port Input Data Sample Timing
Figure 29 displays timing of the GPIO Port input sampling. The input value on a GPIO
Port pin is sampled on the rising edge of the system clock. The Port value is available to
the eZ8 CPU on the second rising clock edge following the change of the Port value.
Zin Input Impedance – 150 kΩIn unbuffered mode at 20
MHz5
Vin Input Voltage Range 0 VDD V Unbuffered Mode
Notes
1. Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
2. Devices are factory calibrated at VDD = 3.3 V and TA = +30 °C, so the ADC is maximally accurate under these
conditions.
3. LSBs are defined assuming 10-bit resolution.
4. This is the maximum recommended resistance seen by the ADC input pin.
5. The input impedance is inversely proportional to the system clock frequency.
Symbol Parameter
VDD = 2.7 V to 3.6 V
TA = -40 °C to +105 °C
Units ConditionsMinimum Typical Maximum
VOS Input DC Offset 5 mV
VCREF Programmable Internal
Reference Voltage
+5 % 20-/28-pin devices
+3 % 8-pin devices
TPROP Propagation Delay 200 ns
VHYS Input Hysteresis 4 mV
VIN Input Voltage Range VSS VDD-1 V
Table 125. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)
Symbol Parameter
VDD = 3.0 V to 3.6 V
TA = 0 °C to +70 °C
(unless otherwise stated)
Units ConditionsMinimum Typical Maximum
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
203
Figure 29. Port Input Sample Timing
Table 127. GPIO Port Input Timing
Parameter Abbreviation
Delay (ns)
Minimum Maximum
TS_PORT Port Input Transition to XIN Rise Setup Time (Not pictured) 5 –
TH_PORT XIN Rise to Port Input Transition Hold Time (Not pictured) 0 –
TSMR GPIO Port Pin Pulse Width to ensure Stop Mode Recovery (for GPIO
Port Pins enabled as SMR sources)
1 µs
System
TCLK
Port Pin
Port Value
Changes to 0
0 Latched
Into Port Input
Input Value
Port Input Data
Register Latch
Clock
Data Register
Port Input Data
Read on Data Bus
Port Input Data Register
Value 0 Read
by eZ8
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
204
General Purpose I/O Port Output Timing
Figure 30 and Table 128 provide timing information for GPIO Port pins.
Figure 30. GPIO Port Output Timing
Table 128. GPIO Port Output Timing
Parameter Abbreviation
Delay (ns)
Minimum Maximum
GPIO Port pins
T1XIN Rise to Port Output Valid Delay – 15
T2XIN Rise to Port Output Hold Time 2 –
XIN
Port Output
TCLK
T1 T2
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
205
On-Chip Debugger Timing
Figure 31 and Table 129 provide timing information for the DBG pin. The DBG pin
timing specifications assume a 4 ns maximum rise and fall time.
Figure 31. On-Chip Debugger Timing
Table 129. On-Chip Debugger Timing
Parameter Abbreviation
Delay (ns)
Minimum Maximum
DBG
T1XIN Rise to DBG Valid Delay – 15
T2XIN Rise to DBG Output Hold Time 2 –
T3DBG to XIN Rise Input Setup Time 5 –
T4DBG to XIN Rise Input Hold Time 5 –
XIN
DBG
TCLK
T1 T2
(Output)
DBG
T3 T4
(Input)
Output Data
Input Data
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
206
UART Timing
Figure 32 and Table 130 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit
data register has been loaded with data prior to CTS assertion.
Figure 32. UART Timing With CTS
Table 130. UART Timing With CTS
Parameter Abbreviation
Delay (ns)
Minimum Maximum
UART
T1CTS Fall to DE output delay 2 * XIN
period
2 * XIN period
+ 1 bit time
T2DE assertion to TXD falling edge (start bit) delay ± 5
T3End of Stop Bit(s) to DE deassertion delay ± 5
CTS
DE
T1
(Output)
TXD
T2
(Output)
(Input)
start bit 0 bit 1bit 7 parity stop
end of
stop bit(s)
T3
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
207
Figure 33 and Table 131 provide timing information for UART pins for the case where
CTS is not used for flow control. DE asserts after the transmit data register has been
written. DE remains asserted for multiple characters as long as the transmit data register is
written with the next character before the current character has completed.
Figure 33. UART Timing Without CTS
Table 131. UART Timing Without CTS
Parameter Abbreviation
Delay (ns)
Minimum Maximum
UART
T1DE assertion to TXD falling edge (start bit) delay 1 * XIN
period
1 bit time
T2End of Stop Bit(s) to DE deassertion delay (Tx
data register is empty)
± 5
DE
T1
(Output)
TXD
T2
(Output)
start bit0 bit 1
bit 7 parity stop
end of
stop bit(s)
PS024314-0308 Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
208
PS024314-0308 Packaging
Z8 Encore! XP® F0823 Series
Product Specification
209
Packaging
Figure 34 displays the 8-pin Plastic Dual Inline Package (PDIP) available for the
Z8 Encore! XP® F0823 Series devices.
Figure 34. 8-Pin Plastic Dual Inline Package (PDIP)
eA
E
B1
Q1
B
S
A2
L
e
A1
C
D
E1
1
8
4
5
CONTROLLING DIMENSIONS : MM.
PS024314-0308 Packaging
Z8 Encore! XP® F0823 Series
Product Specification
211
Figure 36 displays the 8-pin Quad Flat No-Lead package (QFN)/MLF-S available for the
Z8 Encore! XP F0823 Series devices. This package has a footprint identical to that of the
8-pin SOIC, but with a lower profile.
Figure 36. 8-Pin Quad Flat No-Lead Package (QFN)/MLF-S
Figure 37 displays the 20-pin Plastic Dual Inline Package (PDIP) available for
Z8 Encore! XP F0823 Series devices.
Figure 37. 20-Pin Plastic Dual Inline Package (PDIP)
PS024314-0308 Packaging
Z8 Encore! XP® F0823 Series
Product Specification
212
Figure 38 displays the 20-pin Small Outline Integrated Circuit Package (SOIC) available
for Z8 Encore! XP F0823 Series devices.
Figure 38. 20-Pin Small Outline Integrated Circuit Package (SOIC)
Figure 39 displays the 20-pin Small Shrink Outline Package (SSOP) available for
Z8 Encore! XP F0823 Series devices.
Figure 39. 20-Pin Small Shrink Outline Package (SSOP)
PS024314-0308 Packaging
Z8 Encore! XP® F0823 Series
Product Specification
215
Figure 42 displays the 28-pin Small Shrink Outline Package (SSOP) available for
Z8 Encore! XP F0823 Series devices.
Figure 42. 28-Pin Small Shrink Outline Package (SSOP)
SYMBOL
A
A1
B
C
A2
e
MILLIMETER INCH
MIN MAX MIN MAX
1.73
0.05
1.68
0.25
5.20
0.65 TYP
0.09
10.07
7.65
0.63
1.86
0.0256 TYP
0.13
10.20
1.73
7.80
5.30
1.99
0.21
1.78
0.75
0.068
0.002
0.066
0.010
0.205
0.004
0.397
0.301
0.025
0.073
0.005
0.068
0.209
0.006
0.402
0.307
0.030
0.078
0.008
0.070
0.015
0.212
0.008
0.407
0.311
0.037
0.38
0.20
10.33
5.38
7.90
0.95
NOM NOM
D
E
H
L
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES .
H
C
DETAIL A
E
D
28 15
114
SEATING PLANE
A2
e
A
Q1
A1
B
L
0 - 8
PS024314-0308 Packaging
Z8 Encore! XP® F0823 Series
Product Specification
216
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
217
Ordering Information
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
Z8 Encore! XP with 8 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 °C to 70 °C
Z8F0823PB005SC 8 KB 1 KB 6 12 2 4 1 PDIP 8-pin package
Z8F0823QB005SC 8 KB 1 KB 6 12 2 4 1 QFN 8-pin package
Z8F0823SB005SC 8 KB 1 KB 6 12 2 4 1 SOIC 8-pin package
Z8F0823SH005SC 8 KB 1 KB 16 18 2 7 1 SOIC 20-pin package
Z8F0823HH005SC 8 KB 1 KB 16 18 2 7 1 SSOP 20-pin package
Z8F0823PH005SC 8 KB 1 KB 16 18 2 7 1 PDIP 20-pin package
Z8F0823SJ005SC 8 KB 1 KB 22 18 2 8 1 SOIC 28-pin package
Z8F0823HJ005SC 8 KB 1 KB 22 18 2 8 1 SSOP 28-pin package
Z8F0823PJ005SC 8 KB 1 KB 22 18 2 8 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0823PB005EC 8 KB 1 KB 6 12 2 4 1 PDIP 8-pin package
Z8F0823QB005EC 8 KB 1 KB 6 12 2 4 1 QFN 8-pin package
Z8F0823SB005EC 8 KB 1 KB 6 12 2 4 1 SOIC 8-pin package
Z8F0823SH005EC 8 KB 1 KB 16 18 2 7 1 SOIC 20-pin package
Z8F0823HH005EC 8 KB 1 KB 16 18 2 7 1 SSOP 20-pin package
Z8F0823PH005EC 8 KB 1 KB 16 18 2 7 1 PDIP 20-pin package
Z8F0823SJ005EC 8 KB 1 KB 22 18 2 8 1 SOIC 28-pin package
Z8F0823HJ005EC 8 KB 1 KB 22 18 2 8 1 SSOP 28-pin package
Z8F0823PJ005EC 8 KB 1 KB 22 18 2 8 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
218
Z8 Encore! XP with 8 KB Flash
Standard Temperature: 0 °C to 70 °C
Z8F0813PB005SC 8 KB 1 KB 6 12 2 0 1 PDIP 8-pin package
Z8F0813QB005SC 8 KB 1 KB 6 12 2 0 1 QFN 8-pin package
Z8F0813SB005SC 8 KB 1 KB 6 12 2 0 1 SOIC 8-pin package
Z8F0813SH005SC 8 KB 1 KB 16 18 2 0 1 SOIC 20-pin package
Z8F0813HH005SC 8 KB 1 KB 16 18 2 0 1 SSOP 20-pin package
Z8F0813PH005SC 8 KB 1 KB 16 18 2 0 1 PDIP 20-pin package
Z8F0813SJ005SC 8 KB 1 KB 24 18 2 0 1 SOIC 28-pin package
Z8F0813HJ005SC 8 KB 1 KB 24 18 2 0 1 SSOP 28-pin package
Z8F0813PJ005SC 8 KB 1 KB 24 18 2 0 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0813PB005EC 8 KB 1 KB 6 12 2 0 1 PDIP 8-pin package
Z8F0813QB005EC 8 KB 1 KB 6 12 2 0 1 QFN 8-pin package
Z8F0813SB005EC 8 KB 1 KB 6 12 2 0 1 SOIC 8-pin package
Z8F0813SH005EC 8 KB 1 KB 16 18 2 0 1 SOIC 20-pin package
Z8F0813HH005EC 8 KB 1 KB 16 18 2 0 1 SSOP 20-pin package
Z8F0813PH005EC 8 KB 1 KB 16 18 2 0 1 PDIP 20-pin package
Z8F0813SJ005EC 8 KB 1 KB 24 18 2 0 1 SOIC 28-pin package
Z8F0813HJ005EC 8 KB 1 KB 24 18 2 0 1 SSOP 28-pin package
Z8F0813PJ005EC 8 KB 1 KB 24 18 2 0 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
219
Z8 Encore! XP with 4 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 °C to 70 °C
Z8F0423PB005SC 4 KB 1 KB 6 12 2 4 1 PDIP 8-pin package
Z8F0423QB005SC 4 KB 1 KB 6 12 2 4 1 QFN 8-pin package
Z8F0423SB005SC 4 KB 1 KB 6 12 2 4 1 SOIC 8-pin package
Z8F0423SH005SC 4 KB 1 KB 16 18 2 7 1 SOIC 20-pin package
Z8F0423HH005SC 4 KB 1 KB 16 18 2 7 1 SSOP 20-pin package
Z8F0423PH005SC 4 KB 1 KB 16 18 2 7 1 PDIP 20-pin package
Z8F0423SJ005SC 4 KB 1 KB 22 18 2 8 1 SOIC 28-pin package
Z8F0423HJ005SC 4 KB 1 KB 22 18 2 8 1 SSOP 28-pin package
Z8F0423PJ005SC 4 KB 1 KB 22 18 2 8 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0423PB005EC 4 KB 1 KB 6 12 2 4 1 PDIP 8-pin package
Z8F0423QB005EC 4 KB 1 KB 6 12 2 4 1 QFN 8-pin package
Z8F0423SB005EC 4 KB 1 KB 6 12 2 4 1 SOIC 8-pin package
Z8F0423SH005EC 4 KB 1 KB 16 18 2 7 1 SOIC 20-pin package
Z8F0423HH005EC 4 KB 1 KB 16 18 2 7 1 SSOP 20-pin package
Z8F0423PH005EC 4 KB 1 KB 16 18 2 7 1 PDIP 20-pin package
Z8F0423SJ005EC 4 KB 1 KB 22 18 2 8 1 SOIC 28-pin package
Z8F0423HJ005EC 4 KB 1 KB 22 18 2 8 1 SSOP 28-pin package
Z8F0423PJ005EC 4 KB 1 KB 22 18 2 8 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
220
Z8 Encore! XP with 4 KB Flash
Standard Temperature: 0 °C to 70 °C
Z8F0413PB005SC 4 KB 1 KB 6 12 2 0 1 PDIP 8-pin package
Z8F0413QB005SC 4 KB 1 KB 6 12 2 0 1 QFN 8-pin package
Z8F0413SB005SC 4 KB 1 KB 6 12 2 0 1 SOIC 8-pin package
Z8F0413SH005SC 4 KB 1 KB 16 18 2 0 1 SOIC 20-pin package
Z8F0413HH005SC 4 KB 1 KB 16 18 2 0 1 SSOP 20-pin package
Z8F0413PH005SC 4 KB 1 KB 16 18 2 0 1 PDIP 20-pin package
Z8F0413SJ005SC 4 KB 1 KB 24 18 2 0 1 SOIC 28-pin package
Z8F0413HJ005SC 4 KB 1 KB 24 18 2 0 1 SSOP 28-pin package
Z8F0413PJ005SC 4 KB 1 KB 24 18 2 0 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0413PB005EC 4 KB 1 KB 6 12 2 0 1 PDIP 8-pin package
Z8F0413QB005EC 4 KB 1 KB 6 12 2 0 1 QFN 8-pin package
Z8F0413SB005EC 4 KB 1 KB 6 12 2 0 1 SOIC 8-pin package
Z8F0413SH005EC 4 KB 1 KB 16 18 2 0 1 SOIC 20-pin package
Z8F0413HH005EC 4 KB 1 KB 16 18 2 0 1 SSOP 20-pin package
Z8F0413PH005EC 4 KB 1 KB 16 18 2 0 1 PDIP 20-pin package
Z8F0413SJ005EC 4 KB 1 KB 24 18 2 0 1 SOIC 28-pin package
Z8F0413HJ005EC 4 KB 1 KB 24 18 2 0 1 SSOP 28-pin package
Z8F0413PJ005EC 4 KB 1 KB 24 18 2 0 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
221
Z8 Encore! XP with 2 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 °C to 70 °C
Z8F0223PB005SC 2 KB 512 B 6 12 2 4 1 PDIP 8-pin package
Z8F0223QB005SC 2 KB 512 B 6 12 2 4 1 QFN 8-pin package
Z8F0223SB005SC 2 KB 512 B 6 12 2 4 1 SOIC 8-pin package
Z8F0223SH005SC 2 KB 512 B 16 18 2 7 1 SOIC 20-pin package
Z8F0223HH005SC 2 KB 512 B 16 18 2 7 1 SSOP 20-pin package
Z8F0223PH005SC 2 KB 512 B 16 18 2 7 1 PDIP 20-pin package
Z8F0223SJ005SC 2 KB 512 B 22 18 2 8 1 SOIC 28-pin package
Z8F0223HJ005SC 2 KB 512 B 22 18 2 8 1 SSOP 28-pin package
Z8F0223PJ005SC 2 KB 512 B 22 18 2 8 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0223PB005EC 2 KB 512 B 6 12 2 4 1 PDIP 8-pin package
Z8F0223QB005EC 2 KB 512 B 6 12 2 4 1 QFN 8-pin package
Z8F0223SB005EC 2 KB 512 B 6 12 2 4 1 SOIC 8-pin package
Z8F0223SH005EC 2 KB 512 B 16 18 2 7 1 SOIC 20-pin package
Z8F0223HH005EC 2 KB 512 B 16 18 2 7 1 SSOP 20-pin package
Z8F0223PH005EC 2 KB 512 B 16 18 2 7 1 PDIP 20-pin package
Z8F0223SJ005EC 2 KB 512 B 22 18 2 8 1 SOIC 28-pin package
Z8F0223HJ005EC 2 KB 512 B 22 18 2 8 1 SSOP 28-pin package
Z8F0223PJ005EC 2 KB 512 B 22 18 2 8 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
222
Z8 Encore! XP with 2 KB Flash
Standard Temperature: 0 °C to 70 °C
Z8F0213PB005SC 2 KB 512 B 6 12 2 0 1 PDIP 8-pin package
Z8F0213QB005SC 2 KB 512 B 6 12 2 0 1 QFN 8-pin package
Z8F0213SB005SC 2 KB 512 B 6 12 2 0 1 SOIC 8-pin package
Z8F0213SH005SC 2 KB 512 B 16 18 2 0 1 SOIC 20-pin package
Z8F0213HH005SC 2 KB 512 B 16 18 2 0 1 SSOP 20-pin package
Z8F0213PH005SC 2 KB 512 B 16 18 2 0 1 PDIP 20-pin package
Z8F0213SJ005SC 2 KB 512 B 24 18 2 0 1 SOIC 28-pin package
Z8F0213HJ005SC 2 KB 512 B 24 18 2 0 1 SSOP 28-pin package
Z8F0213PJ005SC 2 KB 512 B 24 18 2 0 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0213PB005EC 2 KB 512 B 6 12 2 0 1 PDIP 8-pin package
Z8F0213QB005EC 2 KB 512 B 6 12 2 0 1 QFN 8-pin package
Z8F0213SB005EC 2 KB 512 B 6 12 2 0 1 SOIC 8-pin package
Z8F0213SH005EC 2 KB 512 B 16 18 2 0 1 SOIC 20-pin package
Z8F0213HH005EC 2 KB 512 B 16 18 2 0 1 SSOP 20-pin package
Z8F0213PH005EC 2 KB 512 B 16 18 2 0 1 PDIP 20-pin package
Z8F0213SJ005EC 2 KB 512 B 24 18 2 0 1 SOIC 28-pin package
Z8F0213HJ005EC 2 KB 512 B 24 18 2 0 1 SSOP 28-pin package
Z8F0213PJ005EC 2 KB 512 B 24 18 2 0 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
223
Z8 Encore! XP with 1 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 °C to 70 °C
Z8F0123PB005SC 1 KB 256 B 6 12 2 4 1 PDIP 8-pin package
Z8F0123QB005SC 1 KB 256 B 6 12 2 4 1 QFN 8-pin package
Z8F0123SB005SC 1 KB 256 B 6 12 2 4 1 SOIC 8-pin package
Z8F0123SH005SC 1 KB 256 B 16 18 2 7 1 SOIC 20-pin package
Z8F0123HH005SC 1 KB 256 B 16 18 2 7 1 SSOP 20-pin package
Z8F0123PH005SC 1 KB 256 B 16 18 2 7 1 PDIP 20-pin package
Z8F0123SJ005SC 1 KB 256 B 22 18 2 8 1 SOIC 28-pin package
Z8F0123HJ005SC 1 KB 256 B 22 18 2 8 1 SSOP 28-pin package
Z8F0123PJ005SC 1 KB 256 B 22 18 2 8 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0123PB005EC 1 KB 256 B 6 12 2 4 1 PDIP 8-pin package
Z8F0123QB005EC 1 KB 256 B 6 12 2 4 1 QFN 8-pin package
Z8F0123SB005EC 1 KB 256 B 6 12 2 4 1 SOIC 8-pin package
Z8F0123SH005EC 1 KB 256 B 16 18 2 7 1 SOIC 20-pin package
Z8F0123HH005EC 1 KB 256 B 16 18 2 7 1 SSOP 20-pin package
Z8F0123PH005EC 1 KB 256 B 16 18 2 7 1 PDIP 20-pin package
Z8F0123SJ005EC 1 KB 256 B 22 18 2 8 1 SOIC 28-pin package
Z8F0123HJ005EC 1 KB 256 B 22 18 2 8 1 SSOP 28-pin package
Z8F0123PJ005EC 1 KB 256 B 22 18 2 8 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
224
Z8 Encore! XP with 1 KB Flash
Standard Temperature: 0 °C to 70 °C
Z8F0113PB005SC 1 KB 256 B 6 12 2 0 1 PDIP 8-pin package
Z8F0113QB005SC 1 KB 256 B 6 12 2 0 1 QFN 8-pin package
Z8F0113SB005SC 1 KB 256 B 6 12 2 0 1 SOIC 8-pin package
Z8F0113SH005SC 1 KB 256 B 16 18 2 0 1 SOIC 20-pin package
Z8F0113HH005SC 1 KB 256 B 16 18 2 0 1 SSOP 20-pin package
Z8F0113PH005SC 1 KB 256 B 16 18 2 0 1 PDIP 20-pin package
Z8F0113SJ005SC 1 KB 256 B 24 18 2 0 1 SOIC 28-pin package
Z8F0113HJ005SC 1 KB 256 B 24 18 2 0 1 SSOP 28-pin package
Z8F0113PJ005SC 1 KB 256 B 24 18 2 0 1 PDIP 28-pin package
Extended Temperature: -40 °C to 105 °C
Z8F0113PB005EC 1 KB 256 B 6 12 2 0 1 PDIP 8-pin package
Z8F0113QB005EC 1 KB 256 B 6 12 2 0 1 QFN 8-pin package
Z8F0113SB005EC 1 KB 256 B 6 12 2 0 1 SOIC 8-pin package
Z8F0113SH005EC 1 KB 256 B 16 18 2 0 1 SOIC 20-pin package
Z8F0113HH005EC 1 KB 256 B 16 18 2 0 1 SSOP 20-pin package
Z8F0113PH005EC 1 KB 256 B 16 18 2 0 1 PDIP 20-pin package
Z8F0113SJ005EC 1 KB 256 B 24 18 2 0 1 SOIC 28-pin package
Z8F0113HJ005EC 1 KB 256 B 24 18 2 0 1 SSOP 28-pin package
Z8F0113PJ005EC 1 KB 256 B 24 18 2 0 1 PDIP 28-pin package
Replace C with G for Lead-Free Packaging
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
225
Z8 Encore! XP® F0823 Series Development Kit
Z8F08A28100KITG Z8 Encore! XP F082A Series Development Kit (20- and 28-Pin)
Z8F04A28100KITG Z8 Encore! XP F042A Series Development Kit (20- and 28-Pin)
Z8F04A08100KITG Z8 Encore! XP F042A Series Development Kit (8-Pin)
ZUSBSC00100ZACG USB Smart Cable Accessory Kit
ZUSBOPTSC01ZACG Opto-Isolated USB Smart Cable Accessory Kit
ZENETSC0100ZACG Ethernet Smart Cable Accessory Kit
Part Number
Flash
RAM
I/O Lines
Interrupts
16-Bit Timers
w/PWM
10-Bit A/D Channels
UART with IrDA
Description
PS024314-0308 Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
226
Part Number Suffix Designations
Z8 F 04 23 S H 005 S C
Environmental Flow
C = Standard Plastic Packaging Compound
G = Green Plastic Packaging Compound
Temperature Range
S = Standard, 0 °C to 70 °C
E = Extended, -40 °C to +105 °C
Speed
020 = 20 MHz
Pin Count
B = 8
H = 20
J = 28
Package
H = SSOP
P = PDIP
S = SOIC
Device Type
23 = 6-22 I/O lines, 4-8 ADC channels
13 = 6-24 I/O lines, no ADC channels
Memory Size
08 = 8 KB Flash, 1 KB RAM
04 = 4 KB Flash, 1 KB RAM
02 = 2 KB Flash, 512 B RAM
01 = 1 KB Flash, 256 B RAM
Memory Type
F = Flash
Device Family
Z8 = Zilog’s 8-Bit Microcontroller
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
227
Index
Symbols
# 174
% 174
@ 174
Numerics
10-bit ADC 4
40-lead plastic dual-inline package 214, 215
A
absolute maximum ratings 193
AC characteristics 197
ADC 175
architecture 117
automatic power-down 118
block diagram 118
continuous conversion 120
control register 122, 124
control register definitions 122
data high byte register 124
data low bits register 125
electrical characteristics and timing 201
operation 118
single-shot conversion 119
ADCCTL register 122, 124
ADCDH register 124
ADCDL register 125
ADCX 175
ADD 175
add - extended addressing 175
add with carry 175
add with carry - extended addressing 175
additional symbols 174
address space 13
ADDX 175
analog signals 10
analog-to-digital converter (ADC) 117
AND 177
ANDX 177
arithmetic instructions 175
assembly language programming 171
assembly language syntax 172
B
B 174
b 173
baud rate generator, UART 103
BCLR 176
binary number suffix 174
BIT 176
bit 173
clear 176
manipulation instructions 176
set 176
set or clear 176
swap 176
test and jump 178
test and jump if non-zero 178
test and jump if zero 178
bit jump and test if non-zero 178
bit swap 178
block diagram 3
block transfer instructions 176
BRK 178
BSET 176
BSWAP 176, 178
BTJ 178
BTJNZ 178
BTJZ 178
C
CALL procedure 178
CAPTURE mode 84, 85
CAPTURE/COMPARE mode 85
cc 173
CCF 176
characteristics, electrical 193
clear 177
CLR 177
COM 177
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
228
COMPARE 84
compare - extended addressing 175
COMPARE mode 84
compare with carry 175
compare with carry - extended addressing 175
complement 177
complement carry flag 176
condition code 173
continuous conversion (ADC) 120
CONTINUOUS mode 84
control register definition, UART 104
Control Registers 13, 17
COUNTER modes 84
CP 175
CPC 175
CPCX 175
CPU and peripheral overview 4
CPU control instructions 176
CPX 175
Customer Support 237
D
DA 173, 175
data memory 15
DC characteristics 194
debugger, on-chip 151
DEC 175
decimal adjust 175
decrement 175
decrement and jump non-zero 178
decrement word 175
DECW 175
destination operand 174
device, port availability 35
DI 176
direct address 173
disable interrupts 176
DJNZ 178
dst 174
E
EI 176
electrical characteristics 193
ADC 201
flash memory and timing 200
GPIO input data sample timing 202
Watchdog Timer 200, 202
enable interrupt 176
ER 173
extended addressing register 173
external pin reset 25
eZ8 CPU features 4
eZ8 CPU instruction classes 174
eZ8 CPU instruction notation 172
eZ8 CPU instruction set 171
eZ8 CPU instruction summary 179
F
FCTL register 137, 143, 144
features, Z8 Encore! 1
first opcode map 190
FLAGS 174
flags register 174
flash
controller 4
option bit address space 144
option bit configuration - reset 141
program memory address 0000H 144
program memory address 0001H 145
flash memory 129
arrangement 130
byte programming 135
code protection 133
configurations 129
control register definitions 137, 143
controller bypass 136
electrical characteristics and timing 200
flash control register 137, 143, 144
flash option bits 134
flash status register 137
flow chart 132
frequency high and low byte registers 139
mass erase 135
operation 131
operation timing 133
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
229
page erase 135
page select register 138, 139
FPS register 138, 139
FSTAT register 137
G
GATED mode 84
general-purpose I/O 35
GPIO 4, 35
alternate functions 36
architecture 36
control register definitions 43
input data sample timing 202
interrupts 43
port A-C pull-up enable sub-registers 48,
49
port A-H address registers 44
port A-H alternate function sub-registers 45
port A-H control registers 44
port A-H data direction sub-registers 45
port A-H high drive enable sub-registers 47
port A-H input data registers 49
port A-H output control sub-registers 46
port A-H output data registers 50
port A-H stop mode recovery sub-registers
47
port availability by device 35
port input timing 203
port output timing 204
H
H 174
HALT 176
halt mode 32, 176
hexadecimal number prefix/suffix 174
I
I2C 4
IM 173
immediate data 173
immediate operand prefix 174
INC 175
increment 175
increment word 175
INCW 175
indexed 173
indirect address prefix 174
indirect register 173
indirect register pair 173
indirect working register 173
indirect working register pair 173
infrared encoder/decoder (IrDA) 113
Instruction Set 171
instruction set, eZ8 CPU 171
instructions
ADC 175
ADCX 175
ADD 175
ADDX 175
AND 177
ANDX 177
arithmetic 175
BCLR 176
BIT 176
bit manipulation 176
block transfer 176
BRK 178
BSET 176
BSWAP 176, 178
BTJ 178
BTJNZ 178
BTJZ 178
CALL 178
CCF 176
CLR 177
COM 177
CP 175
CPC 175
CPCX 175
CPU control 176
CPX 175
DA 175
DEC 175
DECW 175
DI 176
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
230
DJNZ 178
EI 176
HALT 176
INC 175
INCW 175
IRET 178
JP 178
LD 177
LDC 177
LDCI 176, 177
LDE 177
LDEI 176
LDX 177
LEA 177
load 177
logical 177
MULT 175
NOP 176
OR 177
ORX 178
POP 177
POPX 177
program control 178
PUSH 177
PUSHX 177
RCF 176
RET 178
RL 178
RLC 178
rotate and shift 178
RR 178
RRC 178
SBC 175
SCF 176, 177
SRA 179
SRL 179
SRP 177
STOP 177
SUB 175
SUBX 175
SWAP 179
TCM 176
TCMX 176
TM 176
TMX 176
TRAP 178
Watchdog Timer refresh 177
XOR 178
XORX 178
instructions, eZ8 classes of 174
interrupt control register 64
interrupt controller 53
architecture 53
interrupt assertion types 56
interrupt vectors and priority 56
operation 55
register definitions 58
software interrupt assertion 57
interrupt edge select register 63
interrupt request 0 register 58
interrupt request 1 register 59
interrupt request 2 register 59
interrupt return 178
interrupt vector listing 53
interrupts
UART 101
IR 173
Ir 173
IrDA
architecture 113
block diagram 113
control register definitions 116
operation 113
receiving data 115
transmitting data 114
IRET 178
IRQ0 enable high and low bit registers 60
IRQ1 enable high and low bit registers 61
IRQ2 enable high and low bit registers 62
IRR 173
Irr 173
J
JP 178
jump, conditional, relative, and relative condi-
tional 178
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
231
L
LD 177
LDC 177
LDCI 176, 177
LDE 177
LDEI 176, 177
LDX 177
LEA 177
load 177
load constant 176
load constant to/from program memory 177
load constant with auto-increment addresses
177
load effective address 177
load external data 177
load external data to/from data memory and
auto-increment addresses 176
load external to/from data memory and auto-in-
crement addresses 177
load instructions 177
load using extended addressing 177
logical AND 177
logical AND/extended addressing 177
logical exclusive OR 178
logical exclusive OR/extended addressing 178
logical instructions 177
logical OR 177
logical OR/extended addressing 178
low power modes 31
M
master interrupt enable 55
memory
data 15
program 13
mode
CAPTURE 84, 85
CAPTURE/COMPARE 85
CONTINUOUS 84
COUNTER 84
GATED 84
ONE-SHOT 84
PWM 84, 85
modes 84
MULT 175
multiply 175
MULTIPROCESSOR mode, UART 99
N
NOP (no operation) 176
notation
b 173
cc 173
DA 173
ER 173
IM 173
IR 173
Ir 173
IRR 173
Irr 173
p 173
R 173
r 173
RA 173
RR 173
rr 173
vector 173
X 173
notational shorthand 173
O
OCD
architecture 151
auto-baud detector/generator 154
baud rate limits 155
block diagram 151
breakpoints 156
commands 157
control register 161
data format 154
DBG pin to RS-232 Interface 152
DEBUG mode 153
debugger break 178
interface 152
serial errors 155
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
232
status register 163
timing 205
OCD commands
execute instruction (12H) 161
read data memory (0DH) 160
read OCD control register (05H) 158
read OCD revision (00H) 158
read OCD status register (02H) 158
read program counter (07H) 159
read program memory (0BH) 160
read program memory CRC (0EH) 161
read register (09H) 159
read runtime counter (03H) 158
step instruction (10H) 161
stuff instruction (11H) 161
write data memory (0CH) 160
write OCD control register (04H) 158
write program counter (06H) 159
write program memory (0AH) 159
write register (08H) 159
on-chip debugger (OCD) 151
on-chip debugger signals 10
ONE-SHOT mode 84
opcode map
abbreviations 189
cell description 188
first 190
second after 1FH 191
Operational Description 21, 31, 35, 53, 67, 87,
93, 113, 117, 127, 129, 141, 151, 165, 169
OR 177
ordering information 217
ORX 178
P
p 173
packaging
20-pin PDIP 211, 212
20-pin SSOP 212, 215
28-pin PDIP 213
28-pin SOIC 214
8-pin PDIP 209
8-pin SOIC 210
PDIP 214, 215
part selection guide 2
PC 174
PDIP 214, 215
peripheral AC and DC electrical characteristics
199
pin characteristics 10
Pin Descriptions 7
polarity 173
POP 177
pop using extended addressing 177
POPX 177
port availability, device 35
port input timing (GPIO) 203
port output timing, GPIO 204
power supply signals 10
power-down, automatic (ADC) 118
Power-on and Voltage Brownout electrical
characteristics and timing 199
Power-On Reset (POR) 23
program control instructions 178
program counter 174
program memory 13
PUSH 177
push using extended addressing 177
PUSHX 177
PWM mode 84, 85
PxADDR register 44
PxCTL register 45
R
R 173
r 173
RA
register address 173
RCF 176
receive
IrDA data 115
receiving UART data-interrupt-driven method
98
receiving UART data-polled method 97
register 173
ADC control (ADCCTL) 122, 124
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
233
ADC data high byte (ADCDH) 124
ADC data low bits (ADCDL) 125
flash control (FCTL) 137, 143, 144
flash high and low byte (FFREQH and
FREEQL) 139
flash page select (FPS) 138, 139
flash status (FSTAT) 137
GPIO port A-H address (PxADDR) 44
GPIO port A-H alternate function sub-regis-
ters 46
GPIO port A-H control address (PxCTL) 45
GPIO port A-H data direction sub-registers
45
OCD control 161
OCD status 163
UARTx baud rate high byte (UxBRH) 110
UARTx baud rate low byte (UxBRL) 110
UARTx Control 0 (UxCTL0) 107, 110
UARTx control 1 (UxCTL1) 108
UARTx receive data (UxRXD) 105
UARTx status 0 (UxSTAT0) 105
UARTx status 1 (UxSTAT1) 106
UARTx transmit data (UxTXD) 104
Watchdog Timer control (WDTCTL) 90,
128
watch-dog timer control (WDTCTL) 167
Watchdog Timer reload high byte (WDTH)
91
Watchdog Timer reload low byte (WDTL)
91
Watchdog Timer reload upper byte (WD-
TU) 91
register file 13
register pair 173
register pointer 174
reset
and stop mode characteristics 22
and stop mode recovery 21
carry flag 176
sources 22
RET 178
return 178
RL 178
RLC 178
rotate and shift instructions 178
rotate left 178
rotate left through carry 178
rotate right 178
rotate right through carry 178
RP 174
RR 173, 178
rr 173
RRC 178
S
SBC 175
SCF 176, 177
second opcode map after 1FH 191
set carry flag 176, 177
set register pointer 177
shift right arithmetic 179
shift right logical 179
signal descriptions 9
single-sho conversion (ADC) 119
software trap 178
source operand 174
SP 174
SRA 179
src 174
SRL 179
SRP 177
stack pointer 174
STOP 177
STOP mode 31, 177
Stop Mode Recovery
sources 26
using a GPIO port pin transition 27, 28
using Watchdog Timer time-out 27
SUB 175
subtract 175
subtract - extended addressing 175
subtract with carry 175
subtract with carry - extended addressing 175
SUBX 175
SWAP 179
swap nibbles 179
symbols, additional 174
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
234
T
TCM 176
TCMX 176
test complement under mask 176
test complement under mask - extended ad-
dressing 176
test under mask 176
test under mask - extended addressing 176
timer signals 9
timers 67
architecture 67
block diagram 67
CAPTURE mode 74, 75, 84, 85
CAPTURE/COMPARE mode 78, 85
COMPARE mode 76, 84
CONTINUOUS mode 69, 84
COUNTER mode 70, 71
COUNTER modes 84
GATED mode 77, 84
ONE-SHOT mode 68, 84
operating mode 68
PWM mode 72, 73, 84, 85
reading the timer count values 79
reload high and low byte registers 80
timer control register definitions 80
timer output signal operation 79
timers 0-3
control registers 82, 83
high and low byte registers 80, 81
TM 176
TMX 176
tools, hardware and software 226
transmit
IrDA data 114
transmitting UART data-polled method 95
transmitting UART dat-interrupt-driven method
96
TRAP 178
U
UART 4
architecture 93
baud rate generator 103
control register definitions 104
controller signals 9
data format 94
interrupts 101
MULTIPROCESSOR mode 99
receiving data using interrupt-driven meth-
od 98
receiving data using the polled method 97
transmitting data using the interrupt-driven
method 96
transmitting data using the polled method
95
x baud rate high and low registers 110
x control 0 and control 1 registers 107
x status 0 and status 1 registers 105, 106
UxBRH register 110
UxBRL register 110
UxCTL0 register 107, 110
UxCTL1 register 108
UxRXD register 105
UxSTAT0 register 105
UxSTAT1 register 106
UxTXD register 104
V
vector 173
Voltage Brownout reset (VBR) 24
W
Watchdog Timer
approximate time-out delay 87
CNTL 24
control register 89, 127, 167
electrical characteristics and timing 200,
202
interrupt in normal operation 88
interrupt in STOP mode 88
refresh 88, 177
reload unlock sequence 89
reload upper, high and low registers 90
reset 25
reset in normal operation 89
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
235
reset in STOP mode 89
time-out response 88
Watchdog Timer Control Register (WDTCTL)
90
WDTCTL register 90, 128, 167
WDTH register 91
WDTL register 91
WDTU register 91
working register 173
working register pair 173
X
X 173
XOR 178
XORX 178
Z
Z8 Encore!
block diagram 3
features 1
part selection guide 2
Z8 Encore! XP® F0823 Series
Product Specification
PS024314-0308 Index
236
PS024314-0308 Customer Support
Z8 Encore! XP® F0823 Series
Product Specification
237
Customer Support
For answers to technical questions about the product, documentation, or any
other issues with Zilog’s offerings, please visit Zilog’s Knowledge
Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit Zilog’s
Technical Support at http://support.zilog.com.
