FN8713 Rev 7.00 Page 1 of 24
Sep 28, 2018
FN8713
Rev 7.00
Sep 28, 2018
ISL78235
5A Automotive Synchronous Buck Regulator
DATASHEET
The ISL78235 is a highly efficient, monolithic, synchronous
step-down DC/DC converter that can deliver 5A of continuous
output current from a 2.7V to 5.5V input supply. The device uses
peak current mode control architecture to achieve very low duty
cycle operation at high frequency with fast transient response and
excellent loop stability.
The ISL78235 integrates a low ON-resistance P-channel
(35mΩ, typical) high-side FET and N-channel (11mΩ, typical)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty cycle operation allows less
than 250mV dropout voltage at 5A output current. The
operating frequency of the Pulse-Width Modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 2MHz is set by connecting the FS pin high.
The ISL78235 can be configured for discontinuous (PFM) or
forced continuous (PWM) operation at light load. Forced
continuous operation reduces noise and RF interference;
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short-circuit and overcurrent conditions. The
device also integrates output overvoltage and
over-temperature protections. A power-good monitor indicates
when the output is in regulation. The ISL78235 features a 1ms
Power-Good (PG) timer at power-up.
When in shutdown, the ISL78235 discharges the output
capacitor through an internal 100Ω soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
The ISL78235 is available in a 3mmx3mm 16 Ld Thin Quad Flat
No-lead (TQFN) Pb-free package and in a 5mmx5mm 16 Ld
Wettable Flank Quad Flat No-Lead (WFQFN) package with an
exposed pad for improved thermal performance. The
ISL78235 is rated to operate across the temperature range of
-40°C to +105°C in the 3mmx3mm package and -40°C to
+125°C in the 5mmx5mm package.
Features
• 2.7V to 5.5V input voltage range
• 2MHz default switching frequency
• 100ns guaranteed phase minimum on time for wide output
regulation
• Adjustable switching frequency from 500kHz to 4MHz
• External synchronization from 1MHz to 4MHz
• Optional PFM mode for light-load efficiency improvement
• Very low ON-resistance HS/LS switches: 35mΩ/11mΩ
• Internal 1ms or adjustable external soft-start
• Soft-stop output discharge during disable
• OTP, OCP, output OVP, and input UVLO protections
• 1% reference accuracy over-temperature
•Up to 95% efficiency
•AEC-Q100 qualified
• Common pinout family allows migration from 3A to 5A
without PCB change:
- ISL78233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A
- ISL78234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4A
- ISL78235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A
Applications
• DC/DC POL modules
•μC/µP, FPGA, and DSP power
• Video processor/SOC power
• Automotive infotainment power
Related Literature
For a full list of related documents, visit our website
-ISL78235 product page
FIGURE 1. TYPICAL APPLICATION: 5A BUCK REGULATOR FIGURE 2. EFFICIENCY vs LOAD (VIN = 5V; fsw = 2MHz; SYNC = GND)
1
3
4
VIN
VDD
SYNC
VIN
PHASE
PHASE
COMP
2
7
56
FB
PGND
EN
FS
PG
SS
8
11
9
10
16 13
15 14
12
SGND
PGND
PHASE
2.7V TO 5.5V
VOUT 5A LOAD
DSP, FPGA
*ISL78235
*Pin Compatible
ISL78233 - 3A BUCK
ISL78234 - 4A BUCK
L
COUT
CIN
40
50
60
70
80
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
4.5 5.0
2.5VOUT
1.2VOUT
3.3VOUT
TA = +25°C
100
1.5VOUT
1.8VOUT
ISL78235
FN8713 Rev 7.00 Page 2 of 24
Sep 28, 2018
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Skip Mode (PFM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L16.3x3D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L16.5x5D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ISL78235
FN8713 Rev 7.00 Page 3 of 24
Sep 28, 2018
Functional Block Diagram
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
PHASE
++
CSA
+
+
OCP
SKIP
+
+
+
Slope
COMP
SLOPE
Soft
START
SOFT-
EAMP
COMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
FB
+
0.85*VREF
PG
SYNC
SHUTDOWN
VIN
PGND
OSCILLATOR
ZERO-CROSS
SENSING
BANDGAP
SCP
+
0.5V
EN
SHUTDOWN
1ms
DELAY
55pF
100kΩ
SGND
3pF
6kΩ
-
--
-
-
-
-
VDD
COMP
100Ω
SHUTDOWN
LS
DRIVER
FS
ISET
THRESHOLD
VREF
+
NEG CURRENT
SENSING
P
N
+
0.8V
-
UV
OV
SS
ISL78235
FN8713 Rev 7.00 Page 4 of 24
Sep 28, 2018
Pin Configuration
ISL78235
(16 LD TQFN, WFQFN)
TOP VIEW
1
3
4
VIN
VDD
SYNC
VIN
PHASE
PHASE
COMP
2
7
56
FB
PGND
EN
FS
PG
SS
8
11
9
10
16 13
15 14
12
SGND
PGND
PHASE
EPAD
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1, 16 VIN Input supply voltage. Place a minimum of two 22µF low ESR ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
2 VDD Input supply voltage for the logic circuitry. A 0.1µF high frequency decoupling ceramic capacitor should also be
placed close to the VDD and SGND pin. Connect to the VIN pin.
3 PG PG is an open-drain output for power-good indication. Use a 10kΩ to 100kΩ pull-up resistor connected from PG to
VIN. At power-up or EN high, the PG rising edge is delayed by 1ms upon output voltage within regulation.
4 SYNC Mode selection pin. Connect to logic high or input voltage VIN for forced PWM mode. Connect to logic low or ground
for PFM mode. Connect to an external function generator for synchronization with a positive edge trigger. In external
synchronization the ISL78235 operates in forced PWM mode. The transition to and from the internal oscillator to
external synchronization is seamless and does not require disabling the ISL78235. An internal 1MΩ pull-down
resistor to SGND prevents an undefined logic state if the SYNC pin is floating.
5 EN Regulator enable pin. The regulator is enabled when driven logic high. The regulator is shut down and the PHASE
pin discharges the output capacitor when the enable pin is driven low.
6 FS This pin sets the internal oscillator switching frequency using a resistor, RFS, from the FS pin to GND. The frequency
of operation may be programmed between 500kHz to 4MHz. The switching frequency is 2MHz if FS is connected
to VIN.
7 SS SS is used to adjust the soft-start time. Connect the SS pin to SGND for an internal 1ms soft-start time. Connect a
capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF on the SS pin.
8 COMP COMP is the output of the error amplifier if COMP is not connected to VDD. An external compensation network must
be used if COMP is not tied to VDD. If COMP is tied to VDD, the error amplifier output is internally compensated.
External compensation network across COMP and SGND may be required to improve the loop compensation of the
amplifier.
9 FB The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage
can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. In addition,
the regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage.
10 SGND Signal ground. Connect to PGND.
11, 12 PGND Power ground.
13, 14, 15 PHASE Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω resistor
when the device is disabled. See “Functional Block Diagram” on page 3 for more detail.
Exposed Pad EPAD The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as
possible under the pad connecting to SGND plane for optimal thermal performance.
ISL78235
FN8713 Rev 7.00 Page 5 of 24
Sep 28, 2018
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
OUTPUT VOLTAGE
(V) TEMP. RANGE (°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL78235ARZ (Note 2) 8235 Adjustable -40°C to +105°C - 16 Ld 3x3mm TQFN L16.3x3D
ISL78235ARZ-T (Notes 1, 2) 8235 Adjustable -40°C to +105°C 6k 16 Ld 3x3mm TQFN L16.3x3D
ISL78235ARZ-T7A (Notes 1, 2) 8235 Adjustable -40°C to +105°C 250 16 Ld 3x3mm TQFN L16.3x3D
ISL78235AARZ (Note 3) 78235A ARZ Adjustable -40°C to +125°C - 16 Ld 5x5mm WFQFN L16.5x5D
ISL78235AARZ-T (Notes 1, 3) 78235A ARZ Adjustable -40°C to +125°C 6k 16 Ld 5x5mm WFQFN L16.5x5D
ISL78235AARZ-T7A (Notes 1, 3) 78235A ARZ Adjustable -40°C to +125°C 250 16 Ld 5x5mm WFQFN L16.5x5D
ISL78235EVAL1Z 3x3mm TQFN Evaluation Board
ISL78235EVAL2Z 5x5mm WFQFN Evaluation Board
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
4. For Moisture Sensitivity Level (MSL), refer to the ISL78235 product information page. For more information about MSL, refer to TB363.
TABLE 1. KEY DIFFERENCE BETWEEN FAMILY OF PARTS
PART NUMBER IOUT MAX (A)
ISL78235 5
ISL78234 4
ISL78233 3
ISL78235
FN8713 Rev 7.00 Page 6 of 24
Sep 28, 2018
Typical Application Diagram
FIGURE 4. TYPICAL APPLICATION DIAGRAM
9,1
9''
3*
6<1&
3*1'
)%
3*1'
6*1'
9287
&
[ȝ)
&
9,1
,6/
9729 9$
5
N
32:(5*22'
,1',&$725
N
5
5
N
/
[ȝ)
&
&,6237,21$/,7,6
5(&200(1'('72387$
3/$&(+2/'(5)25,7$1'&+(&.
/223$1$/<6,6%()25(86(
&(5$0,& &(5$0,&
ȝ+
(;7(51$/
6<1&+521,=$7,21
,1387
(1$%/(,1387
5)6 &66 5&203
&&203
9,1
3+$6(
3+$6(
3+$6(
&203
66
)6)6
(1
TABLE 2. COMPONENT SELECTION TABLE WITH INTERNAL COMPENSATION
VOUT 1.2V 1.5V 1.8V 2.5V 3.3V
C12 x 22µF 2 x 22µF 2 x 22µF 2x22µF 2 x 22µF
C2 (Note 5) 3 x 22µF 3 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF
C3 22pF 10pF 10pF 10pF 10pF
L1 0.33µH-0.68µH 0.33µH-0.68µH 0.33µH-0.68µH 0.47µH-0.78µH 0.47µH-0.78µH
R2 100kΩ150kΩ200kΩ316kΩ450kΩ
R3100kΩ100kΩ100kΩ100kΩ100kΩ
NOTE:
5. C2 values are minimum recommended values for ceramic capacitors. Higher capacitance may be needed based on system requirements.
ISL78235
FN8713 Rev 7.00 Page 7 of 24
Sep 28, 2018
Absolute Maximum Ratings (Reference to GND) Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per AEC-Q100-003). . . . . . . . . . . . . . . . . . 300V
Charge Device Model (Tested per AEC-Q100-011) . . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per AEC-Q100-004, Class II, Level A) . . . . . . . . . . 100mA
Thermal Resistance θJA (°C/W) θJC (°C/W)
16 Ld TQFN Package (Notes 6, 7) . . . . . . . 43 3.5
16 Ld WFQFN Package (Notes 6, 7) . . . . . 33 3.5
Operating Junction Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A
Ambient Temperature Range
3x3mm TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
5x5mm WFQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. Refer to
TB379.
7. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Specification limits are established at the following conditions: TA = -40°C to +105°C or TA = -40°C to +125°C
depending on package, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA= +25°C. Boldface limits apply across the operating
temperature range specified in the Recommended Operating Conditions table for the specified package.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNIT
INPUT SUPPLY
VIN Undervoltage Lockout Threshold VUVLO Rising, no load 2.5 2.7 V
Falling, no load 2.20 2.45 V
Quiescent Supply Current IVIN SYNC = GND, no load at the output 47 µA
SYNC = GND, no load at the output and no
switches switching
47 60 µA
SYNC = VIN, fSW = 2MHz, no load at the output 19 25 mA
Shutdown Supply Current ISD SYNC = GND, VIN = 5.5V, EN = low 4 10 µA
OUTPUT REGULATION
Reference Voltage VREF 0.594 0.600 0.606 V
VFB Bias Current IVFB VFB = 0.75V 0.1 µA
Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.2 %/V
Soft-Start Ramp Time Cycle SS = SGND 1 ms
Soft-Start Charging Current ISS VSS = 0.1V 1.7 2.1 2.5 µA
OVERCURRENT PROTECTION
Current Limit Blanking Time tOCON 17 Clock
pulses
Overcurrent and Auto Restart Period tOCOFF 8 SS cycle
Positive Peak Current Limit IPLIMIT TA = +25°C 6.2 7.8 9.4 A
TA = -40°C to +105°C 6.1 11.0 A
5x5 mm WFQFN package
TA = +105°C to +125°C
12.5 A
Peak Skip Limit ISKIP TA = +25°C 0.85 1.10 1.40 A
TA = -40°C to +105°C 0.83 1.60 A
5x5 mm WFQFN package
TA = +105°C to +125°C
1.65 A
ISL78235
FN8713 Rev 7.00 Page 8 of 24
Sep 28, 2018
Zero Cross Threshold -275 375 mA
Negative Current Limit INLIMIT TA = +25°C -5.1 -2.8 -1.3 A
-6.0 -0.6 A
COMPENSATION
Error Amplifier Transconductance COMP = VDD, internal compensation 125 µA/V
External compensation 130 µA/V
Transresistance RT TA = -40°C to +105°C 0.11 0.17 0.22 Ω
5x5 mm WFQFN package
TA = +105°C to +125°C
0.1 Ω
MOSFET
P-Channel ON-Resistance VIN = 5V, IO = 200mA 26 35 50 mΩ
VIN = 2.7V, IO = 200mA 38 52 78 mΩ
N-Channel ON-Resistance VIN = 5V, IO = 200mA 511 20 mΩ
VIN = 2.7V, IO = 200mA 815 31 mΩ
PHASE
PHASE Maximum Duty Cycle 100 %
PHASE Minimum On-Time SYNC = High 100 ns
OSCILLATOR
Nominal Switching Frequency fSW FS = VIN 1730 2000 2350 kHz
FS with RS = 402kΩ420 kHz
FS with RS = 42.2kΩ4200 kHz
SYNC Logic LOW to HIGH Threshold 0.67 0.75 0.84 V
SYNC Logic Hysteresis 0.10 0.17 0.20 V
SYNC Logic Input Leakage Current SYNC = 3.6V 3.7 5.0 µA
POWER-GOOD (PG)
Output Low Voltage IPG = 1mA 0.3 V
PG Delay Time (Rising Edge) Time from VOUT reached regulation 0.5 1.0 2.0 ms
PG Delay Time (Falling Edge) 6.5 µs
PG Pin Leakage Current PG = VIN 0.01 0.10 µA
OVP PG Rising Threshold 0.80 V
UVP PG Rising Threshold 80 85 90 %
UVP PG Hysteresis 5.5 %
EN
Logic Input Low (Note 9)EN_VIL 0.4 V
Logic Input High EN_VIH 0.9 V
EN Logic Input Leakage Current EN = 3.6V 0.1 1.0 µA
OVER-TEMPERATURE PROTECTION
Thermal Shutdown Temperature rising 150 °C
Thermal Shutdown Hysteresis Temperature falling 25 °C
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
9. EN should be held below the EN_VIL until VIN exceeds VUVLO rising.
Electrical Specifications Specification limits are established at the following conditions: TA = -40°C to +105°C or TA = -40°C to +125°C
depending on package, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA= +25°C. Boldface limits apply across the operating
temperature range specified in the Recommended Operating Conditions table for the specified package. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8)TYP
MAX
(Note 8)UNIT
ISL78235
FN8713 Rev 7.00 Page 9 of 24
Sep 28, 2018
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A.
FIGURE 5. EFFICIENCY vs LOAD (3.3VIN; SYNC = VDD)FIGURE 6. EFFICIENCY vs LOAD (3.3VIN; SYNC = GND)
FIGURE 7. EFFICIENCY vs LOAD (
5V
IN
; SYNC = VDD
)
FIGURE 8. EFFICIENCY vs LOAD (
5V
IN
; SYNC = GND)
FIGURE 9. POWER DISSIPATION vs LOAD (
3.3V
IN
; SYNC = VDD
)
FIGURE 10. POWER DISSIPATION vs LOAD (
5V
IN
; SYNC = VDD
)
40
50
60
70
80
90
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
4.5 5.0
1.2VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.0VOUT
40
50
60
70
80
90
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT LOAD (A)
EFFICIENCY (%)
0.9VOUT
1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
40
50
60
70
80
90
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
4.5 5.0
1.2VOUT
1.5VOUT
3.3VOUT
2.5VOUT
1.8VOUT
40
50
60
70
80
90
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
EFFICIENCY (%)
4.5 5.0
3.3VOUT 1.2VOUT
1.5VOUT
1.8VOUT
2.5VOUT
0
0.5
1.0
1.5
2.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
POWER DISSIPATION (W)
4.5 5.0
2.5
1.8VOUT
2.5VOUT
1.0VOUT
1.2VOUT
0
0.5
1.0
1.5
2.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
POWER DISSIPATION (W)
4.5 5.0
2.5
1.2VOUT
1.8VOUT
2.5VOUT
3.3VOUT
ISL78235
FN8713 Rev 7.00 Page 10 of 24
Sep 28, 2018
FIGURE 11. VOUT REGULATION vs LOAD (VOUT = 1.2V) FIGURE 12. VOUT REGULATION vs LOAD (VOUT = 1.8V)
FIGURE 13. VOUT REGULATION vs LOAD (VOUT =1.0V) FIGURE 14. PHASE MINIMUM ON-TIME vs VIN
FIGURE 15. EN START-UP AT NO LOAD (SYNC = GND) FIGURE 16. EN START-UP AT NO LOAD (SYNC = VDD)
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
1.179
1.184
1.194
1.199
1.204
1.209
1.214
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
4.5 5.0
1.219
1.189
3.3V PWM
5V PFM
5V PWM
3.3V PFM
1.770
1.775
1.785
1.790
1.795
1.800
1.805
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
4.5 5.0
1.810
1.780
OUTPUT VOLTAGE (V)
5V PWM
3.3V PWM
5V PFM
3.3V PFM
0.980
0.985
0.995
1.000
1.005
1.010
1.015
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
4.5 5.0
1.020
0.990
3.3V PFM
3.3V PWM
50
55
60
65
70
75
3.0 3.5 4.0 4.5 5.0 5.5
V
IN
(V)
PHASE MINIMUM ON-TIME (ns)
T = +25°C
T = -40°C
T = +125°C
PHASE 5V/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
ISL78235
FN8713 Rev 7.00 Page 11 of 24
Sep 28, 2018
FIGURE 17. VIN START-UP AT NO LOAD (SYNC = GND) FIGURE 18. VIN START-UP AT NO LOAD (SYNC = VDD)
FIGURE 19. EN SHUTDOWN AT NO LOAD (SYNC = GND) FIGURE 20. EN SHUTDOWN AT NO LOAD (SYNC = VDD)
FIGURE 21. VIN SHUTDOWN AT NO LOAD (SYNC = GND) FIGURE 22. VIN SHUTDOWN AT NO LOAD (SYNC = VDD)
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
PHASE 5V/DIV
VIN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
VIN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
1ms/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
1ms/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
VIN 2V/DIV
PG 2V/DIV
VOUT 1V/DIV
2ms/DIV
SS = GND
COUT = 4 x 22µF
PHASE 5V/DIV
VIN 2V/DIV
PG 2V/DIV
VOUT 1V/DIV
2ms/DIV
SS = GND
COUT = 4 x 22µF
ISL78235
FN8713 Rev 7.00 Page 12 of 24
Sep 28, 2018
FIGURE 23. EN START-UP AT 5A LOAD (SYNC = GND) FIGURE 24. EN START-UP AT 5A LOAD (SYNC = VDD)
FIGURE 25. VIN START-UP AT 5A LOAD (SYNC = GND) FIGURE 26. VIN START-UP AT 5A LOAD (SYNC = VDD)
FIGURE 27. EN SHUTDOWN AT 5A LOAD (SYNC = GND) FIGURE 28. EN SHUTDOWN AT 5A LOAD (SYNC = VDD)
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
IOUT 5A/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
IOUT 5A/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
IOUT 5A/DIV
VIN 5V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
IOUT 5A/DIV
VIN 5V/DIV
PG 5V/DIV
VOUT 1V/DIV
500µs/DIV
SS = GND
COUT = 4 x 22µF
IOUT 5A/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
100µs/DIV
SS = GND
COUT = 4 x 22µF
IOUT 5A/DIV
EN 2V/DIV
PG 5V/DIV
VOUT 1V/DIV
100µs/DIV
SS = GND
COUT = 4 x 22µF
ISL78235
FN8713 Rev 7.00 Page 13 of 24
Sep 28, 2018
FIGURE 29. JITTER AT NO LOAD (SYNC = VDD) FIGURE 30. JITTER AT 5A LOAD (SYNC = VDD)
FIGURE 31. STEADY STATE AT NO LOAD (SYNC = GND) FIGURE 32. STEADY STATE AT NO LOAD (SYNC = VDD)
FIGURE 33. STEADY STATE AT 5A (SYNC = VDD)
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
5ns/DIV
PHASE 1V/DIV
5ns/DIV
PHASE 1V/DIV
PHASE 5V/DIV
I_PHASE 1A/DIV AC
VOUT 20mV/DIV AC
20ms/DIV
COUT = 4 x 22µF
PHASE 5V/DIV
I_PHASE 1A/DIV AC
VOUT 20mV/DIV AC
200ns/DIV
COUT = 4 x 22µF
PHASE 5V/DIV
I_PHASE 1A/DIV AC
VOUT 20mV/DIV AC
200ns/DIV
COUT = 4 x 22µF
ISL78235
FN8713 Rev 7.00 Page 14 of 24
Sep 28, 2018
FIGURE 34. LOAD TRANSIENT 0A TO 5A; 0.5A/µs (SYNC = GND) FIGURE 35. LOAD TRANSIENT 0A TO 5A; 0.5A/µs (SYNC = VDD)
FIGURE 36. OUTPUT SHORT-CIRCUIT FIGURE 37. OUTPUT SHORT-CIRCUIT RECOVERY TO 1A LOAD
FIGURE 38. SHORT-CIRCUIT HICCUP WAVEFORM FIGURE 39. OVERCURRENT PROTECTION
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
I_LOAD 2A/DIV
VOUT 100mV/DIV AC
500µs/DIV
RCOMP = 154kΩ
CCOMP = 220pF
COUT = 4 x 22µF
500µs/DIV
RCOMP = 154kΩ
CCOMP = 220pF
I_LOAD 2A/DIV
VOUT 100mV/DIV AC COUT = 4 x 22µF
VOUT
PHASE
I_PHASE
PG
VOUT
PHASE
I_PHASE
PG
VOUT
SS
I_PHASE
I_LOAD
CSS = 33nF
VOUT
PHASE
I_PHASE
PG
LOAD = 4A TO 8A STEP
ISL78235
FN8713 Rev 7.00 Page 15 of 24
Sep 28, 2018
FIGURE 40. OVERVOLTAGE PROTECTION FIGURE 41. OVERVOLTAGE RECOVERY
FIGURE 42. OVER-TEMPERATURE PROTECTION FIGURE 43. OVER-TEMPERATURE RECOVERY
Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN =V
DD = 5V,
VOUT =1.8V, EN=V
DD, SYNC = VDD, L = 0.68µH, fSW = 2MHz, CIN = 2 x 22µF, COUT = 2 x 22µF, IOUT = 0A to 5A. (Continued)
VOUT
PHASE
I_PHASE
PG
VOUT INTO 3V SUPPLY
VOUT
PHASE
I_PHASE
PG
VOUT FROM 3V SUPPLY
VOUT
PG
V_TEMP
+125°C TO +170°C TRANSIENT
LOAD = 4A
TEMP = (V_TEMP-1.1092)/4.1mV
VOUT
PG
V_TEMP
+125°C TO +170°C TRANSIENT
LOAD = 4A
TEMP = (V_TEMP-1.1092)/4.1mV
ISL78235
FN8713 Rev 7.00 Page 16 of 24
Sep 28, 2018
Theory of Operation
The ISL78235 is a step-down switching regulator optimized for
automotive point-of-load powered applications. The regulator
operates at a 2MHz default switching frequency for high
efficiency and smaller form factor while staying out of the AM
frequency band. By connecting a resistor from FS to SGND, the
operational frequency is adjustable in the range of 500kHz to
4MHz. At light load, the regulator reduces the switching
frequency by operating in Pulse Frequency Modulation (PFM)
mode, unless forced to operate in fixed frequency PWM mode, to
minimize the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically only
45µA. The supply current is typically only 3.8µA when the
regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current, bypassing the PFM operation
at light load. The ISL78235 uses the current-mode Pulse-Width
Modulation (PWM) control scheme for fast transient response
and pulse-by-pulse current limiting (see Figure 3 on page 3). The
current loop consists of the oscillator, the PWM comparator,
current-sensing circuit, and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts (Ts is
the switching period), which changes proportionally with
frequency. The gain for the
current-sensing circuit is typically 170mV/A. The control
reference for the current loops comes from the Error Amplifier's
(EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
PFET and turn on the N-channel MOSFET. The NFET stays on until
the end of the PWM cycle. Figure 44 shows the typical operating
waveforms during the PWM operation. The dotted lines on VCSA
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and is discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.5V.
Skip Mode (PFM)
Pulling the SYNC pin low (<0.4V), forces the converter into PFM
mode. The ISL78235 enters a pulse-skipping mode at light load
to minimize the switching loss by reducing the switching
frequency. Figure 45 on page 17 illustrates Skip mode operation.
A zero-cross sensing circuit shown in Figure 3 on page 3 monitors
the NFET current for zero crossing. When 16 consecutive cycles
are detected, the regulator enters Skip mode. During the
16 detecting cycles, the current in the inductor is allowed to
become negative. The counter is reset to zero when the current in
any cycle does not cross zero.
When Skip mode is entered, the pulse modulation starts being
controlled by the Skip comparator shown in Figure 3 on page 3.
Each pulse cycle is still synchronized by the PWM clock. The PFET
is turned on at the clock's rising edge and turned off when the
output is higher than 1.2% of the nominal regulation or when its
current reaches the peak skip current limit value. Then, the
inductor current discharges to 0A and stays at zero (the internal
clock is disabled), and the output voltage reduces gradually due
to the load current discharging the output capacitor. When the
output voltage drops to the nominal voltage, the PFET is turned
on again at the rising edge of the internal clock as it repeats the
previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.2% below the nominal voltage.
FIGURE 44. PWM OPERATION WAVEFORMS
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
ISL78235
FN8713 Rev 7.00 Page 17 of 24
Sep 28, 2018
Frequency Adjust
The frequency of operation is fixed at 2MHz when FS is tied to VIN.
The switching frequency is adjustable in the range from 500kHz to
4MHz with a resistor from FS to SGND according to Equation 1:
Connect the SYNC pin to an external square pulse waveform to
enable the ISL78235’s frequency synchronization capability. The
frequency synchronization feature synchronizes the positive edge
trigger and its switching frequency up to 4MHz. The
synchronization positive pulse width should be 100ns or greater
for proper operation. The minimum external SYNC frequency is
half of the free running oscillator frequency (either the default
2MHz when FS is tied to VIN or determined by the resistor from
FS to SGND).
Overcurrent Protection
The overcurrent protection is enabled by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 3.
The current-sensing circuit has a gain of 170mV/A typical, from
the PFET current to the CSA output. When the CSA output reaches
the threshold, the OCP comparator is tripped to turn off the PFET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
When an overcurrent condition is detected, the upper MOSFET is
immediately turned off and is not turned on again until the next
switching cycle. When the initial overcurrent condition is
detected, the overcurrent fault counter is set to 1. The OC fault
counter is incremented if another overcurrent condition is
detected on the subsequent cycle. If 17 sequential OC fault
detections occur, the regulator is shut down under an overcurrent
fault condition. An overcurrent fault condition causes the
regulator to attempt to restart in hiccup mode within the delay of
eight soft-start periods. At the end of the eighth soft-start wait
period, the fault counters are reset and soft-start is attempted
again. If the overcurrent condition stops during the delay of
eight soft-start periods, the output will resume back into the
regulation point after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is enabled
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 3. When the valley point of the inductor current
reaches -3A for four consecutive cycles, both PFET and NFET are
off. A 100Ω discharge circuit in parallel to the NFET activates to
discharge the output into regulation. The regulator resumes
switching operation when the output is within regulation. The
regulator will be in PFM for 20µs before switching to PWM if
necessary.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. PG is a 1ms delay after the soft-start period that
becomes high impedance as long as the output voltage is within the
nominal regulation voltage set by VFB. When the voltage at the FB
pin drops 15% below 0.6V or rises above 0.8V, the ISL78235 pulls
PG low. Any fault condition forces PG low until the fault condition is
cleared and after soft-start completes. For logic level output
voltages, connect an external pull-up resistor between PG and VIN.
A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold (2.5V typical), the regulator is disabled.
Soft Start-Up
The soft start-up circuit reduces the inrush current during
power- up. The soft-start block outputs a ramp reference to the
input of the error amplifier. This voltage ramp limits the slew rate
of inductor current as well as the output voltage, so that the
output voltage rises in a controlled fashion. When VFB is less
than 0.1V at the beginning of the soft-start, the switching
frequency is reduced to 200kHz, so that the output can start-up
smoothly at light load condition. During soft-start, the IC operates
in Skip mode to support prebiased output conditions.
FIGURE 45. SKIP MODE OPERATION WAVEFORMS
CLOCK
IL
VOUT
NOMINAL +1.2%
NOMINAL
PFM CURRENT LIMIT
0
16 CYCLES
PWM PFM
NOMINAL -1.2%
PWM
LOAD CURRENT
RFS kΩ[] 220 103
⋅
fOSC kHz[]
------------------------------ 14–= (EQ. 1)
ISL78235
FN8713 Rev 7.00 Page 18 of 24
Sep 28, 2018
Tie SS to SGND for internal soft-start (1ms typical). Connect a
capacitor from SS to SGND to adjust the soft-start time. This
capacitor, along with an internal 2.1µA current source, sets the
soft-start interval of the converter, tSS, as shown by Equation 2.
CSS must be less than 33nF to ensure proper soft-start reset
after fault condition.
Enable
The Enable (EN) input allows the user to turn the regulator on or
off for purposes such as power-up sequencing or minimizing
power dissipation when the output is not needed. When the
regulator is enabled, a typical 600µs delay occurs for waking up
the bandgap reference, then the soft start-up begins. EN should
be held below the EN_VIL until VIN exceeds VUVLO rising.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, (EN low or fault
condition) or the VIN UVLO is set, the output is discharged to GND
through an internal 100Ω switch on the PHASE pin.
Power MOSFETs
The power MOSFETs are optimized for highest efficiency. The
ON-resistance for the PFET is typically 35mΩ and the
ON-resistance for the NFET is typically 11mΩ.
100% Duty Cycle
The ISL78235 features a 100% duty cycle operation to maximize
the battery operation life and provide very low dropout down to
the minimum operating voltage. When the battery voltage drops
to a level that the ISL78235 can no longer maintain the
regulation at the output, the regulator completely turns on the
PFET. The maximum dropout voltage under the 100% duty cycle
operation is the product of the load current and the
ON-resistance of the PFET.
Thermal Shutdown
The ISL78235 has built-in over-temperature thermal protection.
When the internal temperature reaches +150°C, the regulator
completely shuts down. As the temperature drops to +125°C, the
ISL78235 resumes operation after a soft-start cycle.
Applications Information
Output Inductor and Capacitor Selection
The ISL78235 typically uses a 0.33µH to 0.78µH output inductor
for steady state and transient operation. Higher or lower inductor
values can be used to optimize the total converter system
performance. For example, the output inductor value can be
increased for a higher output voltage 3.3V application in order to
decrease the inductor current ripple and output voltage ripple.
Set the ripple inductor current to approximately 30% of the
maximum output current for optimized performance. The
inductor ripple current can be expressed as shown in Equation 3:
The inductor’s saturation current rating must be larger than the
positive peak current limit specified on page 7 of the Electrical
Specifications table. The ISL78235 has a typical peak current
limit of 7.5A. The inductor saturation current must be over 7.5A
for proper operation.
The ISL78235 uses an internal compensation network for
regulator stability and the output capacitor value is dependent on
the output voltage. The recommended ceramic capacitors are
low ESR X7R rated or better. The recommended minimum output
capacitor values are shown in Table 2 on page 6.
Table 2 shows that the minimum output capacitor value is given
for the different output voltages to ensure that the whole
converter system is stable. Additional output capacitance should
be added for better performance in applications in which high
load transient or low output ripple is required. Renesas
recommends checking the system level performance along with
the simulation model.
Output Voltage Selection
The output voltage of the regulator is programmed with an external
resistor divider that scales the output voltage relative to the internal
reference voltage (0.6V) and is fed back to the inverting input of the
error amplifier FB pin (see Figure 46).
The output voltage programming resistor R2 (from VOUT to FB)
depends on the value chosen for the feedback resistor and the
desired output voltage of the regulator. The value for the
feedback resistor, R3 (from FB to GND), is typically between
10kΩ and 100kΩ. R2 is chosen as shown in Equation 4, where
VFB = 0.6V and VOUT is the output voltage.
CSS μF[] 3.1 tSS s[]⋅=(EQ. 2)
ΔI
VOUT 1
VOUT
VIN
----------------
–



•
Lf
SW
•
-----------------------------------------------------
=
(EQ. 3)
FIGURE 46. PROGRAMMING OUTPUT VOLTAGE WITH R2 AND R3
1
3
4
VIN
VDD
SYNC
VIN
PHASE
PHASE
COMP
2
7
56
FB
PGND
EN
FS
PG
SS
8
11
9
10
16 13
15 14
12
SGND
PGND
PHASE
V
OUT
ISL78235
R
2
V
IN
R
3
R2R3
VOUT
VFB
----------------1–


=(EQ. 4)
ISL78235
FN8713 Rev 7.00 Page 19 of 24
Sep 28, 2018
There is a leakage current from VIN to PHASE. Renesas
recommends preloading the output with 10µA minimum for
accurate output voltage. For improved loop stability
performance, add 10pF to 22pF in parallel with R2. Check loop
analysis before use in an application. See “Loop Compensation
Design” for more information.
Input Capacitor Selection
The main functions for the input capacitor are decoupling the
parasitic inductance and providing a filtering function to prevent
the switching current flowing back to the input rail. Place two
22µF low ESR X7R rated ceramic capacitors in parallel with a
0.1µF high frequency decoupling capacitor very close to the
VIN/VDD and SGND/PGND pins.
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL78235 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current-sensing circuit
in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered a state variable because its peak current is constant
and the system becomes a single order system. It is much easier
to design a type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 47 shows the small signal model of the
synchronous buck regulator.
Figure 48 shows the type II compensator and its transfer function
is expressed as Equation 5:
where
Compensator design goal:
High DC gain
Choose Loop bandwidth fc ~100kHz or less
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 6.
where GM is the transconductance, gm, of the voltage error
amplifier and Rt is the gain of the current sense amplifier.
Compensator capacitors C6 and C7 are given by Equation 7.
Set one compensator pole at zero frequency to achieve high DC
gain, and set another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. ωCZ2 is
a zero due to R2 and C3.
Set compensator zero 2 to 5 times fc:
dVin
dIL
in
in
iL
+
1:D
+
L
i
Co
Rc
-Av(S)
d
comp
v
RT
Fm
He(S)
+
Ti(S)
K
o
v
Tv(S)
I
LP
+
1:D
+
Rc
Ro
-Av(S)
RT
Fm
He(S)
Ti(S)
K
o
T(S)
^^
V^^
^
^
^
^
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
RLP
GAIN (VLOOP (S(fi))
-
+
R6
VREF
VFB
Vo
GM
VCOMP
C7
-
+
C6
REF
FB
Vo
FIGURE 48. TYPE II COMPENSATOR
C3
R2
R3
AvS()
v
ˆcomp
v
ˆFB
-----------------GM R3
⋅
C6C7
+()R2R3
+()⋅
--------------------------------------------------------
1S
ωcz1
-------------
+


1S
ωcz2
-------------
+


S1 S
ωcp1
-------------
+


1S
ωcp2
-------------
+


---------------------------------------------------------------
== (EQ. 5)
ωcz1
1
R6C6
---------------ωcz2
1
R2C3
---------------
=ωcp1
,
C6C7
+
R6C6C7
-----------------------ωcp2
R2R3
+
C3R2R3
-----------------------
=,=,=
R6
2πfcVoCoRt
GM VFB
⋅
----------------------------------13.7 3
×10 fcVoCo
⋅== (EQ. 6)
C6
RoCo
R6
---------------VoCo
IoR6
---------------C7max RcCo
R6
---------------1
πfsR6
----------------(, )=,== (EQ. 7)
C3
1
πfcR2
----------------
=(EQ. 8)
ISL78235
FN8713 Rev 7.00 Page 20 of 24
Sep 28, 2018
Example: VIN = 5V, VO = 1.8V, IO = 5A, fSW = 2MHz, R2 = 200kΩ,
R3 = 100kΩ, Co= 2 x22µF/10mΩ, L = 0.68µH, fc = 100kHz, then
compensator resistance R6:
It is acceptable to use 107kΩ as the closest standard value for
R6.
It is also acceptable to use the closest standard values for C6 and
C7
. There is approximately 3pF parasitic capacitance from VCOMP to
GND. Therefore, C7 is optional. Use C6 = 150pF and C7 = OPEN.
Use C3 = 10pF. Note that C3 may increase the loop bandwidth
from the previous estimated value. Figure 49 shows the
simulated voltage loop gain. It has a 120kHz loop bandwidth
with a 58° phase margin and 8dB gain margin. It may be more
desirable to achieve an increased phase and gain margin. This
can be accomplished by lowering R6 by 10% to 20%.
PCB Layout Recommendation
Proper PCB layout is a very important converter design step to
ensure the designed converter works well. The ISL78235 power
loop is composed of the output inductor L0, the output capacitor
CO, the PHASE pins, and the PGND pin. Make the power loop as
small as possible. The connecting traces among them should be
direct, short, and wide. The switching node of the converter, the
PHASE pins, and the traces connected to the node are very noisy,
so keep the voltage feedback trace away from these noisy traces.
Place the input capacitor as close as possible to the VIN pin. The
ground of the input and output capacitors should be connected
as close as possible. The IC heat is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. Refer to TB389 for
information about via placement on the copper area of the PCB
underneath the thermal pad for optimum thermal performance.
R613.7 3
×10 100kHz 1.8V 44μF⋅⋅⋅ 108kΩ==
(EQ. 9)
C6
1.8V 44⋅μF
5A 107kΩ⋅
--------------------------------148pF== (EQ. 10)
C7max 10mΩ44μF⋅
107kΩ
------------------------------------1
π2MHz 107kΩ()⋅
------------------------------------------------(, )4.1pF 1.5pF(,)== (EQ. 11)
C3
1
π100kHz 200kΩ⋅
------------------------------------------------
=16pF=(EQ. 12)
FIGURE 49. SIMULATED LOOP GAIN AND PHASE
60
40
20
0
-20
-40
-60
100 1k 10k 100k 1M
FREQUENCY (Hz)
150
100
50
0
-50
-100
-150
100 1k 10k 100k 1M
FREQUENCY (Hz)
CLOSED LOOP PHAE (°) CLOSED LOOP GAIN (dB)
200
ISL78235
FN8713 Rev 7.00 Page 21 of 24
Sep 28, 2018
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE REVISION CHANGE
Sep 28, 2018 FN8713.7 Updated Related Literature Section
Updated the Ordering Information table on page 5.
Added Note 9 on page 8.
Added specification symbols for the Logic Input Low and Logic Input High specifications on page 8.
Added information about EN_VIL to the “Enable” section on page 18.
Removed About Intersil section and updated disclaimer.
Sep 22, 2016 FN8713.6 Corrected shifted connection in Block Diagram on page 3.
Apr 1, 2016 FN8713.5 Updated Figure 10 title on page 9.
Dec 11, 2015 FN8713.4 Added a new User Guide to Related Literature section on page 1.
Added ISL78235EVAL2Z to the ordering information table on page 5.
Added table1 on page 5.
Nov 10, 2015 FN8713.3 Added 5x5mmWFQFN information throughout datasheet.
Removed “Li-Ion Battery Powered devices” application bullet from page 1.
Updated Note 1 on page 5 from “Add “-T*” suffix for tape and reel.” to “Add “-T” suffix for 6k unit or “-T7A” suffix
for 250 unit tape and reel options.”
On page 8, removed the test condition “TA = -40°C to +105°C” for the INLIMIT specifications.
On page 8, added “TA = -40°C to +105°C to the test conditions of the Transresistance specification.”
In “PWM Control Scheme” on page 16 (last sentence) corrected a typo by changing “1.6V to “2.5V”.
Updated the “PCB Layout Recommendation” section.
Jul 1, 2015 FN8713.2 Figures 15 through 28 changed “CSS = 33nF” to “SS = GND”.
Feb 20, 2015 FN8713.1 Electrical Spec table, Oscillator section on page 8:
Changed nominal switching frequency minimum from 1700kHz to 1730kHz.
Feb 3, 2015 FN8713.0 Initial Release
ISL78235
FN8713 Rev 7.00 Page 22 of 24
Sep 28, 2018
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance: Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.25mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(4X) 0.15
INDEX AREA
PIN 1
A
3.00
B
3.00
PIN #1
B0.10 M AC
4
6
6
±0.05
1
12
4
9
13 16
85
1.60 SQ
16X 0.23
16X 0.40±0.10
4X 1.50
12X 0.50
(16X 0.60)
( 1.60)(2.80 TYP)
(16X 0.23)
(12X 0.50)
C0 . 2 REF
0 . 05 MAX.
0 . 02 NOM.
5
0.75 ±0.05
0.08
0.10 C
C
C
INDEX AREA
SEE DETAIL “X”
JEDEC reference drawing: MO-220 WEED.
7.
For the most recent package outline drawing, see L16.3x3D.
ISL78235
FN8713 Rev 7.00 Page 23 of 24
Sep 28, 2018
Package Outline Drawing
L16.5x5D
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN WITH WETTABLE FLANK)
Rev 2, 5/14
For the most recent package outline drawing, see L16.5x5D.
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
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