General Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B low-
quiescent-current, low-dropout (LDO) regulators contain
simple boost preregulators operating at a high frequency.
The devices seamlessly provide a preset 3.3V
(MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B)
LDO output voltage from an automotive cold-crank
through load-dump (3.5V to 80V) input voltage condi-
tions. The MAX5092_/MAX5093_ deliver up to 250mA
with excellent load and line regulation. During normal
operation, when the battery is healthy, the boost preregu-
lator is completely turned off, reducing quiescent current
to 65µA (typ). This makes the devices suitable for
always-on power supplies.
The buck-boost operation achieved by this combination
of LDO and boost preregulator offers the advantage of
using a single off-the-shelf inductor in place of the mul-
tiple-winding custom magnetics needed in typical sin-
gle-ended primary inductor converter (SEPIC) and
transformer-based flyback topologies. The high operat-
ing frequency of the boost regulator significantly
reduces component size. The MAX5092_ integrates a
blocking diode to further reduce the external compo-
nent count. The boost preregulator output voltage is
preset to 7V. Both LDO and boost output voltages are
programmable using external resistors. The boost pre-
regulator output voltage is adjustable up to 11V
(MAX5092_), or up to 12V (MAX5093_). The LDO output
voltage is adjustable from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_).
The devices feature a shutdown mode with 5µA (typ)
shutdown current, a HOLD input to implement a self-hold-
ing circuit, and a power-on-reset output (RESET) with an
externally programmable timeout period. Additional fea-
tures include output overload, short-circuit, and thermal
protection.
The MAX5092_/MAX5093_ are available in a thermally
enhanced, 16-pin 5mm x 5mm thin QFN package and
can dissipate up to 2.7W at +70°C on a multilayer PC
board (PCB).
Applications
Automotive—Body Electronics
Automotive—ECU
Industrial
Features
oWide Operating Input Voltage Range: 3.5V to 72V
with a 4V Startup Voltage
oLDO Output Regulates to 5V Seamlessly from an
Input Voltage of 3.5V to 72V
oUp to 250mA Output Current
oPreset 3.3V, 5V, or Externally Programmable LDO
Output Voltage from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_)
oPreset 7V or Externally Programmable Boost
Output Voltage Up to 11V (MAX5092_) or Up to
12V (MAX5093_)
o65µA Quiescent Current in LDO Mode (VIN ≥8V)
o5µA Shutdown Current
oPower-On Reset (RESET) with Programmable
Timeout Period
oOutput Short-Circuit and Thermal Protection
oTQFN Package Capable of Dissipating Up to 2.7W
at +70°C
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
________________________________________________________________
Maxim Integrated Products
1
15
16
14
13
6
5
7
EN
HOLD
8
IN
LX
BSOUT
PGND_BST
1
+
2
VL
4
12 11 9
CT
RESET
OUT
OUT_SENSE
SET
PGND_LDO
MAX5092_/
MAX5093_
SGND LX
3
10
BSFB
THIN QFN
(5mm x 5mm)
TOP VIEW
PART TEMP RANGE PIN-
PACKAGE
PKG
CODE
MAX5092AATE+ -40°C to +125°C 16 TQFN-EP* T1655-3
MAX5092BATE+ -40°C to +125°C 16 TQFN-EP* T1655-3
MAX5093AATE+ -40°C to +125°C 16 TQFN-EP* T1655-3
MAX5093BATE+ -40°C to +125°C 16 TQFN-EP* T1655-3
Pin Configuration
Ordering Information
19-0659; Rev 1; 1/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes lead-free package.
*
EP = Exposed pad.
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
EVALUATION KIT
AVAILABLE
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: As per JEDEC Standard 51 (Multilayer Board).
IN, EN, LX, BSOUT to SGND..................................-0.3V to +80V
PGND_BST, PGND_LDO to SGND .......................-0.3V to +0.3V
RESET, OUT, OUT_SENSE to SGND .....................-0.3V to +12V
BSOUT to LX (MAX5092_)......................................-0.3V to +12V
VL, SET, BSFB, SGND..............................................-0.3V to +6V
HOLD to SGND….....................................-0.3V to (VOUT + 0.3V)
CT to SGND.................................................-0.3V to (VVL + 0.3V)
OUT Current (IOUT) Short Circuit to PGND_LDO,
(VIN ≤28V) ..............................................................Continuous
RESET Sinking Current .........................................................5mA
Continuous Power Dissipation (TA= +70°C)
16-Pin Thin QFN (derate 33.3mW/°C
above +70°C)...............................................2666mW (Note 1)
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY
Input Voltage Range VIN (Note 3) 4 72 V
VUVLOF VIN falling 3.0 3.2 3.4
Internal Input Undervoltage
Lockout VUVLOR VIN rising 3.4 3.6 3.8 V
LDO mode,
IOUT = 100µA
TJ = -40°C to +125°C
(Note 4) 65 85
Supply Current (Boost Converter
Off) IQ
LDO mode, IOUT = 250mA 70 100
µA
Supply Current (Boost Converter
On) ISVIN = 5V 0.4 1.0 mA
Shutdown Supply Current ISHDN VEN ≤ +0.4V TJ = -40°C to +125°C
(Note 4) 610µA
BOOST CONVERTER
Minimum BSOUT Output Current IBSOUT VIN = 4V 250 mA
Boost Converter Enable
Threshold VBST_EN VBSOUT – VOUT falling (Note 5) 1.7 2.0 2.3 V
Boost Converter Disable
Threshold VBST_DIS VBSOUT – VOUT rising (Note 5) 2.2 2.5 2.8 V
Boost Converter Disable
Hysteresis VBST_HYS 0.5 V
BSOUT Output Voltage VBSOUT VIN = 4V, BSFB = SGND, VOUT = 5V 7.00 V
MAX5092_ 11
Maximum BSOUT Output Voltage VBSOUT
(
MAX
)
MAX5093_ 12 V
BSFB Regulation Voltage VBSFB 1.18 1.24 1.30 V
BSFB Input Bias Current IBSFB 100 nA
Boost Internal Switch
On-Resistance RDS(ON) 0.5 1.2 Ω
Boost Internal Switch Minimum
Off-Time tOFF 0.80 1 1.25 µs
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Boost Internal Switch Maximum
On-Time tON-MAX 1.80 2.25 2.70 µs
Internal Switch Current Limit ILIM Measured in steady-state condition 1.5 3.0 A
Boost Turn-On Response Time Time from VBSOUT falling below regulation
to switch on-time 25µs
Internal Diode Forward Voltage
Drop VFMAX5092_ only, IF = 1A 0.95 V
LDO
Guaranteed Output Current IOUT VBSOUT - VOUT = 2V (Note 6) 250 mA
IOUT = 1mA 3.25 3.3 3.35
SET = SGND,
MAX5092A/
MAX5093A 100µA ≤ IOUT ≤ 250mA 3.2 3.3 3.4
IOUT = 1mA 4.900 5 5.075
Output Voltage VOUT
SET = SGND,
MAX5092B/
MAX5093B 100µA ≤ IOUT ≤ 250mA 4.85 5 5.10
V
Minimum Adjustable Output
Voltage VADJMIN Boost operation, VIN = 4V, VBSOUT = 7V 1.5 V
MAX5092_,
VBSOUT = 11V 9
Maximum Adjustable Output
Voltage VADJMAX Boost operation,
VIN = 4V MAX5093_,
VBSOUT = 12V 10
V
Adjustable Output Voltage VADJ LDO operation, VIN ≥ VBST_DIS
(boost converter off) (Note 7) 1.5 10.0 V
Dropout Voltage ΔVDO IOUT = 250mA (Note 8) 0.9 1.6 V
LDO Startup Response Time Rising edge of VBSOUT to the rising edge of
VOUT, RL = 500Ω, SET = SGND 200 µs
MAX5092A/MAX5093A 0.4
7V ≤ VIN ≤ 72V,
ILOAD = 10mA MAX5092B/MAX5093B 0.5
Line Regulation ΔVOUT /
ΔVIN 7V ≤ VIN ≤ 28V, ILOAD = 250mA 1.6
mV/V
SET Reference Voltage VSET 1.205 1.235 1.265 V
SET Input Bias Current ISET 0.5 100 nA
Load Regulation ΔVOUT /
ΔIOUT IOUT = 1mA to 250mA 0.2 0.6 mV/mA
f = 100Hz IOUT = 10mA, VBSOUT(AC)
= 500mVP-P, VOUT = 5V 80
Power-Supply Rejection Ratio PSRR
f = 1MHz IOUT = 10mA, VBSOUT(AC)
= 500mVP-P, VOUT = 5V 60
dB
Short-Circuit Current ISC 255 490 mA
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at TA= +25°C.) (Note 2)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= TJ= -40°C to +125°C, unless otherwise
noted. See Figures 4–7 as applicable. Typical specifications are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ENABLE, HOLD and RESET
EN High Input Threshold ENH2.4 V
EN Low Input Threshold ENL0.4 V
EN Input Bias Current IEN 0.25 2 µA
HOLD Low Input Threshold VIL Regulator on, EN transition from high to low 0.4 V
HOLD Release Voltage VIH EN = low VOUT -
0.4 V
HOLD Pullup Current IHOLD Internally connected to OUT 4 µA
RESET Voltage Threshold VRESET % of VOUT, VOUT falling 87 90 92 %
RESET Threshold Hysteresis VRHYST % of VOUT 2%
RESET Output Low Voltage VRL ISINK = 1mA 0.4 V
RESET Output High Leakage
Current IRH V
R E S E T
= 5V 1 µA
RESET Output Minimum Timeout
Period CCT not connected 25 µs
EN to RESET Minimum Timeout
Delay CCT not connected 260 µs
Delay Comparator Threshold
(Rising) VCTTH 1.205 1.24 1.265 V
Delay Comparator Threshold
Hysteresis VCTTH-HYS 100 mV
CT Charge Current ICT-CHG 1.5 2 2.5 µA
CT Discharge Current ICT-DIS 5mA
Thermal Shutdown Temperature
Threshold TJ
(
SHDN
)
Temperature rising 165 °C
Thermal Shutdown Temperature
Hysteresis TJ
(
HYST
)
20 °C
Note 2: Limits at -40°C are guaranteed by design and characterization; not production tested.
Note 3: Guaranteed minimum operating voltage is 3.5V on VIN falling only.
Note 4: Guaranteed by design and not production tested.
Note 5: The boost converter disable threshold (VBST_DIS) is a static measurement. Internal comparator delay may cause a higher
disable level.
Note 6: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed
by the package thermal constraints.
Note 7: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maxi-
mum dropout across the pass transistor.
Note 8: Dropout voltage is defined as (VBSOUT - VOUT) when VOUT is 2% below the value of VOUT for VBSOUT = VOUT + 2V.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________
5
QUIESCENT SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc01
INPUT VOLTAGE (V)
QUIESCENT SUPPLY CURRENT (μA)
645616 24 32 40 48
55
60
65
70
75
80
85
90
50
872
IOUT = 100μA
IOUT = 10mA
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = IIN - IOUT
INPUT CURRENT (IIN)
vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc02
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
6.56.05.55.04.5
1
10
100
0.1
4.0 7.0
IOUT = 100μA
IOUT = 10mA
BOOST CONVERTER SWITCHING
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
MAX5092/93 toc03
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (μA)
11085603510-15
50
60
70
80
90
100
40
-40 135
IOUT = 10mA
IOUT = 100μA
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = IIN - IOUT
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5093B)
MAX5092/93 toc04
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (μA)
11085603510-15
50
60
70
80
90
100
40
-40 135
IOUT = 10mA
IOUT = 100μA
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = IIN - IOUT
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc05
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (μA)
645444342414
2
4
6
8
10
0
474
VEN = 0V
SWITCHING WAVEFORMS
VBSOUT PROGRAMMED < (VOUT + VBST_DIS)
MAX5092/93 toc08
100μs/div
VIN
1V/div
VBSOUT
2V/div
VOUT
100mV/div
ILX
2A/div
5V
(AC-COUPLED)
8.5V
(AC-COUPLED)
5V
(AC-COUPLED)
0
VIN = 5V, IOUT = 100mA,
VBSOUT PROGRAMMED TO 11V
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5093B)
MAX5092/93 toc06
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (μA)
645444342414
2
4
6
8
10
0
474
VEN = 0V
Typical Operating Characteristics
(VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
MAX5092/93 toc07
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (μA)
11085603510-15
4
6
8
10
2
-40 135
VEN = 0V
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
6 _______________________________________________________________________________________
LINE-TRANSIENT RESPONSE
(VIN STEP FROM 4V TO 7V)
MAX5092/93 toc09
200μs/div
VOUT
50mV/div
VIN
1V/div
VBSOUT
1V/div
5V (AC-COUPLED)
7V
4V
7V (AC-COUPLED)
IOUT = 250mA
LINE-TRANSIENT RESPONSE
(VIN STEP FROM 3.5V TO 72V)
MAX5092/93 toc10
40ms/div
VIN
50V/div
VOUT
50mV/div
VBSOUT
50V/div
72V
3.5V
5V (AC-COUPLED)
72V
7V
IOUT = 5mA
SWITCHING WAVEFORMS
VBSOUT PROGRAMMED < (VOUT + VBST_DIS)
MAX5092/93 toc11
100μs/div
VIN
1V/div
VBSOUT
2V/div
VOUT
100mV/div
ILX
2A/div
5V
(AC-COUPLED)
7V
(AC-COUPLED)
5V
(AC-COUPLED)
0
VIN = 5V, IOUT = 100mA,
VBSOUT PROGRAMMED TO 7V
LINE-TRANSIENT RESPONSE
(VIN STEP FROM 3.5V TO 14V)
MAX5092/93 toc12
200μs/div
VOUT
100mV/div
VBSOUT
5V/div
VIN
5V/div
14V
14V
7V
5V (AC-COUPLED)
3.5V
DROPOUT VOLTAGE (VBSOUT - VOUT)
vs. LDO LOAD CURRENT
MAX5092/93 toc13
LDO LOAD CURRENT (mA)
DROPOUT VOLTAGE (mV)
20015010050
200
400
600
800
1000
0
0250
LDO OUTPUT VOLTAGE
vs. LDO LOAD CURRENT (MAX5092B)
MAX5092/93 toc14
LDO LOAD CURRENT (mA)
LDO OUTPUT VOLTAGE (V)
200100
4.90
4.95
5.00
5.05
5.10
5.15
4.85
0300
TA = -40°C: CIN = 10μF, CBSOUT = 4.7μF, COUT = 10μF
(CERAMIC)
TA = +25°C, +135°C: CIN = 47μF, CBSOUT = 22μF
(ELECTROLYTIC), COUT = 10μF (CERAMIC)
TA = +25°C, VIN = 4V
TA = +25°C, VIN = 14V TA = -40°C, VIN = 4V
TA = -40°C, VIN = 14V
TA = +135°C, VIN = 4V
TA = +135°C, VIN = 14V
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX5092/93 toc15
FREQUENCY (Hz)
100k10k1k
-70
0
10dB/div
100 1M
VIN = 14V, IOUT = 10mA
PSRR (dB)
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
_______________________________________________________________________________________
7
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX5092/93 toc16
FREQUENCY
(
Hz
)
100k10k1k
-70
0
100 1M
VIN = 8V, IOUT = 10mA
PSRR (dB)
10dB/div
STARTUP THROUGH INPUT VOLTAGE
MAX5092/93 toc17
100μs/div
0V
VIN
10V/div
VBSOUT
10V/div
ILX
5A/div
VOUT
5V/div
0V
0A
0V
IOUT = 250mA
SHUTDOWN THROUGH VIN
MAX5092/93 toc18
2ms/div
VIN
10V/div
ILX
1A/div
VOUT
5V/div
VBSOUT
10V/div
0V
0V
0A
0V
IOUT = 250mA
STARTUP THROUGH ENABLE
MAX5092/93 toc19
200μs/div
14V
VIN
10V/div
VBSOUT
10V/div
VOUT
5V/div
VEN
2V/div
14V
0V
0V
IOUT = 250mA
SHUTDOWN THROUGH ENABLE
MAX5092/93 toc20
200μs/div
VIN
10V/div
VOUT
5V/div
VEN
2V/div
VBSOUT
10V/div
14V
14V
0V
0V
IOUT = 250mA
RESET TIMING RESPONSE
MAX5092/93 toc21
200μs/div
VOUT
2V/div
VEN
2V/div
VRESET
2V/div
0V
0V
0V
IOUT = 250mA
CT = 680pF
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
8 _______________________________________________________________________________________
VOUT vs. TEMPERATURE
MAX5092/93 toc22
TEMPERATURE (°C)
VOUT (V)
11085603510-15
3.26
3.28
3.30
3.32
3.34
3.36
3.24
-40 135
IOUT = 10mA, R5 = 100kΩ,
R4 = 165kΩ, FIGURE 6
VOUT vs. TEMPERATURE
(MAX5092B)
MAX5092/93 toc23
TEMPERATURE (°C)
VOUT (V)
11085603510-15
4.95
5.00
5.05
5.10
4.90
-40 135
IOUT = 1mA, VSET = 0V
LDO LOAD-TRANSIENT RESPONSE
(MAX5092B)
MAX5092/93 toc24
2ms/div
VOUT
50mV/div
IOUT
100mA/div
(AC-COUPLED)
0mA
INPUT-VOLTAGE STEP RESPONSE
MAX5092/93 toc25
200ms/div
VOUT
20mV/div
VIN
20V/div
5V
(AC-COUPLED)
72V
3.5V
IOUT = 5mA
ENABLE AND HOLD TIMING
MAX5092/93 toc26
200ms/div
VEN
5V/div
VHOLD
5V/div
VOUT
5V/div
0V
0V
0V
INTERNAL BOOST DIODE FORWARD DROP
(MAX5092)
MAX5092/93 toc27
DIODE CURRENT (A)
DIODE VOLTAGE (mV)
2.52.01.51.00.5
250
500
750
1000
1250
1500
0
03.0
VIN = 8V, BOOST CONVERTER
NOT SWITCHING
BOOST CONVERTER POWER LOSS
(VBSOUT = 7V)
MAX5092/93 toc28
IOUT (mA)
POWER LOSS (W)
30025020015010050
0.2
0.4
0.6
0.8
1.0
0
0350
TA = +105°C: VIN = 3.5V
VIN = 4V
VIN = 5V
TA = +25°C: VIN = 3.5V
VIN = 4V
VIN = 5V
BOOST CONVERTER POWER LOSS
(VBSOUT = 11V)
MAX5092/93 toc29
IOUT (mA)
POWER LOSS (W)
30025020015010050
0.2
0.4
0.6
0.8
1.0
1.2
0
0 350
VIN = 5V
VIN = 3.5V
VIN = 4V
TA = +105°C: VIN = 4V
VIN = 5V
VIN = 3.5V
GROUND CURRENT DISTRIBUTION
(162 UNITS TESTED)
MAX5092/93 toc30
IGND (μA)
NUMBER OF UNITS
5
10
15
20
25
30
35
40
0
TA = TJ = +125°C
TA = TJ = -40°C
70
68
52 54 56 60 62 64 66
58
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA= +25°C, unless otherwise noted.) (See Figures 4–7 as
applicable.)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1IN
Input Supply Voltage. Bypass IN to the power ground plane with a 47µF (low-ESR) aluminum electrolytic
capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible.
2EN
Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for
always-on operation.
3 SGND Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power
ground and signal ground plane together at the negative terminal of the input capacitor(s).
4HOLD
Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the
regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is
pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally
connected to OUT through a 4µA pullup current.
5 PGND_LDO LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and
signal ground plane together.
6 SET
Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the
preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center
tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. VSET
regulates to 1.24V when using an adjustable output.
7 OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load.
8 OUT
LDO Regulator Output. Bypass OUT to the power ground plane with a 10µF ceramic capacitor. VOUT
regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is
adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_).
9 BSOUT
Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22µF (low-ESR)
aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as
possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for VIN ≤
7V. VBSOUT follows VIN for VBSOUT - VOUT > 2.5V (typ). VBSOUT is programmable up to 11V (MAX5092_) or
12V (MAX5093_) by connecting BSFB to the center tap of an external resistor-divider connected between
the BOOST output and PGND_BST.
10, 11 LX
Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the
inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also
connect LX to the anode of the external Schottky diode.
12 PGND_BST Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST
ground plane and the signal ground plane together at the negative terminal of the input capacitor(s).
13 BSFB
Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output
voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT
and SGND to set the output voltage. VBSFB regulates to 1.24V when using an adjustable output.
14 VL Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1µF/6.3V ceramic capacitor placed as
close to the IC as possible. VVL regulates to 5.5V with VBSOUT ≥ 5.5V.
15 CT RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout
period. See the CT Capacitor Selection section.
16 RESET
RESET Output. RESET is an open-drain output that goes high impedance when VOUT exceeds 92% of the
output voltage threshold after a programmed time delay. RESET pulls low immediately once VOUT drops
below 90% of the regulated LDO output voltage.
—EP
Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for
increased thermal performance.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
10 ______________________________________________________________________________________
MAX5092_ INTERNAL
LDO
Q
Q
VPK
R1
RS
IN
VL
VL
LX
LX
BSOUT
BSOUT
BSFB
OUT
OUT
OUT_SENSE
SET
CT
RESET
R2
LDO
ERROR AMPLIFIER
MUX
S
R
INOUT
DRIVER
2.25μs
ONE-SHOT
1μs
ONE-SHOT
CURRENT-LIMITING
COMPARATOR
INOUT
MUX
DELAY
COMPARATOR
CT
COMPARATOR
0.92 x VREF
VL
2μA
SGND PGND_LDO
P
PGND_BST
CONTROL LOGIC,
THERMAL SHUTDOWN,
AND OVERCURRENT
PROTECTION R3
R4
VREF
VREF
HOLD
OUT
BST_DIS
VDIS_TH
BSOUT
EN
Figure 1. MAX5092_ Functional Diagram
Functional Diagrams
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 11
MAX5093_ INTERNAL
LDO
Q
Q
VPK
R1
RS
IN
VL
LX
LX
BSOUT
BSFB
OUT
OUT_SENSE
SET
CT
RESET
R2
LDO
ERROR AMPLIFIER
MUX
S
R
INOUT
DRIVER
2.25μs
ONE-SHOT
1μs
ONE-SHOT
CURRENT-LIMITING
COMPARATOR
INOUT
MUX
DELAY
COMPARATOR
CT
COMPARATOR
0.92 x VREF
VL
2μA
SGND PGND_LDO
P
PGND_BST
CONTROL LOGIC,
THERMAL SHUTDOWN,
AND OVERCURRENT
PROTECTION R3
R4
VREF
VREF
HOLD
EN
VL
OUT
BST_DIS
VDIS_TH
BSOUT
BSOUT
OUT
Figure 2. MAX5093_ Functional Diagram
Functional Diagrams (continued)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
12 ______________________________________________________________________________________
Detailed Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B
include a step-up, switch-mode DC-DC converter and a
linear regulator to provide step-up/-down voltage con-
version over a wide range of input voltages. This combi-
nation of an LDO and a boost converter offers the
advantage of using a single off-the-shelf inductor in
place of the multiple-winding custom magnetics needed
in typical SEPIC or transformer-based flyback topolo-
gies. The boost preregulator is completely turned off
during normal automotive operation (VIN = 14V),
reduces quiescent current to 65µA (typ), and makes the
devices suitable for always-on power supplies.
The devices have an internal UVLO threshold of 3.8V
(max, VIN rising) that must be exceeded before the
device is enabled. When VIN is above VUVLO, the inter-
nal boost converter starts switching and regulates
VBSOUT to the programmed boost output voltage. The
low quiescent-current LDO steps down VBSOUT to the
programmed LDO output voltage. The LDO output is
preset to 3.3V (MAX5092A/MAX5093A) or 5V
(MAX5092B/MAX5093B). Both output voltages can be
adjusted by using external resistor-dividers.
If (VBSOUT - VOUT) rises above 2.5V (typ), the boost con-
verter is disabled, forcing VBSOUT to follow VIN. If
VBSOUT - VOUT falls below 2V (typ), the boost converter
starts switching and regulates VBSOUT to the pro-
grammed voltage. The boost converter regulates
VBSOUT for VIN down to 3.5V, providing uninterrupted
operation during low cold-crank voltages even if the pro-
grammed LDO output voltage is greater than VIN (but
less than 9V). The boost converter turn-on response time
is less than 10µs, making cold-crank input glitches trans-
parent to the system even at full load.
The boost-converter output is followed by a high PSRR,
low-quiescent-current LDO. The LDO rejects the
switching noise present at BSOUT and provides a
clean, regulated output voltage. The linear regulator
uses an internal p-channel MOSFET pass element.
Additional features include a power-on-reset function
with an externally adjustable timeout, an enable (EN)
input, and a hold (HOLD) regulator control input.
Boost Converter
The switch-mode converter uses a minimum off-time,
maximum on-time pulse frequency modulation (PFM)
control scheme. The internal MOSFET turns on whenev-
er VBSOUT falls below the regulation point determined
by VBSFB (see the
Setting the Boost Output Voltage
(V
BSOUT
)
section). The MOSFET turns off when the
inductor current reaches the peak current limit (2.5A
typ) or after 2.25µs maximum on-time, whichever
occurs first. The MOSFET is held off for at least 1µs
after the turn-on phase. A new switching cycle initiates
once VBSOUT falls below the threshold. In this control
scheme, switching frequency and output ripple are
functions of load current and input voltage. No frequen-
cy compensation is needed in the PFM control scheme.
The output of the boost converter is preset to 7V and is
adjustable by using external resistors. See the
Setting
the Boost Output Voltage V
BSOUT
section.
If VBSOUT is programmed greater than (VOUT +
VBST_DIS), larger ripple is observed on BSOUT. The rea-
son is as VBSOUT rises above VOUT + VBST_DIS, the
boost converter is disabled, causing VBSOUT to fall. As
VBSOUT falls to VOUT + VBST_EN, the boost converter
turns back on, and VBSOUT rises. For the lowest VBSOUT
ripple, program VBSOUT within the boost disable thresh-
old. See the
Typical Operating Characteristics
for the
Switching Waveforms.
Due to the integrated blocking diode in the MAX5092_,
VBSOUT is limited to 11V. Use the MAX5093_ for higher
boost output voltages (or to reduce the power dissipa-
tion in to the package). The MAX5093_ requires an
external diode for the boost converter. Select the exter-
nal diode according to the
Schottky Diode Selection
(MAX5093_)
section.
Linear Regulator
The MAX5092_/MAX5093_ contain an internal p-chan-
nel MOSFET used as the pass transistor for the LDO.
The output of the boost regulator is connected to the
source of the p-MOSFET. The LDO starts up 200µs
after the boost regulator starts up. The LDO supplies
up to 250mA with a typical dropout voltage of 0.9V. The
maximum LDO output current is determined by the
package power-dissipation limit as well as the internal
current limit. The LDO is designed to be a low-quies-
cent-current type. During normal operation when the
battery voltage is > 9V, the MAX5092_/MAX5093_ con-
sume only 75µA (max) at +85°C and 100µA load.
The output voltage of the LDO is set using the SET
input. Connect SET to SGND to use the factory-preset
output voltage. Connect SET to the center of an exter-
nal resistor-divider connected from OUT to SGND to
program a different output voltage. See the
Setting the
LDO Output Voltage (V
OUT
)
section.
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 13
Internal Regulator (VL)
An internal regulator (VL) is used to supply all internal
low-voltage blocks. Bypass VL to SGND with a 1µF
ceramic capacitor placed as close to the IC as possi-
ble. VVL regulates to 5.5V when VBSOUT is above 5.5V.
VVL tracks the voltage at BSOUT when VBSOUT is
below 5.5V.
Power-On-Reset Output (
RESET
)
The MAX5092_/MAX5093_ contain an open-drain output
(RESET) that indicates when the LDO output (VOUT) is
out of regulation. If the output of the LDO falls below 90%
of the nominal output voltage, RESET pulls low after a
short delay. Once the output rises above 92% of the
nominal output voltage, RESET goes high impedance
after the programmed reset timeout period. Connect a
100kΩpullup resistor from OUT to RESET. See the
CT
Capacitor Selection
section for details on setting the
RESET timeout period.
Enable and Hold Inputs
The MAX5092_/MAX5093_ utilize two logic inputs, EN
(active-high) and HOLD (active low), to implement a
self-holding circuit with no additional components. For
example, an automotive ignition switch drives EN high
and the regulator turns on. If HOLD is then driven low,
the regulator remains on even if EN goes low. As long
as HOLD is forced low and remains low after initial reg-
ulator power-up, the regulator remains on. From this
state, release HOLD (an internal current source con-
nects HOLD to OUT), or connect HOLD to OUT to turn
the regulator off. Drive EN low and HOLD high to place
the IC into shutdown mode. Shutdown mode reduces
supply current to 5µA. Figure 3 shows the timing dia-
gram for the enable and hold functions. Table 1 shows
the state of the regulator output with respect to the volt-
age level at EN and HOLD with reference to Figure 3.
Connect HOLD to OUT or leave unconnected to dis-
able the hold feature and use EN as a standard on/off
control input.
3
1
HOLD
EN
OUT
ORDER 2456
Figure 3. Enable and Hold Timing Diagram
ORDER
EN
HOLD OUT
COMMENTS
1
Low
X
Off
Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT.
HOLD follows OUT.
2
High Released On
Regulator output is active when EN is pulled high. HOLD is in release state, and it follows
OUT.
3
Low Released Off
HOLD is in release state. OUT follows EN.
4
High
Low
On
HOLD is pulled low externally after OUT turns on. The regulator output is forced on
regardless of the state of EN. A self-holding state.
5
Low Released Off
HOLD is released after EN is pulled low. Output turns off.
5
High
X
On
Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT.
Table 1. Truth Table for Enable and Hold Timing Diagram
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
14 ______________________________________________________________________________________
Applications Information
MAX5092B
U1
1
10 11
16
2
3
15
VL 14
9
12
13
4
7
8
P
5
6
LX LX
RESET
IN
EN
SGND
RESET
ON
OFF
INPUT
4V TO 72V
L1
4.7μH
C1*
47μF
C2*
1μF
C6
1μF
C3*
1μF
C4*
22μF
C7
10μF
C5
0.22μF
R1
100kΩ
VOUT
CT
***
P
BSOUT
BSFB
HOLD
OUT_SENSE
OUT
SET
PGND_LDO VOUT
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PCB LAYOUT GUIDELINES SECTION.
μP
SIGNAL
OUTPUT
5V AT 250mA**
7V
PGND_BST
Figure 4. MAX5092B Typical Application Circuit with Factory Preprogrammed LDO and Boost Output Voltages
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 15
Applications Information (continued)
MAX5093B
U1
1
10 11
16
2
3
15
VL 14
9
12
13
4
7
8
5
6
LX LX
RESET
IN
EN
SGND
RESET
ON
OFF
INPUT
4V TO 72V
L1
4.7μH
C1*
47μF
C2*
1μF
C6
1μF
C3*
1μF
C4*
22μF
C7
10μF
C5
0.22μF
R1
100kΩ
VOUT
CT
BSOUT
BSFB
HOLD
OUT_SENSE
OUT
SET
PGND_LDO VOUT
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PCB LAYOUT GUIDELINES SECTION.
μP
SIGNAL
OUTPUT
5V AT 250mA**
7V
PGND_BST
***
P
P
Figure 5. MAX5093B Typical Application Circuit with Factory Preprogrammed Boost and LDO Output Voltages
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
16 ______________________________________________________________________________________
Applications Information (continued)
MAX5092A
U1
1
10 11
16
2
3
15
VL 14
9
12
13
4
7
8
P
5
6
LX LX
RESET
IN
EN
SGND
RESET
INPUT
4V TO 72V
L1
4.7μH
C1*
47μF
C2*
1μF
C6
1μF
C3*
1μF
C4*
22μF
C7
10μF
C5
0.22μF
R3
100kΩ
VOUT
CT
BSOUT
BSFB
HOLD
OUT_SENSE
OUT
SET
PGND_LDO
VOUT
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PCB LAYOUT GUIDELINES SECTION.
μP
SIGNAL
OUTPUT
5.3V
5.5V
PGND_BST
R1
1.65MΩ
R2
499kΩ
ON
OFF
***
P
OUTPUT
3.3V**
Figure 6. MAX5092A Typical Application Circuit with User-Programmed LDO and Boost Output Voltages
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 17
Applications Information (continued)
MAX5093A
U1
1
10 11
16
2
3
15
VL 14
9
12
13
4
7
8
5
6
LX LX
RESET
IN
EN
SGND
RESET
INPUT
4V TO 72V
L1
4.7μH
C1*
47μF
C2*
1μF
C6
1μF
C3*
1μF
C4*
22μF
C7
10μF
C5
0.22μF
R3
100kΩ
VOUT
CT
BSOUT
BSFB
HOLD
OUT_SENSE
OUT
SET
PGND_LDO
VOUT
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE.
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PCB LAYOUT GUIDELINES SECTION.
μP
SIGNAL
OUTPUT
10V**
OUTPUT
12V
PGND_BST
R1
4.32MΩ
R2
499kΩ
ON
OFF
R4
698kΩ
R5
100kΩ
***
P
Figure 7. MAX5093A Typical Application Circuit with User-Programmable Boost Output Voltage and LDO Output Voltage
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
18 ______________________________________________________________________________________
Design Guidelines
Input Capacitor (CIN) and
Boost Capacitor (CBSOUT) Selection
The input current waveform of the boost converter is
continuous, and usually does not demand high capaci-
tance at its input. However, the MAX5092_/MAX5093_
boost converter is designed to fully turn on as soon as
the input drops below a certain voltage in order to ride
out cold-crank droops. This operation demands low
input source impedance for proper operation. If the
source (battery) is located far from the IC, high-capaci-
ty, low-ESR capacitors are recommended for CIN. The
worst-case peak capacitor current could be as high as
3A. Use a 47µF, 100mΩlow-ESR capacitor placed as
close as possible to the input of the device. Note that
the aluminum electrolytic capacitor ESR increases sig-
nificantly at cold temperatures. In the cold temperature
case, choose an electrolyte capacitor with ESR lower
than 40mΩor connect a low-ESR ceramic capacitor
(10µF) in parallel with the electrolytic capacitor.
The boost converter output (BSOUT) is fed to the input
of the internal 250mA LDO. The boost-converter output
current waveform is discontinuous and requires high-
capacity, low-ESR capacitors at BSOUT to ensure low
VBSOUT ripple. During the on-time of the internal MOSFET,
the BSOUT capacitor supplies 250mA current to the
LDO input. During the off-time, the inductor dumps cur-
rent into the output capacitor while supplying the output
load current. The internal 250mA LDO is designed with
high PSRR; however, high-frequency spikes may not be
rejected by the LDO. Thus, high-value, low-ESR elec-
trolytic capacitors are recommended for CBSOUT.
Peak-to-peak VBSOUT ripple depends on the ESR of the
electrolyte capacitor. Use the following equation to cal-
culate the required ESR (ESRBSOUT) of the BSOUT
capacitor:
where ΔVESRBS is 75% of total peak-to-peak ripple at
BSOUT, ILIM is the internal switch current limit (3A max),
and IOUT is the LDO output current. Use a 100mΩor
lower ESR electrolytic capacitor. Make sure the ESR at
cold temperatures does not cause excessive ripple
voltage. Alternately, use a 10µF ceramic capacitor in
parallel with the electrolyte capacitor.
During the switch on-time, the BSOUT capacitor dis-
charges while supplying IOUT. The ripple caused by
the capacitor discharge (ΔVCBS) is estimated by using
the following equation:
where IOUT is the LDO output current and CBSOUT is
the BSOUT capacitance.
Inductor Selection
The control scheme of the MAX5092/MAX5093 permits
flexibility in choosing an inductor value. Smaller induc-
tance values typically offer smaller physical size for a
given series resistance, allowing the smallest overall
circuit dimensions. Circuits using larger inductance
may provide higher efficiency and exhibit less ripple,
but also may reduce the maximum output current. This
occurs when the inductance is sufficiently large to pre-
vent the LX current limit (ILIM) from being reached
before the maximum on-time (tON-MAX) expires.
For maximum output current, choose the inductor value
so that the controller reaches the current limit before
the maximum on-time is reached:
where tON-MAX is typically 2.25µs, and the current limit
(ILIM) is a maximum of 3A (see the
Electrical
Characteristics
). Choose an inductor with the maximum
saturation current (ISAT) greater than 3A.
LVt
I
IN ON MAX
LIM
≤×−
ΔVI
C
CBS OUT
BSOUT
=××
−
27 10 6
.
ESR V
II
BSOUT ESRBS
LIM OUT
=−
Δ
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 19
Setting the Boost
Output Voltage (VBSOUT)
The MAX5092_/MAX5093_ feature Dual Mode™ opera-
tion for the internal boost converter output voltage.
These devices operate in a preset output-voltage mode
or an adjustable output-voltage mode. In preset mode,
internal trimmed feedback resistors set VBSOUT to a
fixed 7V. Select the preset mode by directly connecting
BSFB to SGND (Figures 4 and 5). Ensure a low-imped-
ance path between BSFB and SGND to limit the tran-
sient at BSFB to below 100mV. In adjustable mode,
connect BSFB to the center tap of an external resistor-
divider connected between BSOUT and SGND to pro-
gram VBSOUT (Figures 6 and 7). Program (VBSOUT <
VOUT + VBST_DIS) for lower VBSOUT ripple. Note that
the current drawn by the resistor-divider at BSOUT
adds to the quiescent current and the shutdown current
of the IC. Use the resistor-divider only if VBSOUT is
required to be significantly different than 7V. Select
499kΩor lower resistance value for the bottom resistor
(R2) of the divider connected to SGND. The top resistor
(R1) value is calculated as:
where VBSFB is the regulation voltage at BSFB (1.24V
typ) and VBSOUT is the desired output voltage for
BSOUT.
Setting the LDO Output Voltage (VOUT)
The LDO output voltage is also Dual Mode (preset and
adjustable). Preset mode is selected by connecting
SET to SGND (Figures 4 and 5). In preset mode, VOUT
regulates to 3.3V (MAX5092A/MAX5093A) or 5V
(MAX5092B/MAX5093B) by internal trimmed feedback
resistors. Adjustable mode is selected by connecting
SET to the center tap of an external resistor-divider
connected between OUT and SGND (Figures 6 and 7).
Note that the current drawn by the resistor-divider at
OUT adds to the quiescent current of the LDO. Use the
resistor-divider only if VOUT is required to be signifi-
cantly different than the preset voltage. Select 100kΩor
lower value for the bottom resistor (R5) of the divider
connected to SGND. The top resistor (R4) value is cal-
culated as:
where VSET is the regulation voltage at SET (1.24V typ)
and VOUT is the desired output voltage for the LDO
output.
Schottky Diode Selection (MAX5093_)
The MAX5093_ requires an external diode connected
between LX and BSOUT (Figures 5 and 7). Proper
selection of an external diode can offer a lower forward-
voltage drop and a higher reverse-voltage handling
capability. Since the high switching frequency of the IC
demands a high-speed rectifier, Schottky diodes are
recommended for most applications because of their
fast recovery time and low forward-voltage drop.
Ensure that the diode’s peak current rating is greater
than or equal to the peak current limit of internal boost
converter MOSFET. A diode average forward current
rating of at least 1A is recommended. Additionally, the
diode reverse breakdown voltage must be greater than
the worst-case load-dump-condition voltage.
CT Capacitor Selection
The MAX5092_/MAX5093_ contain an open-drain
power-on-reset output (RESET) that indicates when the
LDO output voltage (VOUT) is out of regulation. When
VOUT rises above 92% of the nominal output voltage,
RESET goes high impedance after a user-programma-
ble time delay. This time duration is programmable by a
capacitor (CCT) from CT to SGND (Figures 4–7). For a
chosen RESET active timeout period (tDELAY), calculate
the required capacitor value as:
When VOUT drops below 90% of the LDO output regula-
tion voltage, a 5mA pulldown current from CT to SGND
discharges CCT. The time required to discharge CT
determines the delay necessary to pull RESET low. This
delay provides glitch immunity to the RESET function.
The glitch immunity delay is directly proportional to the
CT capacitor and is approximately 70µs for a 0.1µF
capacitor at CT.
Ct
CT DELAY
=××
−
210
124
6
.
RR V
V
OUT
SET
45 1=×
⎛
⎝
⎜
⎞
⎠
⎟
−
RR V
V
BSOUT
BSFB
12 1=×
⎛
⎝
⎜
⎞
⎠
⎟
−
Dual Mode is a trademark of Maxim Integrated Products, Inc.
MAX5092/MAX5093
Maximum Output Current (IOUT_MAX)
The MAX5092_/MAX5093_ high input voltage (+72V
max) provides up to 250mA of current from OUT.
Package power-dissipation limits the amount of output
current available for a given input/output voltage and
ambient temperature. Figure 8 depicts the maximum
power-dissipation curve for the devices. The graph
assumes that the exposed metal pad of the IC package
is soldered to the PCB copper according to the JEDEC
51 standard (multilayer board). Use Figure 8 to deter-
mine the allowable package dissipation for a given
ambient temperature. Alternately, use the following for-
mula to calculate the allowable package dissipation
(PDISS) in watts:
For TA≤+70°C:
PDISS = 2.67
For +70°C < TA≤+125°C:
PDISS = 2.67 - (0.0333 x (TA- 70))
where +70°C < TA≤+125°C and 0.0333W/°C is the
package thermal derating. After determining the allow-
able package dissipation, calculate the maximum out-
put current (IOUT_MAX) using the following formula:
where PDISS is the allowable package power dissipa-
tion and PLOSS(BST) is the boost converter power loss.
PDISS includes the losses in the boost converter opera-
tion and the LDO itself. The boost converter loss
PLOSS(BST), depends on VIN, VBSOUT, and IOUT. See
the Boost Converter Power Loss graphs in the
Typical
Operating Characteristics
to estimate the losses at a
given VIN and VBSOUT at room temperature. At a higher
ambient temperature of +105°C, PLOSS(BST) increases
by up to 20% due to higher RDS-ON and switching loss-
es of the internal boost converter MOSFET. (Note:
IOUT_MAX must be less than 250mA).
PCB Layout Guidelines
Good PCB layout and routing are required in high-fre-
quency switching power supplies to achieve proper
regulation and stability. It is strongly recommended that
the evaluation kit PCB layouts be followed as closely as
possible. Refer to the MAX5092 EV kit for an example
layout. Follow these guidelines for good PCB layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PCB and ambient, expose this copper area on
the top and bottom side of the PCB. Do not make a
direct connection from the EP copper plane to pin 3
(SGND) underneath the IC so as to minimize
ground bounce.
2) Isolate the power components and high-current
path from the sensitive analog circuit.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
4) Connect the return terminals of input capacitors
and boost output capacitors to the PGND_BST
power ground plane. Connect the power ground
(PGND_BST) and signal ground (SGND) planes
together at the negative terminal of the input capac-
itors. Do not connect them anywhere else. Connect
PGND_LDO ground plane to SGND ground plane
at a single point.
5) Ensure that the feedback connections are short and
direct. Ensure a low-impedance path between
BSFB and SGND to limit the transient at BSFB to
100mV.
6) Route high-speed switching nodes away from the
sensitive analog areas. Use the internal PCB layer
for SGND as an EMI shield to keep radiated noise
away from the IC, feedback dividers, and bypass
capacitors.
IPP
VV
OUT MAX DISS LOSS BST
IN OUT
_()
=−
−
4V to 72V Input LDOs with Boost Preregulator
20 ______________________________________________________________________________________
MAXIMUM POWER DISSIPATION
vs. AMBIENT TEMPERATURE
MAX5092/93 fig08
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
1109580655035205-10-25
0.5
1.0
1.5
2.0
2.5
3.0
0
-40 125
Figure 8. MAX5092/MAX5093 Package Power Dissipation
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 21
Chip Information
PROCESS: BiCMOS
Selector Guide
Typical Operating Circuit
MAX5092B
IN VL
LX LX
RESET
EN
SGND
RESET
OUTPUT
ENABLE
INPUT
4V TO 72V
VOUT
CT
P
BSOUT
BSFB
HOLD
OUT_SENSE
OUT
SET
PGND_LDO
VOUT
+5V OUTPUT
+7V OUTPUT
PGND_BST
*
P
*SEE PCB LAYOUT GUIDELINES SECTION.
PART PRESET LDO
OUTPUT (V)
ADJUSTABLE
LDO OUTPUT
PRESET BSOUT
OUTPUT (V)
ADJUSTABLE BSOUT
OUTPUT BOOST DIODE
MAX5092AATE+ 3.3 Yes 7 Yes Internal
MAX5092BATE+ 5 Yes 7 Yes Internal
MAX5093AATE+ 3.3 Yes 7 Yes External
MAX5093BATE+ 5 Yes 7 Yes External
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
22 ______________________________________________________________________________________
QFN THIN.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
______________________________________________________________________________________ 23
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX5092/MAX5093
4V to 72V Input LDOs with Boost Preregulator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/06 Initial release —
1 1/08
Updated Ordering Information and Electrical Characteristics table, added
two tocs, updated Functional Diagrams and Applications Diagrams, added
boost converter details
1–12, 14–17, 19, 22,
23
