PSoCTM Mixed-Signal Array Final Data Sheet CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 Features Flexible On-Chip Memory Powerful Harvard Architecture Processor 8K Flash Program Storage 50,000 Erase/Write Cycles 512 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash M8C Processor Speeds to 24 MHz Low Power at High Speed 2.4V to 5.25V Operating Voltage Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 4 Analog Type "E" PSoC Blocks Provide: Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory - 2 Comparators with DAC Refs - Two 8-Bit 28 Channel ADCs 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART, SPITM Master or Slave - Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Port 3 Port 2 Port 1 Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator Internal Oscillator for Watchdog and Sleep SystemBus Global Analog Interconnect SRAM 512 Bytes SROM Flash 8K CPU Core (M8C) Interrupt Controller Sleep and Watchdog Clock Sources (Includes IMO and ILO) ANALOG SYSTEM DIGITAL SYSTEM Analog PSoC Block Array Digital PSoC Block Array 25 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of IO Combinations Capacitive Sensing Application Capability Additional System Resources I2CTM Master, Slave and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference PSoCTM Functional Overview Port 0 PSoC CORE Global Digital Interconnect Programmable Pin Configurations Analog Ref. The PSoCTM family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, as illustrated on the left, is comprised of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects. The PSoC Core Digital Clocks POR and LVD I2C System Resets Sw itch Mode Pump SYSTEM RESOURCES December 17, 2004 Internal Voltage Ref. Analog Mux The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12025 Rev. *E 1 CY8C21x34 Final Data Sheet PSoCTM Overview CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. Port 3 Port 1 Port 2 DigitalClocks FromCore System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC mixed-signal arrays, I2C functionality for implementing an I2C master, slave, MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems, a switch mode pump (SMP) that generates normal operating voltages off a single battery cell, and various system resets supported by the M8C. Port 0 To Analog System To System Bus DIGITAL SYSTEM The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global buses that can route any signal to any pin. Freeing designs form the constraints of a fixed peripheral controller. Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration Row Input Configuration Digital PSoC Block Array 8 8 8 8 GIE[7:0] The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital System Block Diagram The Digital System The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below. The Analog System PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) The Analog System is composed of 4 configurable blocks, allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are listed below. Counters (8 to 32 bit) Analog-to-digital converters (up to 2, with 8-bit resolution) Timers (8 to 32 bit) Pin-to-pin comparator UART 8 bit with selectable parity SPI master and slave Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference I2C slave and multi-master 1.3V reference (as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit) In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The CY8C21x34 devices provide limited functionality Type "E" analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Mixed-Signal Array Technical Reference Manual for detailed information on the CY8C21x34's Type E analog blocks. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3. December 17, 2004 Document No. 38-12025 Rev. *E 2 CY8C21x34 Final Data Sheet PSoCTM Overview Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. Array Input Configuration ACI0[1:0] Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. Versatile analog multiplexer system. ACI1[1:0] All IO X X X ACOL1MUX X AnalogMuxBus X Array ACE00 ACE01 ASE10 ASE11 Analog System Block Diagram PSoC Device Characteristics The Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Flash Size PSoC Device Characteristics Digital IO Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below. CY8C29x66 up to 64 4 16 12 4 4 12 2K 32K Chip-wide mux that allows analog input from any IO pin. CY8C24794 up to 56 1 4 48 2 2 6 1K 16K Crosspoint connection between any IO pin combinations. CY8C27x43 up to 44 2 8 12 4 4 12 256 Bytes 16K CY8C24x23 up to 24 1 4 12 2 2 6 256 Bytes 4K CY8C24x23A up to 24 1 4 12 2 2 6 256 Bytes 4K CY8C21x34 up to 28 1 4 28 0 2 4a 512 Bytes 8K CY8C21x23 16 1 4 8 0 2 4a 256 Bytes 4K Track pad, finger sensing. PSoC Part Number a. Limited analog functionality. December 17, 2004 Document No. 38-12025 Rev. *E 3 CY8C21x34 Final Data Sheet PSoCTM Overview Getting Started Development Tools The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Importable Design Database PSoC Configuration Sheet Device Database PSoC TM Designer Core Engine Application Database Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Results Technical Training Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. Context Sensitive Help Graphical Designer Interface PSoC TM Designer Commands For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. Project Database Manufacturing Information File User Modules Library Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are organized by part number. December 17, 2004 Document No. 38-12025 Rev. *E 4 CY8C21x34 Final Data Sheet PSoCTM Overview PSoC Designer Software Subsystems Device Editor Debugger The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. December 17, 2004 Document No. 38-12025 Rev. *E 5 CY8C21x34 Final Data Sheet PSoCTM Overview Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. Device Editor User Module Selection The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. December 17, 2004 Source Code Generator Generate Application Application Editor Project Manager To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. Placement and Parameter -ization Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Document No. 38-12025 Rev. *E 6 CY8C21x34 Final Data Sheet PSoCTM Overview Document Conventions Table of Contents Acronyms Used For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual on http://www.cypress.com. This document encompasses and is organized into the following chapters and sections. The following table lists the acronyms that are used in this document. Acronym Description AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoCTM Programmable System-on-ChipTM PWM pulse width modulator SC switched capacitor SLIMO slow IMO SMP switch mode pump SRAM static random access memory 1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 16-Pin Part Pinout ..................................... 8 1.1.2 20-Pin Part Pinout ..................................... 9 1.1.3 28-Pin Part Pinout ................................... 10 1.1.4 32-Pin Part Pinout ................................... 11 2. Register Reference ..................................................... 12 2.1 Register Conventions ........................................... 12 2.2 Register Mapping Tables ..................................... 12 3. Electrical Specifications ............................................ 15 3.1 Absolute Maximum Ratings ................................. 16 3.2 Operating Temperature ........................................ 16 3.3 DC Electrical Characteristics ................................ 16 3.3.1 DC Chip-Level Specifications ................... 16 3.3.2 DC General Purpose IO Specifications .... 17 3.3.3 DC Operational Amplifier Specifications ... 18 3.3.4 DC Switch Mode Pump Specifications ..... 19 3.3.5 DC Analog Mux Bus Specifications .......... 20 3.3.6 DC POR and LVD Specifications ............. 20 3.3.7 DC Programming Specifications ............... 21 3.4 AC Electrical Characteristics ................................ 22 3.4.1 AC Chip-Level Specifications ................... 22 3.4.2 AC General Purpose IO Specifications .... 24 3.4.3 AC Operational Amplifier Specifications ... 25 3.4.4 AC Analog Mux Bus Specifications .......... 25 3.4.5 AC Digital Block Specifications ................. 25 3.4.6 AC External Clock Specifications ............. 27 3.4.7 AC Programming Specifications ............... 28 3.4.8 AC I2C Specifications ............................... 28 4. Packaging Information ............................................... 30 4.1 Packaging Dimensions ......................................... 30 4.2 Thermal Impedances .......................................... 32 4.3 Solder Reflow Peak Temperature ........................ 33 Units of Measure 5. A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 15 lists all the abbreviations used to measure the PSoC devices. Ordering Information .................................................. 34 5.1 Ordering Code Definitions .................................... 34 6. Sales and Service Information .................................. 35 6.1 Revision History ................................................... 35 6.2 Copyrights and Code Protection .......................... 35 Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. December 17, 2004 Document No. 38-12025 Rev. *E 7 1. Pin Information This chapter describes, lists, and illustrates the CY8C21x34 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 16-Pin Part Pinout Table 1-1. 16-Pin Part Pinout (SOIC) Type CY8C21234 16-Pin PSoC Device Pin No. Digital Analog 1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input. 3 IO I, M P0[3] Analog column mux input, integrating input. 4 IO I, M P0[1] Analog column mux input, integrating input. SMP Switch Mode Pump (SMP) connection to required external components. 5 Power 6 7 Power IO 8 M Description Vss Ground connection. P1[1] I2C Serial Clock (SCL). Vss Ground connection. 9 IO M P1[0] I2C Serial Data (SDA). 10 IO M P1[2] 11 IO M P1[4] Optional External Clock Input (EXTCLK). 12 IO I, M P0[0] Analog column mux input. 13 IO I, M P0[2] Analog column mux input. 14 IO I, M P0[4] Analog column mux input. 15 IO I, M P0[6] Analog column mux input. Vdd Supply voltage. 16 Power Name Power A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] SMP Vss M,I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P1[4], EXTCLK,M P1[2],M P1[0], I2C SDA, M LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 8 CY8C21x34 Final Data Sheet 1.1.2 1. Pin Information 20-Pin Part Pinout Table 1-2. 20-Pin Part Pinout (SSOP) Type Pin No. Digital Analog 1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input. 3 IO I, M P0[3] Analog column mux input, integrating input. 4 IO I, M P0[1] Analog column mux input, integrating input. Vss Ground connection. 5 Power Name Description 6 IO M P1[7] I2C Serial Clock (SCL). 7 IO M P1[5] I2C Serial Data (SDA). 8 IO M P1[3] 9 IO M P1[1] 10 Power Ground connection. I2C Serial Data (SDA). IO M P1[0] 12 IO M P1[2] 13 IO M P1[4] 14 IO M P1[6] 15 Input XRES Active high external reset with internal pull down. IO I, M P0[0] Analog column mux input. 17 IO I, M P0[2] Analog column mux input. 18 IO I, M P0[4] Analog column mux input. 19 IO I, M P0[6] Analog column mux input. Vdd Supply voltage. Power 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA, M Optional External Clock Input (EXTCLK). 16 20 A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] Vss M,I2C SCL, P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL, P1[1] Vss I2C Serial Clock (SCL). Vss 11 CY8C21334 20-Pin PSoC Device LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 9 CY8C21x34 Final Data Sheet 1.1.3 1. Pin Information 28-Pin Part Pinout Table 1-3. 28-Pin Part Pinout (SSOP) Type Pin No. Digital Analog 1 IO I, M P0[7] Analog column mux input. 2 IO I, M P0[5] Analog column mux input and column output. 3 IO I, M P0[3] Analog column mux input and column output, integrating input. 4 IO I, M P0[1] Analog column mux input, integrating input. 5 IO M P2[7] 6 IO M P2[5] 7 IO I, M P2[3] Direct switched capacitor block input. 8 IO I, M P2[1] Direct switched capacitor block input. 9 Power Name Vss Ground connection. 10 IO M P1[7] I2C Serial Clock (SCL). I2C Serial Data (SDA). 11 IO M P1[5] 12 IO M P1[3] 13 IO M P1[1] 14 Power Ground connection. I2C Serial Data (SDA). IO M P1[0] 16 IO M P1[2] 17 IO M P1[4] 18 IO M P1[6] 19 Input XRES Active high external reset with internal pull down. IO I, M P2[0] Direct switched capacitor block input. 21 IO I, M P2[2] Direct switched capacitor block input. 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog column mux input. 25 IO I, M P0[2] Analog column mux input. 26 IO I, M P0[4] Analog column mux input 27 IO I, M P0[6] Analog column mux input. Vdd Supply voltage. Power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4],EXTCLK,M P1[2],M P1[0],I2C SDA, M Optional External Clock Input (EXTCLK). 20 28 A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M,P2[7] M,P2[5] M, P2[3] M, P2[1] Vss M,I2C SCL, P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL, P1[1] Vss I2C Serial Clock (SCL). Vss 15 CY8C21534 28-Pin PSoC Device Description LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. December 17, 2004 Document No. 38-12025 Rev. *E 10 CY8C21x34 Final Data Sheet 1.1.4 1. Pin Information 32-Pin Part Pinout Table 1-4. 32-Pin Part Pinout (MLF*) IO M P2[7] 3 IO M P2[5] 4 IO M P2[3] 5 IO M P2[1] 6 IO 6 7 M Power IO 7 M Power P3[3] In CY8C21434 part. SMP Switch Mode Pump (SMP) connection to required external components in CY8C21634 part. P3[1] In CY8C21434 part. Vss Ground connection in CY8C21634 part. 8 IO M P1[7] I2C Serial Clock (SCL). I2C Serial Data (SDA). 9 IO M P1[5] 10 IO M P1[3] 11 IO M P1[1] 12 Power Ground connection. I2C Serial Data (SDA). IO M P1[0] 14 IO M P1[2] 15 IO M P1[4] 16 IO M P1[6] 17 Input XRES Active high external reset with internal pull down. IO M 19 IO M P3[2] 20 IO M P2[0] 21 IO M P2[2] 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog column mux input. 25 IO I, M P0[2] Analog column mux input. 26 IO I, M P0[4] Analog column mux input. 27 IO I, M P0[6] Analog column mux input. Vdd Supply voltage. IO I, M P0[7] Analog column mux input. 30 IO I, M P0[5] Analog column mux input. 31 IO I, M P0[3] Analog column mux input, integrating input. Vss Ground connection. Power 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES CY8C21634 32-Pin PSoC Device A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. * The MLF package has a center pad that must be connected to ground (Vss). December 17, 2004 MLF (Top View ) P3[0] 29 32 Power 1 2 3 4 5 6 7 8 Optional External Clock Input (EXTCLK). 18 28 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] I2C Serial Clock (SCL). Vss 13 Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M 2 Analog column mux input, integrating input. 32 31 30 29 28 27 26 25 P0[1] 9 10 11 12 13 14 15 16 I, M CY8C21434 32-Pin PSoC Device M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] IO Description Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M 1 Name Document No. 38-12025 Rev. *E 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 Analog MLF (Top View ) 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 Digital P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] Type Pin No. 11 2. Register Reference This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, reference the PSoCTM Mixed-Signal Array Technical Reference Manual. 2.1 Register Conventions 2.2 The register conventions specific to this section are listed in the following table. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific December 17, 2004 Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed. Document No. 38-12025 Rev. *E 12 CY8C21x34 Final Data Sheet 2. Register Reference Register Map 0 Table: User Space # # RW RW RW RW RW RW RW RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 RW RW RW RW RW RW RW CPU_F DAC_D CPU_SCR1 CPU_SCR0 Document No. 38-12025 Rev. *E C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW Addr (0,Hex) # Name RW RW RW 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access December 17, 2004 ASE10CR0 Addr (0,Hex) 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W AMUXCFG 61 DBB00DR2 22 RW PWM_CR 62 DBB00CR0 23 # 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # ADC0_CR 68 DCB02DR1 29 W ADC1_CR 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # TMP0_DR 6C DCB03DR1 2D W TMP1_DR 6D DCB03DR2 2E RW TMP2_DR 6E DCB03CR0 2F # TMP3_DR 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. Name Access Addr (0,Hex) Name Access Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 RW RW RW RW RW RW # RW # RW RW RW RW RW RW RC W RW RW RL RW # # 13 CY8C21x34 Final Data Sheet 2. Register Reference Register Map 1 Table: Configuration Space RW RW RW RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 MUX_CR0 D8 MUX_CR1 D9 MUX_CR2 DA MUX_CR3 DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 ADC0_TR E5 ADC1_TR E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC DAC_CR FD CPU_SCR1 FE CPU_SCR0 FF Document No. 38-12025 Rev. *E Access RW RW RW RW RW RW Addr (1,Hex) RW RW RW Name RW RW RW RW RW 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access ASE10CR0 Addr (1,Hex) December 17, 2004 Name 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 DBB00IN 21 RW CLK_CR1 61 DBB00OU 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW CMP_GO_EN 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B CLK_CR3 6B DCB03FN 2C RW TMP0_DR 6C DCB03IN 2D RW TMP1_DR 6D DCB03OU 2E RW TMP2_DR 6E 2F TMP3_DR 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed. Access Addr (1,Hex) Name Access Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RL RW RW # # 14 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC as specified, except where noted. 5.25 SLIMO Mode = 0 Refer to Table 3-14 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. 5.25 SLIMO Mode=1 4.75 Vdd Voltage Vdd Voltage lid ng Va rati n e io Op Reg 4.75 3.60 3.00 3.00 2.40 2.40 93 kHz 12 MHz 3 MHz SLIMO Mode=0 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 24 MHz 93 kHz 6 MHz 12 MHz 24 MHz IMO Frequency CPU Frequency Figure 3-1a. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol Unit of Measure Symbol Unit of Measure oC degree Celsius W microwatts dB decibels mA milli-ampere fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts k kilohm ohm MHz megahertz pA picoampere M megaohm pF picofarad A microampere pp peak-to-peak F microfarad ppm H microhenry ps picosecond s microsecond sps samples per second V microvolts sigma: one standard deviation microvolts root-mean-square V volts Vrms December 17, 2004 parts per million Document No. 38-12025 Rev. *E 15 CY8C21x34 Final Data Sheet 3.1 3. Electrical Specifications Absolute Maximum Ratings Table 3-2. Absolute Maximum Ratings Symbol Description Min Typ Max Units TSTG Storage Temperature -55 - +100 oC TA Ambient Temperature with Power Applied -40 - +85 oC Vdd Supply Voltage on Vdd Relative to Vss -0.5 - +6.0 V VIO DC Input Voltage Vss - 0.5 - Vdd + 0.5 V VIOZ DC Voltage Applied to Tri-state Vss - 0.5 - Vdd + 0.5 V IMIO Maximum Current into any Port Pin -25 - +50 mA ESD Electro Static Discharge Voltage 2000 - - V LU Latch-up Current - - 200 mA 3.2 Notes Higher storage temperatures will reduce data retention time. Human Body Model ESD. Operating Temperature Table 3-3. Operating Temperature Symbol Description Min Typ Max Units TA Ambient Temperature -40 - +85 oC TJ Junction Temperature -40 - +100 oC 3.3 3.3.1 Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 32. The user must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-4. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 2.40 - 5.25 V See table titled "DC POR and LVD Specifications" on page 20. IDD Supply Current, IMO = 24 MHz - 3 4 mA Conditions are Vdd = 5.0V, TA = 25oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. IDD3 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.2 2 mA Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. IDD27 Supply Current, IMO = 6 MHz using SLIMO mode. - 1.1 1.5 mA Conditions are Vdd = 2.55V, TA = 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. ISB27 Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. - 2.5 3. A Vdd = 2.55V, 0oC TA 40oC. ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. - 2.8 5 A Vdd = 3.3V, -40oC TA 85oC. VREF Reference Voltage (Bandgap) 1.28 1.30 1.32 V Trimmed for appropriate Vdd. Vdd = 3.0V to 5.25V. VREF27 Reference Voltage (Bandgap) 1.16 1.30 1.33 V Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. AGND Analog Ground VREF - 0.003 VREF VREF + 0.003 V December 17, 2004 Document No. 38-12025 Rev. *E 16 CY8C21x34 Final Data Sheet 3.3.2 3. Electrical Specifications DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 3-5. 5V and 3.3V DC GPIO Specifications Symbol Description Min Typ Max Units Notes 4 5.6 8 k Pull-down Resistor 4 5.6 8 k High Output Level Vdd - 1.0 - - V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOL Low Output Level - - 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 0.8 V Vdd = 3.0 to 5.25. V Vdd = 3.0 to 5.25. RPU Pull-up Resistor RPD VOH VIL Input Low Level - - VIH Input High Level 2.1 - VH Input Hysteresis - 60 - mV IIL Input Leakage (Absolute Value) - 1 - nA Gross tested to 1 A. CIN Capacitive Load on Pins as Input - 3.5 10 pF Package and pin dependent. Temp = 25oC. COUT Capacitive Load on Pins as Output - 3.5 10 pF Package and pin dependent. Temp = 25oC. Table 3-6. 2.7V DC GPIO Specifications Symbol Description Min Typ Max Units Notes 4 5.6 8 k Pull-down Resistor 4 5.6 8 k High Output Level Vdd - 0.4 - - V IOH = 2.5 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). VOL Low Output Level - - 0.75 V IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). RPU Pull-up Resistor RPD VOH VIL Input Low Level - - 0.75 V Vdd = 2.4 to 3.0. VIH Input High Level 2.0 - - V Vdd = 2.4 to 3.0. VH Input Hysteresis - 90 - mV IIL Input Leakage (Absolute Value) - 1 - nA Gross tested to 1 A. CIN Capacitive Load on Pins as Input - 3.5 10 pF Package and pin dependent. Temp = 25oC. COUT Capacitive Load on Pins as Output - 3.5 10 pF Package and pin dependent. Temp = 25oC. December 17, 2004 Document No. 38-12025 Rev. *E 17 CY8C21x34 Final Data Sheet 3.3.3 3. Electrical Specifications DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-7. 5V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units VOSOA Input Offset Voltage (absolute value) - 2.5 15 mV TCVOSOA Average Input Offset Voltage Drift - 10 - V/oC Notes IEBOA Input Leakage Current (Port 0 Analog Pins) - 200 - pA Gross tested to 1 A. CINOA Input Capacitance (Port 0 Analog Pins) - 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0.0 - Vdd - 1 V GOLOA Open Loop Gain - 80 - dB ISOA Amplifier Supply Current - 10 30 A Table 3-8. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units VOSOA Input Offset Voltage (absolute value) - 2.5 15 mV TCVOSOA Average Input Offset Voltage Drift - 10 - V/oC Notes IEBOA Input Leakage Current (Port 0 Analog Pins) - 200 - pA Gross tested to 1 A. CINOA Input Capacitance (Port 0 Analog Pins) - 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0 - Vdd - 1 V GOLOA Open Loop Gain - 80 - dB ISOA Amplifier Supply Current - 10 30 A Table 3-9. 2.7V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units VOSOA Input Offset Voltage (absolute value) - 2.5 15 mV V/oC Notes TCVOSOA Average Input Offset Voltage Drift - 10 - IEBOA Input Leakage Current (Port 0 Analog Pins) - 200 - pA Gross tested to 1 A. CINOA Input Capacitance (Port 0 Analog Pins) - 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0 - Vdd - 1 V GOLOA Open Loop Gain - 80 - dB ISOA Amplifier Supply Current - 10 30 A December 17, 2004 Document No. 38-12025 Rev. *E 18 CY8C21x34 Final Data Sheet 3.3.4 3. Electrical Specifications DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-10. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP5V 5V Output Voltage from Pump 4.75 5.0 5.25 V Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. VPUMP3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. VPUMP2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 2.55V. IPUMP Available Output Current VBAT = 1.8V, VPUMP = 5.0V 5 - - mA SMP trip voltage is set to 5.0V. VBAT = 1.5V, VPUMP = 3.25V 8 - - mA SMP trip voltage is set to 3.25V. VBAT = 1.3V, VPUMP = 2.55V 8 - - mA SMP trip voltage is set to 2.55V. VBAT5V Input Voltage Range from Battery 1.8 - 5.0 V Configuration of footnote.a SMP trip voltage is set to 5.0V. VBAT3V Input Voltage Range from Battery 1.0 - 3.3 V Configuration of footnote.a SMP trip voltage is set to 3.25V. VBAT2V Input Voltage Range from Battery 1.0 - 2.8 V Configuration of footnote.a SMP trip voltage is set to 2.55V. VBATSTART Minimum Input Voltage from Battery to Start Pump 1.2 - - V Configuration of footnote.a 0oC TA 100. 1.25V at TA = -40oC. VPUMP_Line Line Regulation (over Vi range) - 5 - %VO Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 312 on page 20. VPUMP_Load Load Regulation - 5 - %VO Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 312 on page 20. VPUMP_Ripple Output Voltage Ripple (depends on cap/load) - 100 - mVpp Configuration of footnote.a Load is 5 mA. E3 Efficiency 35 50 - % Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V. E2 Efficiency 35 80 - % For I load = 1mA, VPUMP = 2.55V, VBAT = 1.3V, 10 uH inductor, 1 uF capacitor, and Schottky diode. FPUMP Switching Frequency - 1.3 - MHz DCPUMP Switching Duty Cycle - 50 - % Configuration of footnote.a a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 3-2. D1 Vdd V PUMP L1 V BAT + SMP Battery PSoCTM C1 V ss Figure 3-2. Basic Switch Mode Pump Circuit December 17, 2004 Document No. 38-12025 Rev. *E 19 CY8C21x34 Final Data Sheet 3.3.5 3. Electrical Specifications DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-11. DC Analog Mux Bus Specifications Symbol Description Min Typ Max Units RSW Switch Resistance to Common Analog Bus - - 400 800 RVDD Resistance of Initialization Switch to Vdd - - 800 3.3.6 Notes Vdd 2.7V 2.4V Vdd 2.7V DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-12. DC POR and LVD Specifications Symbol Description Min Typ Max Units Vdd Value for PPOR Trip VPPOR0 PORLEV[1:0] = 00b VPPOR1 PORLEV[1:0] = 01b VPPOR2 PORLEV[1:0] = 10b - 2.36 2.40 V 2.82 2.95 V 4.55 4.70 V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Vdd Value for LVD Trip VLVD0 VM[2:0] = 000b 2.40 2.45 2.51a V VLVD1 VM[2:0] = 001b 2.85 2.92 2.99b V VLVD2 VM[2:0] = 010b 2.95 3.02 3.09 V VLVD3 VM[2:0] = 011b 3.06 3.13 3.20 V VLVD4 VM[2:0] = 100b 4.37 4.48 4.55 V VLVD5 VM[2:0] = 101b 4.50 4.64 4.75 V VLVD6 VM[2:0] = 110b 4.62 4.73 4.83 V VLVD7 VM[2:0] = 111b 4.71 4.81 4.95 V Vdd Value for PUMP Trip VPUMP0 VM[2:0] = 000b 2.45 2.55 2.62c V VPUMP1 VM[2:0] = 001b 2.96 3.02 3.09 V VPUMP2 VM[2:0] = 010b 3.03 3.10 3.16 V VPUMP3 VM[2:0] = 011b 3.18 3.25 3.32d V VPUMP4 VM[2:0] = 100b 4.54 4.64 4.74 V VPUMP5 VM[2:0] = 101b 4.62 4.73 4.83 V VPUMP6 VM[2:0] = 110b 4.71 4.82 4.92 V VPUMP7 VM[2:0] = 111b 4.89 5.00 5.12 V a. b. c. d. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. Always greater than 50 mV above VLVD0. Always greater than 50 mV above VLVD3. December 17, 2004 Document No. 38-12025 Rev. *E 20 CY8C21x34 Final Data Sheet 3.3.7 3. Electrical Specifications DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-13. DC Programming Specifications Symbol Description Min Typ Max Units Notes VddIWRITE Supply Voltage for Flash Write Operations 2.70 - - V IDDP Supply Current During Programming or Verify - 5 25 mA VILP Input Low Voltage During Programming or Verify - - 0.8 V VIHP Input High Voltage During Programming or Verify 2.2 - - V IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify - - 0.2 mA Driving internal pull-down resistor. IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify - - 1.5 mA Driving internal pull-down resistor. VOLV Output Low Voltage During Programming or Verify - - Vss + 0.75 V VOHV Output High Voltage During Programming or Verify Vdd - 1.0 - Vdd V FlashENPB Flash Endurance (per block) 50,000 - - - Erase/write cycles per block. FlashENT Flash Endurance (total)a 1,800,000 - - - Erase/write cycles. FlashDR Flash Data Retention 10 - - Years a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. December 17, 2004 Document No. 38-12025 Rev. *E 21 CY8C21x34 Final Data Sheet 3.4 3. Electrical Specifications AC Electrical Characteristics 3.4.1 AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-14. 5V and 3.3V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FIMO24 Internal Main Oscillator Frequency for 24 MHz 23.4 24 24.6a,b,c MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 0. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. FCPU1 CPU Frequency (5V Nominal) 0.93 24 24.6a,b MHz 24 MHz only for SLIMO mode = 0. FCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.3b,c MHz FBLK5 Digital PSoC Block Frequency0(5V Nominal) 0 48 49.2a,b,d MHz FBLK33 Digital PSoC Block Frequency (3.3V Nominal) 0 24 24.6b,d MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz Jitter32k 32 kHz Period Jitter - 100 200 ns TXRST External Reset Pulse Width 10 - - s DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size - 50 - kHz Fout48M 48 MHz Output Frequency 46.8 48.0 49.2a,c MHz Jitter24M1 24 MHz Period Jitter (IMO) - 600 FMAX Maximum frequency of signal on row input or row output. - - 12.3 MHz TRAMP Supply Ramp Time 0 - - s a. b. c. d. Refer to the AC Digital Block Specifications below. Trimmed. Utilizing factory trim values. ps 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. Table 3-15. 2.7V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FIMO12 Internal Main Oscillator Frequency for 12 MHz 11.5 120 12.7a,b,c MHz Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz Trimmed for 2.7V operation using factory trim values. See Figure 3-1b on page 15. SLIMO mode = 1. FCPU1 CPU Frequency (2.7V Nominal) 0.093 3 3.15a,b MHz 24 MHz only for SLIMO mode = 0. FBLK27 Digital PSoC Block Frequency (2.7V Nominal) 0 12 12.5a,b,c MHz Refer to the AC Digital Block Specifications below. F32K1 Internal Low Speed Oscillator Frequency 8 32 96 kHz Jitter32k 32 kHz Period Jitter - 150 200 ns TXRST External Reset Pulse Width 10 - - s FMAX Maximum frequency of signal on row input or row output. - - 12.3 MHz TRAMP Supply Ramp Time 0 - - s a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency for user modules. December 17, 2004 Document No. 38-12025 Rev. *E 22 CY8C21x34 Final Data Sheet 3. Electrical Specifications Jitter24M1 F 24M Figure 3-3. 24 MHz Period Jitter (IMO) Timing Diagram Jitter32k F 32K1 Figure 3-4. 32 kHz Period Jitter (ILO) Timing Diagram December 17, 2004 Document No. 38-12025 Rev. *E 23 CY8C21x34 Final Data Sheet 3.4.2 3. Electrical Specifications AC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-16. 5V and 3.3V AC GPIO Specifications Symbol FGPIO Description Min Typ Max Units Notes GPIO Operating Frequency 0 - 12 MHz Normal Strong Mode TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 - 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 - 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 7 27 - ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 7 22 - ns Vdd = 3 to 5.25V, 10% - 90% Table 3-17. 2.7V AC GPIO Specifications Symbol FGPIO Description Min Typ Max Units Notes GPIO Operating Frequency 0 - 3 MHz Normal Strong Mode TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 6 - 50 ns Vdd = 2.4 to 3.0V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 6 - 50 ns Vdd = 2.4 to 3.0V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 3-5. GPIO Timing Diagram December 17, 2004 Document No. 38-12025 Rev. *E 24 CY8C21x34 Final Data Sheet 3.4.3 3. Electrical Specifications AC Operational Amplifier Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-18. AC Operational Amplifier Specifications Symbol TCOMP 3.4.4 Description Min Typ Max Comparator Mode Response Time, 50 mV Overdrive Units 100 200 ns ns Notes Vdd 3.0V. 2.4V < Vcc < 3.0V. AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-19. AC Analog Mux Bus Specifications Symbol FSW 3.4.5 Description Min Switch Rate Typ - Max - Units 3.17 Notes MHz AC Digital Block Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-20. 5V and 3.3V AC Digital Block Specifications Function Description Min Typ All Functions Maximum Block Clocking Frequency (> 4.75V) Timer Capture Pulse Width 50a - Maximum Frequency, No Capture - Maximum Frequency, With or Without Capture - Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Max Units Notes 49.2 MHz 4.75V < Vdd < 5.25V. 24.6 MHz 3.0V < Vdd < 4.75V. - ns - 49.2 MHz - 24.6 MHz 50 - - ns - - 49.2 MHz - - 24.6 MHz Asynchronous Restart Mode 20 - - ns Synchronous Restart Mode 50 - - ns Disable Mode 50 - - ns - - 49.2 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (PRS Mode) - - 49.2 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (CRC Mode) - - 24.6 MHz SPIM Maximum Input Clock Frequency - - 8.2 MHz SPIS Maximum Input Clock Frequency - - 4.1 MHz Width of SS_ Negated Between Transmissions 50 - - ns Transmitter Maximum Input Clock Frequency - - 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Receiver Maximum Input Clock Frequency - - 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Counter Dead Band Maximum Block Clocking Frequency (< 4.75V) 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Kill Pulse Width: Maximum Frequency Maximum data rate at 4.1 MHz due to 2 x over clocking. a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). December 17, 2004 Document No. 38-12025 Rev. *E 25 CY8C21x34 Final Data Sheet 3. Electrical Specifications Table 3-21. 2.7V AC Digital Block Specifications Function Description Min All Functions Maximum Block Clocking Frequency Timer Capture Pulse Width 100a Maximum Frequency, With or Without Capture - Enable Pulse Width Typ Max Units Notes 12.7 MHz - - ns - 12.7 MHz 100 - - ns Maximum Frequency, No Enable Input - - 12.7 MHz Maximum Frequency, Enable Input - - 12.7 MHz Asynchronous Restart Mode 20 - - ns Synchronous Restart Mode 100 - - ns Disable Mode 100 - - ns - - 12.7 MHz CRCPRS Maximum Input Clock Frequency (PRS Mode) - - 12.7 MHz CRCPRS Maximum Input Clock Frequency (CRC Mode) - - 12.7 MHz SPIM Maximum Input Clock Frequency - - 6.35 MHz SPIS Maximum Input Clock Frequency - - 4.1 MHz Width of SS_ Negated Between Transmissions 100 - - ns Transmitter Maximum Input Clock Frequency - - 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Receiver Maximum Input Clock Frequency - - 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Counter Dead Band 2.4V < Vdd < 3.0V. Kill Pulse Width: Maximum Frequency Maximum data rate at 3.17 MHz due to 2 x over clocking. a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). December 17, 2004 Document No. 38-12025 Rev. *E 26 CY8C21x34 Final Data Sheet 3.4.6 3. Electrical Specifications AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-22. 5V AC External Clock Specifications Symbol FOSCEXT Description Min Frequency Typ Max Units 0.093 - 24.6 MHz ns - High Period 20.6 - 5300 - Low Period 20.6 - - ns - Power Up IMO to Switch 150 - - s Notes Table 3-23. 3.3V AC External Clock Specifications Symbol Description Min Typ FOSCEXT Frequency with CPU Clock divide by 1 0.093 - FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - High Period with CPU Clock divide by 1 - Low Period with CPU Clock divide by 1 - Power Up IMO to Switch 150 Max Units Notes 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. - 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 41.7 - 5300 ns 41.7 - - ns - - s Table 3-24. 2.7V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency with CPU Clock divide by 1 0.093 - 3.080 MHz Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 6.35 MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. ns - High Period with CPU Clock divide by 1 160 - 5300 - Low Period with CPU Clock divide by 1 160 - - ns - Power Up IMO to Switch 150 - - s December 17, 2004 Document No. 38-12025 Rev. *E 27 CY8C21x34 Final Data Sheet 3.4.7 3. Electrical Specifications AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-25. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 - 20 ns TFSCLK Fall Time of SCLK 1 - 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 - - ns THSCLK Data Hold Time from Falling Edge of SCLK 40 - - ns FSCLK Frequency of SCLK 0 - 8 MHz TERASEB Flash Erase Time (Block) - 15 - ms TWRITE Flash Block Write Time - 30 - ms TDSCLK Data Out Delay from Falling Edge of SCLK - - 45 ns 3.6 < Vdd TDSCLK3 Data Out Delay from Falling Edge of SCLK - - 50 ns 3.0 Vdd 3.6 TDSCLK2 Data Out Delay from Falling Edge of SCLK - - 70 ns 2.4 Vdd 3.0 3.4.8 AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 3-26. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V Standard Mode Symbol Description Min Fast Mode Max Min Max Units FSCLI2C SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 - 0.6 - s TLOWI2C LOW Period of the SCL Clock 4.7 - 1.3 - s THIGHI2C HIGH Period of the SCL Clock 4.0 - 0.6 - s TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 - 0.6 - s THDDATI2C Data Hold Time 0 - 0 - s TSUDATI2C Data Set-up Time 250 - 100a - ns TSUSTOI2C Set-up Time for STOP Condition 4.0 - 0.6 - s TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 - 1.3 - s TSPI2C Pulse Width of spikes are suppressed by the input filter. - 0 50 ns - Notes a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Table 3-27. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Standard Mode Symbol Description Min Fast Mode Max Min Max Units FSCLI2C SCL Clock Frequency 0 100 - - kHz THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 - - - s TLOWI2C LOW Period of the SCL Clock 4.7 - - - s THIGHI2C HIGH Period of the SCL Clock 4.0 - - - s TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 - - - s THDDATI2C Data Hold Time 0 - - - s December 17, 2004 Document No. 38-12025 Rev. *E Notes 28 CY8C21x34 Final Data Sheet 3. Electrical Specifications Table 3-27. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued) Standard Mode Symbol Description Min Fast Mode Max Min Max Units TSUDATI2C Data Set-up Time 250 - - - ns TSUSTOI2C Set-up Time for STOP Condition 4.0 - - - s TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 - - - s TSPI2C Pulse Width of spikes are suppressed by the input filter. - - - ns - SDA TLOWI2C TSUDATI2C THDSTAI2C Notes TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 3-6. Definition for Timing for Fast/Standard Mode on the I2C Bus December 17, 2004 Document No. 38-12025 Rev. *E 29 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 4.1 Packaging Dimensions PIN 1 ID 8 1 MIN. MAX. DIMENSIONS IN INCHES[MM] * 0.291[7.391] 0.299[7.594] REFERENCE JEDEC MO-119 * 0.394[10.007] 0.419[10.642] 9 16 PART # S16.3 STANDARD PKG. SZ16.3 LEAD FREE PKG. 0.026[0.660] 0.032[0.812] SEATING PLANE 0.397[10.083] 0.413[10.490] 0.092[2.336] 0.105[2.667] * 0.004[0.101] 0.050[1.270] TYP. 0.004[0.101] 0.0118[0.299] * 0.015[0.381] 0.050[1.270] 0.0091[0.231] 0.0125[0.317] 0.013[0.330] 0.019[0.482] 51-85022 *B Figure 4-1. 16-Lead (150-Mil) SOIC December 17, 2004 Document No. 38-12025 Rev. *E 30 CY8C21x34 Final Data Sheet 4. Packaging Information 51-85077 *C Figure 4-2. 20-Lead (210-MIL) SSOP 51-85079 - *C Figure 4-3. 28-Lead (210-Mil) SSOP December 17, 2004 Document No. 38-12025 Rev. *E 31 CY8C21x34 Final Data Sheet 4. Packaging Information 51-85188 ** Figure 4-4. 32-Lead (5x5 mm) MLF 4.2 Thermal Impedances Table 4-1. Thermal Impedances per Package Package Typical JA * 16 SOIC 96 C/W 20 SSOP 95 oC/W 28 SSOP 101 oC/W 32 MLF 22 oC/W o * TJ = TA + Power x JA December 17, 2004 Document No. 38-12025 Rev. *E 32 CY8C21x34 Final Data Sheet 4.3 4. Packaging Information Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 4-2. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature 16 SOIC 220oC 260oC 20 SSOP 240oC 260oC 28 SSOP 240oC 260oC 32 MLF 220oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. December 17, 2004 Document No. 38-12025 Rev. *E 33 5. Ordering Information The following table lists the CY8C21x34 PSoC device's key package features and ordering codes. Temperature Range Digital Blocks Analog Blocks Digital IO Pins Analog Outputs XRES Pin 8K 512 Yes -40C to +85C 4 4 12 12a 0 No 16 Pin (150-Mil) SOIC (Tape and Reel) CY8C21234-24SXIT 8K 512 Yes -40C to +85C 4 4 12 12a 0 No 20 Pin (300-Mil) SSOP CY8C21334-24PVXI 8K 512 No -40C to +85C 4 4 16 16a 0 Yes 20 Pin (300-Mil) SSOP (Tape and Reel) CY8C21334-24PVXIT 8K 512 No -40C to +85C 4 4 16 16a 0 Yes 28 Pin (210-Mil) SSOP CY8C21534-24PVXI 8K 512 No -40C to +85C 4 4 24 24a 0 Yes 28 Pin (210-Mil) SSOP (Tape and Reel) CY8C21534-24PVXIT 8K 512 No -40C to +85C 4 4 24 24a 0 Yes 32 Pin (5x5) MLF b CY8C21434-24LFXI 8K 512 No -40C to +85C 4 4 28 28a 0 Yes CY8C21434-24LFXIT 8K 512 No -40C to +85C 4 4 28 28a 0 Yes 32 Pin (5x5) MLF b CY8C21634-24LFXI 8K 512 Yes -40C to +85C 4 4 26 26a 0 Yes 32 Pin (5x5) MLF b (Tape and Reel) CY8C21634-24LFXIT 8K 512 Yes -40C to +85C 4 4 26 26a 0 Yes Package 32 Pin (5x5) MLF (Tape and Reel) b Analog Switch Mode Pump CY8C21234-24SXI Inputs a SRAM (Bytes) 16 Pin (150-Mil) SOIC Ordering Code Flash (Bytes) CY8C21x34 PSoC Device Key Features and Ordering Information a. All Digital IO Pins also connect to the common analog mux. b. Refer to the "32-Pin Part Pinout" on page 11 for pin differences. 5.1 Ordering Code Definitions CY 8 C 21 xxx-24xx Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = MLF Pb-Free AX = TQFP Pb-Free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress December 17, 2004 Document No. 38-12025 Rev. *E 34 6. Sales and Service Information To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled "Getting Started" on page 4 in this document. Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: Facsimile: 800.669.0557 425.787.4641 Web Sites: Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm 6.1 Revision History Document Title: CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 PSoC Mixed-Signal Array Final Data Sheet Document Number: 38-12025 Origin of Revision ECN # Issue Date Description of Change Change ** 227340 05/19/2004 HMT New silicon and document (Revision **). *A 235992 See ECN SFV Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part. Revised the register mapping tables. Added a SSOP 28-pin part. *B 248572 See ECN SFV Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634. 277832 See ECN HMT Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs. Update PSoC Characteristics table. Update diagrams and specs. Final. *D 285293 See ECN HMT Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table. *E 301739 See ECN HMT DC Chip-Level Specification changes. Update links to new CY.com Portal. *C Distribution: External/Public 6.2 Posting: None Copyrights and Code Protection (c) Cypress MicroSystems, Inc. 2004. All rights reserved. PSoCTM, PSoC DesignerTM, and Programmable System-on-ChipTM are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress MicroSystems. Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products. December 17, 2004 (c) Cypress MicroSystems, Inc. 2004 -- Document No. 38-12025 Rev. *E 35