fax id: 7023 1CY 29FCT8 18T CY29FCT818T Diagnostic Scan Register Features circuits, where it is desirable to load known data at a specific location in the circuit and to read the data at that location. * Function, pinout and drive compatible with FCT, F Logic and AM29818 * FCT-C speed at 6.0 ns max. (Com'l), * Reduced VOH (typically = 3.3V) versions of equivalent FCT functions * Edge-rate control circuitry for significantly improved noise characteristics * Power-off disable feature * Matched rise and fall times * Fully compatible with TTL input and output logic levels * Sink current 64 mA (Com'l), 20 mA (Mil) Source current 32 mA (Com'l), 3 mA (Mil) * 8-Bit pipeline and shadow register * ESD > 2000V The shadow registers can load data from the output of the FCT818T, and can be used as a right-shift register with bit-serial input SDI and output SDO, using DCLK. The data register input is multiplexed to enable loading from the shadow register or from the data input pins using PCLK. Note that data can be loaded simultaneously from the shadow register to the pipeline register, and from the pipeline register to the shadow register provided set-up and hold time requirements are satisfied with respect to the two independent clock inputs. In a typical application, the general-purpose register in the FCT818T replaces an 8-bit data register in the normal data path of a system. The shadow register is placed in an auxiliary bit-serial loop which is used for diagnostics. During diagnostic operation, data is shifted serially into the shadow register, then transferred to the general purpose register to load a known value into the data path. To read the contents at that point in the data path, the data is transferred from the data register into the shadow register, then shifted serially in the auxiliary diagnostic loop to make it accessible to the diagnostics controller. This data is then compared with the expected value to diagnose faulty operation of the sequential circuit. Functional Description The FCT818T contains a high-speed 8-bit general-purpose data pipeline register and a high-speed 8-bit shadow register. The general-purpose register can be used in an 8-bit wide data path for a normal system application. The shadow register is designed for applications, such as diagnostics in sequential Logic Block Diagram The outputs are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations DIP, SOIC, QSOP Top View D6 D5 D4 NC D3 D2 D1 LCC Top View D0 -D 7 SDI 8-BIT SHADOW REGISTER DCLK CLK 11 10 9 8 7 6 5 SDO S0 -S 7 8 D Q D7 SDI GND NC PCLK SDO Y7 12 13 14 15 16 17 18 D0 DCLK OE NC Vcc MODE Y0 Y4 NC Y3 Y2 Y1 MUX Y5 MODE Y6 19 2021 222324 25 4 3 2 1 28 27 26 8 PCLK OE 1 24 VCC DCLK 2 23 MODE D0 3 22 Y0 D1 4 21 Y1 D2 5 20 Y2 D3 6 19 Y3 D4 7 18 Y4 D5 8 17 Y5 D6 9 16 Y6 D7 10 15 Y7 SDI 11 14 SDO GND 12 13 PCLK 8-BIT PIPELINE REGISTER 8 P0 -P 7 OE 8 Y0 -Y 7 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 May 1994 - Revised March 17, 1997 CY29FCT818T Function Table[1] Inputs MODE SDI L X L X H H H L H X Inputs DCLK Shadow Register Pipeline Register NA S7 S0SDI SiSi-1 NA PiDi Load Pipeline Register from Data Input L H SDI SiYi Hold NA NA NA PiSi Load Shadow Register from Y Output Hold Shadow Register; D7-D0 Output Enabled Load Pipeline Register from Shadow Register PCLK SDO X S7 X X X X Maximum Ratings[2, 3] Operation Serial Shift; D7-D0 Output Disabled Power Dissipation.......................................................... 0.5W Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Operating Range Ambient Temperature with Power Applied............................................. -65C to +135C Range Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V Range Ambient Temperature VCC Commercial All -40C to +85C 5V 5% Military[4] All -55C to +125C 5V 10% DC Output Voltage ......................................... -0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin)....... 120 mA Electrical Characteristics Over the Operating Range Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions Min. Typ.[5] Max. Unit VCC=Min., IOH=-32 mA Com'l 2.0 VCC=Min., IOH=-15 mA Com'l 2.4 3.3 V VCC=Min., IOH=-3 mA Mil 2.4 3.3 VCC=Min., IOL=64 mA Com'l 0.3 0.55 V VCC=Min., IOL=20 mA Mil 0.3 0.55 V V V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V VH Hysteresis[6] All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA -0.7 -1.2 V II Input HIGH Current VCC=Max., VIN=VCC 5 A IIH Input HIGH Current VCC=Max., VIN=2.7V 1 A IIL Input LOW Current VCC=Max., VIN=0.5V 1 A IOZH Off State HIGH-Level Output Current VCC=Max., VOUT=2.7V 10 A IOZL Off State LOW-Level Output Current VCC=Max., VOUT=0.5V -10 A IOS Output Short Circuit Current[7] VCC=Max., VOUT=0.0V -225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V 1 A 0.8 -60 -120 V V Notes: 1. NA = Not Applicable 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V CC or ground. 4. TA is the "instant on" case temperature. 5. Typical values are at VCC=5.0V, TA=+25C ambient. 6. This parameter is guaranteed but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameters tests. In any sequence of parameter tests, IOS tests should be performed last. 2 CY29FCT818T Capacitance[8] Parameter Description Test Conditions Typ.[5] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Power Supply Characteristics Parameter ICC Description Quiescent Power Supply Current Test Conditions VCC=Max., VIN<0.2V, VIN>VCC-0.2V Typ.[5] Max. Unit 0.2 1.5 mA 0.5 2.0 mA ICC Quiescent Power Supply Current (TTL inputs HIGH) ICCD Dynamic Power Supply Current[9] VCC=Max., 50% Duty Cycle, Outputs Open, One Input Toggling, OE=GND, VIN<0.2V or VIN>VCC-0.2V 0.25 mA/MHz IC Total Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, One Bit Toggling at f1=5 MHz, OE=GND, VIN<0.2V or VIN>VCC-0.2V 5.3 mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, One Bit Toggling at f1=5 MHz, OE=GND, VIN=3.4V or VIN=GND 7.3 mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, Eight Bits and Four Controls Toggling, f1=5 MHz, OE=GND, VIN<0.2V or VIN>VCC-0.2V 17.8[11] mA VCC=Max., 50% Duty Cycle, Outputs Open, f0=10 MHz, Eight Bits and Four Controls Toggling, f1=5 MHz, OE=GND, VIN=3.4V or VIN=GND 30.8[11] mA VCC=Max., VIN=3.4V, f1=0, Outputs Open Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = I QUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = I CC+ICCDHNT+ICCD(f0/2 + f 1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 3 [8] CY29FCT818T Switching Characteristics Over the Operating Range[12] FCT818AT Military Parameter tPD tS tH tPLZ Description Min. Propagation Delay PCLK to Y MODE to SDO SDI to SDO DCLK to SDO Max. FCT818CT Commercial Commercial Min. Min. 12 18 18 30 Max. 9 16 15 25 Max. Unit Fig. No.[13] 6.0 7.2 7.1 7.2 ns ns ns ns 5 6 3 5 Set-Up Time D to PCLK MODE to PCLK Y to DCLK MODE to DCLK SDI to DCLK DCLK to PCLK PCLK to DCLK 6 15 5 12 10 15 45 4 15 5 12 10 15 40 2.0 3.5 2.0 3.5 3.5 3.5 8.5 ns ns ns ns ns ns ns 4 Hold Time D to PCLK MODE to PCLK Y to DCLK MODE to DCLK SDI to DCLK 2 0 5 5 0 2 0 5 2 0 1.5 0 1.5 1.5 0 ns ns ns ns ns 4 Output Disable Time LOW OE to Y DCLK to D 20 45 15 45 5.5 5.5 ns ns 7 5 tPHZ Output Disable Time HIGH OE to Y DCLK to D 30 90 25 80 8.0 8.0 ns ns 8 5 tPZL Output Enable Time LOW OE to Y DCLK to D 20 35 15 25 8.0 9.0 ns ns 7 5 tPZH Output Enable Time HIGH OE to Y DCLK to D 20 30 15 25 8.5 9.0 ns ns 8 5 tW Pulse Width PCLK (HIGH and LOW) DCLK (HIGH and LOW) ns ns 5 5 Speed (ns) 6.0 9.0 12.0 Ordering Code 15 25 10 15 Package Name 5.0 5.0 Package Type CY29FCT818CTPC P13/13A CY29FCT818CTQC Q13 24-Lead (150-Mil) QSOP CY29FCT818CTSOC S13 24-Lead (300-Mil) Molded SOIC CY29FCT818ATPC P13/13A 24-Lead (300-Mil) Molded DIP 24-Lead (300-Mil) Molded DIP CY29FCT818ATSOC S13 24-Lead (300-Mil) Molded SOIC CY29FCT818ATDMB D14 24-Lead (300-Mil) CerDIP CY29FCT818ATLMB L64 28-Square Leadless Chip Carrier Notes: 12. Minimum limits are guaranteed but not tested on Propagation Delays. 13. See "Parameter Measurement Information" in the General Information section. Document #: 38-00275-B 4 Operating Range Commercial Commercial Military CY29FCT818T Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 28-Square Leadless Chip Carrier L64 D-9 Config.A MIL-STD-1835 C-4 24-Lead (300-Mil) Molded DIP P13/P13A 5 CY29FCT818T Package Diagrams (continued) 24-Lead Quarter Size Outline Q13 24-Lead (300-Mil) Molded SOIC S13 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.