Diagnostic Scan Register
fax id: 7023
CY29FCT818T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
May 1994 – Revised March 17, 1997
1CY29FCT818T
Features
•Function, pinout and drive compatible with FCT , F Logic
and AM29818
•FCT-C speed at 6.0 ns max. (Com’l),
•Reduced VOH (typically = 3.3V) versions of equiv ale nt
FCT functions
•Edge-rate con trol circuitry for s ignificantly improved
noise c h aracteristics
•Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL inp ut and outp ut logic levels
• Sink current 64 mA (Com’l) ,
20 mA (Mil)
Source current 32 mA (Com’l),
3 mA (Mil)
•8-Bit pipeline and shadow register
•ESD > 2000V
Functional Description
The FCT818T contains a high-speed 8-bit general-purpose
data pipeline register and a high-speed 8-bit shadow register.
The g eneral-purpos e register can be u sed in an 8-bit wide data
path for a normal system a ppli cation. The shadow register is
designed for applications, such as diagnostics in sequential
circui ts, where it is d esira ble to load k nown dat a at a s pecific
location in the circuit and to r e ad the data at that location.
The shadow registers can load data from the output of the
FCT818T, and can be used as a right-shift register with
bit-serial input SDI and output SDO, using DCLK. The data
reg is ter input is multiplex ed to enable loading from the s hadow
reg ister or from the data input pins using PCLK. No te that data
can be loaded simultaneously from the shadow register to the
pipeline register, and f rom the pipelin e register t o the shado w
register provided set-up and hold time requirements are
satisfied wit h respect to the two independent clock inputs.
In a typical application, the general-purpose register in the
FCT818T replaces an 8-bit data register in the normal data
path of a sy stem. The s hadow register is p laced in an auxiliary
bit-serial lo op which is used f or diagnos tics . During diagnostic
operation , da ta is shifted serially into the shadow register , then
transferred to the general purpose register to load a known
value into the data path. To read the contents at that point in
the data path, the data is transferred from th e data register into
the shadow register, then shifted serially in the auxiliary
diagnostic loop to make it accessible to the diagnostics
controller. This data is then compared w ith the expec ted value
to diagnose fa ulty operation of t h e sequential circuit.
The outputs are designed with a power-off disable feature to
allow for live insertion of b oards.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
OE
DCLK
D1
D2
D3
D4
D5
D0
D6
D7
SDI
GND
VCC
MODE
SDO
Y0
Y1
Y3
Y4
Y5
Y7
Y6
15
Y2
Top View
28
4
3
2
1
27
2021 222324 26
19
D5
D4
Y2
Y5
25
Y1
Y7
D7
SDI D0
NC
NC
DCLK
OE
MODE
Y0
GND
NC NC
Y4
D2
LCC
Top View
Y3
Vcc
567891011
D1
D3
12
13
14
15
16
17
18
D6
PCLK
Y6
SDO
PCLK
DIP, SOIC, QSOP
8-BIT
SHADOW
REGISTER
CLK
D Q
MUX
8-BIT
PIPELINE
REGISTER
OE
PCLK
MODE
DCLK
SDI
SDO
D0−D7
P0−P7
Y0−Y7
8
8
8
8
S0−S7
CY29FCT818T
2
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperat ure ......... ........................–65°C to +150°C
Ambient Temperature wi th
Power Applied.............................................–65°C to +135°C
Supply Volta ge to Gro und Pote ntial.. ............. –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).. .....120 mA
Power Dissipation. ..... ...................... ........................ ...... 0.5W
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Function Table[1]
Inputs Inputs Shadow
Register Pipeline
Register OperationMODE SDI DCLK PCLK SDO
L
L
X
XX
X S7
S7
S0←SDI
Si←Si-1
NA
NA
Pi←Di
Serial Shift; D7–D0 Output Disabled
Load Pipeline Register from Data Input
H
H
H
L
H
XX
X
XL
H
SDI
Si←Yi
Hold
NA
NA
NA
Pi←Si
Load Shadow Register from Y Output
Hold Shadow Register; D7−D0 O utput Enabled
Load Pipeline Register from Shadow Register
Operating Range
Range Range Ambient
Temperature VCC
Commercial All –40°C to +85°C 5V ± 5%
Military[4] All –55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Condit ions Min. Typ.[5] Max. Unit
VOH Output HIGH Volt ag e VCC=Min., IOH=–32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–3 m A Mil 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
VCC=Min., IOL=20 mA Mil 0.3 0.55 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHHysteresis[6] All inputs 0.2 V
VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
IIInpu t HIGH Current VCC=Max., VIN=VCC 5µA
IIH Inpu t HIGH Current VCC=Max., VIN=2.7V ±1µA
IIL Input LOW Current VCC=Max., VIN=0.5V ±1µA
IOZH Off State HIGH-Level Output
Current VCC=Max., VOUT=2.7V 10 µA
IOZL Off State LOW-Lev el
Output Current VCC=Max., VOUT=0.5V –10 µA
IOS Output Short Circuit Current[7] VCC=Max., VOUT=0.0V –60 –120 –225 mA
IOFF Powe r-Off Disable VCC=0V, VOUT=4.5V ±1µA
Notes:
1. NA = Not Applicable
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or gr ound.
4. TA is the “instant on” case temperature.
5. Typical values are at VCC=5.0V, TA=+25°C ambient.
6. This parameter is guaranteed but not tes ted.
7. Not more than one output s hould be s hor ted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus an d/or sample
and ho ld techniques ar e preferable in order to minimize internal chip heating and more accurately reflec t operational values. Otherwise prolonged s hor ting of
a high output may raise the c hip temperature well above normal and thereby cause invalid r eadings in other parameters tes ts. In any sequence of parameter
tests, IOS tests shoul d be performed l ast.
CY29FCT818T
3
Capacitance[8]
Parameter Description Test Conditions Typ.[5] Max. Unit
CIN Input Capacitance 5 10 pF
COUT Output Capacitance 9 12 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.[5] Max. Unit
ICC Quiescent Power Supply Current VCC=Max., VIN<0.2V, VIN>VCC–0.2V 0.2 1.5 mA
∆ICC Quiescent Power Supply Current
(TTL inputs HIGH) VCC=Max., VIN=3.4V, f1=0, Outputs Open [8] 0.5 2.0 mA
ICCD Dynamic Power Su pply Curr ent[9] VCC=Max., 50% Duty Cycle, Outputs Open,
One Input Toggling, OE=GND,
VIN<0.2V or VIN>VCC–0.2V
0.25 mA/MHz
ICTotal Power S upply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open,
f0=10 MHz, One Bit Toggling at f1=5 MHz,
OE=GND, VIN<0.2V or VIN>VCC–0.2V
5.3 mA
VCC=M ax. , 50% Duty Cycle, Outputs Open,
f0=10 MHz, One Bit Toggling at f1=5 MHz,
OE=GND, VIN=3.4V or VIN=GND
7.3 mA
VCC=M ax. , 50% Duty Cycle, Outputs Open,
f0=10 MH z, Eight Bits and Four Controls
Toggling, f1=5 MHz, OE=GND,
VIN<0.2V or VIN>VCC–0.2V
17.8[11] mA
VCC=M ax. , 50% Duty Cycle, Outputs Open,
f0=10 MH z, Eight Bits and Four Controls
Toggling, f1=5 MHz, OE=GND,
VIN=3.4V or VIN=GND
30.8[11] mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
CY29FCT818T
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Document #: 38-00275-B
Switching Characteristics Over the Operating Range[12]
Parameter Description
FCT818AT FCT818CT
Unit Fig. No.[13]
Military Commercial Commercial
Min. Max. Min. Max. Min. Max.
tPD Propagation Delay
PCLK to Y
MODE to SDO
SDI to SDO
DCLK to SDO
12
18
18
30
9
16
15
25
6.0
7.2
7.1
7.2
ns
ns
ns
ns
5
6
3
5
tSSet-Up Time
D to PCLK
MODE to PCLK
Y to DCLK
MODE to DCLK
SDI to DCLK
DCLK to PCLK
PCLK to DCLK
6
15
5
12
10
15
45
4
15
5
12
10
15
40
2.0
3.5
2.0
3.5
3.5
3.5
8.5
ns
ns
ns
ns
ns
ns
ns
4
tHHold Tim e
D to PCLK
MODE to PCLK
Y to DCLK
MODE to DCLK
SDI to DCLK
2
0
5
5
0
2
0
5
2
0
1.5
0
1.5
1.5
0
ns
ns
ns
ns
ns
4
tPLZ Output Disable Time LOW
OE to Y
DCLK to D 20
45 15
45 5.5
5.5 ns
ns 7
5
tPHZ Output Disable Time HIGH
OE to Y
DCLK to D 30
90 25
80 8.0
8.0 ns
ns 8
5
tPZL Output Enable Time LOW
OE to Y
DCLK to D 20
35 15
25 8.0
9.0 ns
ns 7
5
tPZH Output Enable Time HIGH
OE to Y
DCLK to D 20
30 15
25 8.5
9.0 ns
ns 8
5
tWPulse Width
PCLK (HIGH and LOW)
DCLK (HIGH and LOW) 15
25 10
15 5.0
5.0 ns
ns 5
5
Speed
(ns) Order ing Code Package
Name Package Type Operating
Range
6.0 CY29FCT818CTPC P13/13A 2 4-Lead (300- Mil) Molded DIP Commercial
CY29FCT818CTQC Q13 2 4-Lead (150- Mil) QSO P
CY29FCT818CTSOC S13 2 4-Lead (300- Mil) Molded SOIC
9.0 CY29FCT818ATPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial
CY29FCT818ATSOC S13 24-Lead (3 00-Mil) Molded SOIC
12.0 CY29FCT818ATDMB D14 24-Lead (3 00-Mil) Cer DIP Military
CY29FCT818ATLMB L64 28-Square Leadless Chip Carrier
Notes:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
CY29FCT818T
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Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D-9 Config.A 28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
24-Lead (300-Mil) Molded DIP P13/P13A
CY29FCT818T
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cypress Semi conductor does not authori ze
its products for use as critical components in life- support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypre ss Semiconductor against all charges.
Package Diagrams (continued)
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC S13
