General Description Tae MAX178 Is a complete. calipratea 12 bil AYO con- verter (ADC) wh ch includes e precision voltage refer- ence, track-and-halc, and conversion clock. Interna calibration circuitry maintains tue 12-bt performance over the thiloperaling temperature range withour externa adustnents. In addition. each conversion mciudes an aulo-zero cycle which reduces zero errars to typically below 100uv CHIP SELECT. READ, and WRITE riputs are ing ded tor easy Ticroprocessur iterfacing without additional logic, 2-byte, 12-bit conversion data is provided over ar 6-pit three-state ourout bus Fither byte may be read first. Two converter busy flags faci tate polling of the converlers status The MAX178's analog irout -arge ig OV to +5 when using a +5 reference. The MAX17845 internal refer- ence accuracy 18 +0.3%. while the MAX178B 1s intenged for use with ac external releerce. Applications Digilal-Signal Processing Audio anc Te ecom Processing High-Speed Data Acquisition High-Accuracy Process Contral Pin Configuration MA AAIMI Calibrated 12-Bit ADC with T/H and Reference Features # Continuous Transparent Calibration of Offset and Gain # True 12-Bit Performance without Adjustments @ T/H Front End and Internal Reference # DC and Dynamically Specified @ Zero Error Typically <100uV # Standard Microprocessor Interface + 24-Pin DIP and Wide SO Packages Ordering Information PART TEMP. RANGE PIN-PACKAGE | | WAX FBACKG oC +706 D4 Placa OIF MAX FBBCNG Note OG 21 Plasie DF HAXITBAGWG Ofte +4700 24 Wide SO MAX 1 7BBCWG ole +706 24 Wade SO MAXI7BACNG 200-0 +850 24 Blasi DIP MAXITBSENG a0 Cte 15 Of Flastic DIP MAXIZSAEWG 40 Gt 85C ed yiels SOP MAKITSBEWO = -40 Cto +85 C 24 Wee SOP MAC FBAMRG -55 Clo +128 C oa CFRIIF MAXITABMHG -bb Clo +125 0 ee CLALP " Consunt factory Functional Diagram TOP VIEW [ . CAR Vin Wy 1 epee |? MALAMLSA To a, oe nal om _ > er cAY 24 is a (2 MAXIE AlN - AlN [2 23 vss : _ ALO ZERO S13] Aaaxim 2 FEOUT wee ae HFFIN 4 [MAKI Yt, oLe AGhO =| 120] bus reels 2 12-EI" DAY | OGM S| Ha] avs : wee D7 = i Wie 18| wk A 14 1 AGE a [ has ve: [8 7] 58 loo. i nee! gs he! as SA nas ey 1 2 - WL PU ayy nae [10] AS WSLS) GLE SP" eg | GRIEF 1 - i a ped |r| 4 Rt 1 ie _ 20 2312 13, TE? amr Ge | KIS i _ lea ay ous Tay Mn DIP/SO Ro Gh WA Be Ue /vVisl <1 /hL_ Maxim Integrated Products 1 faxed ig crogisterad tradernars o Maxim Integrated Proc ucts. SZLIXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference ABSOL UTF MAXIMUM RATINGS VoL toUiGRD ooo. Veg ta DGNE . AGN to DION ecto OGhD . ROUIM co AGNE AIN tO AGND .., C gical Input Voktage toCGN> [gral Output voltage to LGRhD Wied! Undies Absolute Aden ange " uP ocaly MY ro Operat 1g Tevperatui Rang WAAL MAKITB Eo... MAX178_ M LOM, +N +O.8Y, -7Y -O 4V) RFFIN +O av O.OV, +7V 4 ay, Vin OOM Power fissipatier any Pe kage) 0 3) Vin -O 3V To 75C 38V Vien -~03 Deraic above +75 C by. . UY, VoL -U.Y Storage Temperature . Lead lerperaure (Se deraq inser.) Rai Hey x Mdy Se ranggilyp ELECTRICAL CHARACTERISTICS Wop = 45V,Voo = roV. Ves PARAMETER oY, BEFIB - 12 OV al specifications Ta - Th to va fol SiO G/6r2 csceral, | symeot | CONDITIONS MIN = TYP ACCURACY Sosculon | 12 Tote: Unad usted Freer (Neve 14 TUF : Jleren! alNorilirearity ~ JIKL | homussing codes guara teed ~ ~dll-Scale Corer (Gain Error} Ta ~25C6 i =ull-Scale Error Tar pea os Zero Crear Ta - +250 cero Ereor Tamipee os ANALOG INPUT ; Inout Vallage Hange VaEFO LOY al On-Cranrel Input Caaac tance , Cain a | . AK OW te by , , Input leakage Current LAI Ta = 4250 Ta, = TMIN TMAx | DYNAMIC ACCURACY (ya - 14 51-Hz fain 2 GMIkde,Ta 250, Note 2) Signa -1c-Jeise + 0 start oq SAN +) | 70) Tata Hareierie Distortion TEN | : - Peas Harmonic 7 Spurious Meise | REFERENCE INPUT , y For specried pecker at ue 4E +5%o REFIM Hance VREFIN Poe aa . Degraded warsfar ace wracy +4 RFFIN Input Giant R-FIN = -5y ; REFERENCE OUTPUT MAKI784 | RE GUT voltage Ta - PSC 14 985 iS REFQUT Tera ic) OO . a +16 RL: OU! Sink Curren | MAX *73B se Poceral Reerence Grily eer 2 BES bh Gio +1250 6h Cio + MAX alte Le +h he 149 +5 in FO 012 +201 1 1,u0ore Wy 1omwict By SHG 6300 C Pes tatis ony tl ftiad fev ait vada es DM EP Tada th 2 Ulli yrae | UNITS Bits LSB "SR Su ppm! C [sl pemec pmo A fKIA AI VICalibrated 12-Bit ADC with T/H and Reference ELECTRICAL CHARACTERISTIC (continued) Won = 41h, veo 18 veg =-b ROPIM - +5 0, all specications Ta = Iviriic Tag foc: = POO 07k De ovternal, unless othoawise noted 4 MIN TYP MAX UNITS PARAMETER | SYMBOL CONDITIONS LOGIC INPUTS RA CS. WH, BYSL Inout High Vetage | VI | Vou __ i ied Vv Inpul Lew Voltage ViN Virp= Oto Vor Ionia Current lI AS Ha C =| HA | _ a IAS Mita Tax _ | _ 410 Input Capac ance CIM | iMate 3! ee 1G | pF | cLock oO Tnpurt Figh Vo tage _ Lt VIB Wyre - -5V 2o8, a _ | 4 Gu | v | Input | ow Vohage Vil Ls = +5 55, +08 v Irngo: Higa Sumert _ lik | OL = FSV 5%., _ - 15 may | __ rout -ow Curren , tl | Voc - +8V 45% f _ _ aA LOGIC OUTPUTS __ Le a _ OBO DAV BUSY _ Ourput I igh Voltage _ | vou Mos BV 5%, IscunGr = 200A -40 | y ~ulput Low velade a VoL + Veg 45 45%. sine = 1 mA _ ee -o4 y Conont insane ha | your ~ GY to Yon | 4 [ WA Hoang State Gutput | | | Court (Nelo 2) 15 | itl Capacita ice (BRO-3B7) CONVERSION TIME (Note 4} Wilh osteal Clack oLh | 266 67 4H co ls With Irrerna! Cock a= 4250 a an) wee | us POWER REQUIREMENTS | (Note 5) ~14.4 Power Supoly Vo age ; -1f v t 4 a a : 44 ro _ Voc Supply Rejeclon Le rp | LSB Vas Supply Re ecto ! ; 416 ; sa | vo. Suoply Reyectien | = Yon +11 Wta+'2 VY Vs55 - -AV HR | LEB vas Supply Rejection | Veg -7BV te -5 BBY, VoD = 1 lev | HVS LSB | | Iau Vo Va ue vid _ 8 ira Power-Gapoly OLrant Ine 3 ma | Ings | Noted: Inoludes For-Scae Ener Otfeet rear Revetve Accuracy Note 2: Up te ath Harmonic is reasured Note 3. Goaratteed by design Note 4: TrackHolo aquisitior Une included in conversant time Using ta cenditan (see Timi Charac ens tics) Note 5: Powar-supoly curreat is measarec wher MAX" 75 1g inaclive iS = WR =ROD- BUS? Fgh) /VUAXAL Sl _ 3 8ZLXVIWMAX178 Calibrated 12-Bit ADC with T/H and Reference TIMING CHARACTERISTICS (Note 6, Figures 1 and 2) Woo - 415. ver 15, Ves =-5 GOFIN = -S OV uness othervise noted 1 Ta = +25C Ta =-40C to +85 C| Ta= -55 0 10 4125 C | PARAMETER SYMBOL | CONDITIONS - ______ UNITS. MIN TYP MAX MIN TYP MAX! MIN TYP MAX CS to WR Setup Timea 4 Q q 0 ns Wr Pulge Woden {2 eo 170 eo ne. CS vo WR deld Tre in 0 0 a 1's | WH co BUSY on no tees F _ Sranaqation Gelay 4 Bo tea WO Ta a 1h | j SUSY te CS Soto Time 15 (Noted) a) a 4 rs | CS te RM Setup lime s 0 o G ns HE Poise Wieth 7 12u 120 | 1A) a OS te RO Hole lime % qd g u ns BYS_ to RD Setup ime 9 So oo ao Ws BYS. lo RD Held [ree aah) o u U ns RD to Vale Data (ele 7) ta ves ACCES 60 100 Fo. 110 a0 130 | ne Ime} AM te |hres-Stace Cutout (Bue Pelingyusti | >: oa tn iy or - ne | iNule 8) ha Time) 29 uo 20 1OU) ey foc 1 WG lO CLE for 16 Clack 9 on ae . Convers ons (Khote 9) ia 20 ed a . | We ta GL far be Glock < Conversions tale 3) tia a0 eo eu | me Note 6: Data stimee fray View Vea: all iol contol signals ane tmed fran 9 voltage lavalof + 1.6 sad soee fled witht - lo = 2uns (10%. 10 GUM cf +54) Note 7: t-). the > me requirec: aren Gupul lo cross O 8Ver 2 4v, 2 maasiad wth me inad circuits of Figur 3 Note 8: t-, the vive required lor che cata lines va c7ang2 CSV ig meas rea wil ithe oat cireuns olf qui Note 9: Ses Figure 7. Fagura 7. Stad yore hiring 4 MAXIi BA A i HiGh AS PEDAMCE Tie 2 Fee COMMER SIGH REGU! | pan re ACA IM NACE OROEY URLLEK Wan CHANGSS WINLE Gs AYP BL ARLE LOW SATS WIL" THis FGIRE IS OR SMD V TE bIGH-BY TF SaBHOE BO aEELEGHE Calibrated 12-Bit ADC with T/H and Reference 3YoL INCU Fioure 2 Read Cycle Tavag I NAME FUNCTION 1 | CAZ Aute-Zerd Capacror |mput Connect | | | | viherendtat capacitor lo AGKD. | L Ally | Analog Input | | 3 | SLC Ll No Cor ject re Sen | acu Voltage Reference isput. The | METIN Ol Maxiveis spssiied wih REFIN~ | | L +5. | 5 | acno | Sualog Ground | | 8 | GaP GigtGreuna | ? | Vee. bogs suput'y Cigiteu igis are | | ditous are TL comoatibie for | | Vu ~ AY | | 8-18 j bee ou; | Ihree Stato Data Gutpus Active | | whenGs 3 ard AM are treaghr lev. | | fnd vidual pir fusetiais degend upon | Ly Te SELECHBYSUrp [ _DATA BUS OUTPUT, 1. CS, RD = LOW | | PIN | BYSL = HIGH | |. a - Ae SY (Mote 1% | nes _ re 9 | Lowe nT ow, Hate 1) OBB Jd ay [lowmoein oR | 12) DRI MsaL Voge | 3) Be lope A, Be io _| D338 | LPGILSdi Pin Description PIN] NAME | FUNCTION re Fo /READ jipet sce with OS | | the th ee-siele data cuiputs | actives low |CHIF SECC i Ininut _ PD oF WH dor contr Waite {rout In cambraon wen cS | [this actiee low sigaal starts ran | SOnversior | RBYTF SFLECT, BYSL slots bigne or | Iow- bye alow dur gacdal@ ALA | Satie TREO OS oa) bee pos, le. 15 ony T BUSY ic Convener Sratus L. de pmigeuw Sversion, CLs SLOck Inout deleresbeheuk cpt ae [toa ow th this or floatag ann wdUoaded typically rests in 120us leneversion broe (Pinuare & Te can be lowered Oy usitig ar celeria FAG ving k souree (F1 - = 4 ty eristole AU is | Lignecl wiih either CSs ac te cay | a] we | a | a BYSL BUSY fe ontly boyy gure @ ' RLFOUT Tacterence Output | Vs5 | [Neganve Sunny Voollage, 5M | | Vou Hgh ou flay Whree SYS) is twab ons GT teutpat a legic dow. The oor digitel result is in OBG-OBI1, CAT s ihe MSB | Pesitisc Supp y Voltage + [SV | arg a converso1 BUSY OS a cerverer thats SZLXVWMAX178 Calibrated 12-Bit ADC with T/H and Reference Detaifed Operation Operating Information F'qure 5 srows an operat onal diagram forthe MAX178. Tre anly required passive curmpenents are a hold capacitor (CAZ) ard a reference bypass capacitor and es stor. |nci- vidual pir functions arc Lsted r the Pin Description tab e On-Chip Clock Operation The o1 chip oscil ater requires no exterral camponenis. Therefore, tie CLK pin can oe lett uncennected result 1g ina typical 120us conversion ime The conversion time car oe incraased by add'ng a capach ve load on Ine CLK pn The timing diagrams n Figures 6 and 7 show the resulting cracking duration tor relative positions ol WR and CLK Figure 8isascherat c toran chip cloc< operat. Anew cowversion is intiated by bringing WR low, with CS low, [his starls @ track acquisitian seauence. In this staie, tre TIH goes inte tracs mode. Caoacitor CAZ charges to the ealog nput voltage minus the input offsct vo tage of the conparaor Nore wher WRis low (with CS ow), the MAX182 isivtack mode When WA qoes high. tracsing time is exterded by another 4 ta 5 clock periods (4clack periods heqinring with the firstfalling clock edge following tye ising edge ot WR). 16 le 17 coc periods are recuired far each canvers or (Figure 7). ay I ae hi) + 1 ce = + Oe * T Wo2F ~~ q1Q5F uM LiGrD VIGH-? OiEn ITH 2 TOMY __ figure 3 Load Crcuds for Access Time Test sty) ae _ CEN * 23 T OT | 1apr ie ~ [GND Yor QHGH 2 Yio (VAI GH-? Aguied Load Creuits for Qutort Trree-Glate Delay Test (ro) 5 [he MAX178 isinirack mode beween coqvergions wien BUSY is high. After the trackirg sequence, the mast significant Git (MSB) decision is made Followiig this, ine remaining 1 oits are digttized on successive clock cy- cles, as indicated i Figure &. [he WR pu se need not be synchroe zed with the internal clock. External Clock Operation For external clock operalon, drive tre OLA input with a 74HC comipatiple clock scurce (Figire 9} IhoMAX178 auromatical y tracks forse aporopr ale lime by means cot anor-chip counter Both WR and CS must be ow lo intiale a rew conversion Whenever WR ard CS are ow, the chip eriters iia track Node until WR or CS rises. After the rising edge of WR. the next falliag edge of the clock starts a counter, which extends the tracking time by 4 to 5 external clock oer ods The analog iiaulacquisition s compete atire and of tre tracking penad, and the signal is stared in the internal track-and-icld The external clock source need not be synchron zed wih lhe WR pulse Reading Data Toe 12-bilresultat a conversion plus tae converte: status flag are accessinle over an 8-bit data bus The datas avai able from tue MAK178 ip ight-ustified formal (the loast signiican bit (LSB) ts the nghi-most bin a 16-bit word) Two byte sizec reac ooerators are needed The Byte Se sct (BYSL) Inpulveternines woenbyle 5 le be read first SLSBs or 4MSRs pilus slatus lag Itis 1OcCEsary to walt for the enc of acanvers onto ohtan vaid 12-bit data from the MAK178 5 successive ypprox- WAS all 4 j A OE aaa - ALY he =) OGNE ov "Tite | : Be WDA! | - WDB ivOP alee UB RTE | | penes baie | I ob ll ; bata Blt, Figura 5 MAXxd 78 Operahinat aq gen fIATAIL SYCalibrated 12-Bit ADC with T/H and Reference aoa i -RAC-ING) * Naif Teig Bo Ie (MES; frgite: 6. MAKITA Tang Diagrani mation regisle (SAR) lla read operation instruction ts perforrred during a covers or, the MAX'7& will dump the existicg contents of the SAR cv.o the cata bus. Ihere are three metiods to ensure correct aperation: 1. Insert a so*ware delay lenge: trai che ADC con- version cime oetween the conves 07 start and tre data read coeratioss SO lane BUSY output $ low during tre convers on and righ at tne conversion erd Use this signal as an interrut to the uP. 4. Pol the converer status flag, BUSY, at wser-de- fined intervals after a canverson scart. Te status flagis available on DB? during a high-byte READ Tre flag is the lett-mos: bit and can be shifted directly into the wP's cary fag for testing BUSY is high during a conversion A wrte ooeratiod to te MAX178 during a co-version restarts the Gonversion. ee WEE sb CISION FARE WS wa |_| TRACKING - we MSE DEC S ay fre -ta-20rs MIP . VA8TK IRL D3 3BE BLA) DBD ISR: Application Hints Auto-Zero Capacitor (CAZ) CAZ (Figure 5) must be a ow-lcakace, low-dielectric absorption capacior such as polyprapylore, polysty- rene, orteflon. Connecs the outside toil af CAY to AGND te Tirimize noise, CAZ should be 4+,700p! . Clock Figure 10 shows typrcal conversion time versus temper ature when usieg the MAX17&'s on-chip cack De to varations ia racufacuring, the actua operatiig fre- quency can ditter trom chip-toe-chip by upto 70% For this reason. itis sugges:ed that anexcerral clock be used when ixed conversion times are equred. Analog inputs Tre high-trpecarce analog imput. AIN, allows simnole analog interfacing Signal sources frare OV ta +5V may be contecced direct y to AIN wilhoul extra ouffering for source impedances up to Sh (Figure 11). The inputfout out (O} transfer characte istic and cratsilian porvs tor iris irpulsigna ange ave dertiongtraled nF yure 12 anel Table 1. The M.A178 transfe: character stic has racsi #VLAXLAA MAN TS Pre l TORAH TT Tf tLe eiguee 7 Veith of fracrang interval as a Funciion of WA Arsing boge fing wit Hesuecl io CLAW Paling Edge MIAAINI gun d feteral Check Gooration SZIEXVINMAX178 Calibrated 12-Bit ADC with T/H and Reference tion ooins designed co occur of integer nu Liples of ILSB. The output code ts natural binary with: ILSB = tul' Seale (FS)4096 = (S/096)V = - 22my For gigna ranges other than CV to +5, use resister divider nelworks to provide OV to +5V s gral ranges at the MAAt78 inout pns The connection in F gure 13 shows @ divider network ara OV to +10 signal range. Resistors should be of ine sane tyoe ard manufacturer lo cnsLre matched temperature coeficients. The sauree impedance must Tow be as low as possible sires itaads to ihe resislor divider impedarce Figure 14 shows how bipaar siguals -GV ta 15V arc accommodated by referencing the resister divider nel- work to REFIN Tre signal sou'ce must be capable cf fC nyicy COMPATIBLE cide SLOGR SOURCE AAAMLAA | MARI 78 [OND Figure 9 External Claow Owerativr: UE = le - b ue Ft = ing . yy . . 1H ta TT I FAG ! Bt PM 1 TEMPSHAT IHL: Ss sinking 0 5mA with the resistor values shown, Reter ta Figure 15 ana Table @ for tne I/O transter charactenstic and transition 2oints for this signal rarge Ovtout cudirg is offsel binary with an | SB size of (FSi 1/4096) (10/4096)V = 2 dairy To adjust oipolar zero error, amply 1 22mm (+1/2L SR} lo AIN and adiusl ine offset of Al so trat lhe ADC output sw iches between 1900 0C00 0000 and 1900 a0Nc GUO Power-Supply Decoupling Power supplies a tie MAX178 should be byoassed with gilhe a 10uT electrolytic cr tantulum capacitor in para el with a OG! disc ceramic capacitor for clean, bigh- requency oerformance Place all capacitors as close as possible to tho MAX 178 supply pns Alt AALAXMLAA MAKI VE AGHA Adqure tt Unapoiar OV to +5 Operate 1a Kb Th 10] x K og nt ; do Lie FyoY wk Gir Pb bf | ea acn : : : I | Wo TER ZL85 3ILE Te eLhb bh 1 oP APG C3 IMP AT Figure 10. Typical Change in Conversion Lime Vanaton s famacrature wher Using lorernal Crook es Figure 12 lueal inpubOudoul Tanster Characrershe fer Urupevar Cintuitaf Figure Vt SVIAXALSVIinternal Reference The inrarna reteronce (REFOUT) should be bypassec with a 1 resistor n series with a capacitor The capac- iter s.0ud oc a 10UF electrolytic or tantalum in parallel with a C.O1pF disc ceramic (Tigure 16) Figure 17 snows a circuit tha: allows input adjestment which is useful for trimrring our ivtial (room temperature) eras in the rever- ence volrage. Table 1. Transition Points for Unipolar 0V to +5V Operation Analog Input{) Digital Output pose aoos ooo: OobC O00 UOlo 6.00122 G OCl44 j Grit ptty ittt 1OUE OOK S0CC ans coon oot Wt AGATE wets Table 2. Transition Points for Bipolar -5 to +5V Operation _. Analog Input{) Digital Output -4 99875 O09 GO00 O01 -4 99634 ANAS Ona oN1e 000122 1660 GOGO O00 -900122 1600 GOW? ONC +4 993489 111101111 1710 +: 90634 11441117 110: Calibrated 12-Bit ADC with T/H and Reference External Reference Circuit Tigure 18 stows how to setup 2 M&SS4LH to generate a reference voltage of 5 OOV Atyorcal acjustmentrange of 75mV 5 orovided py R29 Over tne cornmercial lem peralure range, the MKS&41LH cortrifutes no more thar +1L58 of gain error. During a conversion, lransierl| currents flow at tre ROP IN inpul. To prevect dynamic errars, place enher a 10.F electrolytic or tamalum smocthing capacilo' i paral el witha O O1pF disc ceramic from the RCCIN pin te AGND QUT Ya ' a oO eo, | Max na. 2 MAXI AG 4 my L * 4 AGN Figure 130 Upotar CY to + fa Oocrahorn te ee ONT HRN | , HI luk: | AADC ida xaty) Vast a , - MAXT/8 Al fe ae alt a heh | i SHODh. So BVT Sy . . Tach Figure tl Bineiar -OV te 40 Oneraton MMA XALSFI SZLXVWMAX178 Calibrated 12-Bit ADC with T/H and Reference Layout When designing ayout for a printed circur board, keep digital and analoy signal ines separated whenever ous- sible It is critical chat ro dig ta line runs alongside an analog $ gnal line or rear Ih CAZ. Guard the analog Inputs, tre reference input ane tre CAZ input with AGND, Establisr a single-point analog ground (AGND) as c ose tu he MAA178 as pussiole, isolated from the logic sys- tem. Conrec: the sicgle-aoint analog ground to the digi-al system ground, which is atlached lo DGND alone noitt. as close as possible to the MAX178 Ihe allowing should ge returred to the ame og ground paint input-sig- nal commor. input guares ine CAZ. anu any bypass capacitors for the refereace aout and the analog sup- plies | ow- mpedance aralog and digital power-suoply common returns, with wide trace widths, are cssertial tor quict operation of ttc MAX17&. on ote ocp = Ee 1y2L8e J oe cae a - . OT . wor | _ Susp | 18 wea | | ww uy 5 rw To oo | TS Peat uy ANALOD MPLT idea! inputOunput Transfer Charactariatic for Agure 15 Pipclar Crow of Figure tt Noise Te minimize input noise coupling. input signal leads 10 AIN ane sigral relurn eads frum AGND shoulc be kep: as short as pessiole A shieloed cable setween source and ADC is suggesld in applications where longer leads are required. Also. care should be taacn to reduce ground circull impecances as much as possible s nce any potential diferonce iq grounds oetween the = qnal source ard ADC creates an errov voltage nm series with the nour signal When interfacing to continuously husy and rersy uP buses, ts possible to get errors ache LSB eve, Irese errors exisl because of [gedthrough trom the bus. to the integrated circut Arocgh the gackage Toe problernican be mir mized in ceramic packaged chips by grounding the metalic, Ancther sel.rie7 is to solate the MAX 176 from the noisy uP bus using th-oc-state buers Ayal Th WPL Pigaie dy 4dushog Aradog taut Gaui do fem Ole fa Bota unee Vallge brrur MAXUM MANTES ap 1 EFM REGIT] ea # 1p = t Gut a Pigurg 18 internal defercase Hooke Nolo Aeforonce Vaiuc is Not Adiustable 10 eos a _ sh iL ub 7 | aca | 1 rae A GER) oP Wasi |. Sout vw [2 re ann BAS MAX TT Rl 2 md AGRI ADSS4l Hf ae Aefersned Geo ay /vIA XL FICalibrated 12-Bit ADC with T/H and Reference Chip Topography 4 REFIN CLK | 0.160" {4.054 mm) BUSY AGND HE, BYSt i WR DGNOD 5 Is | Voc } h 5 DBT | os : it a6 3 zh pe En a ri DB6 a ee Pe Wr ieee \ 1445 DBO (LSB} 085 DBS DBI 0434 (3.40 mm) _ _ MRR CS RORST Bs GL Me Ahawin, poses on [he ragdet te : SC OLA ere 5 ine cucutry are speciicaian MAX __ oa SZLLXVW