SCLS109G - MARCH 1984 - REVISED APRIL 2004 D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 16 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max Encode Eight Data Lines to 3-Line Binary (Octal) Applications Include: - n-Bit Encoding - Code Converters and Generators SN54HC148 . . . J OR W PACKAGE SN74HC148 . . . D, DW, N, OR NS PACKAGE (TOP VIEW) 4 5 6 7 EI A2 A1 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC EO GS 3 2 1 0 A0 SN54HC148 . . . FK PACKAGE (TOP VIEW) 5 4 NC VCC EO description/ordering information The 'HC148 devices feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. These devices encode eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. Data inputs and outputs are active at the low logic level. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 A1 GND NC 6 7 NC EI A2 GS 3 NC 2 1 A0 0 D D D D D D D NC - No internal connection ORDERING INFORMATION PACKAGE TA PDIP - N -40C to 85C -55C 125C -55 C to 125 C ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74HC148N Tube of 40 SN74HC148D Reel of 2500 SN74HC148DR Reel of 250 SN74HC148DT SOIC - DW Reel of 2000 SN74HC148DWR HC148 SOP - NS Reel of 2000 SN74HC148NSR HC148 CDIP - J Tube of 25 SNJ54HC148J SNJ54HC148J CFP - W Tube of 150 SNJ54HC148W SNJ54HC148W LCCC - FK Tube of 55 SNJ54HC148FK SOIC - D SN74HC148N HC148 SNJ54HC148FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) %(#"! "%' / 0 '' %$$! $ $!$( #'$!! *$,!$ $() '' *$ %(#"! %(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS109G - MARCH 1984 - REVISED APRIL 2004 FUNCTION TABLE OUTPUTS INPUTS EI 2 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 logic diagram (positive logic) 0 10 15 14 1 2 11 4 6 7 EI A0 13 1 7 5 GS 12 9 3 EO A1 2 3 4 6 A2 5 Pin numbers shown are for the D, DW, J, N, NS, and W packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS109G - MARCH 1984 - REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC148 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage 0 Input transition rise/fall time SN74HC148 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25C TYP MAX MIN MAX SN74HC148 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 8 160 80 A 3 10 10 10 pF 6V Ci SN54HC148 2 V to 6 V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER SN54HC148 SN74HC148 TO (OUTPUT) VCC 2V 69 180 270 225 1-7 A0, A1, or A2 4.5 V 23 36 54 45 6V 21 31 46 38 EO 0-7 GS tpd A0, A1, or A2 EI GS EO tt TA = 25C TYP MAX FROM (INPUT) Any MIN MIN MAX MIN MAX 2V 60 150 225 190 4.5 V 20 30 45 38 6V 17 26 38 33 2V 75 190 285 240 4.5 V 25 38 57 48 6V 21 32 48 41 2V 78 195 295 245 4.5 V 26 39 59 49 6V 22 33 50 42 2V 57 145 220 180 4.5 V 19 29 44 36 6V 16 25 38 31 2V 66 165 250 205 4.5 V 22 33 50 41 6V 19 28 43 35 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT ns ns 5 SCLS109G - MARCH 1984 - REVISED APRIL 2004 operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP UNIT 35 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time, with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 APPLICATION INFORMATION 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 'HC148 'HC148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS 'HC08 0 1 2 Priority Flag (active low) 3 Encoded Data (active low) 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 'HC148 'HC148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS 'HC00 0 1 2 Priority Flag (active high) 3 Encoded Data (active high) Figure 2. Priority Encoder for 16 Bits Because the 'HC148 devices are combinational logic circuits, wrong addresses can appear during input transients. Moreover, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be considered when strobing the outputs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN54HC148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC148J SN74HC148D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148DW OBSOLETE SOIC DW 16 TBD Call TI Call TI -40 to 85 SN74HC148N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC148N SN74HC148NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC148N SN74HC148NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SN74HC148NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 SNJ54HC148FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54HC 148FK SNJ54HC148J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54HC148J Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) SNJ54HC148W ACTIVE Package Type Package Pins Package Drawing Qty CFP W 16 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD A42 N / A for Pkg Type Op Temp (C) Device Marking (4/5) -55 to 125 SNJ54HC148W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN54HC148, SN74HC148 : Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 * Catalog: SN74HC148 * Military: SN54HC148 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC148DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC148DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC148DR SOIC D 16 2500 364.0 364.0 27.0 SN74HC148DRG4 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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