74F433 First-In First-Out (FIFO) Buffer Memory General Description Features The 'F433 is an expandable fall-through type high-speed first-in first-out (FIFO) buffer memory that is optimized for high-speed disk or tape controller and communication buffer applications. It is organized as 64 words by 4 bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories. The 'F433 has TRI-STATEE outputs that provide added versatility, and is fully compatible with all TTL families. Y Commercial Package Number 74F433SPC N24C Y Y Y Y Y Y Serial or parallel input Serial or parallel output Expandable without additional logic TRI-STATE outputs Fully compatible with all TTL families Slim 24-pin package 9423 replacement Package Description 24-Lead (0.300x Wide) Molded Dual-In-Line Logic Symbol Connection Diagram Pin Assignment for DIP TL/F/9544 - 2 TL/F/9544 - 1 TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9544 RRD-B30M105/Printed in U. S. A. 54F/74F433 First-In First-Out (FIFO) Buffer Memory August 1995 Unit Loading/Fan Out 74F Pin Names PL CPSI IES TTS MR OES TOP TOS CPSO OE D 0 - D3 DS Q0 - Q3 QS IRF ORE Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Parallel Load Input Serial Input Clock Serial Input Enable Transfer to Stack Input Master Reset Serial Output Enable Transfer Out Parallel Transfer Out Serial Serial Output Clock Output Enable Parallel Data Inputs Serial Data Input Parallel Data Outputs Serial Data Output Input Register Full Output Register Empty 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 1.0/0.66 285/10 285/10 20/5 20/5 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 20 mA/400 mA 5.7 mA/16 mA 5.7 mA/16 mA 400 mA/8 mA 400 mA/8 mA Functional Description After the fourth clock transition, the four data bits are located in flip-flops F0 -F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final positions in an 'F433 resulting from a 256-bit serial bit train (B0 is the first bit, B255 the last). As shown in the block diagram, the 'F433 consists of three sections: 1. An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input handshaking and expansion. 2. A 4-bit-wide, 62-word-deep fall-through stack with selfcontained control logic. 3. An Output Register with parallel and serial data outputs, as well as control inputs and outputs for output handshaking and expansion. These three sections operate asynchronously and are virtually independent of one another. Input Register (Data Entry) The Input Register can receive data in either bit-serial or 4-bit parallel form. It stores this data until it is sent to the fallthrough stack, and also generates the necessary status and control signals. This 5-bit register (see Figure 1 ) is initialized by setting flipflop F3 and resetting the other flip-flops. The Q-output of the last flip-flop (FC) is brought out as the Input Register Full (IRF) signal. After initialization, this output is HIGH. Parallel EntryA HIGH on the Parallel Load (PL) input loads the D0 - D3 inputs into the F0 - F3 flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock (CPSI) input must be LOW. Serial EntryData on the Serial Data (DS) input is serially entered into the shift register (F3, F2, F1, F0, FC) on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable (IES) signal is LOW. During serial entry, the PL input should be LOW. Block Diagram TL/F/9544 - 4 2 Functional Description (Continued) TL/F/9544 - 5 FIGURE 1. Conceptual Input Section Once in the stack, data falls through automatically, pausing only when it is necessary to wait for an empty next location. In the 'F433, the master reset (MR) input only initializes the stack control section and does not clear the data. Output Register The Output Register (see Figure 3 ) receives 4-bit data words from the bottom stack location, stores them, and outputs data on a TRI-STATE, 4-bit parallel data bus or on a TRI-STATE serial data bus. The output section generates and receives the necessary status and control signals. Parallel ExtractionWhen the FIFO is empty after a LOW pulse is applied to the MR input, the Output Register Empty (ORE) output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the Transfer Out Parallel (TOP) input is HIGH. As a result of the data transfer, ORE goes HIGH, indicating valid data on the data outputs (provided that the TRI-STATE buffer is enabled). The TOP input can then be used to clock out the next word. When TOP goes LOW, ORE also goes LOW, indicating that the output data has been extracted; however, the data itself remains on the output bus until a HIGH level on TOP permits the transfer of the next word (if available) into the output register. During parallel data extraction, the serial output clock (CPSO) line should be LOW. The Transfer Out Serial (TOS) line should be grounded for single-slice operation or connected to the appropriate ORE line for expanded operation (refer to the `Expansion' section). The TOP signal is not edge-triggered. Therefore, if TOP goes HIGH before data is available from the stack but data becomes available before TOP again goes LOW, that data is transferred into the output register. However, internal TL/F/9544 - 6 FIGURE 2. Final Positions in an 'F433 Resulting from a 256-Bit Serial Train Fall-Through StackThe outputs of flip-flops F0 - F3 feed the stack. A LOW level on the Transfer to Stack (TTS) input initiates a fall-through action; if the top location of the stack is empty, data is loaded into the stack and the input register is reinitialized. (Note that this initialization is delayed until PL is LOW). Thus, automatic FIFO action is achieved by connecting the IRF output to the TTS input. An RS-type flip-flop (the initialization flip-flop) in the control section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack even though IRF and TTS may still be LOW; the initialization flip-flop is not cleared until PL goes LOW. 3 Functional Description (Continued) new word is being loaded into the output register. The fourth transition empties the shift register, forces ORE LOW, and disables the serial output, QS. For serial operation, the ORE output may be tied to the TOS input, requesting a new word from the stack as soon as the previous one has been shifted out. Expansion Vertical ExpansionThe 'F433 may be vertically expanded, without external components, to store more words. The interconnections necessary to form a 190-word by 4-bit FIFO are shown in Figure 4 . Using the same technique, any FIFO of (63n a 1)-words by 4-bits can be configured, where n is the number of devices. Note that expansion does not sacrifice any of the 'F433 flexibility for serial/parallel input and output. control circuitry prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from the stack, ORE remains LOW, indicating that there is no valid data at the outputs. Serial ExtractionWhen the FIFO is empty after a LOW is applied to the MR input, the ORE output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register, if the TOS input is LOW and TOP is HIGH. As a result of the data transfer, ORE goes HIGH, indicating that valid data is in the register. The TRI-STATE Serial Data Output (QS) is automatically enabled and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO. To prevent false shifting, CPSO should be LOW when the TL/F/9544 - 7 FIGURE 3. Conceptual Output Section 4 Functional Description (Continued) TL/F/9544 - 8 FIGURE 4. A Vertical Expansion Scheme 5 Functional Description (Continued) In the 'F433 array of Figure 6 , devices 1 and 5 are the row masters; the other devices are slaves to the master in their rows. No slave in a given row initializes its input register until it has received a LOW on its IES input from a row master or a slave of higher priority. Similarly, the ORE outputs of slaves do not go HIGH until their inputs have gone HIGH. This interlocking scheme ensures that new input data may be accepted by the array when the IRF output of the final slave in that row goes HIGH and that output data for the array may be extracted when the ORE output of the final slave in the output row goes HIGH. The row master is established by connecting its IES input to ground, while a slave receives its IES input from the IRF output of the next-higher priority device. When an array of 'F433 FIFOs is initialized with a HIGH on the MR inputs of all devices, the IRF outputs of all devices are HIGH. Thus, only the row master receives a LOW on the IES input during initialization. Horizontal ExpansionThe 'F433 can be horizontally expanded, without external logic, to store long words (in multiples of 4-bits). The interconnections necessary to form a 64word by 12-bit FIFO are shown in Figure 5 . Using the same technique, any FIFO of 64-words by 4n-bits can be constructed, where n is the number of devices. The right-most (most significant) device is connected to the TTS inputs of all devices. Similarly, the ORE output of the most significant device is connected to the TOS inputs of all devices. As in the vertical expansion scheme, horizontal expansion does not sacrifice any of the 'F433 flexibility for serial/parallel input and output. It should be noted that the horizontal expansion scheme shown in Figure 5 exacts a penalty in speed. Horizontal and Vertical ExpansionThe 'F433 can be expanded in both the horizontal and vertical directions without any external components and without sacrificing any of its FIFO flexibility for serial/parallel input and output. The interconnections necessary to form a 127-word by 16-bit FIFO are shown in Figure 6 . Using the same technique, any FIFO of (63m a 1)-words by 4n-bits can be configured, where m is the number of devices in a column and n is the number of devices in a row. Figures 7 and 8 illustrate the timing diagrams for serial data entry and extraction for the FIFO shown in Figure 6 . Figure 9 illustrates the final positions of bits in an expanded 'F433 FIFO resulting from a 2032-bit serial bit train. Interlocking CircuitryMost conventional FIFO designs provide status signal analogous to IRF and ORE. However, when these devices are operated in arrays, variations in unit-to-unit operating speed require external gating to ensure that all devices have completed an operation. The 'F433 incorporates simple but effective `master/slave' interlocking circuitry to eliminate the need for external gating. Figure 10 is a conceptual logic diagram of the internal circuitry that determines master/slave operation. When MR and IES are LOW, the master latch is set. When TTS goes LOW, the initialization flip-flop is set. If the master latch is HIGH, the input register is immediately initialized and the initialization flip-flop reset. If the master latch is reset, the input register is not initialized until IES goes LOW. In array operation, activating TTS initiates a ripple input register initialization from the row master to the last slave. A similar operation takes place for the output register. Either a TOS or TOP input initiates a load-from-stack operation and sets the ORE request flip-flop. If the master latch is set, the last output register flip-flop is set and the ORE line goes HIGH. If the master latch is reset, the ORE output is LOW until a Serial Output Enable (OES) input is received. TL/F/9544 - 9 FIGURE 5. A Horizontal Expansion Scheme 6 Functional Description (Continued) TL/F/9544 - 10 FIGURE 6. A 127 x 16 FIFO Array TL/F/9544 - 11 FIGURE 7. Serial Data Entry for Array of Figure 6 7 Functional Description (Continued) TL/F/9544 - 12 FIGURE 8. Serial Data Extraction for Array of Figure 6 TL/F/9544 - 13 FIGURE 9. Final Position of a 2032-Bit Serial Input TL/F/9544 - 14 FIGURE 10. Conceptual Diagram, Interlocking Circuitry 8 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions b 65 C to a 150 C Storage Temperature Ambient Temperature under Bias b 55 C to a 125 C Junction Temperature under Bias VCC Pin Potential to Ground Pin Free Air Ambient Temperature Commercial b 55 C to a 150 C 0 C to a 70 C Supply Voltage Commercial b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) a 4.5V to a 5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.5 V Min IIN e b18 mA V Min IOH IOH IOH IOH VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VOL Output LOW Voltage 74F 10% VCC 0.50 V Min IOL e 16 mA (Qn, Qs) IIH Input HIGH Current 74F 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 74F 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 74F 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.4 mA Max VIN e 0.5V IOZH Output Leakage Current 50 mA Max VOUT e 2.7V (Qn, Qs) IOZL Output Leakage Current b 50 mA Max VOUT e 0.5V (Qn, Qs) IOS Output Short-Circuit Current b 130 mA Max VOUT e 0V ICC Power Supply Current 215 mA Max 2.4 2.4 2.7 2.7 4.75 b 20 150 9 e e e e 400 mA (ORE, IRF) 5.7 mA (Qn, Qs) 400 mA (ORE, IRF) 5.7 mA (Qn, Qs) AC Electrical Characteristics Symbol Parameter 74F 74F TA e a 25 C VCC e a 5.0V CL e 50 pF TA, VCC e Com CL e 50 pF Units Fig. No. ns 433-a,b Min Max Min Max tPHL Propagation Delay, Negative-Going CPSI to IRF Output 2.0 17.0 2.0 18.0 tPLH Propagation Delay, Negative-Going TTS to IRF 9.0 34.0 8.0 38.0 tPLH tPHL Propagation Delay, NegativeGoing CPSO to QS Output 4.0 5.0 25.0 20.0 3.0 5.0 27.0 21.0 ns 433-c,d tPLH tPHL Propagation Delay, PositiveGoing TOP to Q0 - Q3 Outputs 8.0 7.0 35.0 30.0 7.0 7.0 38.0 32.0 ns 433-e tPHL Propagation Delay, Negative-Going CPSO to ORE 7.0 25.0 6.0 28.0 ns 433-c,d tPHL Propagation Delay, Negative-Going TOP to ORE 6.0 26.0 6.0 28.0 ns 433-e tPLH Propagation Delay, Positive-Going TOP to ORE 13.0 48.0 12.0 51.0 tPLH Propagation Delay, Negative-Going TOS to Positive-Going ORE 13.0 45.0 12.0 50.0 ns 433-c,d tPHL Propagation Delay, PositiveGoing PL to Negative-Going IRF 4.0 22.0 4.0 23.0 ns 433-g,h tPLH Propagation Delay, NegativeGoing PL to Positive-Going IRF 7.0 31.0 6.0 35.0 tPLH Propagation Delay, Positive-Going OES to ORE 9.0 38.0 8.0 44.0 ns tPLH Propagation Delay Positive-IRF Going IES to Positive-Going 5.0 25.0 5.0 27.0 ns tPHL Propagation Delay MR to ORE 7.0 28.0 7.0 31.0 ns tPLH Propagation Delay MR to IRF 5.0 27.0 5.0 30.0 ns tPZH tPZL Enable Time OE to Q0 - Q3 1.0 1.0 16.0 14.0 1.0 1.0 18.0 16.0 tPHZ tPLZ Disable Time OE to Q0 - Q3 1.0 1.0 10.0 23.0 1.0 1.0 12.0 30.0 tPZH tPZL Enable Time Negative-Going OES to QS 1.0 1.0 10.0 14.0 1.0 1.0 12.0 15.0 tPHZ tPLZ Disable Time Negative-Going OES to QS 1.0 1.0 10.0 14.0 1.0 1.0 12.0 16.0 tPZH tPZL Enable Time TOS to QS 1.0 1.0 35.0 35.0 1.0 1.0 42.0 39.0 ns tDFT Fall-Through Time 0.2 0.9 0.2 1.0 ns tAP Parallel Appearance Time ORE to Q0 - Q3 b 20.0 b 2.0 b 20.0 b 2.0 tAS Serial Appearance Time ORE to QS b 20.0 5.0 b 20.0 5.0 ns ns ns 10 433-h 433-f AC Operating Requirements Symbol Parameter 74F 74F TA e a 25 C VCC e a 5.0V TA, VCC e Com Min Max Min Units Fig. No. ns 433-a,b Max ts(H) ts(L) Setup Time, HIGH or LOW DS to Negative CPSI 7.0 7.0 7.0 7.0 th(H) th(L) Hold Time, HIGH or LOW DS to CPSI 2.0 2.0 2.0 2.0 ts(L) Setup Time, LOW TTS to IRF, Serial or Parallel Mode 0.0 0.0 ns 433-a,b,g,h ts(L) Setup Time, LOW Negative-Going ORE to Negative-Going TOS 0.0 0.0 ns 433-c,d ts(L) Setup Time, LOW NegativeGoing IES to CPSI 8.0 9.0 ns ts(L) Setup Time, LOW NegativeGoing TTS to CPSI 30.0 33.0 ns ts(H) ts(L) Setup Time, HIGH or LOW Parallel Inputs to PL 0.0 0.0 0.0 0.0 th(H) th(L) Hold Time, HIGH or LOW Parallel Inputs to PL 4.0 4.0 4.0 4.0 tw(H) tw(L) CPSI Pulse Width HIGH or LOW 10.0 5.0 11.0 6.0 ns 433-a,b tw(H) PL Pulse Width, HIGH 7.0 9.0 ns 433-g,h tw(L) TTS Pulse Width, LOW Serial or Parallel Mode 7.0 9.0 ns 433-a,b,c,d tw(L) MR Pulse Width, LOW 7.0 9.0 ns 433-f tw(H) tw(L) TOP Pulse Width HIGH or LOW 14.0 7.0 16.0 7.0 ns 433-e tw(H) tw(L) CPSO Pulse Width HIGH or LOW 14.0 7.0 16.0 7.0 ns 433-c,d trec Recovery Time MR to Any Input 8.0 15.0 ns 433-f 433-b 11 ns Timing Waveforms TL/F/9544 - 15 Conditions: Stack not full, IES, PL LOW FIGURE 433-a. Serial Input, Unexpanded or Master Operation TL/F/9544 - 16 Conditions: Stack not full, IES HIGH when initiated, PL LOW FIGURE 433-b. Serial Input, Expanded Slave Operation TL/F/9544 - 17 Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW FIGURE 433-c. Serial Output, Unexpanded or Master Operation 12 Timing Waveforms (Continued) TL/F/9544 - 18 Conditions: Data in stack, TOP HIGH, IES HIGH when initiated FIGURE 433-d. Serial Output, Slave Operation TL/F/9544 - 19 Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack FIGURE 433-e. Parallel Output, 4-Bit Word or Master in Parallel Expansion TL/F/9544 - 20 Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH FIGURE 433-f. Fall Through Time 13 Timing Waveforms (Continued) TL/F/9544 - 21 Conditions: Stack not full, IES LOW when initialized FIGURE 433-g. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion TL/F/9544 - 22 Conditions: Stack not full, device initialized (Note 1) with IES HIGH FIGURE 433-h. Parallel Load, Slave Mode Note 1: Initialization requires a master reset to occur after power has been applied. Note 2: TTS normally connected to IRF. Note 3: If stack is full, IRF will stay LOW. 14 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 433 Temperature Range Family 74F e Commercial SP C Temperature Range C e Commercial (0 C to a 70 C) Device Type Package Code SP e Slim Plastic DIP 15 54F/74F433 First-In First-Out (FIFO) Buffer Memory Physical Dimensions inches (millimeters) 24-Lead (0.300x Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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