74F433SPC - National Semiconductor

TL/F/9544

54F/74F433 First-In First-Out (FIFO) Buffer Memory

August 1995

74F433

First-In First-Out (FIFO) Buffer Memory

General Description

The ’F433 is an expandable fall-through type high-speed

first-in first-out (FIFO) buffer memory that is optimized for

high-speed disk or tape controller and communication buffer

applications. It is organized as 64 words by 4 bits and may

be expanded to any number of words or any number of bits

in multiples of four. Data may be entered or extracted asyn-

chronously in serial or parallel, allowing economical imple-

mentation of buffer memories.

The ’F433 has TRI-STATEÉoutputs that provide added ver-

satility, and is fully compatible with all TTL families.

Features

YSerial or parallel input

YSerial or parallel output

YExpandable without additional logic

YTRI-STATE outputs

YFully compatible with all TTL families

YSlim 24-pin package

Y9423 replacement

Commercial Package Package Description

Number

74F433SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line

Logic Symbol

TL/F/9544–1

Connection Diagram

Pin Assignment for DIP

TL/F/9544–2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Unit Loading/Fan Out

74F

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

PL Parallel Load Input 1.0/0.66 20 mA/400 mA

CPSI Serial Input Clock 1.0/0.66 20 mA/400 mA

IES Serial Input Enable 1.0/0.66 20 mA/400 mA

TTS Transfer to Stack Input 1.0/0.66 20 mA/400 mA

MR Master Reset 1.0/0.66 20 mA/400 mA

OES Serial Output Enable 1.0/0.66 20 mA/400 mA

TOP Transfer Out Parallel 1.0/0.66 20 mA/400 mA

TOS Transfer Out Serial 1.0/0.66 20 mA/400 mA

CPSO Serial Output Clock 1.0/0.66 20 mA/400 mA

OE Output Enable 1.0/0.66 20 mA/400 mA

D0–D3Parallel Data Inputs 1.0/0.66 20 mA/400 mA

DSSerial Data Input 1.0/0.66 20 mA/400 mA

Q0–Q3Parallel Data Outputs 285/10 5.7 mA/16 mA

QSSerial Data Output 285/10 5.7 mA/16 mA

IRF Input Register Full 20/5 400 mA/8 mA

ORE Output Register Empty 20/5 400 mA/8 mA

Functional Description

As shown in the block diagram, the ’F433 consists of three

sections:

1. An Input Register with parallel and serial data inputs, as

well as control inputs and outputs for input handshaking

and expansion.

2. A 4-bit-wide, 62-word-deep fall-through stack with self-

contained control logic.

3. An Output Register with parallel and serial data outputs,

as well as control inputs and outputs for output hand-

shaking and expansion.

These three sections operate asynchronously and are virtu-

ally independent of one another.

Input Register (Data Entry)

The Input Register can receive data in either bit-serial or

4-bit parallel form. It stores this data until it is sent to the fall-

through stack, and also generates the necessary status and

control signals.

This 5-bit register (see

Figure 1

) is initialized by setting flip-

flop F3and resetting the other flip-flops. The Q-output of the

last flip-flop (FC) is brought out as the Input Register Full

(IRF) signal. After initialization, this output is HIGH.

Parallel EntryÐA HIGH on the Parallel Load (PL) input

loads the D0–D3inputs into the F0–F3flip-flops and sets

the FC flip-flop. This forces the IRF output LOW, indicating

that the input register is full. During parallel entry, the Serial

Input Clock (CPSI) input must be LOW.

Serial EntryÐData on the Serial Data (DS) input is serially

entered into the shift register (F3,F

, FC) on each

HIGH-to-LOW transition of the CPSI input when the Serial

Input Enable (IES) signal is LOW. During serial entry, the PL

input should be LOW.

After the fourth clock transition, the four data bits are locat-

ed in flip-flops F0–F3. The FC flip-flop is set, forcing the IRF

output LOW and internally inhibiting CPSI pulses from af-

fecting the register.

Figure 2

illustrates the final positions in

an ’F433 resulting from a 256-bit serial bit train (B0is the

first bit, B255 the last).

Block Diagram

TL/F/9544–4

Functional Description (Continued)

TL/F/9544–5

FIGURE 1. Conceptual Input Section

TL/F/9544–6

FIGURE 2. Final Positions in an ’F433

Resulting from a 256-Bit Serial Train

Fall-Through StackÐThe outputs of flip-flops F0–F3feed

the stack. A LOW level on the Transfer to Stack (TTS) input

initiates a fall-through action; if the top location of the stack

is empty, data is loaded into the stack and the input register

is reinitialized. (Note that this initialization is delayed until PL

is LOW). Thus, automatic FIFO action is achieved by con-

necting the IRF output to the TTS input.

An RS-type flip-flop (the initialization flip-flop) in the control

section records the fact that data has been transferred to

the stack. This prevents multiple entry of the same word into

the stack even though IRF and TTS may still be LOW; the

initialization flip-flop is not cleared until PL goes LOW.

Once in the stack, data falls through automatically, pausing

only when it is necessary to wait for an empty next location.

In the ’F433, the master reset (MR) input only initializes the

stack control section and does not clear the data.

Output Register

The Output Register (see

Figure 3

) receives 4-bit data

words from the bottom stack location, stores them, and out-

puts data on a TRI-STATE, 4-bit parallel data bus or on a

TRI-STATE serial data bus. The output section generates

and receives the necessary status and control signals.

Parallel ExtractionÐWhen the FIFO is empty after a LOW

pulse is applied to the MR input, the Output Register Empty

(ORE) output is LOW. After data has been entered into the

FIFO and has fallen through to the bottom stack location, it

is transferred into the output register, if the Transfer Out

Parallel (TOP) input is HIGH. As a result of the data transfer,

ORE goes HIGH, indicating valid data on the data outputs

(provided that the TRI-STATE buffer is enabled). The TOP

input can then be used to clock out the next word.

When TOP goes LOW, ORE also goes LOW, indicating that

the output data has been extracted; however, the data itself

remains on the output bus until a HIGH level on TOP per-

mits the transfer of the next word (if available) into the out-

put register. During parallel data extraction, the serial output

clock (CPSO) line should be LOW. The Transfer Out Serial

(TOS) line should be grounded for single-slice operation or

connected to the appropriate ORE line for expanded opera-

tion (refer to the ‘Expansion’ section).

The TOP signal is not edge-triggered. Therefore, if TOP

goes HIGH before data is available from the stack but data

becomes available before TOP again goes LOW, that data

is transferred into the output register. However, internal

Functional Description (Continued)

control circuitry prevents the same data from being trans-

ferred twice. If TOP goes HIGH and returns to LOW before

data is available from the stack, ORE remains LOW, indicat-

ing that there is no valid data at the outputs.

Serial ExtractionÐWhen the FIFO is empty after a LOW is

applied to the MR input, the ORE output is LOW. After data

has been entered into the FIFO and has fallen through to

the bottom stack location, it is transferred into the output

result of the data transfer, ORE goes HIGH, indicating that

valid data is in the register.

The TRI-STATE Serial Data Output (QS) is automatically en-

abled and puts the first data bit on the output bus. Data is

serially shifted out on the HIGH-to-LOW transition of CPSO.

To prevent false shifting, CPSO should be LOW when the

new word is being loaded into the output register. The fourth

transition empties the shift register, forces ORE LOW, and

disables the serial output, QS. For serial operation, the ORE

output may be tied to the TOS input, requesting a new word

from the stack as soon as the previous one has been shift-

ed out.

Expansion

Vertical ExpansionÐThe ’F433 may be vertically expand-

ed, without external components, to store more words. The

interconnections necessary to form a 190-word by 4-bit

FIFO are shown in

Figure 4

. Using the same technique, any

FIFO of (63na1)-words by 4-bits can be configured, where

n is the number of devices. Note that expansion does not

sacrifice any of the ’F433 flexibility for serial/parallel input

and output.

TL/F/9544–7

FIGURE 3. Conceptual Output Section

Functional Description (Continued)

TL/F/9544–8

FIGURE 4. A Vertical Expansion Scheme

Functional Description (Continued)

Horizontal ExpansionÐThe ’F433 can be horizontally ex-

panded, without external logic, to store long words (in multi-

ples of 4-bits). The interconnections necessary to form a 64-

word by 12-bit FIFO are shown in

Figure 5

. Using the same

technique, any FIFO of 64-words by 4n-bits can be con-

structed, where n is the number of devices.

The right-most (most significant) device is connected to the

TTS inputs of all devices. Similarly, the ORE output of the

most significant device is connected to the TOS inputs of all

devices. As in the vertical expansion scheme, horizontal ex-

pansion does not sacrifice any of the ’F433 flexibility for

serial/parallel input and output.

It should be noted that the horizontal expansion scheme

shown in

Figure 5

exacts a penalty in speed.

Horizontal and Vertical ExpansionÐThe ’F433 can be ex-

panded in both the horizontal and vertical directions without

any external components and without sacrificing any of its

FIFO flexibility for serial/parallel input and output. The inter-

connections necessary to form a 127-word by 16-bit FIFO

are shown in

Figure 6

. Using the same technique, any FIFO

of (63ma1)-words by 4n-bits can be configured, where m is

the number of devices in a column and n is the number of

devices in a row.

Figures 7

and

illustrate the timing dia-

grams for serial data entry and extraction for the FIFO

shown in

Figure 6

Figure 9

illustrates the final positions of

bits in an expanded ’F433 FIFO resulting from a 2032-bit

serial bit train.

Interlocking CircuitryÐMost conventional FIFO designs

provide status signal analogous to IRF and ORE. However,

when these devices are operated in arrays, variations in

unit-to-unit operating speed require external gating to en-

sure that all devices have completed an operation. The

’F433 incorporates simple but effective ‘master/slave’ inter-

locking circuitry to eliminate the need for external gating.

In the ’F433 array of

Figure 6

, devices 1 and 5 are the row

masters; the other devices are slaves to the master in their

rows. No slave in a given row initializes its input register until

it has received a LOW on its IES input from a row master or

a slave of higher priority.

Similarly, the ORE outputs of slaves do not go HIGH until

their inputs have gone HIGH. This interlocking scheme en-

sures that new input data may be accepted by the array

when the IRF output of the final slave in that row goes HIGH

and that output data for the array may be extracted when

the ORE output of the final slave in the output row goes

HIGH.

The row master is established by connecting its IES input to

ground, while a slave receives its IES input from the IRF

output of the next-higher priority device. When an array of

’F433 FIFOs is initialized with a HIGH on the MR inputs of

all devices, the IRF outputs of all devices are HIGH. Thus,

only the row master receives a LOW on the IES input during

initialization.

Figure 10

is a conceptual logic diagram of the internal cir-

cuitry that determines master/slave operation. When MR

and IES are LOW, the master latch is set. When TTS goes

LOW, the initialization flip-flop is set. If the master latch is

HIGH, the input register is immediately initialized and the

initialization flip-flop reset. If the master latch is reset, the

input register is not initialized until IES goes LOW. In array

operation, activating TTS initiates a ripple input register ini-

tialization from the row master to the last slave.

A similar operation takes place for the output register. Either

a TOS or TOP input initiates a load-from-stack operation

and sets the ORE request flip-flop. If the master latch is set,

the last output register flip-flop is set and the ORE line goes

HIGH. If the master latch is reset, the ORE output is LOW

until a Serial Output Enable (OES) input is received.

TL/F/9544–9

FIGURE 5. A Horizontal Expansion Scheme

Functional Description (Continued)

TL/F/9544–10

FIGURE 6. A 127 x 16 FIFO Array

TL/F/9544–11

FIGURE 7. Serial Data Entry for Array of

Figure 6

Functional Description (Continued)

TL/F/9544–12

FIGURE 8. Serial Data Extraction for Array of

Figure 6

TL/F/9544–13

FIGURE 9. Final Position of a 2032-Bit Serial Input

TL/F/9544–14

FIGURE 10. Conceptual Diagram, Interlocking Circuitry

Absolute Maximum Ratings (Note 1)

Storage Temperature b65§Ctoa

150§C

Ambient Temperature under Bias b55§Ctoa

125§C

Junction Temperature under Bias b55§Ctoa

150§C

VCC Pin Potential to

Ground Pin b0.5V to a7.0V

Input Voltage (Note 2) b0.5V to a7.0V

Input Current (Note 2) b30 mA to a5.0 mA

Voltage Applied to Output

in HIGH State (with VCC e0V)

Standard Output b0.5V to VCC

TRI-STATE Output b0.5V to a5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may

be damaged or have its useful life impaired. Functional operation under

these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating

Conditions

Free Air Ambient Temperature

Commercial 0§Ctoa

70§C

Supply Voltage

Commercial a4.5V to a5.5V

DC Electrical Characteristics

Symbol Parameter 74F Units VCC Conditions

Min Typ Max

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage b1.5 V Min IIN eb

18 mA

VOH Output HIGH 74F 10% VCC 2.4 IOH e400 mA (ORE, IRF)

Voltage 74F 10% VCC 2.4 V Min IOH e5.7 mA (Qn,Q

)

74F 5% VCC 2.7 IOH e400 mA (ORE, IRF)

74F 5% VCC 2.7 IOH e5.7 mA (Qn,Q

)

OL Output LOW Voltage 74F 10% VCC 0.50 V Min IOL e16 mA (Qn,Q

)

IH Input HIGH Current 74F 5.0 mA Max VIN e2.7V

IBVI Input HIGH Current 74F 7.0 mA Max VIN e7.0V

Breakdown Test

ICEX Output HIGH 74F 50 mA Max VOUT eVCC

Leakage Current

VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA

Test All Other Pins Grounded

IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current b0.4 mA Max VIN e0.5V

IOZH Output Leakage Current 50 mA Max VOUT e2.7V (Qn,Q

)

OZL Output Leakage Current b50 mA Max VOUT e0.5V (Qn,Q

)

OS Output Short-Circuit Current b20 b130 mA Max VOUT e0V

ICC Power Supply Current 150 215 mA Max

AC Electrical Characteristics

74F 74F

TAea

25§CTA,V

CC eCom Fig.

Symbol Parameter VCC ea

5.0V CLe50 pF Units No.

CLe50 pF

Min Max Min Max

tPHL Propagation Delay, Negative-Going 2.0 17.0 2.0 18.0

CPSI to IRF Output ns 433-a,b

tPLH Propagation Delay, 9.0 34.0 8.0 38.0

Negative-Going TTS to IRF

tPLH Propagation Delay, Negative- 4.0 25.0 3.0 27.0 ns 433-c,d

tPHL Going CPSO to QSOutput 5.0 20.0 5.0 21.0

tPLH Propagation Delay, Positive- 8.0 35.0 7.0 38.0 ns 433-e

tPHL Going TOP to Q0–Q3Outputs 7.0 30.0 7.0 32.0

tPHL Propagation Delay, 7.0 25.0 6.0 28.0 ns 433-c,d

Negative-Going CPSO to ORE

tPHL Propagation Delay, 6.0 26.0 6.0 28.0

Negative-Going TOP to ORE ns 433-e

tPLH Propagation Delay, Positive-Going 13.0 48.0 12.0 51.0

TOP to ORE

tPLH Propagation Delay, Negative-Going 13.0 45.0 12.0 50.0 ns 433-c,d

TOS to Positive-Going ORE

tPHL Propagation Delay, Positive- 4.0 22.0 4.0 23.0

Going PL to Negative-Going IRF ns 433-g,h

tPLH Propagation Delay, Negative- 7.0 31.0 6.0 35.0

Going PL to Positive-Going IRF

tPLH Propagation Delay, 9.0 38.0 8.0 44.0 ns

Positive-Going OES to ORE

tPLH Propagation Delay Positive-IRF 5.0 25.0 5.0 27.0 ns 433-h

Going IES to Positive-Going

tPHL Propagation Delay 7.0 28.0 7.0 31.0 ns

MR to ORE

tPLH Propagation Delay 5.0 27.0 5.0 30.0 ns

MR to IRF

tPZH Enable Time 1.0 16.0 1.0 18.0

tPZL OE to Q0–Q31.0 14.0 1.0 16.0 ns

tPHZ Disable Time 1.0 10.0 1.0 12.0

tPLZ OE to Q0–Q31.0 23.0 1.0 30.0

tPZH Enable Time 1.0 10.0 1.0 12.0

tPZL Negative-Going OES to QS1.0 14.0 1.0 15.0 ns

tPHZ Disable Time 1.0 10.0 1.0 12.0

tPLZ Negative-Going OES to QS1.0 14.0 1.0 16.0

tPZH Enable Time 1.0 35.0 1.0 42.0 ns

tPZL TOS to QS1.0 35.0 1.0 39.0

tDFT Fall-Through Time 0.2 0.9 0.2 1.0 ns 433-f

tAP Parallel Appearance Time b20.0 b2.0 b20.0 b2.0

ORE to Q0–Q3ns

tAS Serial Appearance Time b20.0 5.0 b20.0 5.0

ORE to QS

AC Operating Requirements

74F 74F

Symbol Parameter TAea

25§CTA,V

CC eCom Units Fig.

VCC ea

5.0V No.

Min Max Min Max

ts(H) Setup Time, HIGH or LOW 7.0 7.0

ts(L) DSto Negative CPSI 7.0 7.0 ns 433-a,b

th(H) Hold Time, HIGH or LOW 2.0 2.0

th(L) DSto CPSI 2.0 2.0

ts(L) Setup Time, LOW TTS to 0.0 0.0 ns 433-a,b,g,h

IRF, Serial or Parallel Mode

ts(L) Setup Time, LOW Negative-Going 0.0 0.0 ns 433-c,d

ORE to Negative-Going TOS

ts(L) Setup Time, LOW Negative- 8.0 9.0 ns

Going IES to CPSI 433-b

ts(L) Setup Time, LOW Negative- 30.0 33.0 ns

Going TTS to CPSI

ts(H) Setup Time, HIGH or LOW 0.0 0.0

ts(L) Parallel Inputs to PL 0.0 0.0 ns

th(H) Hold Time, HIGH or LOW 4.0 4.0

th(L) Parallel Inputs to PL 4.0 4.0

tw(H) CPSI Pulse Width 10.0 11.0 ns 433-a,b

tw(L) HIGH or LOW 5.0 6.0

tw(H) PL Pulse Width, HIGH 7.0 9.0 ns 433-g,h

tw(L) TTS Pulse Width, LOW 7.0 9.0 ns 433-a,b,c,d

Serial or Parallel Mode

tw(L) MR Pulse Width, LOW 7.0 9.0 ns 433-f

tw(H) TOP Pulse Width 14.0 16.0 ns 433-e

tw(L) HIGH or LOW 7.0 7.0

tw(H) CPSO Pulse Width 14.0 16.0 ns 433-c,d

tw(L) HIGH or LOW 7.0 7.0

trec Recovery Time 8.0 15.0 ns 433-f

MR to Any Input

Timing Waveforms

TL/F/9544–15

Conditions: Stack not full, IES,PLLOW

FIGURE 433-a. Serial Input, Unexpanded or Master Operation

TL/F/9544–16

Conditions: Stack not full, IES HIGH when initiated, PL LOW

FIGURE 433-b. Serial Input, Expanded Slave Operation

TL/F/9544–17

Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW

FIGURE 433-c. Serial Output, Unexpanded or Master Operation

Timing Waveforms (Continued)

TL/F/9544–18

Conditions: Data in stack, TOP HIGH, IES HIGH when initiated

FIGURE 433-d. Serial Output, Slave Operation

TL/F/9544–19

Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack

FIGURE 433-e. Parallel Output, 4-Bit Word or Master in Parallel Expansion

TL/F/9544–20

Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES,OE, CPSO LOW, TOP HIGH

FIGURE 433-f. Fall Through Time

Timing Waveforms (Continued)

TL/F/9544–21

Conditions: Stack not full, IES LOW when initialized

FIGURE 433-g. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion

TL/F/9544–22

Conditions: Stack not full, device initialized (Note 1) with IES HIGH

FIGURE 433-h. Parallel Load, Slave Mode

Note 1: Initialization requires a master reset to occur after power has been applied.

Note 2: TTS normally connected to IRF.

Note 3: If stack is full, IRF will stay LOW.

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74F 433 SP C

Temperature Range Family Temperature Range

74FeCommercial CeCommercial (0§Ctoa

70§C)

Device Type

Package Code

SP eSlim Plastic DIP

54F/74F433 First-In First-Out (FIFO) Buffer Memory

Physical Dimensions inches (millimeters)

24-Lead (0.300×Wide) Molded Dual-In-Line Package (SP)

NS Package Number N24C

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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