0 Spartan-II 2.5V FPGA Family: DC and Switching Characteristics R DS001-3 (v2.4) August 28, 2001 0 0 Preliminary Product Specification Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All limits are representative of worst-case supply voltage and junction temperature conditions. Typical numbers are based on measurements taken at a nominal VCCINT level of 2.5V and a junction temperature of 25C. The parameters included are common to popular designs and typical applications. All specifications are subject to change without notice. DC Specifications Absolute Maximum Ratings (1) Symbol Description Min Max Units VCCINT Supply voltage relative to GND (2) -0.5 3.0 V VCCO Supply voltage relative to GND (2) -0.5 4.0 V VREF Input reference voltage -0.5 3.6 V 5V tolerant I/O (4) -0.5 5.5 V No 5V tolerance (5) -0.5 VCCO + 0.5 V 5V tolerant I/O (4) -0.5 5.5 V No 5V tolerance (5) -0.5 VCCO + 0.5 V -65 +150 C - +125 C VIN VTS TSTG TJ Input voltage relative to GND (3) Voltage applied to 3-state output Storage temperature (ambient) Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Power supplies may turn on in any order. 3. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day). 4. Spartan-II I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to either -0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to -2.0V or overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 5. Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either V CCO + 0.5V or 10 mA, and undershoot must be limited to -0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to -2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 6. For soldering guidelines, see the Packaging Information on the Xilinx website: www.xilinx.com/partinfo/pkgs.htm (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 1 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Recommended Operating Conditions Symbol TJ Description Junction temperature (1) Min VCCINT VCCO TIN Supply voltage relative to Supply voltage relative to GND (3,5) Input signal transition Units 0 85 C -40 100 C Commercial 2.5 - 5% 2.5 + 5% V Industrial 2.5 - 5% 2.5 + 5% V Commercial 1.4 3.6 V Industrial 1.4 3.6 V - 250 ns Commercial Industrial GND (2,5) Max time (4) Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 2. Functional operation is guaranteed down to a minimum V CCINT of 2.25V (Nominal V CCINT - 10%). For every 50 mV reduction in VCCINT below 2.375V (nominal VCCINT - 5%), all delay parameters increase by 3%. 3. Minimum and maximum values for VCCO vary according to the I/O standard selected. 4. Input and output measurement threshold is ~50% of VCCO. 5. Supply voltages may be applied in any order desired. DC Characteristics Over Operating Conditions Symbol Description Min Typ Max Units VDRINT Data Retention VCCINT voltage (below which configuration data may be lost) 2.0 - - V VDRIO Data Retention VCCO voltage (below which configuration data may be lost) 1.2 - - V Commercial - 10 30 mA Industrial - 10 60 mA ICCINTQ Quiescent VCCINT supply current (1) XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 ICCOQ IREF IL Quiescent VCCO supply Commercial - 10 30 mA Industrial - 10 60 mA Commercial - 12 50 mA Industrial - 12 100 mA Commercial - 12 50 mA Industrial - 12 100 mA Commercial - 15 50 mA Industrial - 15 100 mA Commercial - 15 75 mA Industrial - 15 150 mA - - 2 mA - - 20 A -10 - +10 A - - 8 pF current (1) VREF current per VREF pin Input or output leakage current CIN Input capacitance (sample tested) VQ, CS, TQ, PQ, FG packages IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V (sample tested) (2) - - 0.25 mA IRPD Pad pull-down (when selected) @ VIN = 3.6V (sample tested) (2) - - 0.15 mA Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not provide valid logic levels when input pins are connected to other circuits. Module 3 of 4 2 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Supply Current Requirements During Power-On A maximum limit for ICCPO is not specified. Be careful when using foldback/crowbar supplies and fuses. It is possible to control the magnitude of ICCPO by limiting the supply current available to the FPGA. A current limit below the trip level will avoid inadvertently activating over-current protection circuits. Spartan-II FPGAs require that a minimum supply current ICCPO be provided to the VCCINT lines for a successful power-on. If more current is available, the FPGA can consume more than ICCPO min., though this cannot adversely affect reliability. Symbol I CCPO TCCPO Description 0C TJ -40C TJ < 0C 100C(2) Total VCCINT supply current required during power-on VCCINT ramp time(3,4) Min(1) Max Units 500 - mA 2 - A - 50 ms Notes: 1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 2.5V. 2. Applies to both Commercial and Industrial devices. 3. The ramp time is measured from GND to V CCINT max on a fully loaded board. 4. VCCINT must not dip in the negative direction during power on. DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for VOL and VOH are guaranteed output voltages over the recommended operating conditions. Only selected standards are tested. These are chosen to ensure that all Input/Output Standard VIL V, Min standards meet their specifications. The selected standards are tested at minimum VCCO with the respective IOL and IOH currents shown. Other standards are sample tested. VIH VOH IOL IOH V, Min V, Max V, Max V, Min mA mA 0.8 2.0 5.5 0.4 2.4 24 -24 0.7 1.7 5.5 0.4 1.9 12 -12 44% VCCINT 60% VCCINT VCCO + 0.5 Note (2) 0.8 2.0 5.5 90% VCCO 2.4 Note (2) -0.5 10% VCCO 0.55 Note (2) Note (2) GTL -0.5 VREF - 0.05 VREF + 0.05 3.6 0.4 N/A 40 N/A GTL+ -0.5 VREF - 0.1 VREF + 0.1 3.6 0.6 N/A 36 N/A HSTL I -0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 8 -8 HSTL III -0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 24 -8 HSTL IV -0.5 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 48 -8 SSTL3 I -0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.6 VREF + 0.6 8 -8 SSTL3 II -0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.8 VREF + 0.8 16 -16 SSTL2 I -0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.6 VREF + 0.6 7.6 -7.6 LVTTL(1) -0.5 LVCMOS2 -0.5 PCI, 3.3V -0.5 PCI, 5.0V V, Max VOL SSTL2 II -0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.8 VREF + 0.8 15.2 -15.2 CTT -0.5 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.4 VREF + 0.4 8 -8 AGP -0.5 VREF - 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note (2) Note (2) Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications. DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 3 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Switching Characteristics Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-II devices unless otherwise noted. Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin) (1) Speed Grade Symbol Description Device TICKOFDLL Global clock input to output delay using output flip-flop for LVTTL, 12 mA, fast slew rate, with DLL. All All -6 -5 Min Max Max Units 2.9 3.3 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 10. 3. DLL output jitter is already included in the timing calculation. 4. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different Standards, page 9. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 11. Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1) Speed Grade All -6 -5 Min Max Max Units Symbol Description Device TICKOF Global clock input to output delay using output flip-flop for LVTTL, 12 mA, fast slew rate, without DLL. XC2S15 4.5 5.4 ns XC2S30 4.5 5.4 ns XC2S50 4.5 5.4 ns XC2S100 4.6 5.5 ns XC2S150 4.6 5.5 ns XC2S200 4.7 5.6 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 10. 3. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different Standards, page 9. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 11. Module 3 of 4 4 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin) Speed Grade -6 -5 Symbol Description Device Min Min Units TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal for LVTTL standard, no delay, IFF,(1) with DLL All 1.7 / 0 1.9 / 0 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation. 4. A zero hold time listing indicates no hold time or a negative hold time. 5. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different Standards, page 7. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 11. Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin) Speed Grade -6 -5 Symbol Description Device Min Min Units TPSFD / TPHFD Input setup and hold time relative to global clock input signal for LVTTL standard, no delay, IFF,(1) without DLL XC2S15 2.2 / 0 2.7 / 0 ns XC2S30 2.2 / 0 2.7 / 0 ns XC2S50 2.2 / 0 2.7 / 0 ns XC2S100 2.3 / 0 2.8 / 0 ns XC2S150 2.4 / 0 2.9 / 0 ns XC2S200 2.4 / 0 3.0 / 0 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. A zero hold time listing indicates no hold time or a negative hold time. 4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different Standards, page 7. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 11. DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 5 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics IOB Input Switching Characteristics (1) Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in IOB Input Delay Adjustments for Different Standards, page 7. Speed Grade -6 Symbol Propagation Delays Description -5 Device Min Max Min All - 0.8 - Max Units TIOPI Pad to I output, no delay 1.0 ns TIOPID Pad to I output, with delay All - 1.5 - 1.8 ns TIOPLI Pad to output IQ via transparent latch, no delay All - 1.7 - 2.0 ns TIOPLID Pad to output IQ via transparent latch, with delay XC2S15 - 3.8 - 4.5 ns XC2S30 - 3.8 - 4.5 ns XC2S50 - 3.8 - 4.5 ns XC2S100 - 3.8 - 4.5 ns XC2S150 - 4.0 - 4.7 ns XC2S200 - 4.0 - 4.7 ns All - 0.7 - 0.8 ns Sequential Delays TIOCKIQ Clock CLK to output IQ Setup/Hold Times with Respect to Clock CLK (2) TIOPICK / TIOICKP TIOPICKD / TIOICKPD Pad, no delay Pad, with delay (1) All 1.7 / 0 - 1.9 / 0 - ns XC2S15 3.8 / 0 - 4.4 / 0 - ns XC2S30 3.8 / 0 - 4.4 / 0 - ns XC2S50 3.8 / 0 - 4.4 / 0 - ns XC2S100 3.8 / 0 - 4.4 / 0 - ns XC2S150 3.9 / 0 - 4.6 / 0 - ns XC2S200 3.9 / 0 - 4.6 / 0 - ns All 0.9 / 0.01 - 0.9 / 0.01 - ns TIOICECK / TIOCKICE ICE input Set/Reset Delays TIOSRCKI SR input (IFF, synchronous) All - 1.1 - 1.2 ns TIOSRIQ SR input to IQ (asynchronous) All - 1.5 - 1.7 ns TGSRQ GSR to output IQ All - 9.9 - 11.7 ns Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 10. 2. A zero hold time listing indicates no hold time or a negative hold time. Module 3 of 4 6 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics IOB Input Delay Adjustments for Different Standards (1) Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Speed Grade Symbol Description Standard -6 -5 Units 0 0 ns LVCMOS2 -0.04 -0.05 ns TIPCI33_3 PCI, 33 MHz, 3.3V -0.11 -0.13 ns TIPCI33_5 PCI, 33 MHz, 5.0V 0.26 0.30 ns TIPCI66_3 PCI, 66 MHz, 3.3V -0.11 -0.13 ns TIGTL GTL 0.20 0.24 ns TIGTLP GTL+ 0.11 0.13 ns TIHSTL HSTL 0.03 0.04 ns TISSTL2 SSTL2 -0.08 -0.09 ns TISSTL3 SSTL3 -0.04 -0.05 ns TICTT CTT 0.02 0.02 ns TIAGP AGP -0.06 -0.07 ns Data Input Delay Adjustments TILVTTL TILVCMOS2 Standard-specific data input delay adjustments LVTTL Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 10. 1 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 7 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Delay Adjustments for Different Standards, page 9. Speed Grade -6 Symbol Propagation Delays Description -5 Min Max Min Max Units TIOOP O input to pad - 2.9 - 3.4 ns TIOOLP O input to pad via transparent latch - 3.4 - 4.0 ns TIOTHZ T input to pad high-impedance (1) - 2.0 - 2.3 ns TIOTON 3-state Delays T input to valid data on pad - 3.0 - 3.6 ns TIOTLPHZ T input to pad high impedance via transparent latch (1) - 2.5 - 2.9 ns TIOTLPON T input to valid data on pad via transparent latch - 3.5 - 4.2 ns TGTS impedance (1) - 5.0 - 5.9 ns - 2.9 - 3.4 ns - 2.3 - 2.7 ns - 3.3 - 4.0 ns 1.1 / 0 - 1.3 / 0 - ns 0.9 / 0.01 - 0.9 / 0.01 - ns GTS to pad high Sequential Delays TIOCKP Clock CLK to pad (synchronous)(1) TIOCKHZ Clock CLK to pad high impedance TIOCKON Clock CLK to valid data on pad (synchronous) Setup/Hold Times with Respect to Clock TIOOCK / TIOCKO CLK (2) O input TIOOCECK / TIOCKOCE OCE input TIOSRCKO / TIOCKOSR SR input (OFF) 1.2 / 0 - 1.3 / 0 - ns TIOTCK / TIOCKT 3-state setup times, T input 0.8 / 0 - 0.9 / 0 - ns TIOTCECK / TIOCKTCE 3-state setup times, TCE input 1.0 / 0 - 1.0 / 0 - ns TIOSRCKT / TIOCKTSR 3-state setup times, SR input (TFF) 1.1 / 0 - 1.2 / 0 - ns Set/Reset Delays TIOSRP SR input to pad (asynchronous) - 3.7 - 4.4 ns TIOSRHZ SR input to pad high impedance (asynchronous)(1) - 3.1 - 3.7 ns TIOSRON SR input to valid data on pad (asynchronous) - 4.1 - 4.9 ns TIOGSRQ GSR to pad - 9.9 - 11.7 ns Notes: 1. Three-state turn-off delays should not be adjusted. 2. A zero hold time listing indicates no hold time or a negative hold time. Module 3 of 4 8 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics IOB Output Delay Adjustments for Different Standards (1) Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Speed Grade Symbol Description Standard -6 -5 Units LVTTL, Slow, 2 mA 14.2 16.9 ns 4 mA 7.2 8.6 ns 6 mA 4.7 5.5 ns TOLVTTL_S8 8 mA 2.9 3.5 ns TOLVTTL_S12 12 mA 1.9 2.2 ns TOLVTTL_S16 16 mA 1.7 2.0 ns TOLVTTL_S24 24 mA 1.3 1.5 ns 12.6 15.0 ns Output Delay Adjustments (Adj) TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, C SL) TOLVTTL_F2 LVTTL, Fast, 2 mA TOLVTTL_F4 4 mA 5.1 6.1 ns TOLVTTL_F6 6 mA 3.0 3.6 ns TOLVTTL_F8 8 mA 1.0 1.2 ns TOLVTTL_F12 12 mA 0 0 ns TOLVTTL_F16 16 mA -0.1 -0.1 ns TOLVTTL_F24 24 mA -0.1 -0.2 ns LVCMOS2 0.2 0.2 ns TOPCI33_3 PCI, 33 MHz, 3.3V 2.4 2.9 ns TOPCI33_5 PCI, 33 MHz, 5.0V 2.9 3.5 ns TOPCI66_3 PCI, 66 MHz, 3.3V -0.3 -0.4 ns TOGTL GTL 0.6 0.7 ns TOGTLP GTL+ 0.9 1.1 ns TOHSTL_I HSTL I -0.4 -0.5 ns TOHSTL_III HSTL III -0.8 -1.0 ns TOHSTL_IV HSTL IV -0.9 -1.1 ns TOSSTL2_I SSTL2 I -0.4 -0.5 ns TOSSLT2_II SSTL2 II -0.8 -1.0 ns TOSSTL3_I SSTL3 I -0.4 -0.5 ns TOSSTL3_II SSTL3 II -0.9 -1.1 ns TOCTT CTT -0.5 -0.6 ns TOAGP AGP -0.8 -1.0 ns TOLVCMOS2 Notes: 1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 10. 1 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 9 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Calculation of TIOOP as a Function of Capacitance Constants for Calculating TIOOP CSL(1) (pF) FL (ns/pF) TIOOP is the propagation delay from the O Input of the IOB to the pad. The values for TIOOP are based on the standard capacitive load (C SL) for each I/O standard as listed in the table Constants for Calculating TIOOP, below. LVTTL Fast Slew Rate, 2 mA drive 35 0.41 LVTTL Fast Slew Rate, 4 mA drive 35 0.20 For other capacitive loads, use the formulas below to calculate an adjusted propagation delay, TIOOP1. LVTTL Fast Slew Rate, 6 mA drive 35 0.13 LVTTL Fast Slew Rate, 8 mA drive 35 0.079 LVTTL Fast Slew Rate, 12 mA drive 35 0.044 LVTTL Fast Slew Rate, 16 mA drive 35 0.043 LVTTL Fast Slew Rate, 24 mA drive 35 0.033 LVTTL Slow Slew Rate, 2 mA drive 35 0.41 LVTTL Slow Slew Rate, 4 mA drive 35 0.20 LVTTL Slow Slew Rate, 6 mA drive 35 0.100 LVTTL Slow Slew Rate, 8 mA drive 35 0.086 LVTTL Slow Slew Rate, 12 mA drive 35 0.058 LVTTL Slow Slew Rate, 16 mA drive 35 0.050 LVTTL Slow Slew Rate, 24 mA drive 35 0.048 LVCMOS2 35 0.041 PCI 33 MHz 5V 50 0.050 PCI 33 MHZ 3.3V 10 0.050 PCI 66 MHz 3.3V 10 0.033 GTL 0 0.014 GTL+ 0 0.017 HSTL Class I 20 0.022 HSTL Class III 20 0.016 HSTL Class IV 20 0.014 SSTL2 Class I 30 0.028 SSTL2 Class II 30 0.016 SSTL3 Class I 30 0.029 SSTL3 Class II 30 0.016 CTT 20 0.035 AGP 10 0.037 TIOOP1 = TIOOP + Adj + (CLOAD - CSL) * FL Where: Adj is selected from IOB Output Delay Adjustments for Different Standards, page 9, according to the I/O standard used CLOAD is the capacitive load for the design FL is the capacitance scaling factor Delay Measurement Methodology Meas. VREF Point Typ (2) VL(1) VH (1) LVTTL 0 3 1.4 - LVCMOS2 0 2.5 1.125 - Standard PCI33_5 Per PCI Spec - PCI33_3 Per PCI Spec - PCI66_3 Per PCI Spec - GTL VREF - 0.2 VREF + 0.2 VREF 0.80 GTL+ VREF - 0.2 VREF + 0.2 VREF 1.0 HSTL Class I VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL Class III VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL Class IV VREF - 0.5 VREF + 0.5 VREF 0.90 SSTL3 I and II VREF - 1.0 VREF + 1.0 VREF 1.5 SSTL2 I and II VREF - 0.75 VREF + 0.75 VREF 1.25 CTT VREF - 0.2 VREF + 0.2 VREF 1.5 AGP VREF + VREF - (0.2xVCCO) (0.2xVCCO) VREF Per AGP Spec Notes: 1. Input waveform switches between VL and VH. 2. Measurements are made at VREF Typ, Maximum, and Minimum. Worst-case values are reported. 3. I/O parameter measurements are made with the capacitance values shown in the previous table, Constants for Calculating TIOOP. See Xilinx application note XAPP179 for the appropriate terminations. 4. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. Module 3 of 4 10 Standard Notes: 1. I/O parameter measurements are made with the capacitance values shown above. See Xilinx application note XAPP179 for the appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Clock Distribution Guidelines (1) Speed Grade Symbol Description -6 -5 Max Max Units 0.13 0.14 ns GCLK Clock Skew TGSKEWIOB Global clock skew between IOB flip-flops Notes: 1. These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise values for a particular design are provided by the timing analyzer. Clock Distribution Switching Characteristics TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock Input Adjustments. Speed Grade Symbol Description -6 -5 Max Max Units GCLK IOB and Buffer TGPIO Global clock pad to output 0.7 0.8 ns TGIO Global clock buffer I input to O output 0.7 0.8 ns I/O Standard Global Clock Input Adjustments Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the values shown. A delay adjusted in the way constitutes a worst-case limit. Speed Grade Symbol Description Standard -6 -5 Units LVTTL 0 0 ns Data Input Delay Adjustments TGPLVTTL Standard-specific global clock input delay adjustments LVCMOS2 -0.04 -0.05 ns TGPPCI33_3 PCI, 33 MHz, 3.3V -0.11 -0.13 ns TGPPCI33_5 PCI, 33 MHz, 5.0V 0.26 0.30 ns TGPPCI66_3 PCI, 66 MHz, 3.3V -0.11 -0.13 ns TGPGTL GTL 0.80 0.84 ns TGPGTLP GTL+ 0.71 0.73 ns TGPHSTL HSTL 0.63 0.64 ns TGPSSTL2 SSTL2 0.52 0.51 ns TGPSSTL3 SSTL3 0.56 0.55 ns TGPCTT CTT 0.62 0.62 ns TGPAGP AGP 0.54 0.53 ns TGPLVCMOS2 Notes: 1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 10. 1 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 11 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics DLL Timing Parameters Switching parameters testing is modeled after testing methods specified by MIL-M-38510/605; all devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parame- ters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -6 Symbol Description -5 Min Max Min Max Units FCLKINHF Input clock frequency (CLKDLLHF) 60 200 60 180 MHz FCLKINLF Input clock frequency (CLKDLL) 25 100 25 90 MHz TDLLPWHF Input clock pulse width (CLKDLLHF) 2.0 - 2.4 - ns TDLLPWLF Input clock pulse width (CLKDLL) 2.5 - 3.0 - ns DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications were determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Figure 1, page 13, provides definitions for various parameters in the table below. CLKDLLHF Symbol Description FCLKIN CLKDLL Min Max Min Max Units TIPTOL Input clock period tolerance - 1.0 - 1.0 ns TIJITCC Input clock jitter tolerance (cycle-to-cycle) - 150 - 300 ps TLOCK Time required for DLL to acquire lock > 60 MHz - 20 - 20 s 50-60 MHz - - - 25 s 40-50 MHz - - - 50 s 30-40 MHz - - - 90 s 25-30 MHz - - - 120 s Output jitter (cycle-to-cycle) for any DLL clock output (1) - 60 - 60 ps TPHIO Phase offset between CLKIN and CLKO (2) - 100 - 100 ps TPHOO Phase offset between clock outputs on the DLL(3) - 140 - 140 ps TPHIOM Maximum phase difference between CLKIN and CLKO (4) - 160 - 160 ps TPHOOM Maximum phase difference between clock outputs on the DLL(5) - 200 - 200 ps TOJITCC Notes: 1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter. 2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding output jitter and input clock jitter. 3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding Output Jitter and input clock jitter. 4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 5. Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter). Module 3 of 4 12 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Period Tolerance: the allowed input clock period change in nanoseconds. T CLKIN = 1 FCLKIN TCLKIN +_ TIPTOL Output Jitter: the difference between an ideal reference clock edge and the actual design. Phase Offset and Maximum Phase Difference Ideal Period Actual Period + Jitter +/- Jitter + Maximum Phase Difference + Phase Offset DS001_52_090800 Figure 1: Period Tolerance and Clock Jitter DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 13 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade -6 Symbol Description -5 Min Max Min Max Units Combinatorial Delays TILO 4-input function: F/G inputs to X/Y outputs - 0.6 - 0.7 ns TIF5 5-input function: F/G inputs to F5 output - 0.7 - 0.9 ns TIF5X 5-input function: F/G inputs to X output - 0.9 - 1.1 ns TIF6Y 6-input function: F/G inputs to Y output via F6 MUX - 1.0 - 1.1 ns TF5INY 6-input function: F5IN input to Y output - 0.4 - 0.4 ns TIFNCTL Incremental delay routing through transparent latch to XQ/YQ outputs - 0.7 - 0.9 ns BY input to YB output - 0.6 - 0.7 ns TCKO FF clock CLK to XQ/YQ outputs - 1.1 - 1.3 ns TCKLO Latch clock CLK to XQ/YQ outputs - 1.2 - 1.5 ns TBYYB Sequential Delays Setup/Hold Times with Respect to Clock CLK (1) TICK / TCKI 4-input function: F/G inputs 1.3 / 0 - 1.4 / 0 - ns TIF5CK / TCKIF5 5-input function: F/G inputs 1.6 / 0 - 1.8 / 0 - ns TF5INCK / TCKF5IN 6-input function: F5IN input 1.0 / 0 - 1.1 / 0 - ns 6-input function: F/G inputs via F6 MUX 1.6 / 0 - 1.8 / 0 - ns BX/BY inputs 0.8 / 0 - 0.8 / 0 - ns CE input 0.9 / 0 - 0.9 / 0 - ns SR/BY inputs (synchronous) 0.8 / 0 - 0.8 / 0 - ns TIF6CK / TCKIF6 TDICK / TCKDI TCECK / TCKCE TRCK / TCKR Clock CLK TCH Minimum pulse width, High - 1.9 - 1.9 ns TCL Minimum pulse width, Low - 1.9 - 1.9 ns Minimum pulse width, SR/BY inputs - 3.1 - 3.1 ns Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) - 1.1 - 1.3 ns Delay from GSR to XQ/YQ outputs - 9.9 - 11.7 ns Toggle frequency (for export control) - 263 - 263 MHz Set/Reset TRPW TRQ TIOGSRQ FTOG Notes: 1. A zero hold time listing indicates no hold time or a negative hold time. Module 3 of 4 14 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade -6 Symbol Description -5 Min Max Min Max Units Combinatorial Delays TOPX F operand inputs to X via XOR - 0.8 - 0.9 ns TOPXB F operand input to XB output - 1.3 - 1.5 ns TOPY F operand input to Y via XOR - 1.7 - 2.0 ns TOPYB F operand input to YB output - 1.7 - 2.0 ns TOPCYF F operand input to COUT output - 1.3 - 1.5 ns TOPGY G operand inputs to Y via XOR - 0.9 - 1.1 ns TOPGYB G operand input to YB output - 1.6 - 2.0 ns TOPCYG G operand input to COUT output - 1.2 - 1.4 ns TBXCY BX initialization input to COUT - 0.9 - 1.0 ns TCINX CIN input to X output via XOR - 0.4 - 0.5 ns TCINXB CIN input to XB - 0.1 - 0.1 ns TCINY CIN input to Y via XOR - 0.5 - 0.6 ns TCINYB CIN input to YB - 0.6 - 0.7 ns CIN input to COUT output - 0.1 - 0.1 ns TFANDXB F1/2 operand inputs to XB output via AND - 0.5 - 0.5 ns TFANDYB F1/2 operand inputs to YB output via AND - 0.9 - 1.1 ns TFANDCY F1/2 operand inputs to COUT output via AND - 0.5 - 0.6 ns TGANDYB G1/2 operand inputs to YB output via AND - 0.6 - 0.7 ns TGANDCY G1/2 operand inputs to COUT output via AND - 0.2 - 0.2 ns TBYP Multiplier Operation Setup/Hold Times with Respect to Clock CLK (1) TCCKX / TCKCX CIN input to FFX 1.1 / 0 - 1.2 / 0 - ns TCCKY / TCKCY CIN input to FFY 1.2 / 0 - 1.3 / 0 - ns Notes: 1. A zero hold time listing indicates no hold time or a negative hold time. DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 15 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics Speed Grade -6 Symbol Sequential Delays Description -5 Min Max Min Max Units TSHCKO16 Clock CLK to X/Y outputs (WE active, 16 x 1 mode) - 2.2 - 2.6 ns TSHCKO32 Clock CLK to X/Y outputs (WE active, 32 x 1 mode) - 2.5 - 3.0 ns 0.7 / 0 - 0.7 / 0 - ns Setup/Hold Times with Respect to Clock CLK (1) TAS / TAH F/G address inputs TDS / TDH BX/BY data inputs (DIN) 0.8 / 0 - 0.9 / 0 - ns CE input (WS) 0.9 / 0 - 1.0 / 0 - ns - 2.9 - 2.9 ns TWS / TWH Clock CLK TWPH Minimum pulse width, High TWPL Minimum pulse width, Low - 2.9 - 2.9 ns TWC Minimum clock period to meet address write cycle time - 5.8 - 5.8 ns Notes: 1. A zero hold time listing indicates no hold time or a negative hold time. CLB Shift Register Switching Characteristics Speed Grade -6 Symbol Sequential Delays TREG Description -5 Min Max Min Max Units - 3.47 - 3.88 ns BX/BY data inputs (DIN) 0.8 - 0.9 - ns CE input (WS) 0.9 - 1.0 - ns Clock CLK to X/Y outputs Setup Times with Respect to Clock CLK TSHDICK TSHCECK Clock CLK TSRPH Minimum pulse width, High - 2.9 - 2.9 ns TSRPL Minimum pulse width, Low - 2.9 - 2.9 ns Module 3 of 4 16 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Block RAM Switching Characteristics Speed Grade -6 Symbol Description -5 Min Max Min Max Units - 3.4 - 4.0 ns Sequential Delays TBCKO Clock CLK to DOUT output Setup/Hold Times with Respect to Clock CLK (1) TBACK / TBCKA ADDR inputs 1.4 / 0 - 1.4 / 0 - ns TBDCK/ TBCKD DIN inputs 1.4 / 0 - 1.4 / 0 - ns TBECK/ TBCKE EN inputs 2.9 / 0 - 3.2 / 0 - ns TBRCK/ TBCKR RST input 2.7 / 0 - 2.9 / 0 - ns TBWCK/ TBCKW WEN input 2.6 / 0 - 2.8 / 0 - ns Clock CLK TBPWH Minimum pulse width, High - 1.9 - 1.9 ns TBPWL Minimum pulse width, Low - 1.9 - 1.9 ns TBCCS CLKA -> CLKB setup time for different ports - 3.0 - 4.0 ns Notes: 1. A zero hold time listing indicates no hold time or a negative hold time. TBUF Switching Characteristics Speed Grade Symbol Description -6 -5 Max Max Units 0 0 ns Combinatorial Delays TIO IN input to OUT output TOFF TRI input to OUT output high impedance 0.1 0.2 ns TON TRI input to valid data on OUT output 0.1 0.2 ns JTAG Test Access Port Switching Characteristics Speed Grade -6 Symbol Description -5 Min Max Min Max Units 4.0 / 2.0 - 4.0 / 2.0 - ns Output delay from clock TCK to output TDO - 11.0 - 11.0 ns Maximum TCK clock frequency - 33 - 33 MHz Setup and Hold Times with Respect to TCK TTAPTCK / TTCKTAP TMS and TDI setup and hold times Sequential Delays TTCKTDO FTCK DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 3 of 4 17 R Spartan-II 2.5V FPGA Family: DC and Switching Characteristics Revision History Version No. Date Description 2.0 09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Updated timing to reflect the latest speed files. Added current supply numbers and XC2S200 -5 timing numbers. Approved -5 timing numbers as preliminary information with exceptions as noted. 2.1 11/02/00 Removed Power Down feature. 2.2 01/19/01 DC and timing numbers updated to Preliminary for the XC2S50 and XC2S100. Industrial power-on current specifications and -6 DLL timing numbers added. Power-on specification clarified. 2.3 03/09/01 Added note on power sequencing. Clarified power-on current requirement. 2.4 08/28/01 Added -6 preliminary timing. Added typical and industrial standby current numbers. Specified min. power-on current by junction temperature instead of by device type (Commercial vs. Industrial). Eliminated minimum VCCINT ramp time requirement. Removed footnote limiting DLL operation to the Commercial temperature range. The Spartan-II Family Data Sheet DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1) DS001-2, Spartan-II 2.5V FPGA Family: Functional Description (Module 2) DS001-3, Spartan-II 2.5V FPGA Family: DC and Switching Characteristics (Module 3) DS001-4, Spartan-II 2.5V FPGA Family: Pinout Tables (Module 4) Module 3 of 4 18 www.xilinx.com 1-800-255-7778 DS001-3 (v2.4) August 28, 2001 Preliminary Product Specification